Flash memory controller chip multi-core synchronization performance test method

Abstract

A multi-core synchronous performance test method for a flash memory controller chip relates to the field of flash memory technology. Multiple test cores are used to send commands to a flash memory controller driver core (backend core) according to a certain synchronization mechanism, instead of a single test core. This method can improve the pressure density of test stimuli and reduce errors introduced by insufficient processor computing power during the testing of performance indicators such as 4K random reads. When the test program firmware runs on multiple processor cores, it can alleviate the problem of insufficient pressure on a single core.

Description

Technical Field

[0001] The present invention relates to the field of flash memory technology, and in particular to a method for testing the multi-core synchronization performance of a flash memory controller chip. Background Art

[0002] A flash controller chip is the main control chip for solid-state drives (SSDs) that rely on flash memory as their storage medium. It typically includes a flash read / write channel driver that interacts with the flash memory, a physical layer interface for command and data transmission, multiple embedded processor cores that serve as the firmware runtime platform, and SRAM / DRAM memory controllers and other hardware acceleration module peripherals. Performance testing of flash controller chips primarily examines whether the read and write rates of the flash memory controller chip for flash memory meet design specifications. This requires the firmware running on the processor to generate or transmit test stimuli (sequences of flash read and write commands). In some test cases, the density and pressure of the stimuli are high (a large number of commands are issued in a short period of time, such as in a 4K read scenario), placing high demands on the processor's computing power. Summary of the Invention

[0003] In order to overcome the deficiencies of the above technologies, the present invention provides a multi-core synchronous performance testing method for a flash memory controller chip, which can alleviate the problem of insufficient pressure on a single core when the test program firmware runs on multiple processor cores.

[0004] The technical solution adopted by the present invention to overcome the technical problems is:

[0005] A method for testing the multi-core synchronization performance of a flash memory controller chip, comprising:

[0006] S1. Place the multi-core flash memory controller SoC chip The processor core is used as the back-end core to run the flash controller driver, and the other cores of the multi-core flash controller SoC chip are used as the back-end core to run the flash controller driver. The processor cores are used as test cores to run the flash memory performance test program. is the number of processor cores of the multi-core flash memory controller SoC chip;

[0007] S2. The flash memory controller chip is powered on. One of the test cores becomes the master test core and initializes the multi-core synchronization test information. The remaining test cores are in a waiting state. The multi-core synchronization test information is a set of sequentially arranged global structures, one for each test core. The contents of the global structure include the synchronization test start flag of the current test core, the synchronization test start timestamp, the synchronization test end flag, the synchronization test end timestamp, the test command type, and the data volume.

[0008] S3. After the test core and backend core are started and ready, the host computer sends a test command to the multi-core flash controller SoC chip;

[0009] S4. After the multi-core flash memory controller SoC chip receives the test command from the host computer, the main test core forwards the test command to each test core designated to participate in the multi-core synchronous test;

[0010] S5. The test core generates a flash read and write test command sequence after receiving the test command;

[0011] S6. After the flash read and write test command sequence is prepared, each test core polls the synchronization test start flag of the corresponding global structure to detect whether the synchronization test start flag of other test cores is set;

[0012] S7. When the synchronous test start flag of each test core is set, all test cores are restored from the waiting state. If the waiting time of the test core during the polling detection exceeds the preset timeout threshold and the synchronous test start flag of each test core is not set, each test core ends the waiting state;

[0013] S8. Each test core independently sends flash memory read and write commands to the corresponding backend core.

[0014] Furthermore, the flash memory performance test program in step S1 is firmware running on the flash memory controller SoC chip for testing the performance of the flash memory controller hardware and its driver.

[0015] Furthermore, in step S1, the flash memory performance test program receives test instructions and parameter texts in character string form through the serial port, and parses the test instructions and parameter texts into test stimuli for the flash memory driver, wherein the test stimuli are read, write or erase commands.

[0016] Furthermore, in step S1, the backend cores are independent of each other, each test core corresponds to a backend core, and the test core generates a test stimulus for the flash controller channel controlled by the corresponding backend core, and sends the generated test stimulus to the corresponding backend core through the inter-core message pipeline for execution.

[0017] Furthermore, in step S2, the method for the main test core to initialize the multi-core synchronous test information is:

[0018] S2-1. Define a memory space accessible to all test cores within the addressable range of the multi-core flash controller SoC chip;

[0019] S2-2. Establish multi-core synchronization test information.

[0020] Furthermore, each test core starts to run independently after detecting that the content of the multi-core synchronization test information is valid. Each structure in the multi-core synchronization test information is maintained by the corresponding test core, and all test cores can query and read the data in the structure.

[0021] Furthermore, in step S3, the host computer transmits a test command in the form of a character string to the multi-core flash memory controller SoC chip through the serial port. The test command includes the flash memory physical address, read and write data memory address, data volume, synchronization bit mask, and output core number.

[0022] Furthermore, in step S4, the main test core uses a text parsing program to forward the test command to each test core designated to participate in the multi-core synchronization test according to the synchronization bit mask in the test command.

[0023] Furthermore, in step S7, after all test cores resume operation from the waiting state, the timestamp of the start of the synchronization test, the test command type, and the data volume are recorded and stored in the global structure corresponding to each test core.

[0024] Furthermore, in step S7, after each test core ends the waiting state, the multi-core synchronization test information is reset, and a timeout exception is output and output to the serial port in the form of a log.

[0025] The beneficial effects of the present invention are as follows: the flash memory controller multi-core synchronous performance test method does not rely on the operating system and hardware mutual exclusion lock mechanisms, is highly versatile and easy to deploy and implement on different platforms, and can be applied to most flash memory controller SoC chips with multiple processor cores, so as to overcome the problem of insufficient test pressure caused by the limitation of software computing power when a single processor is used as a test core. Moreover, it has relatively little additional overhead on storage resources. The basic space occupied by each test core attribute structure in the multi-core synchronous test information is only tens of bytes, and it has certain scalability. In addition to basic attributes such as command type and total amount of test data, other information can be added and expanded. In addition, the test method receives and parses the test command control parameters from the host computer in the form of text characters through a serial port or other debugging interface. The interactive mode is simple and convenient, and does not require the participation of complex front-end communication protocols and flash conversion layer algorithms. It can eliminate the interference of other external factors on the performance results, and more directly and accurately reflect the read and write performance level of the flash memory particles and their controllers themselves. DETAILED DESCRIPTION

[0026] The present invention will be further described below.

[0027] A method for testing the multi-core synchronization performance of a flash memory controller chip, comprising:

[0028] S1. Place the multi-core flash memory controller SoC chip (system on chip) The processor core is used as the back-end core to run the flash controller driver, and the other cores of the multi-core flash controller SoC chip are used as the back-end core to run the flash controller driver. The processor cores are used as test cores to run the flash memory performance test program. This is the number of processor cores in a multi-core flash controller SoC. Large-capacity flash controller SoCs typically have multiple processor cores, each of which executes its own business logic code to increase the parallelism of the flash controller system. (For example, of eight processor cores, four are back-end business cores responsible for interacting with the flash drive module and Nand storage devices; the other four are front-end and algorithm business cores responsible for receiving read and write I / O commands from the host computer and mapping the logical addresses of read and write data blocks to the physical addresses of the flash memory devices).

[0029] S2. The flash memory control chip is powered on, and one of the test cores serves as the main test core. The main test core initializes the multi-core synchronization test information, and the remaining test cores are in a waiting state. The multi-core synchronization test information is a set of sequentially arranged global structures. Each test core corresponds to a global structure. The content of the global structure includes the synchronization test start flag of the current test core, the timestamp of the synchronization test start, the synchronization test end flag, the timestamp of the synchronization test end, the test command type, and the data volume.

[0030] S3. After the test core and the backend core are started and ready, the host computer transmits a test command to the multi-core flash memory controller SoC chip.

[0031] S4. After the multi-core flash memory controller SoC chip receives the test command sent by the host computer, the main test core forwards the test command to each test core designated to participate in the multi-core synchronous test.

[0032] S5. After receiving the test command, the test core generates a flash memory read and write test command sequence.

[0033] S6. After the flash memory read and write test command sequence is prepared, each test core polls the synchronization test start flag of its corresponding global structure to detect whether the synchronization test start flag of other test cores is set.

[0034] S7. When the synchronous test start flags of all test cores are set, all test cores are resumed from the waiting state. If the waiting time of the test core during polling detection exceeds the preset timeout threshold and the synchronous test start flags of all test cores are not set, each test core ends the waiting state.

[0035] S8. Each test core independently sends flash memory read and write commands to the corresponding backend core.

[0036] When a test core completes sending its entire command sequence, it sets its own synchronization test completion flag and records the timestamp of the time the core completed the test. The test core then enters a waiting state, polling to see if the synchronization test completion flags of other test cores are set. After all participating test cores have their synchronization test completion flags set, the test cores resume execution from the blocked waiting state. The test core corresponding to the output core number parameter retrieves information such as the data volume, start and end times, and other information for each test core from the multi-core synchronization test information. It calculates the total amount of flash memory read and write command data generated by each test core, uses the timestamp of the test core that completed the most recent test, and then calculates the read and write rate of the multi-core concurrent test. The performance data is then output as a log via a serial port or other debugging interface. After the multi-core synchronization test process concludes, each test core resets the contents of its corresponding structure in the multi-core synchronization test information for use in the next test.

[0037] In one embodiment of the present invention, the flash memory performance test program in step S1 is firmware running on a flash memory controller SoC chip for testing the performance of the flash memory controller hardware and its driver.

[0038] In one embodiment of the present invention, in step S1, the flash memory performance test program receives test instructions and parameter text in the form of strings via a serial port and parses the test instructions and parameter text into test stimuli for the flash memory driver. The test stimuli are read, write, or erase commands. This replaces the complex firmware running on the front-end and algorithm service core to quickly and directly test the read and write performance of the flash memory.

[0039] In one embodiment of the present invention, the backend cores in step S1 are independent of each other, each test core corresponds to a backend core, and the test core generates a test stimulus for the flash controller channel controlled by the corresponding backend core, and sends the generated test stimulus to the corresponding backend core for execution through the inter-core message pipeline.

[0040] In one embodiment of the present invention, in step S2, the method for the master test core to initialize the multi-core synchronization test information is:

[0041] S2-1. Define a memory space accessible to all test cores within the addressable range of the multi-core flash memory controller SoC chip.

[0042] S2-2. Establish multi-core synchronization test information.

[0043] In one embodiment of the present invention, each test core starts to run independently after detecting that the content of the multi-core synchronization test information is valid. Each structure in the multi-core synchronization test information is maintained by the corresponding test core, and all test cores can query and read the data in the structure.

[0044] In one embodiment of the present invention, in step S3, the host computer transmits a test command in the form of a string to the multi-core flash memory controller SoC chip via a serial port. The test command includes the flash memory physical address, the memory address of the read / write data, the data amount, a synchronization bit mask, and the output core number. The synchronization bit mask specifies, in the form of a binary bitmap, which test cores participate in the synchronization test (for example, if there are four test cores, 0-3, then 0111 indicates that cores 0, 1, and 2 execute the performance test program synchronously, and core 3 does not participate).

[0045] In one embodiment of the present invention, in step S4, the main test core uses a text parsing program to forward the test command to each test core designated to participate in the multi-core synchronization test according to the synchronization bit mask in the test command.

[0046] In one embodiment of the present invention, in step S7, after all test cores resume operation from the waiting state, the timestamp of the start of the synchronization test, the test command type, and the data volume are recorded and stored in the global structure corresponding to each test core.

[0047] In one embodiment of the present invention, after each test core ends the waiting state in step S7, the multi-core synchronization test information is reset, and a timeout exception is output and output to the serial port in the form of a log.

[0048] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art will be able to modify the technical solutions described in the aforementioned embodiments or substitute equivalents for some of the technical features. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A flash memory controller chip multi-core synchronization performance test method, characterized in that: include: S1. Place the multi-core flash memory controller SoC chip The processor core is used as the back-end core to run the flash controller driver, and the other cores of the multi-core flash controller SoC chip are used as the back-end core to run the flash controller driver. The processor cores are used as test cores to run the flash memory performance test program. is the number of processor cores of the multi-core flash memory controller SoC chip; S2. The flash memory controller chip is powered on. One of the test cores becomes the master test core and initializes the multi-core synchronization test information. The remaining test cores are in a waiting state. The multi-core synchronization test information is a set of sequentially arranged global structures, one for each test core. The contents of the global structure include the synchronization test start flag of the current test core, the synchronization test start timestamp, the synchronization test end flag, the synchronization test end timestamp, the test command type, and the data volume. S3. After the test core and backend core are started and ready, the host computer sends a test command to the multi-core flash controller SoC chip; S4. After the multi-core flash memory controller SoC chip receives the test command from the host computer, the main test core forwards the test command to each test core designated to participate in the multi-core synchronous test; S5. The test core generates a flash read and write test command sequence after receiving the test command; S6. After the flash read and write test command sequence is prepared, each test core polls the synchronization test start flag of the corresponding global structure to detect whether the synchronization test start flag of other test cores is set; S7. When the synchronous test start flag of each test core is set, all test cores are restored from the waiting state. If the waiting time of the test core during the polling detection exceeds the preset timeout threshold and the synchronous test start flag of each test core is not set, each test core ends the waiting state; S8. Each test core independently sends flash memory read and write commands to the corresponding backend core.

2. The flash memory controller chip multi-core synchronization performance testing method according to claim 1, characterized in that: The flash memory performance test program in step S1 is firmware running on the flash memory controller SoC chip for testing the performance of the flash memory controller hardware and its driver.

3. The flash memory controller chip multi-core synchronization performance testing method according to claim 1, characterized in that: In step S1, the flash memory performance test program receives test instructions and parameter texts in character string form through the serial port, and parses the test instructions and parameter texts into test stimuli for the flash memory driver, wherein the test stimuli are read, write or erase commands.

4. The method for testing the multi-core synchronization performance of a flash memory controller chip according to claim 1, wherein: In step S1, each backend core is independent of each other, and each test core corresponds to a backend core. The test core generates a test stimulus for the flash controller channel controlled by the corresponding backend core, and sends the generated test stimulus to the corresponding backend core through the inter-core message pipeline for execution.

5. The flash memory controller chip multi-core synchronization performance testing method according to claim 1, characterized in that: In step S2, the method for the main test core to initialize the multi-core synchronous test information is: S2-1. Define a memory space accessible to all test cores within the addressable range of the multi-core flash controller SoC chip; S2-2. Establish multi-core synchronization test information.

6. The method for testing the multi-core synchronization performance of a flash memory controller chip according to claim 5, wherein: Each test core starts to run independently after detecting that the content of the multi-core synchronization test information is valid. Each structure in the multi-core synchronization test information is maintained by the corresponding test core, and all test cores can query and read the data in the structure.

7. The method for testing the multi-core synchronization performance of a flash memory controller chip according to claim 1, wherein: In step S3, the host computer transmits a test command in the form of a character string to the multi-core flash memory controller SoC chip through the serial port. The test command includes the flash memory physical address, read and write data memory address, data amount, synchronization bit mask, and output core number.

8. The method for testing the multi-core synchronization performance of a flash memory controller chip according to claim 7, wherein: In step S4 , the main test core uses a text parsing program to forward the test command to each test core designated to participate in the multi-core synchronization test according to the synchronization bit mask in the test command.

9. The method for testing the multi-core synchronization performance of a flash memory controller chip according to claim 7, wherein: In step S7, after all test cores resume operation from the waiting state, the timestamp of the start of the synchronization test, the test command type, and the data volume are recorded and stored in the global structure corresponding to each test core.

10. The method for testing the multi-core synchronization performance of a flash memory controller chip according to claim 7, wherein: In step S7, after each test core ends the waiting state, the multi-core synchronization test information is reset, and a timeout exception is output and output to the serial port in the form of a log.

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