Chip test method based on MT6877 platform, electronic equipment and medium

Abstract

The invention discloses a chip testing method based on an MT6877 platform, electronic equipment and a medium, and relates to the technical field of chip testing. The method comprises the following steps: acquiring an MT6877 platform; designing an adapter plate according to the layout of the LPDDR5 chip; the test points of the line routing are led out to the surface of the adapter plate and are connected with the corresponding test bonding pads; welding the adapter plate in the mounting area, and connecting the bottom surface bonding pad with the connecting point; a limiting device is arranged on the adapter plate; the LPDDR5 chip is placed in the limiting hole; placing a pressing device on the limiting device, pressing the LPDDR5 chip through the pressing device, and enabling the LPDDR5 chip to be connected with the surface bonding pad; the MT6877 platform tests the LPDDR5 chip through the adapter plate to obtain a test result; and connecting the test bonding pad with an oscilloscope, and displaying a test waveform through the oscilloscope. According to the method, the LPDDR5 chip can be mounted and dismounted more conveniently and quickly.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular to a chip testing method, electronic equipment and medium based on an MT6877 platform. Background Art

[0002] LPDDR5, or Low Power Double Data Rate 5, is a low-power double data rate memory and a new generation of low-power memory technology with the characteristics of low power consumption, high data transmission rate, low latency and support for larger capacity. During the production process of LPDDR5 chips, they need to be tested to verify whether their various functions are normal. In the prior art, when testing LPDDR5 chips, the LPDDR5 chips are usually soldered to a test circuit board, and the chips are tested through the test circuit board. However, in this way, the LPDDR5 chip needs to be soldered to the test circuit board during testing, and the LPDDR5 chip cannot be easily removed after the test, and the installation and removal of the LPDDR5 chip is inconvenient. Moreover, since the entire chip is soldered on the test circuit board, it is only possible to simply verify whether the LPDDR5 chip can work normally, and it is impossible to lead out the various test points of the LPDDR5 chip, and conduct a more in-depth analysis of the various signals of the LPDDR5 chip to accurately evaluate the performance of the LPDDR5 chip. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention proposes a chip testing method, electronic equipment, and medium based on the MT6877 platform, which makes the installation and removal of the LPDDR5 chip more convenient and can perform a more in-depth analysis of each signal of the LPDDR5 chip.

[0004] In a first aspect, a chip testing method based on an MT6877 platform according to an embodiment of the present invention comprises the following steps: Acquire an MT6877 platform; the MT6877 platform is provided with an installation area, and the installation area is provided with a connection point; According to the layout of the LPDDR5 chip, an adapter board is designed; the number of layers of the adapter board is greater than two, the inner layer board of the adapter board is provided with circuit routing, the surface of the adapter board is provided with surface pads and test pads, the bottom surface of the adapter board is provided with bottom pads, and the surface pads are connected to the bottom pads through vias; Leading the test points of the line routing to the surface of the adapter board and connecting them to the corresponding test pads; Welding the adapter plate to the mounting area so that the bottom pad is connected to the connection point; A limiting device is arranged on the adapter plate; the limiting device is provided with a limiting hole adapted to the surface pad and a hollow portion adapted to the test pad; Placing the LPDDR5 chip in the limiting hole; A pressing device is placed on the limiting device, and the LPDDR5 chip is pressed by the pressing device to connect the LPDDR5 chip to the surface pad; The MT6877 platform tests the LPDDR5 chip through the adapter board to obtain a test result; The test pad is connected to an oscilloscope, and the test waveform is displayed by the oscilloscope.

[0005] According to some embodiments of the present invention, the clamping device includes: a base, a pressing block, a connecting rod and a screwing block; wherein a connecting column is provided on the surface of the pressing block, the connecting column is penetrated in the base, the pressing block is located below the base, the screwing block is provided on the surface of the base, the connecting rod is provided in the base, one end of the connecting rod is threadedly connected to the connecting column, and the other end of the connecting rod is connected to the screwing block; the step of placing the clamping device on the limiting device, pressing the LPDDR5 chip by the clamping device, and connecting the LPDDR5 chip to the surface pad includes: Placing the base on the limiting device so that the pressing block is placed in the limiting hole; The screw block is rotated to make the connecting rod drive the connecting column and the pressing block to press down, and the LPDDR5 chip is pressed tightly by the pressing block.

[0006] According to some embodiments of the present invention, a limiting member is further provided between the screw block and the base, the limiting member is rotatably provided on the surface of the base, the connecting rod is penetrated through the limiting member, a limiting groove is provided on the surface of the limiting member, a limiting column is provided at the bottom of the screw block, the limiting column is inserted into the limiting groove, a plurality of adjustment holes are further provided on the side of the limiting member, the base is provided with an elastic adjustment switch, the elastic adjustment switch is provided with an adjustment block adapted to the adjustment hole, and the adjustment block is located in one of the adjustment holes; the step of placing a pressing device on the limiting device, pressing the LPDDR5 chip by the pressing device, and connecting the LPDDR5 chip to the surface pad also includes: Obtaining the thickness of the LPDDR5 chip; Determining the maximum pressing stroke of the pressing block according to the thickness of the LPDDR5 chip; According to the maximum downward stroke, the elastic adjustment switch is pressed to make the adjustment block leave the current adjustment hole, and the limiting member is rotated to make the new adjustment hole located at the adjustment block, and the elastic adjustment switch is released to place the adjustment block in the new adjustment hole.

[0007] According to some embodiments of the present invention, a first magnetic member is disposed at the bottom of the base, and a second magnetic member matching the first magnetic member is disposed on the surface of the limiting device; or, a first threaded hole is disposed at the base, and a second threaded hole matching the first threaded hole is disposed at the limiting device; the step of placing the base on the limiting device includes: Placing the base on the limiting device, and fixing the base by the first magnetic attraction member and the second magnetic attraction member; Alternatively, the base is placed on the limiting device, and screwed into the first threaded hole and the second threaded hole to fix the base.

[0008] According to some embodiments of the present invention, the step of leading the test point of the line routing to the surface of the adapter board and connecting it to the corresponding test pad includes: Lead out the WCK differential signal, RDQS differential signal and two random data single-ended signals of each channel of the LPDDR5 chip as the first signal test point; Lead out the clock differential signal, two random CA signals and two random CS signals of each channel of the LPDDR5 chip as the second signal test point; Lead out the VDDQ signal, VDD1 signal, VDD2H signal and VDD2L signal of the LPDDR5 chip as power supply test points; The first signal test point, the second signal test point and the power supply test point are all connected to the corresponding test pads.

[0009] According to some embodiments of the present invention, the step of leading the test points of the line routing to the surface of the adapter board and connecting them to the corresponding test pads further includes: GND ground holes are evenly arranged around the WCK differential signal, the RDQS differential signal, the data single-ended signal, the clock differential signal, the CA signal, the CS signal, the VDDQ signal, the VDD1 signal, the VDD2H signal and the VDD2L signal to achieve ground package setting; Lead out the signal of the GND ground hole as a ground test point; Connect the ground test point to the corresponding test pad.

[0010] According to some embodiments of the present invention, the test pad includes a signal test pad and a ground test pad, the first signal test point, the second signal test point and the power supply test point are respectively connected to the corresponding signal test pads, the ground test point is connected to the ground test pad, and the shape of the signal test pad is different from the shape of the ground test pad.

[0011] According to some embodiments of the present invention, the signal impedance of the WCK differential signal, the RDQS differential signal, and the clock differential signal is lower than 100Ω, the signal impedance of the data single-ended signal, the CA signal, and the CS signal is lower than 50Ω, and the routing width of the VDDQ signal, the VDD1 signal, the VDD2H signal, and the VDD2L signal is greater than 12 mil.

[0012] In a second aspect, an electronic device according to an embodiment of the present invention includes: A memory for storing program instructions; The processor is used to call the program instructions stored in the memory, and execute the chip testing method based on the MT6877 platform described in the first aspect embodiment according to the obtained program instructions.

[0013] In a third aspect, according to a storage medium of an embodiment of the present invention, the storage medium stores computer executable instructions, and the computer executable instructions are used to enable a computer to execute the chip testing method based on the MT6877 platform described in the embodiment of the first aspect.

[0014] The chip testing method, electronic device, and medium based on the MT6877 platform according to the embodiments of the present invention have at least the following beneficial effects: by designing an adapter board, in addition to being able to test whether the LPDDR5 chip can work normally on the MT6877 platform, the test pads of the adapter board can also be connected to an oscilloscope to obtain the waveforms of various signals of the LPDDR5 chip; by setting a limiting device and a clamping device, the LPDDR5 chip can be limited, and the LPDDR5 chip can be connected to the adapter board, so that the connection between the LPDDR5 chip and the MT6877 platform can be achieved without soldering the LPDDR5 chip on the MT6877 platform, so that the MT6877 platform can test the LPDDR5 chip, and the installation and disassembly of the LPDDR5 chip is more convenient.

[0015] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 The following is a flowchart of a chip testing method based on the MT6877 platform according to an embodiment of the present invention; Figure 2 It is a structural diagram of the MT6877 platform according to an embodiment of the present invention; Figure 3 It is a structural schematic diagram of an adapter board according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the internal wiring of the adapter board according to an embodiment of the present invention; Figure 5 It is a schematic structural diagram of a limiting device and a pressing device according to an embodiment of the present invention; Figure 6 It is a structural schematic diagram of a pressing device according to an embodiment of the present invention; Figure 7 This is a schematic structural diagram of the pressing device of an embodiment of the present invention after the base is removed; Figure 8 An exploded schematic diagram of a clamping device according to an embodiment of the present invention; Fig. 9 It is a structural schematic diagram of a twisting block according to an embodiment of the present invention; Reference numerals: MT6877 platform 100, installation area 200, connection point 210, first positioning hole 220, limiting device 300, limiting hole 310, hollow portion 320, second positioning hole 330, second threaded hole 350, clamping device 400, base 410, pressing block 420, screwing block 430, limiting column 431, connecting rod 440, connecting column 450, limiting member 460, adjusting hole 461, limiting groove 462, through hole 463, elastic adjustment switch 470, adjusting block 471, adapter board 500, surface pad 510, test pad 520, ground test pad 521, signal test pad 522. DETAILED DESCRIPTION

[0017] Embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and are not to be construed as limitations on the present application. For the step numbers in the following embodiments, they are only provided for the convenience of explanation, and the order between the steps is not limited in any way, and the execution order of each step in the embodiment can be adaptively adjusted according to the understanding of those skilled in the art.

[0018] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., and orientations or positional relationships indicated are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0019] The terms "first", "second", "third" and "fourth" etc. in the specification and claims of the present invention and the drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or devices.

[0020] Reference to "embodiments" in the present invention means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0021] In the prior art, when testing the LPDDR5 chip, the LPDDR5 chip is usually soldered to a test circuit board, and the chip is tested through the test circuit board. However, in this way, the LPDDR5 chip needs to be soldered to the test circuit board during testing, and the LPDDR5 chip cannot be easily removed after the test, and the installation and disassembly of the LPDDR5 chip is inconvenient. Moreover, since the entire chip is soldered on the test circuit board, it is only possible to simply verify whether the LPDDR5 chip can work normally, and it is impossible to lead out the various test points of the LPDDR5 chip, and conduct a more in-depth analysis of the various signals of the LPDDR5 chip to accurately evaluate the performance of the LPDDR5 chip.

[0022] To this end, the embodiments of the present invention provide a chip testing method, electronic device, and medium based on the MT6877 platform. By designing an adapter board, in addition to being able to test whether the LPDDR5 chip can work normally on the MT6877 platform, the test pad of the adapter board can also be connected to an oscilloscope to obtain the waveforms of various signals of the LPDDR5 chip; by setting a limiting device and a clamping device, the LPDDR5 chip can be limited, and the LPDDR5 chip can be connected to the adapter board. Therefore, there is no need to solder the LPDDR5 chip on the MT6877 platform, and the connection between the LPDDR5 chip and the MT6877 platform can be achieved, so that the MT6877 platform can test the LPDDR5 chip, and the installation and disassembly of the LPDDR5 chip is more convenient.

[0023] The chip testing method, electronic device, and medium based on the MT6877 platform according to the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0024] On the one hand, the embodiment of the present invention proposes a chip testing method based on the MT6877 platform, such as Figure 1 As shown, the method comprises the following steps: Step S100: Acquire the MT6877 platform 100; The MT6877 platform is provided with an installation area 200, and the installation area 200 is provided with a connection point 210; Specifically, Figure 2 As shown, in this example, the MT6877 platform 100 is also called the MediaTek Dimensity 900 platform, which is an intelligent solution that integrates a high-performance 5G MT6877 SoC (system-on-chip). At present, the MT6877 platform is widely used in devices such as smartphones, and has broad application prospects in multiple fields such as smart Internet of Things, Internet of Vehicles, industrial automation, and artificial intelligence. When the MT6877 platform is applied to mobile phones and other devices, in order to verify whether the LPDDR5 chip can read and write normally when it is installed on the MT6877 platform, in this application, an installation area 200 is set for the installation position of the LPDDR5 chip, and the installation area 200 is provided with a connection point 210 for connecting to the LPDDR5 chip and testing the LPDDR5.

[0025] Step S200: Designing an adapter board 500 according to the layout of the LPDDR5 chip; the number of layers of the adapter board 500 is greater than two layers, the inner layer board of the adapter board 500 is provided with circuit routing, the surface of the adapter board 500 is provided with a surface pad 510 and a test pad 520, the bottom surface of the adapter board 500 is provided with a bottom pad, and the surface pad 510 is connected to the bottom pad through a via; Step S300: Leading the test points of the line routing to the surface of the adapter board 500 and connecting them to the corresponding test pads 520; It should be noted that the surface pads 510 and the bottom pads of the adapter board 500 correspond one to one, and the two are connected through a via hole to achieve the conduction of the circuits of each layer of the adapter board 500. At the same time, the design of the surface pads 510 and the bottom pads corresponds to the layout of the LPDDR5 chip. The circuit routing inside the adapter board 500 includes various circuits required by the LPDDR5 chip, such as power lines, data lines, clock lines, control lines, ground lines, etc. For the circuits that need to be tested, the test points of the corresponding circuit routing are led out to the surface of the adapter board 500 and connected to the corresponding test pads 520, such as Figure 3 and Figure 4 By connecting the surface pad 510 and the bottom pad with a via hole, the electrical interconnection effect is achieved, and the signal test line segment of the line routing is led out in the middle layer to the surface test pad 520, that is, a T-shaped topology structure is adopted, and the led signal test line segment needs to be as short as possible to reduce the reflection caused by the T-shaped topology structure.

[0026] Step S400: welding the adapter board 500 to the mounting area 200 so that the bottom pad is connected to the connection point 210; By welding the adapter board 500 at the mounting area 200 , the bottom pad is connected to the connection point 210 , so that it is convenient to subsequently obtain the connection between the MT6877 platform 100 and the LPDD5 chip through the connection point 210 and the adapter board 500 .

[0027] Step S500: a limiting device 300 is provided on the adapter plate 500; the limiting device 300 is provided with a limiting hole 310 adapted to the surface pad 510 and a hollow portion 320 adapted to the test pad 520; It should be noted that the limiting device 300 is arranged on the adapter plate 500, and the limiting device 300 has a limiting hole 310, which is adapted to the surface pad 510, so that when the LPDDR5 chip is subsequently installed in the limiting hole 310, the LPDDR5 chip is connected to the surface pad 510, and the limiting hole 310 plays a role in limiting the LPDDR5 chip to prevent the LPDDR5 chip from shifting. Figure 3 As shown, in order to set the test pad 520, four protruding extension plates are arranged around the adapter plate 500, and the test pad 520 is evenly arranged on the extension plates. In order to avoid the test pad 520 being affected when the limit device 300 is set, the position of the limit device 300 corresponding to the test pad 520 is hollowed out, that is, a hollow portion 320 is provided, so that the test pad 520 is exposed. Figure 2 and Figure 5As shown, the four corners of the installation area 200 are provided with first positioning holes 220 , and the four corners of the limiting device 300 are provided with second positioning holes 330 . The positioning and fixation of the limiting device 300 are achieved through the first positioning holes 220 and the second positioning holes 330 .

[0028] Step S600: placing the LPDDR5 chip in the limiting hole 310; By placing the LPDDR5 chip in the limiting hole 310, the LPDDR5 chip is connected to the surface pad 510 of the adapter board 500, and the limiting hole 310 can prevent the position of the LPDDR5 chip from being offset.

[0029] Step S700: placing a pressing device 400 on the limiting device 300, pressing the LPDDR5 chip by the pressing device 400, so that the LPDDR5 chip is connected to the surface pad 510; like Figure 5 As shown, after the LPDDR5 chip is placed in the limiting hole 310 , although the LPDDR5 chip can contact the surface pad 510 , there will be poor contact. Therefore, it is necessary to press the LPDDR5 chip by the pressing device 400 to ensure a stable connection between the LPDDR5 chip and the surface pad 510 .

[0030] Step S800: The MT6877 platform 100 tests the LPDDR5 chip through the adapter board 500 to obtain a test result; Step S900: Connect the test pad 520 to an oscilloscope, and display the test waveform through the oscilloscope.

[0031] Specifically, after the MT6877 platform 100 tests the LPDDR5 chip through the adapter board 500, it can verify whether the LPDDR5 chip can read and write normally on the MT6877 platform. It should be noted that the MT6877 platform 100 is also provided with a serial port for connecting to a host computer, so as to display the test results through the host computer. At the same time, in order to obtain the waveform that the LPDDR5 chip needs to be tested, the corresponding test pad 520 is connected to an oscilloscope, and the various waveforms in the working process of the LPDDR5 chip can be displayed and measured through the oscilloscope, thereby realizing various signal tests on the LPDDR5 chip, such as testing whether the eye width and eye height of the eye diagram of the LPDDR5 chip meet the design standards, and testing whether the signal integrity of the LPDDR5 chip meets the requirements.

[0032] According to the chip testing method based on the MT6877 platform of an embodiment of the present invention, by designing the adapter board 500, in addition to being able to test whether the LPDDR5 chip can work normally on the MT6877 platform 100, the test pad 520 of the adapter board 500 can also be connected to an oscilloscope to obtain the waveforms of various signals of the LPDDR5 chip; by setting the limiting device 300 and the clamping device 400, the LPDDR5 chip can be limited, and the LPDDR5 chip can be connected to the adapter board 500. Therefore, there is no need to solder the LPDDR5 chip on the MT6877 platform 100, and the connection between the LPDDR5 chip and the MT6877 platform 100 can be achieved, making the installation and disassembly of the LPDDR5 chip more convenient.

[0033] Furthermore, if Figure 6 and Figure 7 As shown, in some embodiments of the present invention, the clamping device 400 includes: a base 410, a pressing block 420, a connecting rod 440 and a screwing block 430; wherein, a connecting column 450 is provided on the surface of the pressing block 420, the connecting column 450 is penetrated in the base 410, the pressing block 420 is located below the base 410, the screwing block 430 is provided on the surface of the base 410, the connecting rod 440 is provided in the base 410, one end of the connecting rod 440 is threadedly connected to the connecting column 450, and the other end of the connecting rod 440 is connected to the screwing block 430. The above-mentioned step S700: placing the clamping device 400 on the limiting device 300, pressing the LPDDR5 chip by the clamping device 400, and connecting the LPDDR5 chip to the surface pad 510, includes the following two steps: Step S710: placing the base 410 on the limiting device 300 so that the pressing block 420 is placed in the limiting hole 310; Step S720: Rotate the screw block 430 so that the connecting rod 440 drives the connecting column 450 and the pressing block 420 to press down, and the LPDDR5 chip is pressed by the pressing block 420.

[0034] When the screwing block 430 is rotated, the connecting rod 440 will be driven to rotate. Since the connecting rod 440 is threadedly connected to the connecting column 450, when the connecting rod 440 rotates, the connecting column 450 will be driven to descend. The connecting column 450 drives the pressing block 420 to press down, thereby pressing the LPDDR5 chip, so that the LPDDR5 chip is firmly connected to the surface pad 510.

[0035] Furthermore, if Figures 6 to 9As shown, in some embodiments of the present invention, a limiting member 460 is further provided between the screw block 430 and the base 410. The limiting member 460 is rotatably provided on the surface of the base 410. A limiting groove 462 is provided on the surface of the limiting member 460. A limiting column 431 is provided at the bottom of the screw block 430. The limiting column 431 is inserted into the limiting groove 462. A plurality of adjustment holes 461 are further provided on the side of the limiting member 460. The base 410 is provided with an elastic adjustment switch 470. The elastic adjustment switch 470 is provided with an adjustment block 471 adapted to the adjustment hole 461. The adjustment block 471 is located in one of the adjustment holes 461. The limiting member 460 is also provided with a through hole 463 so that the connecting rod 440 can pass through the through hole 463. The above-mentioned step S700: placing the pressing device 400 on the limiting device 300, pressing the LPDDR5 chip by the pressing device 400, and connecting the LPDDR5 chip to the surface pad 510, also includes the following three steps: Step S730: Obtain the thickness of the LPDDR5 chip; Step S740: Determine the maximum downward pressing stroke of the pressing block 420 according to the thickness of the LPDDR5 chip; Step S750: According to the maximum downward stroke, press the elastic adjustment switch 470 to make the adjustment block 471 leave the current adjustment hole 461 and rotate the limiting member 460 to make the corresponding adjustment hole 461 located at the adjustment block 471, release the elastic adjustment switch 470, so that the adjustment block 471 is placed in the corresponding adjustment hole 461.

[0036] It should be noted that, since the LPDDR5 chip is relatively fragile, if the pressing force of the pressing block 420 is large, it may cause damage to the LPDDR5 chip. Therefore, it is necessary to control the downward stroke of the pressing block 420 to ensure that the pressing block 420 can press the LPDDR5 chip tightly without causing damage to the LPDDR5 chip. To this end, the thickness of the LPDDR5 chip is first measured, and then the maximum downward stroke of the pressing block 420 is determined, and then the rotation stroke of the screw block 430 is limited by the limiting member 460. Since the surface of the limiting member 460 is provided with a limiting groove 462, and the bottom of the screw block 430 is provided with a limiting column 431, and the limiting column 431 is inserted in the limiting groove 462, the rotation stroke of the screw block 430 can be limited by rotating the position of the limiting groove 462. When the position of the limit slot 462 is to be changed, the elastic adjustment switch 470 is pressed to make the adjustment block 471 leave the current adjustment hole 461, and then the limit member 460 is rotated to place the limit slot 462 in the desired position, and then the elastic adjustment switch 470 is released to place the adjustment block 471 in the new adjustment hole 461, so as to fix the position of the limit member 460 and determine the rotation stroke of the screw block 430. Through the above design, it can be ensured that the pressing block 420 can press the LPDDR5 chip tightly without damaging the LPDDR5 chip, and the limit member 460 can be applied to chips of different models.

[0037] Further, in some embodiments of the present invention, a first magnetic member is disposed at the bottom of the base 410, and a second magnetic member matching the first magnetic member is disposed on the surface of the limiting device 300; or, the base 410 is disposed with a first threaded hole, and the limiting device 300 is disposed with a second threaded hole 350 matching the first threaded hole. The above-mentioned step S710: placing the base 410 on the limiting device 300 so that the pressing block 420 is placed in the limiting hole 310 includes: Step S711: placing the base 410 on the limiting device 300, and fixing the base 410 by the first magnetic attraction member and the second magnetic attraction member; Step S712: Alternatively, place the base 410 on the limiting device 300, and fix the base 410 by screwing screws into the first threaded hole and the second threaded hole.

[0038] In the present application, the connection method between the base 410 and the limiting device 300 can be magnetic or threaded. When the magnetic method is adopted, a first magnetic member is provided at the bottom of the base 410, and a second magnetic member is provided on the surface of the limiting device 300. The base 410 is fixed to the surface of the limiting device 300 by the cooperation of the first magnetic member and the second magnetic member. When the threaded connection method is adopted, the base 410 is provided with a first threaded hole, and the limiting device 300 is provided with a second threaded hole 350 that cooperates with the first threaded hole. The base 410 can be fixed to the limiting device 300 by screwing the screws into the first threaded hole and the second threaded hole. Through the above two methods, the detachable connection between the base 410 and the limiting device 300 is realized.

[0039] Further, in some embodiments of the present application, the above step 300: the step of leading the test point of the line routing to the surface of the adapter board and connecting it to the corresponding test pad 520, includes the following four steps: Step S310: Lead out the WCK differential signal, RDQS differential signal and two random data single-ended signals of each channel of the LPDDR5 chip as the first signal test point; Step S320: Lead out the clock differential signal of each channel of the LPDDR5 chip, two random CA signals, and two random CS signals as the second signal test point; Step S330: Lead out the VDDQ signal, VDD1 signal, VDD2H signal and VDD2L signal of the LPDDR5 chip as power supply test points; Step S340: Connect the first signal test point, the second signal test point and the power test point to corresponding test pads.

[0040] Specifically, in order to obtain the signal waveform of the LPDDR5 chip, it is necessary to select the key signals of the LPDDR5 chip as test points. In this example, the following signals are used as test points: For data lines: the WCK differential signal, RDQS differential signal and two random data single-ended signals of each channel of the LPDDR5 chip are brought out as the first signal test point; In terms of clock and address / control lines: the clock differential signal (CK), two random CA signals, and two random CS signals of each channel of the LPDDR5 chip are brought out as the second signal test point.

[0041] Power test point: Bring out the VDDQ, VDD1, VDD2H, and VDD2L of the LPDDR5 chip as power test points.

[0042] After selecting the above test points, all the test points are connected to the corresponding test pads 520 by routing. It should be noted that the WCK differential signal is the clock signal used for write operation in the LPDDR5 chip, that is, Write Clock, which is responsible for synchronizing the data transmission from the host to the LPDDR5 chip. The RDQS differential signal is a differential signal pair used for read operation in the LPDDR5 chip, which is used to synchronize the data transmission from the LPDDR5 chip to the host. The LPDDR5 chip achieves more efficient data transmission by introducing the WCK and RDQS signals. The combination of these two signals enables the LPDDR5 chip to achieve higher data transmission rates and better performance while maintaining low power consumption. The CA (Command / Address) signal is a signal used by the memory controller of the LPDDR5 chip to transmit commands, addresses, etc. to the memory device; the CS (Chip Select) signal is a signal used by the memory controller of the LPDDR5 chip to select a specific memory chip. In the LPDDR5 chip, there are usually multiple memory chips coexisting, and the CS signal is used to distinguish and control these chips. VDDQ, VDD1, VDD2H, and VDD2L are several voltage configuration interfaces of the LPDDR5 chip.

[0043] After selecting the first signal test point, the second signal test point and the power test point, the first signal test point, the second signal test point and the power test point also need to be connected to the ground test point as a basis to lead out the GND signal of the LPDDR5 chip as the ground test point. To this end, the above step 300: leading out the test point of the line routing to the surface of the adapter board 500 and connecting it to the corresponding test pad 520, also includes the following three steps: Step S350: GND ground holes are evenly arranged around the WCK differential signal, the RDQS differential signal, the data single-ended signal, the clock differential signal, the CA signal, the CS signal, the VDDQ signal, the VDD1 signal, the VDD2H signal and the VDD2L signal to achieve grounding; Step S360: Lead out the signal of the GND ground hole as a ground test point; Step S370 : connecting the ground test point to the corresponding test pad 520 .

[0044] It should be noted that for the traces that need to be tested, GND grounding treatment is used, and GND ground holes are evenly drilled around the signals to achieve the effect of signal shielding and reduce the crosstalk between high-speed signals.

[0045] like Figure 3As shown, in some embodiments of the present application, the signal test pad 522 corresponding to the first signal test point, the second signal test point and the power test point is designed as an elliptical pad, and the ground test pad 521 corresponding to the GND test point is designed as a rectangular pad design, which is convenient for the later test time division processing. It should be noted that the signal test pad 522 and the ground test pad 521 can also be designed as other shapes, as long as the shapes of the two are different. The differential signal (such as WCK differential signal, RDQS differential signal and clock differential signal, etc.) of the adapter board 500 is controlled within 100Ω impedance, the single-ended signal (such as data single-ended signal, CA signal, CS signal, etc.) is controlled within 50Ω impedance, and the power supply line (such as VDDQ signal, VDD1 signal, VDD2H signal, VDD2L signal, etc.) is kept at a line width of more than 12mil to maintain a good signal transmission rate and quality.

[0046] On the other hand, an embodiment of the present invention further provides an electronic device, including: A memory for storing program instructions; The processor is used to call the program instructions stored in the memory and execute the above-mentioned chip testing method based on the MT6877 platform according to the obtained program instructions.

[0047] The processor may be implemented by a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application; The memory can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device or a random access memory (RAM). The memory can store an operating system and other application programs. When the technical solution provided in the embodiments of this specification is implemented by software or firmware, the relevant program code is stored in the memory, and the processor calls and executes the shift control method of the bicycle electronic transmission in the embodiments of this application; the memory and the processor can be connected through a bus or the like.

[0048] On the other hand, an embodiment of the present invention further provides a storage medium, which is a computer-readable storage medium and stores a computer program. When the computer program is executed by a processor, the above-mentioned chip testing method based on the MT6877 platform is implemented.

[0049] As a non-transient computer-readable storage medium, the memory can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage devices. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and are implemented to be located in one place, or may also be distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0050] Although specific embodiments are described herein, those of ordinary skill in the art will recognize that many other modifications or alternative embodiments are also within the scope of the present disclosure. For example, any of the functions and / or processing capabilities described in conjunction with a particular device or component may be performed by any other device or component. In addition, although various exemplary implementations and architectures have been described according to embodiments of the present disclosure, those of ordinary skill in the art will recognize that many other modifications to the exemplary implementations and architectures described herein are also within the scope of the present disclosure.

[0051] Some aspects of the present disclosure are described above with reference to the block diagram and flow chart of the system, method, system and / or computer program product according to the exemplary embodiments.It should be understood that the combination of one or more blocks in the block diagram and the flow chart and the blocks in the block diagram and the flow chart can be realized by executing computer executable program instructions respectively.Equally, according to some embodiments, some blocks in the block diagram and the flow chart may not need to be executed in the order shown, or may not need to be executed in full.In addition, additional components and / or operations beyond those components and / or operations shown in the blocks in the block diagram and the flow chart may be present in certain embodiments.

[0052] Therefore, the blocks in the block diagrams and flow charts support the combination of devices for performing the specified functions, the combination of elements or steps for performing the specified functions, and the program instruction devices for performing the specified functions. It should also be understood that each block in the block diagrams and flow charts and the combination of blocks in the block diagrams and flow charts can be implemented by a special-purpose hardware computer system or a combination of special-purpose hardware and computer instructions that performs a specific function, element or step.

[0053] The program modules, applications, etc. described herein may include one or more software components, including, for example, software objects, methods, data structures, etc. Each such software component may include computer-executable instructions that, in response to execution, cause at least a portion of the functionality described herein (e.g., one or more operations of the illustrative methods described herein) to be performed.

[0054] Software components can be encoded with any of various programming languages. An exemplary programming language can be a low-level programming language, such as an assembly language associated with a specific hardware architecture and / or an operating system platform. The software component comprising assembly language instructions may need to be converted to executable machine code by an assembler before being executed by hardware architecture and / or platform. Another exemplary programming language can be a higher-level programming language, which can be transplanted across multiple architectures. The software component comprising a higher-level programming language may need to be converted to an intermediate representation by an interpreter or a compiler before execution. Other examples of programming languages ​​include but are not limited to macro languages, shells or command languages, job control languages, scripting languages, database queries or search languages ​​or report writing languages. In one or more exemplary embodiments, the software component comprising the instruction of one of the above-mentioned programming language examples can be directly executed by an operating system or other software components, without first being converted into another form.

[0055] Software components may be stored as files or other data storage structures. Software components of similar type or related functions may be stored together, such as in a specific directory, folder, or library. Software components may be static (e.g., preset or fixed) or dynamic (e.g., created or modified at execution time).

[0056] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in the relevant technical field without departing from the purpose of the present invention.

Claims

1. A chip testing method based on MT6877 platform, characterized in that: The method comprises the following steps: Acquire an MT6877 platform; the MT6877 platform is provided with an installation area, and the installation area is provided with a connection point; According to the layout of the LPDDR5 chip, an adapter board is designed; the number of layers of the adapter board is greater than two, the inner layer board of the adapter board is provided with circuit routing, the surface of the adapter board is provided with surface pads and test pads, the bottom surface of the adapter board is provided with bottom pads, and the surface pads are connected to the bottom pads through vias; Leading the test points of the line routing to the surface of the adapter board and connecting them to the corresponding test pads; Welding the adapter plate to the mounting area so that the bottom pad is connected to the connection point; A limiting device is arranged on the adapter plate; the limiting device is provided with a limiting hole adapted to the surface pad and a hollow portion adapted to the test pad; Placing the LPDDR5 chip in the limiting hole; A pressing device is placed on the limiting device, and the LPDDR5 chip is pressed by the pressing device to connect the LPDDR5 chip to the surface pad; The MT6877 platform tests the LPDDR5 chip through the adapter board to obtain a test result; The test pad is connected to an oscilloscope, and the test waveform is displayed by the oscilloscope.

2. The chip testing method based on the MT6877 platform according to claim 1, characterized in that: The clamping device comprises: a base, a pressing block, a connecting rod and a screwing block; wherein, a connecting column is arranged on the surface of the pressing block, the connecting column is penetrated in the base, the pressing block is located below the base, the screwing block is arranged on the surface of the base, the connecting rod is arranged in the base, one end of the connecting rod is threadedly connected to the connecting column, and the other end of the connecting rod is connected to the screwing block; the step of placing the clamping device on the limiting device, pressing the LPDDR5 chip by the clamping device, and connecting the LPDDR5 chip to the surface pad comprises: Placing the base on the limiting device so that the pressing block is placed in the limiting hole; The screw block is rotated to make the connecting rod drive the connecting column and the pressing block to press down, and the LPDDR5 chip is pressed tightly by the pressing block.

3. The chip testing method based on the MT6877 platform according to claim 2, characterized in that: A limiting member is also provided between the screw block and the base, the limiting member is rotatably provided on the surface of the base, the connecting rod is penetrated through the limiting member, a limiting groove is provided on the surface of the limiting member, a limiting column is provided at the bottom of the screw block, the limiting column is inserted into the limiting groove, a plurality of adjustment holes are also provided on the side of the limiting member, the base is provided with an elastic adjustment switch, the elastic adjustment switch is provided with an adjustment block adapted to the adjustment hole, and the adjustment block is located in one of the adjustment holes; the step of placing a pressing device on the limiting device, pressing the LPDDR5 chip by the pressing device, and connecting the LPDDR5 chip to the surface pad also includes: Obtaining the thickness of the LPDDR5 chip; Determining the maximum pressing stroke of the pressing block according to the thickness of the LPDDR5 chip; According to the maximum downward stroke, the elastic adjustment switch is pressed to make the adjustment block leave the current adjustment hole, and the limiting member is rotated to make the new adjustment hole located at the adjustment block, and the elastic adjustment switch is released to place the adjustment block in the new adjustment hole.

4. The chip testing method based on the MT6877 platform according to claim 2, characterized in that: The bottom of the base is provided with a first magnetic attraction member, and the surface of the limiting device is provided with a second magnetic attraction member that matches the first magnetic attraction member; or, the base is provided with a first threaded hole, and the limiting device is provided with a second threaded hole that matches the first threaded hole; the step of placing the base on the limiting device includes: Placing the base on the limiting device, and fixing the base by the first magnetic attraction member and the second magnetic attraction member; Alternatively, the base is placed on the limiting device, and screwed into the first threaded hole and the second threaded hole to fix the base.

5. The chip testing method based on the MT6877 platform according to claim 1, characterized in that: The step of leading the test point of the line routing to the surface of the adapter board and connecting it to the corresponding test pad includes: Lead out the WCK differential signal, RDQS differential signal and two random data single-ended signals of each channel of the LPDDR5 chip as the first signal test point; Lead out the clock differential signal, two random CA signals and two random CS signals of each channel of the LPDDR5 chip as the second signal test point; Lead out the VDDQ signal, VDD1 signal, VDD2H signal and VDD2L signal of the LPDDR5 chip as power supply test points; The first signal test point, the second signal test point and the power supply test point are all connected to the corresponding test pads.

6. The chip testing method based on the MT6877 platform according to claim 5, characterized in that: The step of leading the test points of the line routing to the surface of the adapter board and connecting them to the corresponding test pads also includes: GND ground holes are evenly arranged around the WCK differential signal, the RDQS differential signal, the data single-ended signal, the clock differential signal, the CA signal, the CS signal, the VDDQ signal, the VDD1 signal, the VDD2H signal and the VDD2L signal to achieve ground package setting; Lead out the signal of the GND ground hole as a ground test point; Connect the ground test point to the corresponding test pad.

7. The chip testing method based on the MT6877 platform according to claim 5, characterized in that: The test pad includes a signal test pad and a ground test pad, the first signal test point, the second signal test point and the power test point are respectively connected to the corresponding signal test pads, the ground test point is connected to the ground test pad, and the shape of the signal test pad is different from that of the ground test pad.

8. The chip testing method based on the MT6877 platform according to claim 5, characterized in that: The signal impedance of the WCK differential signal, the RDQS differential signal, and the clock differential signal is lower than 100Ω, the signal impedance of the data single-ended signal, the CA signal, and the CS signal is lower than 50Ω, and the routing width of the VDDQ signal, the VDD1 signal, the VDD2H signal, and the VDD2L signal is greater than 12 mil.

9. An electronic device, characterized in that: include: A memory for storing program instructions; A processor is used to call the program instructions stored in the memory, and execute the chip testing method based on the MT6877 platform according to any one of claims 1-8 according to the obtained program instructions.

10. A storage medium, characterized in that: The storage medium stores computer executable instructions, and the computer executable instructions are used to enable a computer to execute the chip testing method based on the MT6877 platform according to any one of claims 1 to 8.

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