Method for producing improved SiC substrates and SiC epitaxial layers

Abstract

The present invention relates to a method for manufacturing a silicon carbide (SiC) substrate, the method comprising at least the following steps: a) providing a SiC substrate, the SiC substrate being suitable for growing a SiC epitaxial layer thereon; and b) implanting a Group Va element into the SiC substrate by irradiating at least a portion of the SiC substrate with a Group Va ion, wherein the irradiation is performed at an energy greater than or equal to 100 keV and less than or equal to 200 keV and an irradiation dose greater than or equal to 105 cm <-2 > and less than or equal to 1010 cm <-2 >. Further, the present invention relates to a method for manufacturing a silicon carbide epitaxial layer, a SiC substrate, and a semiconductor device.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a silicon carbide (SiC) substrate and a SiC epitaxial layer located on top of such a substrate, wherein the substrate is modified to capture transition metals (TM). In addition, the present invention further relates to the modified SiC substrate itself and a semiconductor device comprising the SiC substrate. Background Art

[0002] The quality of semiconductor devices is crucial for the functionality and lifetime of state-of-the-art electronics. Especially in the area of ​​epitaxially grown SiC layers, impurities must be avoided, as such impurities can impair the structural and electronic properties of the semiconductor layers. Such defects are particularly detrimental for semiconductor layers that are processed for high voltage (HV) applications. One source of unwanted impurities introduced in processes and layers is TM. TM is typically present in the crucible material and can be incorporated into the SiC ingot or SiC substrate during bulk growth. After substrate preparation, such impurities can diffuse into the final epilayer during homoepitaxy of the epilayer. It is well known that transition metal impurities form deep energy levels in the bandgap of SiC, which can impair the functionality of the device. As a function of the crucible material and the overall processing conditions, the TM concentration in the epilayer can range from 10 13 cm -3 Up to 10 14 cm -3 The presence of such TM in the epitaxial layer poses a serious problem for the manufacture of HV devices, because in HV applications the epitaxial layer is only lightly doped (<10 14 cm -3 ). Therefore, it is important to reduce the TM concentration in the epitaxial layer or to passivate the TM in advance.

[0003] In addition, patent literature discloses suitable means for treating impurities in SiC semiconductor devices. For example, US9508802B2 discloses a process for producing semiconductor devices. The process includes forming a SiC epitaxial layer on a SiC substrate; injecting ions into the epitaxial layer; forming a doping layer having a defect density higher than that of the SiC substrate; and heat treating the epitaxial layer. The semiconductor device includes a SiC substrate, a SiC epitaxial layer formed on the SiC substrate, and a doping layer having a defect density higher than that of the SiC substrate. This method is based on the injection of He into the epitaxial layer. After high temperature treatment, the He-injected region will serve as a doping layer for diffusing TM. The disadvantage of this method is that the injection of the epitaxial layer will produce more electrically active defects, which in turn will affect the electronic properties of the finished HV device in terms of leakage current, minority carrier lifetime and on-resistance. Summary of the invention

[0004] Therefore, the object of the present invention is to provide a solution for improving the quality and performance of SiC epilayers, in particular by reducing the concentration of TM incorporated in the SiC epilayers during processing. In particular, the object of the present invention is to avoid or reduce the disadvantages of the known solutions.

[0005] The objects of the invention are solved by the features of the independent claims. Preferred embodiments are specified in the dependent claims.

[0006] Therefore, the object is solved by a method for producing a silicon carbide (SiC) substrate, the method comprising at least the following steps:

[0007] a) providing a SiC substrate, wherein the SiC substrate is suitable for growing a SiC epitaxial layer thereon; and

[0008] b) implanting a Va group element into the SiC substrate by irradiating at least a portion of the SiC substrate with Va group ions, wherein the irradiation is performed at an energy greater than or equal to 100 keV and less than or equal to 200 keV and a current greater than or equal to 10 5 cm -2 and less than or equal to 10 10 cm -2 of radiation dose.

[0009] In other words, specifically, the present invention proposes a method for manufacturing a silicon carbide (SiC) substrate. The SiC substrate is generally used as a basis for growing a structurally defined SiC epitaxial layer thereon. The material and structure are used as semiconductors in high-voltage and / or high-temperature applications. The substrate may be in the form of an ingot or a wafer. In the case of using an ingot, a wafer may be cut from the ingot in a subsequent step to produce a wafer. In the case where the substrate is in the form of a wafer, the wafer size may be customized according to special needs. Standard wafer thicknesses and diameters may be used in the process of the present invention. For example, the substrate thickness may be in the range of 10–400 μm. A suitable substrate diameter may be in the range of 1 cm to 10 cm. Typical ingot sizes are in the range of 10 cm to 20 cm.

[0010] The method comprises step a). In this step, a SiC substrate is provided, wherein the SiC substrate is suitable for growing a SiC epitaxial layer thereon. This means that the substrate is suitable for providing the necessary features so that a structurally coherent and defined SiC epitaxial layer is deposited thereon in a subsequent step. The defined SiC epitaxial layer may be, for example, a 2H-SiC, 4H-SiC or 6H-SiC epitaxial layer. 4H-SiC and 6H-SiC epitaxial layers are preferred. The substrate may be, for example, a seeded substrate, wherein a special seed layer is included on the top of the substrate. The seed layer may also be deposited after forming the substrate of the present invention. If a suitable epitaxial layer can be formed on the substrate using a high temperature chemical vapor deposition technique or any other technique for realizing a structurally well-defined epitaxial layer, the substrate is particularly suitable for growth.

[0011] In addition, the method includes a step b) of injecting a Va group element into the SiC substrate by irradiating at least a portion of the SiC substrate with Va group ions. The substrate is modified by doping the Va group element into the SiC substrate. The Va group element is an element of the fifth main group in the periodic system of elements, i.e., N, P, As, Sb, Bi. The elements N, P and As are preferred. The implantation or doping can be performed, for example, by accelerating the element in particle form and bombarding the substrate with the accelerated particles. These elements can be dynamically incorporated into the substrate, for example, by irradiation. The appropriate implantation of the Va group element can be based on the doping of the corresponding ions, wherein the Va ions are accelerated by an electric accelerator and directed to the substrate surface.

[0012] The irradiation in step b) is performed with an energy greater than or equal to 100 keV and less than or equal to 200 keV and a wavelength greater than or equal to 10 5 cm -2 and less than or equal to 10 10 cm -2 The overall irradiation conditions in the form of energy and dose are selected in order to achieve a certain Va implantation level in the substrate. The irradiation parameters are chosen in particular so as to enable the creation of carbon vacancies (VC) in the substrate without changing the electrical properties of the substrate. Therefore, the irradiation or implantation process is not intended to specifically influence the resistivity or conductivity of the substrate. Such a change cannot be achieved at the specified dose and energy level. Higher doses and / or higher energy levels may lead to unwanted changes in the electrical substrate properties, wherein in particular the resistivity of the substrate may be affected.

[0013] By means of the present invention and by means of the aspects described in the present application, an improved SiC substrate is provided, wherein the substrate is capable of trapping TM metals at VC sites by forming transition metal VC (TM-VC) complexes. It is well known that transition metals act as acceptors, especially in n-type 4H-SiC. Therefore, it is suggested to use carbon vacancies that are capable of effectively binding to transition metals. VC-TM complexes are easy to form and are energetically stable. By this method, a TM doping / passivation layer is formed in or by the substrate before epitaxial layer growth. In this way, the final device will not be affected by further ion beam treatment. The implantation will result in the formation of VC, but the resistivity of the substrate will not be affected due to the presence of the implanted Va group elements. The proposed implantation characteristics are suitable for achieving a suitable VC concentration in the substrate. The VC concentration achieved by these ranges will not affect the resistivity of the substrate. In addition, the dose is below the amorphization level of the crystal, so high temperature post-implantation treatment is not required.

[0014] TM gettering is done in the substrate without compromising the crystal structure of the deposited epilayer. This leaves the epilayer structurally intact and produces better physical characteristics. The TM-VC complex is energetically very stable, effectively hindering the outward diffusion of TM from the substrate into the epilayer during homoepitaxial growth.

[0015] This solution is more preferred than using an additional buffer layer, since the buffer layer has to be grown in a separate step, whereas the trapping proposed in the present invention is performed by implantation. This implanted layer is much less doped than the highly doped buffer layer, resulting in unchanged electrical properties of the substrate. The high doping of the buffer layer also results in faster TM diffusion, since the Fermi level of the buffer layer is close to the conduction band. This means that the formation energy of the TM in such a buffer layer will be reduced, which will also affect the migration and diffusion energies.

[0016] The proposed solution therefore comprises several benefits compared to buffer layers known in the art.

[0017] The object is further solved by a method for producing a silicon carbide (SiC) epitaxial layer on a SiC substrate, the method comprising at least the following steps:

[0018] a) providing a SiC substrate, wherein the SiC substrate is suitable for growing a SiC epitaxial layer thereon;

[0019] b) implanting a Va group element into the SiC substrate by irradiating at least a portion of the SiC substrate with Va group ions, wherein the irradiation is performed at an energy greater than or equal to 100 keV and less than or equal to 200 keV and a current greater than or equal to 10 5 cm -2 and less than or equal to 1010 cm -2 irradiation dose; and

[0020] c) epitaxially growing a SiC epitaxial layer on top of the SiC substrate obtained in method step b), wherein the growth is performed at a temperature greater than or equal to 1200° C. and less than or equal to 1500° C.

[0021] This method can be considered as a method for producing a final product, wherein the previously described method can be considered as a method for producing an intermediate product. The difference can be seen in the last method step c), in which the epitaxial layer is produced.

[0022] Surprisingly, it has been found that if the epilayer is grown under the conditions defined above, the diffusion of TM out of the substrate is very low, resulting in an improved epilayer. In particular the structural and electrical properties of the epilayer are superior to the standard, so that the SiC epilayer comprises a long life span. With regard to further benefits of the method for producing a SiC epilayer, in particular the method for producing a SiC substrate is mentioned. Higher temperatures in method step b) may be disadvantageous, since in this case TM may diffuse into the epilayer. Lower temperatures may be disadvantageous, since the growth of the epilayer may be hindered.

[0023] The object is further solved by a SiC substrate, wherein the SiC substrate comprises carbon vacancies (VC) and transition metal VC complexes, wherein the sum of the concentrations of VC and transition metal VC complexes is greater than or equal to 10 12 cm -3 and less than or equal to 10 16 cm -3 . The sum of VC and TM-VC complexes in the substrate can be evaluated by electron spin resonance (ESR) experiments. Both substances have clear and unique ESR signatures and can be quantitatively measured. The concentrations of VC and transition metal VC complexes can be evaluated separately, and the two concentrations are added to obtain the sum. The substrate may be in the form of a regular or irregular shaped ingot, or the substrate may be in the form of a flat disk, plate or wafer. Plate-like means that the shape is flat and / or extends at least substantially toward two dimensions in three dimensions. The plate may be flat in one direction, but is substantially elongated in two directions, and all three directions are perpendicular to each other. Specifically, each of the width and length of the plate is at least 2 times, 5 times, 10 times, 50 times, 100 times or more larger than the thickness to be considered to have a plate-like shape. The advantages of the SiC substrate according to the present invention are discussed above in the context of the method for manufacturing the SiC substrate of the present invention.

[0024] In addition, the purpose is further solved by a semiconductor device, which includes a SiC substrate and an epitaxial layer located thereon, wherein the SiC substrate is a SiC substrate according to the present invention. In particular, semiconductor devices may benefit from improved SiC substrates. The device may include better electronic characteristics and may show better life. This benefit is achieved by controlling and reducing the TM content in the epitaxial layer of the device. The semiconductor device may be, for example, a thyristor, a diode, a gate turn-off thyristor, a power metal insulator semiconductor field effect transistor, a power metal oxide semiconductor field effect transistor, a junction field effect transistor, a bipolar junction transistor, an insulated gate bipolar transistor or an integrated gate commutated thyristor. The advantages of the semiconductor device according to the present invention are discussed above in the context of a method for manufacturing a SiC substrate of the present invention and a SiC substrate.

[0025] In a first preferred embodiment of the method for producing a SiC substrate, in an additional method step b'), the SiC substrate obtained in method step b) is subjected to a heat treatment at a temperature greater than or equal to 1000° C. and less than or equal to 1700° C. for a period of greater than or equal to 5 h and less than or equal to 24 h. The heat treatment of the substrate under the above-mentioned conditions enables the substrate to be equilibrated and accelerates the formation of TM-VC complexes in case TM is already present in the substrate. This step may reduce the amount of diffusible TM in the substrate. Preferably, this annealing step may be carried out at a temperature greater than or equal to 1100° C. and less than or equal to 1600° C. for a period of greater than or equal to 8 h and less than or equal to 20 h, furthermore, this annealing step may be carried out at a temperature greater than or equal to 1200° C. and less than or equal to 1400° C. for a period of greater than or equal to 10 h and less than or equal to 18 h. By this annealing, preferably, a uniform distribution of Va ions and VC is produced throughout the substrate. With a concentration difference of less than 10 mol% / cm 3 In the case of , the distribution is uniform throughout the substrate. Using EPR, the concentration can be quantitatively determined as a function of position within the substrate.

[0026] In a second preferred embodiment of the method for manufacturing a SiC substrate, in step b), carbon vacancies (VC) are generated in the substrate, wherein the VC concentration in the substrate is greater than or equal to 10 13 cm -3 and less than or equal to 10 17 cm -3It has been found that this VC concentration can be used to trap sufficient TM in the substrate and largely avoid the possibility of TM diffusion into the epitaxial layer during epitaxial growth. Lower concentrations may be disadvantageous because insufficient complexes with TM may be formed. Higher concentrations may also be disadvantageous because the electrical characteristics of the substrate may be significantly affected. In addition, the VC concentration in the substrate may be greater than or equal to 10 14 cm -3 and less than or equal to 10 16 cm -3 .

[0027] In a third preferred embodiment of the method for manufacturing a SiC substrate, the Va group ions are selected from the group consisting of nitrogen ions, phosphorus ions, or mixtures thereof. It has been found that implanting N ions and P ions into the substrate helps to reliably produce the necessary VC concentration in various substrates without changing the electronic properties of the substrate.

[0028] In a fourth preferred embodiment of the method for manufacturing a SiC substrate, the resistivity of the SiC substrate after step b) is changed to less than 10% compared to the resistivity of the SiC substrate in step a). One of the main advantages of the above method is that the resistivity of the substrate is substantially unchanged due to the implantation of Va group ions and by generating VC. In a preferred embodiment, the resistivity of the SiC substrate after step b) is changed to less than 8% compared to the resistivity of the SiC substrate in step a), and further preferably, the resistivity of the SiC substrate after step b) is changed to less than 5% compared to the resistivity of the SiC substrate in step a). The resistivity of the substrate is evaluated at 20° C. according to methods known to those skilled in the art, such as, for example, a four-point probe method with removable graphite contacts.

[0029] In a fifth preferred embodiment of the method for manufacturing a SiC substrate, the implantation density of Va group ions in the SiC substrate is greater than or equal to 10 10 cm -3 and less than or equal to 10 16 cm -3 It has been found that implanting such Va group ions into the SiC substrate helps to produce an optimal VC concentration in the substrate. The overall electrical and structural characteristics of the substrate remain essentially unchanged. In addition, the density of Va group ions in the SiC substrate is greater than or equal to 10 11 cm -3 and less than or equal to 10 15 cm -3 , and further preferably, the density of Va group ions in the SiC substrate may be greater than or equal to 10 12 cm -3 and less than or equal to 10 14 cm -3It is further preferred that the implantation is uniform across the substrate.

[0030] In a sixth preferred embodiment of the method for manufacturing a SiC substrate, the SiC substrate in method step a) and method step b) comprises n-type conductivity. In particular, for a substrate comprising n-type conductivity, the method according to the present invention can lead to very efficient VC generation and TM complexation. In addition, the formed TM-VC complex is very stable, and an epitaxial layer can be grown on a TM-free substrate.

[0031] In a seventh preferred embodiment of the method for manufacturing a SiC substrate, step b) is performed at a temperature greater than or equal to 20° C. and less than or equal to 800° C. This temperature range in the Va implantation and VC generation steps can result in a reasonably uniform VC distribution in the substrate.

[0032] In a first preferred embodiment of the method for producing a SiC epitaxial layer, after method step b) and before method step c), the SiC substrate is heat treated at a temperature greater than or equal to 1000° C. and less than or equal to 1900° C. for a period of greater than or equal to 0.5 h and less than or equal to 24 h. In order to achieve a safe and reproducible TM complexation in the substrate before epitaxial growth, it has been found useful to anneal the substrate under the conditions given above. The structure of the substrate is not changed, but it is presumed that the TM is trapped due to diffusion processes. Non-diffusible complexes are produced. These complexes are quite stable and these complexes do not interact with the epilayer grown in step c). As a result, a TM-free or TM-reduced epilayer is obtained, which exhibits better electronic properties and a longer lifetime.

[0033] In a second preferred embodiment of the method for manufacturing a SiC epitaxial layer, the thickness of the SiC epitaxial layer is greater than or equal to 50 μm and less than or equal to 250 μm. The method for manufacturing a SiC epitaxial layer is particularly suitable for producing an epitaxial layer of the thickness depicted above. The epitaxial layer is particularly suitable for high voltage applications, and based on the fact that the TM is firmly captured in the substrate, the epitaxial layer shows significant lifetime and uniform electrical properties. In addition, the thickness of the SiC epitaxial layer may be greater than or equal to 60 μm and less than or equal to 200 μm, and further preferably, the thickness of the SiC epitaxial layer may be greater than or equal to 80 μm and less than or equal to 50 μm.

[0034] In a first preferred embodiment of the semiconductor device, the epitaxial layer is an n-type 4H-SiC epitaxial layer. In particular, the n-type 4H-SiC epitaxial layer can benefit from the reduction of the TM concentration in the epitaxial layer.

[0035] In a second preferred embodiment of the semiconductor device, the epitaxial layer has a thickness greater than or equal to 50 μm and less than or equal to 200 μm. The advantages of semiconductor devices comprising epitaxial layers having such a thickness range have been discussed in the context of epitaxial layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.

[0037] In the attached picture:

[0038] Figure 1 A preferred embodiment of a method for manufacturing a silicon carbide (SiC) substrate according to the present invention is shown;

[0039] Figure 2 A preferred embodiment of the method for manufacturing a silicon carbide epitaxial layer on a SiC substrate according to the present invention is shown. DETAILED DESCRIPTION

[0040] The description contains procedural or methodological aspects describing the structural features of the claimed invention; in this way, the structural features can be well understood. It is emphasized to the reader that such structural features can be separated from the described context without hesitation, or separated from the intermediate generalization issues used to form various aspects of the present invention. It is also emphasized to the reader that any structural feature described below can be understood as a single aspect of the present invention to distinguish it from known solutions, although it may be separated from the context.

[0041] exist Figure 1, a process for manufacturing a SiC substrate 1 is shown in . The provided substrate 1 may be in the form of an ingot, a wafer or a plate. A plate-like geometry is depicted in this figure. The SiC substrate 1 contains a transition metal 2. TM 2 is distributed within the SiC substrate 1. In the next process step, method step b), the SiC substrate 1 is irradiated with a Va group element. The Va group element may be in the form of particles or ions. Preferably, the Va group element is provided in the form of ions, and the ions are accelerated and kinetically implanted into the SiC substrate 1. The implantation of Va ions into the SiC substrate 1 results in the formation of carbon vacancies VC 3. The SiC substrate 1 may be annealed at a higher temperature in a separate method step. The annealing results in the diffusion of VC 3 and TM 2, and the formation of a positionally stable TM-VC complex 4. The TM-VC complex 4 remains trapped at the formation site and is no longer able to diffuse into the entire SiC substrate 1. By using this method step, a SiC substrate 1 containing less mobile TM 2 is produced. The SiC substrate 1 may be stored for further processing. Furthermore, the SiC substrate 1 can be used immediately to epitaxially grow an epitaxial layer 5 on the substrate 1. The epitaxial growth of the epitaxial layer 5 can be carried out according to methods known to those skilled in the art. By including this separate method step, a SiC epitaxial layer 5 is produced on the SiC substrate 1, wherein the SiC epitaxial layer 5 does not contain TM 2. Typically, the total concentration of diffusible TM 2 is greatly reduced. By using this method, an epitaxial layer 5 for high voltage applications can be produced. The epitaxial layer 5 can, for example, be a 4-H SiC epitaxial layer.

[0042] exist Figure 2, a process for producing a SiC epitaxial layer 5 on a SiC substrate 1 is shown. The provided substrate 1 may be in the form of an ingot or a wafer or a plate. In this figure, a plate-like geometry is used. The SiC substrate 1 contains a transition metal 2. TM 2 is distributed within the SiC substrate 1. In the next process step, i.e., method step b), the SiC substrate 1 is irradiated with a Va group element. The Va group element may be in the form of particles or ions. Preferably, the Va group element is provided in the form of ions, and the ions are accelerated and kinetically implanted into the SiC substrate 1. The implantation of Va ions into the SiC substrate 1 results in the formation of carbon vacancies 3. Such a SiC substrate 1 can be used for the next method step, in which an epitaxial layer 5 is grown onto the surface of the SiC substrate 1. During the growth of the epitaxial layer 5, TM 2 diffuses through the SiC substrate 1 and is trapped at VC 3. It is depicted in this figure that there is still one diffusible TM 2 that is not bound by VC 3. The remaining TM 2 is converted into a thermodynamically and positionally stable TM-VC complex 4. The TM-VC complex 4 remains in the SiC substrate 1 and does not diffuse into the epitaxial layer 5 during epitaxial growth. This can reduce the TM2 load of the epitaxial layer 5 and improve the electronic characteristics and structural characteristics of the epitaxial layer 5. The epitaxial growth of the epitaxial layer 5 can be carried out according to methods known to those skilled in the art. By using this method, an epitaxial layer 5 for high voltage applications can be produced. The epitaxial layer 5 can, for example, be a 4-H SiC epitaxial layer.

[0043] A possible method sequence may include providing a SiC substrate 1, wherein the SiC substrate 1 comprises a thickness of 350 μm. The SiC substrate 1 is formed by 10 18 cm -3 The concentration is N-doped and includes about 10 14 cm -3 The TM concentration of the Va group element is implanted in process step b). The implantation is carried out by applying N ions at RT. 7 cm -2 The dose is 100 keV and the implant energy is 100 keV. Using these parameters, approximately 3 × 10 14 cm -3 VC, where the implanted N concentration is about 10 12 cm -3 An additional annealing step is carried out at 1200° C. for 10 h. In this step, the Vc-TM complex 4 is formed. In the next step, a 100 μm 4H-SiC epitaxial layer 5 is grown (N about 10 14 cm -3). No TM 2 was found in the epitaxially grown layer 5. Furthermore, the resistivity of the epitaxial layer 5 was not impaired. The device can now be formed. The anode is formed by Al implantation followed by annealing at 1700°C for 30 min. By RIE, the mesa is formed and the ohmic metal is deposited and a 10 kV pin diode is fabricated.

[0044] List of Reference Numerals

[0045] 1 SiC substrate

[0046] 2 Transition Metals (TM)

[0047] 3 Carbon vacancies (VC)

[0048] 4 Transition metal-carbon vacancy (TM-VC) complexes

[0049] 5 Epitaxial layer

Claims

1. A method for manufacturing a silicon carbide (SiC) substrate (1), the method comprising at least the following steps: a) providing the SiC substrate (1), wherein the SiC substrate (1) is suitable for growing a SiC epitaxial layer (5) thereon; and b) implanting a Va group element into the SiC substrate (1) by irradiating at least a portion of the SiC substrate (1) with Va group ions, wherein the irradiation is performed at an energy greater than or equal to 100 keV and less than or equal to 200 keV and a voltage greater than or equal to 10 5 cm -2 and less than or equal to 10 10 cm -2 of radiation dose.

2. The method according to the preceding claim, wherein: In an additional method step b'), the SiC substrate (1) obtained in method step b) is heat treated at a temperature greater than or equal to 1000° C. and less than or equal to 1700° C. for a period of greater than or equal to 5 h and less than or equal to 24 h.

3. The method according to one of the preceding claims, wherein: In step b), carbon vacancies (VC) (3) are generated in the substrate (1), wherein the concentration of the VC (3) in the substrate (1) is greater than or equal to 10 13 cm -3 and less than or equal to 10 17 cm -3 .

4. The method according to one of the preceding claims, wherein: The Va group ions are selected from the group consisting of nitrogen ions, phosphorus ions, or mixtures thereof.

5. The method according to one of the preceding claims, wherein: After step b), the resistivity of the SiC substrate (1) is changed to less than 10% compared with the resistivity of the SiC substrate (1) in step a).

6. The method according to one of the preceding claims, wherein: The implantation density of the Va group ions in the SiC substrate (1) is greater than or equal to 10 10 cm -3 and less than or equal to 10 16 cm -3 .

7. The method according to one of the preceding claims, wherein: The SiC substrate (1) in method step a) and method step b) comprises n-type conductivity.

8. The method according to one of the preceding claims, wherein: Step b) is performed at a temperature greater than or equal to 20°C and less than or equal to 800°C.

9. A method for producing a silicon carbide (SiC) epitaxial layer (5) on a SiC substrate (1), the method comprising at least the following steps: a) providing the SiC substrate (1), wherein the SiC substrate (1) is suitable for growing a SiC epitaxial layer (5) thereon; b) implanting a Va group element into the SiC substrate (1) by irradiating at least a portion of the SiC substrate (1) with Va group ions, wherein the irradiation is performed at an energy greater than or equal to 100 keV and less than or equal to 200 keV and a voltage greater than or equal to 10 5 cm -2 and less than or equal to 10 10 cm -2 irradiation dose; and c) epitaxially growing a SiC epitaxial layer (5) on top of the SiC substrate (1) obtained in method step b), wherein the growth is performed at a temperature greater than or equal to 1200° C. and less than or equal to 1500° C.

10. The method according to claim 9, wherein: After the method step b) and before the method step c), the SiC substrate (1) is heat treated at a temperature greater than or equal to 1000° C. and less than or equal to 1900° C. for a period of time greater than or equal to 0.5 h and less than or equal to 24 h.

11. The method according to claim 9, wherein: The thickness of the SiC epitaxial layer (5) is greater than or equal to 50 μm and less than or equal to 250 μm.

12. A SiC substrate (1), wherein the SiC substrate (1) comprises carbon vacancies (V C ) and transition metal V C Complex (4), wherein the V C (3) With the transition metal V C The sum of the concentrations of complex (4) is greater than or equal to 10 12 cm -3 and less than or equal to 10 16 cm -3 .

13. A semiconductor device comprising a SiC substrate (1) and an epitaxial layer (5) located thereon, wherein the SiC substrate (1) is the SiC substrate (1) according to claim 12.

14. The semiconductor device according to claim 13, wherein: The epitaxial layer (5) is an n-type 4H-SiC epitaxial layer.

15. The semiconductor device according to claim 13 , wherein: The thickness of the epitaxial layer (5) is greater than or equal to 50 μm and less than or equal to 200 μm.

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