Chip packaging method, chip packaging structure and electronic equipment
By replacing the photoresist layer with high structural strength in semiconductor chip package, the problem of the circuit diagram forming a lack of fineness and electroplating collapse after the semiconductor process feature size is reduced, and electrode traces with higher precision and reliability are achieved.
Patent Information
- Application Number
- CN202411848190.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-16
- Publication Date
- 2025-03-28
AI Technical Summary
With the shrinking of the feature size of semiconductor processes, it is difficult for the prior art to achieve more refined circuit diagram formation, and the increase in the aspect ratio of the photoresist layer leads to an increase in the risk of collapse during the electroplating process, affecting the fineness of the electrode trace.
The photoresist layer is replaced by a first hard mask layer, and a first hard mask layer is made on the side where the dielectric layer is away from the first carrier plate, and an electrode trace is formed in its through holes, thereby obtaining a rewiring layer composed of the electrode trace, the dielectric layer and the first hard mask layer. The height-to-face ratio of the first hard mask layer is 3 to 5, which has a higher structural strength and reduces the risk of collapse during the electroplating process.
It effectively reduces the risk of collapse caused by excessive height-to-wide ratio of the photoresist layer during electroplating, improves the precision of the electrode wiring pattern, and ensures high quality and reliability of the chip packaging.
Smart Images
Figure CN119725118A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a chip packaging method, a chip packaging structure and an electronic device. Background Art
[0002] As the feature size of semiconductor processes continues to shrink, how to achieve more sophisticated circuit diagrams has become a technical problem that people in this field urgently need to solve. Summary of the invention
[0003] In order to at least overcome the above-mentioned deficiencies in the prior art, the purpose of the present application is to provide a chip packaging method, a chip packaging structure and an electronic device.
[0004] In a first aspect, an embodiment of the present application provides a chip packaging method, the chip packaging method comprising:
[0005] Providing a first carrier board, and bonding a prefabricated chip layer to one side of the first carrier board layer, wherein the chip layer includes at least one chip and a plastic packaging layer encapsulating the chip, and the electrode pins of the chip face toward a side away from the first carrier board;
[0006] A dielectric layer is formed on a side of the chip layer away from the first carrier, wherein the dielectric layer includes a first through hole exposing the electrode pins of the chip;
[0007] Making a first hard mask layer on a side of the dielectric layer away from the first carrier, the first hard mask layer comprising a second through hole exposing the first through hole, and the aspect ratio of the first hard mask layer is 3-5;
[0008] Electrode wiring is formed in the first through hole and the second through hole to obtain a redistribution layer consisting of the electrode wiring, the dielectric layer and the first hard mask layer.
[0009] In a possible implementation manner, the step of forming a first hard mask layer on a side of the dielectric layer away from the first carrier includes:
[0010] Making a hard material layer on a side of the dielectric layer away from the first carrier board;
[0011] A first photoresist layer is formed on a side of the hard material layer away from the first carrier, and the hard material layer is patterned based on the first photoresist layer to form a second through hole exposing the first through hole, thereby obtaining a first hard mask layer, wherein the thickness of the first photoresist layer is not greater than the thickness of the hard material layer.
[0012] In a possible implementation, the first photoresist layer includes a stacked first photoresist sublayer and a second photoresist sublayer, the first photoresist layer is formed on a side of the hard material layer away from the first carrier, and the hard material layer is patterned based on the first photoresist layer to form a second through hole exposing the first through hole, and the step of obtaining the first hard mask layer includes:
[0013] Coating a first photosensitive material on a side of the hard material layer away from the first carrier to form a first photoresist sublayer;
[0014] Coating a second photosensitive material on a side of the first photoresist sublayer away from the first carrier to form a second photoresist sublayer, wherein the first photosensitive material is different from the second photosensitive material;
[0015] Developing and exposing the second photoresist sublayer to form a first photoresist opening on the second photoresist sublayer, and developing and exposing the first photoresist sublayer to form a second photoresist opening on the first photoresist sublayer, wherein the second photoresist opening overlaps with the first photoresist opening, and an orthographic projection of the first photoresist opening on the first carrier covers an orthographic projection of the first through hole on the first carrier;
[0016] The hard material layer is patterned based on the first photoresist opening and the second photoresist opening to form a second through hole exposing the first through hole, thereby obtaining a first hard mask layer.
[0017] In a possible implementation, after the step of forming a dielectric layer on a side of the chip layer away from the first carrier, the method further includes a step of forming a seed layer, which includes:
[0018] Performing metal sputtering on the dielectric layer to form a seed layer on a side of the dielectric layer away from the first carrier plate and on an inner wall of the first through hole;
[0019] The step of forming electrode wiring in the first through hole and the second through hole to obtain a redistribution layer consisting of the electrode wiring, the dielectric layer and the first hard mask layer includes:
[0020] The dielectric layer on which the first hard mask layer is made is electroplated, and electrode traces are formed in the first through hole and the second through hole based on the seed layer exposed by the first through hole and the second through hole, so as to obtain a redistribution layer consisting of the electrode traces, the dielectric layer and the first hard mask layer.
[0021] In a possible implementation, before the step of providing a first carrier and bonding the prefabricated chip layer to one side of the first carrier layer, the method further includes a step of fabricating the chip layer, which includes:
[0022] providing a second carrier board;
[0023] Placing at least one chip on one side of the second carrier, with the electrode pins of the chip facing the second carrier;
[0024] The second carrier board on which the chip is placed is subjected to a plastic sealing process to form a plastic sealing layer covering the chip, thereby obtaining a chip layer.
[0025] In a possible implementation, the step of forming a dielectric layer on a side of the chip layer away from the first carrier includes:
[0026] Making a dielectric material layer covering the surface of the chip layer on a side of the chip layer away from the first carrier board;
[0027] Forming a covering second hard mask layer and / or a second photoresist layer on a side of the dielectric material layer away from the first carrier;
[0028] The dielectric material layer is subjected to photolithography processing based on the second hard mask layer and / or the second photoresist layer to form a first through hole exposing the electrode pins of the chip, thereby obtaining the dielectric layer.
[0029] In a possible implementation, after the step of forming electrode traces in the first through hole and the second through hole to obtain a redistribution layer consisting of the electrode traces, the dielectric layer and the first hard mask layer, the method further includes:
[0030] A ball planting process is performed on a side of the redistribution layer away from the chip layer to obtain a conductive ball electrically connected to the redistribution layer.
[0031] In a second aspect, an embodiment of the present application further provides a chip packaging structure, which is manufactured by the chip packaging method described in any one of the first aspects, wherein the chip packaging structure comprises a stacked chip layer and a redistribution layer, wherein the chip layer comprises at least one chip and a plastic packaging layer encapsulating the chip;
[0032] The redistribution layer comprises:
[0033] a dielectric layer, the dielectric layer comprising a first through hole exposing an electrode pin of the chip;
[0034] a first hard mask layer, the first hard mask layer being located on a side of the dielectric layer away from the chip layer, wherein the first hard mask layer comprises a second through hole exposing the first through hole, and the aspect ratio of the first hard mask layer is 3-5;
[0035] An electrode wiring is located in the first through hole and the second through hole, and the electrode wiring is electrically connected to the chip.
[0036] In a possible implementation, the material of the first hard mask layer includes silicon dioxide, calcium oxide, nickel, cadmium, polysilicon, amorphous silicon, silicon carbide and tantalum pentoxide.
[0037] In a third aspect, an embodiment of the present application further provides an electronic component, comprising the chip packaging structure described in any one of the second aspects.
[0038] Based on any of the above aspects, the chip packaging method, chip packaging structure and electronic device provided in the embodiment of the present application, after making a first hard mask layer on the side of the dielectric layer away from the first carrier, the electrode routing located in the first through hole and the second through hole is made to obtain a redistribution layer composed of the electrode routing, the dielectric layer and the first hard mask layer. Among them, the aspect ratio of the first hard mask layer is 3 to 5, and the first hard mask layer is used to replace the photoresist layer for electroplating. When electroplating deeper electrode routing, its structural strength can effectively reduce the risk of collapse caused by the excessive aspect ratio of the photoresist layer during the electroplating process, and improve the fineness of the electrode routing pattern. BRIEF DESCRIPTION OF THE DRAWINGS
[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.
[0040] Figure 1 A schematic diagram of a process flow of the chip packaging method provided in this application;
[0041] Figure 2 for Figure 1 The corresponding process diagram;
[0042] Figure 3 for Figure 1 Schematic diagram of the sub-step flow chart of step S130;
[0043] Figure 4 for Figure 3 The corresponding process diagram;
[0044] Figure 5 A schematic diagram of the chip packaging structure provided in this application. DETAILED DESCRIPTION
[0045] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.
[0046] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.
[0047] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.
[0048] In the description of this application, it should be noted that the terms "upper", "lower", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the application is usually placed when in use, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.
[0049] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "disposed", "connected", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0050] It should be noted that, in the absence of conflict, different features in the embodiments of the present application may be combined with each other.
[0051] The inventors have found that as the feature size of semiconductor processes continues to shrink, the aspect ratio of the thickness of the photoresist layer (PR) to the chip line width increases, that is, the ratio of the height to the width of the photoresist layer increases. A larger aspect ratio of the photoresist layer and a smaller depth of focus may increase the probability of the photoresist layer tilting and collapsing. When the electrode routing of the electroplating rewiring layer is tilted and collapsed, the accuracy of the electrode routing pattern may be affected. If the height of the photoresist layer is thinned, a too thin photoresist layer may not meet the deposition requirements of the thicker underlying film material. In other words, a too thin photoresist layer may not be sufficient to support the deposition of deeper electrode routing.
[0052] In order to solve the above-mentioned technical problems, the inventor innovatively designed the following technical solutions, and the specific implementation solutions of the present application will be described in detail below in conjunction with the accompanying drawings. It should be noted that the defects existing in the solutions in the above-mentioned prior art are the results obtained by the inventor after practice and careful research. Therefore, the discovery process of the above-mentioned technical problems and the solutions proposed in this embodiment below for the above-mentioned problems should all be the contributions made by the inventor to the present application in the process of invention and creation, and should not be understood as the technical content known to those skilled in the art.
[0053] In order to solve the problems in the prior art, the present application provides a chip packaging method. Figure 1 and Figure 2 , Figure 1 FIG. 1 is a flow chart of a chip packaging method. Figure 2 for Figure 1 The corresponding process diagram. Figure 1 and Figure 2 Each step of the chip packaging method is described in detail.
[0054] Step S110: providing a first carrier board, and bonding the prefabricated chip layer to one side of the first carrier board layer.
[0055] In this step, an adhesive layer may be first made on one side of the first carrier 210, and then the prefabricated chip layer 110 is bonded to the first carrier 210 through the adhesive layer. At this time, the chip layer 110 is located on the side of the adhesive layer away from the first carrier 210. The chip layer 110 includes at least one chip 111 and a plastic sealing layer 112 for encapsulating the chip, and the electrode pins 1111 of the chip 111 face the side away from the first carrier 210. The first carrier 210 may include, but is not limited to, a glass carrier, a resin carrier, etc.
[0056] Prior to this step, the chip layer 110 may be manufactured by the following method. First, a second carrier is provided, and an adhesive layer is manufactured on one side of the second carrier. Next, at least one chip 111 is placed on one side of the second carrier, with the electrode pins 1111 of the chip 111 facing the second carrier. Finally, the second carrier on which the chip 111 is placed is plastic-sealed to form a plastic-sealing layer 112 covering the chip 111, thereby obtaining the chip layer 110. Specifically, the second carrier on which the chip 111 is placed is placed in a mold, and a plastic-sealing material is pressed into the mold by injection molding, and a plastic-sealing layer 112 wrapping the chip 111 is formed on one side of the second carrier on which the chip 111 is disposed, and the plastic-sealing layer 112 is demolded after the plastic-sealing layer 112 is cooled and solidified, wherein the plastic-sealing material may be an epoxy molding compound (EMC-Epoxy Molding Compound).
[0057] Step S120: forming a dielectric layer on a side of the chip layer away from the first carrier.
[0058] In this step, the dielectric layer 121 may be made of an organic material such as polyimide, wherein the dielectric layer 121 may include a first through hole 1211 exposing the electrode pin 1111 of the chip 111 .
[0059] After this step, metal sputtering may be performed on the dielectric layer 121 to form a seed layer on the side of the dielectric layer 121 away from the first carrier 210 and the inner wall of the first through hole 1211 to enhance the bonding force between the subsequent deposition material and the dielectric layer 121 .
[0060] Step S130: forming a first hard mask layer on a side of the dielectric layer away from the first carrier.
[0061] In this step, the first hard mask layer 122 includes a second through hole 1221 exposing the first through hole 1211, that is, the orthographic projection of the first through hole 1211 on the first carrier 210 is located within the orthographic projection of the second through hole 1221 on the first carrier 210, wherein the first hard mask layer is obtained by, but is not limited to, plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDPCVD), sub-atmospheric pressure chemical vapor deposition (SACVD), low pressure chemical vapor deposition (LPCVD), atomic layer chemical vapor deposition (ALDCVD), etc. The aspect ratio of the first hard mask layer 122 can be 3 to 5, and the material of the first hard mask layer 122 includes, but is not limited to, silicon dioxide, calcium oxide (Si3N4), nickel, cadmium, polysilicon, amorphous silicon, silicon carbide (SiC) and tantalum pentoxide (Ta2O5), etc. The structural strength of the first hard mask layer 122 is greater than that of the photoresist layer. The first hard mask layer 122 is used to replace the photoresist layer for electroplating. When electroplating deeper electrode traces 123, the risk of collapse caused by the excessive aspect ratio of the photoresist layer during the electroplating process can be effectively reduced, thereby improving the fineness of the electrode trace 123 pattern.
[0062] Step S140: forming electrode wiring in the first through hole and the second through hole to obtain a redistribution layer consisting of the electrode wiring, the dielectric layer and the first hard mask layer.
[0063] In this step, electrode traces 123 can be formed in the first through holes 1211 and the second through holes 1221 based on the seed layers exposed by the first through holes 1211 and the second through holes 1221 to obtain a redistribution layer 120 consisting of the electrode traces 123 , the dielectric layer 121 and the first hard mask layer 122 .
[0064] In this embodiment, the first hard mask layer 122 is used to replace the photoresist layer for electroplating. When electroplating the deeper electrode traces 123, its structural strength can effectively reduce the risk of collapse caused by the excessive aspect ratio of the photoresist layer during the electroplating process, thereby improving the fineness of the electrode trace 123 pattern.
[0065] Further, in step S120, a dielectric material layer covering the surface of the chip layer 110 is formed on the side of the chip layer 110 away from the first carrier 210. Next, a second hard mask layer and / or a second photoresist layer covering the side of the dielectric material layer away from the first carrier is formed. Finally, based on the second hard mask layer and / or the second photoresist layer, the dielectric material layer is photolithographically processed to form a first through hole 1211 exposing the electrode pin 1111 of the chip 111, thereby obtaining a dielectric layer 121.
[0066] For further information, please refer to Figure 3 and Figure 4 , step S130 can be implemented by the following method.
[0067] Step S131: forming a hard material layer on a side of the dielectric layer away from the first carrier board.
[0068] In this step, the hard material layer 124 can be made of at least one material such as silicon dioxide, calcium oxide (Si3N4), nickel, cadmium, polysilicon, amorphous silicon, silicon carbide (SiC) and tantalum pentoxide (Ta2O5), and its aspect ratio can be 3-5.
[0069] Step S132: forming a first photoresist layer on a side of the hard material layer away from the first carrier, and patterning the hard material layer based on the first photoresist layer to form a second through hole exposing the first through hole, thereby obtaining a first hard mask layer.
[0070] In this step, a photosensitive material may be first coated on the side of the hard material layer 124 away from the first carrier 210 to form a first photoresist layer 130. The first photoresist layer 130 is then developed and exposed to form a photoresist opening, and then the hard material layer 124 is patterned based on the photoresist opening to form a second through hole 1221 exposing the first through hole 1211, thereby obtaining a first hard mask layer 122.
[0071] In the above process, the first photoresist layer 130 can be made of two photosensitive materials. Specifically, the first photosensitive material can be coated on the side of the hard material layer 124 away from the first carrier 210 to form a first photoresist sublayer. Then, the second photosensitive material is coated on the side of the first photoresist sublayer away from the first carrier to form a second photoresist sublayer, wherein the first photosensitive material can be different from the second photosensitive material or can be the same. Preferably, the first photosensitive material is different from the second photosensitive material to enhance the structural strength of the first photoresist layer and reduce the possibility of collapse of the first photoresist layer.
[0072] Then, the second photoresist sublayer is developed and exposed to form a first photoresist opening on the second photoresist sublayer, and the first photoresist sublayer is developed and exposed to form a second photoresist opening on the first photoresist sublayer, the second photoresist opening coincides with the first photoresist opening, and the orthographic projection of the first photoresist opening on the first carrier 210 covers the orthographic projection of the first through hole 1211 on the first carrier 210.
[0073] Finally, the hard material layer 124 is patterned based on the first photoresist opening and the second photoresist opening to form a second through hole 1221 exposing the first through hole 1211 , thereby obtaining a first hard mask layer 122 .
[0074] After step S130, it is possible to choose whether to remove the first photoresist layer 130 according to the needs. Specifically, the first photoresist layer 130 can be removed first, and then the dielectric layer 121 with the first hard mask layer 122 is electroplated. At this time, the electroplating time can be adjusted according to the required depth of the electrode trace 123. Based on the seed layer exposed by the first through hole 1211 and the second through hole 1221, the electrode trace 123 is formed in the first through hole 1211 and the second through hole 1221, and the redistribution layer 120 composed of the electrode trace 123, the dielectric layer 121 and the first hard mask layer 122 is obtained. Alternatively, in order to shorten the electroplating time, the height of the first hard mask layer 122 can be appropriately reduced, and the dielectric layer 121 can be electroplated using a combined structure of the first photoresist layer 130 and the first hard mask layer 122. At this time, the first photoresist layer 130 can adopt a stacked structure of a first photoresist sublayer and a second photoresist sublayer to increase its structural strength, reduce the risk of collapse caused by an excessively large aspect ratio of the photoresist layer during the electroplating process, and improve the fineness of the electrode routing pattern.
[0075] It is not difficult to understand that after step S140, the chip packaging method provided in the embodiment of the present application may also include the step of making other functional layers. For example, a ball planting process may be performed on the side of the redistribution layer away from the chip layer to obtain a conductive ball electrically connected to the redistribution layer. Specifically, the pre-made conductive ball may be transferred to the electrode trace on the side of the redistribution layer away from the chip layer to connect the conductive ball and the electrode trace. The conductive ball can play a role of adhesion and diffusion when the chip packaging structure is welded with other electronic devices.
[0076] It should be noted that the embodiment of the present application adopts a die first process. In other embodiments, the solution provided by the embodiment of the present application may adopt a redistribution layer first process, that is, the redistribution layer 120 may be made first and then the chip layer 110 and other functional layers may be made. Specifically, a dielectric layer 121 may be made on one side of the first carrier 210, and the dielectric layer 121 includes at least one first through hole 1211. Then, a first hard mask layer 122 is made on the side of the dielectric layer 121 away from the first carrier 210, and the first hard mask layer 122 may include a second through hole 1221 exposing the first through hole 1211. Then, based on the first hard mask layer 122, an electroplating process is performed to form an electrode trace 123 in the first through hole 1211 and the second through hole 1221, so as to obtain a redistribution layer 120 composed of the electrode trace 123, the dielectric layer 121 and the first hard mask layer 122. Finally, a chip layer 110 is fabricated on a side of the redistribution layer 120 away from the first substrate 210 . The chip layer 110 includes at least one chip 111 electrically connected to the electrode traces 123 and a plastic packaging layer 112 located around the chip 111 .
[0077] Based on the same inventive concept, please refer to Figure 5 The present application also provides a chip packaging structure 10 manufactured according to the chip packaging method in the above embodiment, the chip packaging structure 10 may include a stacked chip layer 110 and a redistribution layer 120, the chip layer 110 includes at least one chip 111 and a plastic packaging layer 112 for packaging the chip 111. The redistribution layer 120 includes a dielectric layer 121, a first hard mask layer 122 and electrode traces 123.
[0078] The dielectric layer 121 includes a first through hole 1211 exposing the electrode pin 1111 of the chip 111, and the first hard mask layer 122 is located on the side of the dielectric layer 121 away from the chip layer 110. The first hard mask layer 122 includes a second through hole 1221 exposing the first through hole 1211. The electrode trace 123 is located in the first through hole 1211 and the second through hole 1221, and the electrode trace 123 is electrically connected to the chip 111. The aspect ratio of the first hard mask layer 122 can be 3 to 5, and the material of the first hard mask layer 122 includes but is not limited to silicon dioxide, calcium oxide (Si3N4), nickel, cadmium, polysilicon, amorphous silicon, silicon carbide (SiC) and tantalum pentoxide (Ta2O5).
[0079] In this embodiment, the first hard mask layer 122 is used to replace the photoresist layer for electroplating. When electroplating the deeper electrode traces 123, its structural strength can effectively reduce the risk of collapse caused by the excessive aspect ratio of the photoresist layer during the electroplating process, thereby improving the fineness of the electrode trace 123 pattern.
[0080] In addition, an embodiment of the present application also provides an electronic device, which includes the chip packaging structure in the above embodiment.
[0081] In summary, the embodiments of the present application provide a chip packaging method, a chip packaging structure and an electronic device. In the above chip packaging method, after making a first hard mask layer on the side of the dielectric layer away from the first carrier, an electrode wiring located in the first through hole and the second through hole is made to obtain a redistribution layer composed of the electrode wiring, the dielectric layer and the first hard mask layer. Among them, the aspect ratio of the first hard mask layer is 3 to 5, and the first hard mask layer is used to replace the photoresist layer for electroplating. When electroplating deeper electrode wiring, its structural strength can effectively reduce the risk of collapse caused by the excessive aspect ratio of the photoresist layer during the electroplating process, and improve the fineness of the electrode wiring pattern.
[0082] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A chip packaging method, characterized in that: The method comprises: Providing a first carrier board, and bonding a prefabricated chip layer to one side of the first carrier board layer, wherein the chip layer includes at least one chip and a plastic packaging layer encapsulating the chip, and the electrode pins of the chip face toward a side away from the first carrier board; A dielectric layer is formed on a side of the chip layer away from the first carrier, wherein the dielectric layer includes a first through hole exposing the electrode pins of the chip; Making a first hard mask layer on a side of the dielectric layer away from the first carrier, the first hard mask layer comprising a second through hole exposing the first through hole, and the aspect ratio of the first hard mask layer is 3-5; Electrode wiring is formed in the first through hole and the second through hole to obtain a redistribution layer consisting of the electrode wiring, the dielectric layer and the first hard mask layer.
2. The chip packaging method according to claim 1, characterized in that: The step of forming a first hard mask layer on a side of the dielectric layer away from the first carrier includes: Making a hard material layer on a side of the dielectric layer away from the first carrier board; A first photoresist layer is formed on a side of the hard material layer away from the first carrier, and the hard material layer is patterned based on the first photoresist layer to form a second through hole exposing the first through hole, thereby obtaining a first hard mask layer, wherein the thickness of the first photoresist layer is not greater than the thickness of the hard material layer.
3. The chip packaging method according to claim 2, characterized in that: The first photoresist layer includes a first photoresist sublayer and a second photoresist sublayer stacked together. The first photoresist layer is formed on a side of the hard material layer away from the first carrier. The hard material layer is patterned based on the first photoresist layer to form a second through hole exposing the first through hole. The steps of obtaining the first hard mask layer include: Coating a first photosensitive material on a side of the hard material layer away from the first carrier to form a first photoresist sublayer; Coating a second photosensitive material on a side of the first photoresist sublayer away from the first carrier to form a second photoresist sublayer, wherein the first photosensitive material is different from the second photosensitive material; Developing and exposing the second photoresist sublayer to form a first photoresist opening on the second photoresist sublayer, and developing and exposing the first photoresist sublayer to form a second photoresist opening on the first photoresist sublayer, wherein the second photoresist opening overlaps with the first photoresist opening, and an orthographic projection of the first photoresist opening on the first carrier covers an orthographic projection of the first through hole on the first carrier; The hard material layer is patterned based on the first photoresist opening and the second photoresist opening to form a second through hole exposing the first through hole, thereby obtaining a first hard mask layer.
4. The chip packaging method according to claim 2, characterized in that: After the step of forming a dielectric layer on a side of the chip layer away from the first carrier, the method further comprises the step of forming a seed layer, which step comprises: Performing metal sputtering on the dielectric layer to form a seed layer on a side of the dielectric layer away from the first carrier plate and on an inner wall of the first through hole; The step of forming electrode wiring in the first through hole and the second through hole to obtain a redistribution layer consisting of the electrode wiring, the dielectric layer and the first hard mask layer includes: The dielectric layer on which the first hard mask layer is made is electroplated, and electrode traces are formed in the first through hole and the second through hole based on the seed layer exposed by the first through hole and the second through hole, so as to obtain a redistribution layer consisting of the electrode traces, the dielectric layer and the first hard mask layer.
5. The chip packaging method according to claim 1, characterized in that: Before the step of providing a first carrier board and bonding the prefabricated chip layer to one side of the first carrier board layer, the method further includes a step of fabricating the chip layer, which includes: providing a second carrier board; Placing at least one chip on one side of the second carrier, with the electrode pins of the chip facing the second carrier; The second carrier board on which the chip is placed is subjected to a plastic sealing process to form a plastic sealing layer covering the chip, thereby obtaining a chip layer.
6. The chip packaging method according to claim 1, characterized in that: The step of making a dielectric layer on a side of the chip layer away from the first carrier board includes: Making a dielectric material layer covering the surface of the chip layer on a side of the chip layer away from the first carrier board; Forming a covering second hard mask layer and / or a second photoresist layer on a side of the dielectric material layer away from the first carrier; The dielectric material layer is subjected to photolithography processing based on the second hard mask layer and / or the second photoresist layer to form a first through hole exposing the electrode pins of the chip, thereby obtaining the dielectric layer.
7. The chip packaging method according to claim 1, characterized in that: After the step of forming electrode wiring in the first through hole and the second through hole to obtain a redistribution layer consisting of the electrode wiring, the dielectric layer and the first hard mask layer, the method further includes: A ball planting process is performed on a side of the redistribution layer away from the chip layer to obtain a conductive ball electrically connected to the redistribution layer.
8. A chip packaging structure, characterized in that: Made by the chip packaging method according to any one of claims 1 to 7, the chip packaging structure comprises a stacked chip layer and a redistribution layer, the chip layer comprises at least one chip and a plastic packaging layer encapsulating the chip; The redistribution layer comprises: a dielectric layer, the dielectric layer comprising a first through hole exposing an electrode pin of the chip; a first hard mask layer, the first hard mask layer being located on a side of the dielectric layer away from the chip layer, wherein the first hard mask layer comprises a second through hole exposing the first through hole, and the aspect ratio of the first hard mask layer is 3-5; An electrode wiring is located in the first through hole and the second through hole, and the electrode wiring is electrically connected to the chip.
9. The chip packaging structure according to claim 8, characterized in that: The material of the first hard mask layer includes silicon dioxide, calcium oxide, nickel, cadmium, polysilicon, amorphous silicon, silicon carbide and tantalum pentoxide.
10. An electronic component, characterized in that: A chip packaging structure comprising any one of claims 8 to 9.