Selective layer transfer

Abstract

Methods of selective layer transfer of portions of a layer between substrates, as well as devices and systems formed using the methods, are disclosed herein. In one embodiment, a first substrate having a layer of integrated circuit (IC) components is received, and a second substrate having one or more bonding regions is received. The first substrate is partially bonded to the second substrate such that a subset of the IC components on the first substrate are bonded to the bonding region on the second substrate. The first substrate is then separated from the second substrate, and a subset of the IC components bonded to the second substrate is separated from the first substrate and held on the second substrate.

Description

Background Art

[0001] In semiconductor manufacturing, a layer is typically transferred from one substrate to another using layer transfer techniques on a wafer-level scale. This technique requires the entire layer to be transferred in its entirety, whether or not the entire layer is needed. Therefore, after the transfer, any unwanted portions of the transferred layer must be etched away, which increases cost and process complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Figure 1A-Figure 1I An exemplary process flow for selective layer transfer using selective release technology is shown.

[0003] Figure 2A-2I An exemplary process flow for selective layer transfer using blanket laser exposure is shown.

[0004] Figure 3A-Figure 3I An exemplary process flow for selective layer transfer from a singulated donor substrate is shown.

[0005] Figure 4A-4C An exemplary process flow for selective layer transfer from multiple donor substrates is shown.

[0006] Figure 5A-5F An exemplary process flow for forming an integrated circuit package using selective transfer of a passive interposer is shown.

[0007] Figure 6A-6B An example of selective layer transfer between wafers is shown.

[0008] Figure 7 A flow chart for performing a selective layer transfer is shown.

[0009] Figure 8A-8E An exemplary process flow for selective transfer using blanket wafer laser exposure is shown.

[0010] Figure 9A-9D An exemplary process flow for selective transfer using a structured release layer with residual adhesive anchors is shown.

[0011] Figure 10A-10C A patterned release layer structure using anchors to control residual adhesion is shown.

[0012] Fig.11 An exemplary embodiment of a bonding / debonding tool for selective transfer is shown.

[0013] Figure 12A-12C Various laser debonding techniques for selective transfer are shown.

[0014] Fig.13Graph showing debonding times for selective transfer using various laser debonding techniques.

[0015] Figure 14A-14B A selective transfer process flow for avoiding contact between the surface of the donor wafer and the wafer chuck is shown.

[0016] Fig.15 Shown are top views of wafers and dies that may be included in a microelectronic assembly.

[0017] Fig.16 A cross-sectional side view of an integrated circuit device that can be included in a microelectronic assembly is shown.

[0018] Figures 17A-17D Perspective views of exemplary planar transistors, FinFET transistors, gate-all-around transistors, and stacked gate-all-around transistors are shown.

[0019] Fig.18 A cross-sectional side view of an integrated circuit device assembly that may include a microelectronic assembly is shown.

[0020] Fig.19 A block diagram of an exemplary electrical device that may include a microelectronic assembly is shown. DETAILED DESCRIPTION

[0021] Selective layer transfer

[0022] In semiconductor manufacturing, a layer is typically transferred from one substrate to another using a layer transfer technique on a wafer-level scale. Layer transfer contributes to a variety of applications in semiconductor manufacturing, including two-dimensional (2D) material fabrication, III-V semiconductors on complementary metal oxide semiconductors (CMOS), and traditional CMOS applications (e.g., metal-insulator-metal (MIM) devices and thin devices and / or interconnect layer transfer). However, current layer transfer techniques are limited to full-layer transfers, which may affect cost and performance when full layers are not required. For example, blanket layer transfer techniques (e.g., ion cutting and laser debonding layer transfers) require the entire layer to be transferred as a whole. As a result, after the transfer, any unwanted areas of the transferred layer must be etched away, which results in increased cost and process complexity.

[0023] Alternatively, pick-and-place techniques can be used to transfer specific dies or cores. For example, a core generally refers to an integrated circuit (IC) containing a subset of well-defined functions that is designed to be combined with other cores to form a single IC package. In order to transfer cores (e.g., for MIM core integration in a system on a chip (SoC)), a core device is made on a donor substrate (e.g., a wafer or panel), the donor substrate is singulated into cores, and then the cores are each attached to a receptor substrate (e.g., a SoC wafer or package) using a pick-and-place machine. Since additional processing is required to singulate the wafer and attach the corresponding core dies, this adds a lot of cost. For example, cores are generally manufactured on relatively thick substrates so that they can be handled without being damaged during singulation and attachment steps, and after the attachment step, additional processing is performed to thin the cores and / or remove the carrier substrate, which further increases cost and process complexity. Specifically, cores are typically fabricated on substrates over 700 micrometers (μm or microns) thick to provide structural and mechanical stability during fabrication, and after the singulation / attachment step, the cores can be thinned to approximately 20-100 μm by grinding the backside. However, grinding typically results in chipping along the edges of the core die. Furthermore, thinning the cores to less than 20 μm without creating defects can be challenging. Similarly, since pick and place assembly is difficult for substrates less than 1 square millimeter (mm 2 ) becomes very challenging for die with small size, so the die are typically singulated with die area on the millimeter scale.

[0024] Integrated circuits can also be manufactured monolithically, where all IC components and interconnections are fabricated in sequence on the same underlying substrate or wafer. However, monolithic ICs have various limitations, including design restrictions due to incompatible processes, lack of flexibility, and low yields.

[0025] Therefore, the present disclosure shows a selective layer transfer technology for selectively transferring portions of a layer between substrates, and devices and systems formed using the technology. For example, the described technology enables the transfer of selected areas of a donor substrate to a receptor substrate, which enables the donor substrate to be reused multiple times, while also addressing the limitations of the blanket layer transfer and pick-and-place techniques described above. Specifically, the described solution uses a selective release technology for a donor substrate (e.g., a wafer, a panel, or a die) in conjunction with a patterned bonding template on a receptor substrate (e.g., a wafer, a panel, or a die) to allow the transfer of selected areas of a layer on the donor substrate to the receptor substrate. For the purposes of the present disclosure, a layer may refer to one or more layers formed on a substrate, such as a single material layer, or a layer stack of layers that together form an IC component (e.g., a die, an interconnect, a bridge, a capacitor, and / or other semiconductor devices). A layer may also include stacked wafers, such as wafer-to-wafer bonding and stacked logic cells and / or memory wafers. As an example, a donor wafer may include layers of IC components (eg, IC dies), and selective layer transfer may be used to selectively and simultaneously transfer specific subsets of these IC components to a recipient wafer.

[0026] The described solution provides various advantages. For example, the described solution enables transfer of selected areas of a donor wafer, rather than an entire layer, which enables the donor wafer to be reused for multiple products, thus amortizing the cost of expensive devices (e.g., high-density MIM capacitors or high-density passive interposers) over multiple wafers. The solution also eliminates the need to etch away excess areas as required by a full-layer transfer (and thus, unlike the etched areas after the full-layer transfer, the selectively transferred areas may not have tapered edges resulting from the etching, or may have an inverted taper due to the etching used for singulation prior to the transfer).

[0027] Furthermore, layers of IC components can be selectively transferred at any level of granularity, including complete IC dies and packages, interconnects, transistors, resistors, capacitors, partial layers or layer stacks, and the like.

[0028] The solution also enables selective transfer of areas of ultra-thin layers without the increased processing and yield losses caused by the processing challenges brought by the core pick and place method (e.g., singulation, attaching each core individually, post-attachment thinning of the core). This helps to reduce the Z height of the product (e.g., due to form factor, thermal, and / or power delivery reasons) and the overall process complexity. For example, very thin IC dies or cores can be formed on any substrate and selectively transferred directly from the substrate. Therefore, selectively transferring the die not only eliminates the need for post-attachment thinning, but also enables the die to be much thinner than the die that is singulated, picked and placed, attached and subsequently thinned. For example, in some cases, the described solution can enable the transfer of dies with thicknesses ranging from 100 nanometers (nm) to 5μm or more. In addition, since post-attachment thinning is not required, unlike the cores that are thinned after attachment, the selectively transferred die may have no or minimal fragmentation on the die edge due to the lack of grinding.

[0029] Similarly, the solution supports the selective transfer of very small areas on a donor substrate (e.g., very small dies or core particles), which are extremely challenging when using pick and place techniques. For example, in some cases, the described solution can enable the transfer of a small area with a size of less than 1 mm. 2 (e.g. 100 μm 2 (10×10μm), 10,000μm 2 (100×100μm), 810,000μm 2 (900 x 900 μm, etc.) (there is no limit to the maximum size of the area that can be selectively transferred).

[0030] The solution also supports the selective transfer of dies with non-standard shapes and designs that are difficult to handle using pick and place machines, such as dies with atypical, arbitrary, irregular or non-convex shapes (e.g., L-shape, U-shape, shapes with sharp angles), dies with high aspect ratios (e.g., aspect ratios of 8:1 or higher), dies with holes, etc.

[0031] Furthermore, the solution has very low topography and supports high surface cleanliness and planarization (eg, using chemical mechanical polishing (CMP) processing), which makes it compatible with hybrid bonding and fusion bonding processes. Additional advantages are described throughout this disclosure and will be apparent in the following description.

[0032] Thus, the solution enables the manufacture of complex IC packages and products by selectively transferring certain components (e.g., active circuit systems such as IC dies, passive circuit systems) rather than combining them using traditional processes (e.g.: (i) full-layer transfer with excess areas etched away; (ii) pick-and-place assembly of individual IC components; and / or (iii) monolithic IC fabrication).

[0033] Figure 1A-Figure 1I An exemplary process flow for selective layer transfer using a selective release technique is shown. In the example shown, a layer of an integrated circuit (IC) component is selectively transferred from a donor substrate 100 to an acceptor substrate 110, as described further below.

[0034] exist Figure 1A , a release layer 102 is formed on a carrier substrate, referred to as a donor substrate 100. The release layer 102 is a temporary bonding and debonding layer for the layer 104 to be selectively transferred. In some embodiments, the release layer 102 may include one or more layers and / or materials capable of providing adhesion to the donor substrate 100 and / or absorbing energy from a laser (e.g., a laser beam), such as (multiple) lossy dielectric and / or thin metal layers that provide adhesion and absorb / reflect infrared (IR) light, organic polymer layers (e.g., polyimide) that provide adhesion and absorb visible or ultraviolet (UV) light, and / or a patterned dielectric layer with anchors to provide residual adhesion (e.g., after the metal layer is ablated by an IR laser).

[0035] The selectively transferred layer 104 is formed on the release layer 102 of the donor substrate 100 (e.g., by directly fabricating the layer 104 or blanket transferring the layer 104). The selectively transferred layer 104 may include one or more material layers, such as a single material layer, or a stack of layers that together form an IC component (e.g., a full IC die, a die, an interconnect, a bridge, a capacitor, a transistor, and / or other semiconductor device). For example, in some embodiments, the selectively transferred layer 104 may be a prefabricated semiconductor wafer containing unsingulated integrated circuit (IC) dies that is blanket transferred to the release layer 102 on the donor substrate 100.

[0036] exist Figure 1B In the process, the selective transfer layer 104 is cut over the donor substrate 100 without cutting through the donor substrate 100 using a technique such as etching, reactive ion etching (RIE), plasma cutting, mechanical sawing, etc., thereby partially singulating the IC components 106 in the layer 104. In some embodiments, the release layer 102 may also be singulated (e.g., cut or etched) together with the transfer layer 104.

[0037] exist Figure 1CIn the embodiment of the present invention, a release layer 112 is optionally formed over another carrier substrate, referred to as an acceptor substrate 110. For example, if the selectively transferred IC component 106 will be subsequently debonded from the acceptor substrate 110 after transfer, the release layer 112 can be formed over the acceptor substrate 110. Otherwise, if the selectively transferred IC component 106 will remain on the acceptor substrate 110 after transfer, the release layer 112 on the acceptor substrate 110 can be omitted.

[0038] Next, a bonding template 114 is formed on the surface of the acceptor substrate 110 (e.g., over the release layer 112, if included). The bonding template 114 includes a pattern of bonding features or adhesion areas 114 that enable selective transfer of specific areas of the donor substrate 100 to the acceptor substrate 110. For example, the locations of the bonding features 114 on the acceptor substrate 110 correspond to the areas or IC components 106 on the donor substrate 100 that are to be transferred to the acceptor substrate 110.

[0039] For example, in some embodiments, the bonding features 114 may include "islands" or "mesa" structures that are similar in size to the target area to be transferred from the donor substrate 100. For example, each island or mesa structure 114 may be a raised structure located on the surface of the acceptor substrate 110 that has a similar footprint (e.g., shape / surface area) as the corresponding IC component 106 located on the donor substrate 100. In other embodiments, the mesas 114 may be replaced by a surface treatment of photolithography or additive manufacturing that enhances adhesion in the target area of ​​the acceptor substrate 110 (e.g., the area showing the mesas 114) and prevents adhesion in other areas, including but not limited to: surface topography changes, use of materials with high adhesion and / or low adhesion, treatment with hydrophobic materials and / or self-assembled monolayers (SAMs), and / or surface activation techniques, among other examples.

[0040] In various embodiments, these bonding features 114 may be made of a dielectric material, a conductive material (e.g., a metal), or both, depending on whether an electrical connection is desired between the bonded IC component 106 and the receptor substrate 110. For example, the bonding features 114 may be blanket dielectric structures with no electrical contacts, or if electrical connection across the bonding interface is desired, the bonding features 114 may be dielectric structures with electrical contacts therethrough (e.g., hybrid bond pads).

[0041] exist Figure 1D In the process, the donor substrate 100 and the acceptor substrate 110 are brought into contact with each other with their top surfaces aligned face to face so that the target IC components 106 on the donor 100 are aligned with the corresponding bonding features 114 on the acceptor substrate 110 .

[0042] exist Figure 1E , the donor substrate 100 and the acceptor substrate 110 are partially joined together. For example, an area of ​​the acceptor substrate 110 having a raised surface feature or "mesa" 114 is joined to a corresponding area of ​​the donor substrate 100 having a target IC component 106, while other areas of the donor substrate 100 and the acceptor substrate 110 remain unjoined. For example, in some embodiments, this is controlled by the height of the joining protrusions 114 to prevent undesired contact between areas that will not be transferred. As previously mentioned, this can also be controlled by surface treatment of different areas to achieve good bonding in the target area (e.g., where the mesa 114 is shown) and prevent or reduce bonding in other areas.

[0043] exist Figure 1F In the process, the IC component 106 bonded to the receptor 110 is selectively debonded from the donor 100 using a selective release technique (e.g., IR debonding, selective visible or ultraviolet (UV) laser exposure, etc.). For example, a laser such as an IR or UV laser can be used to selectively remove or ablate the region 103 of the release layer 102 where the IC component 106 is bonded to the donor 100, which forms a gap or void 103 in the release layer 102 and causes the IC component 106 to be released from the donor 100.

[0044] exist Figure 1G , the donor substrate 100 and the acceptor substrate 110 are mechanically separated from each other. At this point, the IC components 106 that were selectively bonded to the acceptor 110 (e.g., via the bonding structures 114) and debonded from the donor 100 remain on the acceptor 110 and are separated from the donor 100. All other IC components 106 that are not bonded to the acceptor 110 remain on the donor 100.

[0045] exist Figure 1H , the receptor substrate 110 is now ready for continued processing, such as dielectric fill 116 around the transferred IC components 106, planarization, selective transfer or pick and place attachment of additional IC dies or other IC components, via formation, formation of interconnect / metallization layers, attaching a structural substrate, debonding the receptor substrate (e.g., via an optional receptor release layer 112), and / or any other processing required for the finished product (e.g., an IC package).

[0046] exist Fig. 1IThe donor substrate 100 is then reused to transfer the remaining IC components 106 (e.g., the remaining areas of the selectively transferred layer 104) to a new acceptor substrate 110'. The donor substrate 100 may continue to be reused in this manner until all IC components 106 or the entire layer 104 have been selectively transferred to any number of acceptor substrates 110.

[0047] It should be understood that the process flow shown for selective layer transfer is shown only as an example, and many other process variations are possible. For example, the donor substrate 100 and the acceptor substrate 110 can be wafers, panels, IC packages, cores, dies, or any combination thereof (e.g., for transfer from wafer to panel, transfer from core to wafer, etc.). In addition, each substrate 100, 110 can be made of a variety of materials, including but not limited to: inorganic materials (e.g., silicon, silicon on insulator (SOI), quartz, glass, and / or III-V materials), organic materials (e.g., IR or UV transparent epoxy resins), etc.

[0048] The materials used in the release layers 102, 112 may vary depending on the type of release or debonding technique used. For example, for infrared (IR) laser debonding, the release layers 102, 112 may include one or more materials capable of absorbing and / or reflecting infrared (IR) light, such as a thin metal layer or multiple metal layers (e.g., aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN)). For ultraviolet (UV) laser debonding, the release layers 102, 112 may include one or more materials capable of absorbing UV light (e.g., a variety of organic polymers, including but not limited to polyimide). In some embodiments, the release layers 102, 112 may additionally or alternatively include one or more layers of dielectric materials, such as silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), aluminum oxide (Al 2 O 3 ), low-k dielectrics (e.g., carbon-doped oxide (CDO) or porous silicon dioxide (SiO 2 ), titanium dioxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 )), which can be used to buffer laser ablation and thermal energy, control thin film interference or adhesion, and / or provide residual adhesion after other materials and / or layers in the release layer 102, 112 are weakened, removed and / or ablated by the laser.

[0049] The number of layers 104 on the donor substrate 100, the arrangement / structure of the layers 104, the materials in each layer 104, and the types of IC components 106 formed in the layers 104 may vary.

[0050] To control the level of adhesion in different areas, any suitable surface treatment or other technique may be used to form the bonding areas or bonding features 114 on the receptor substrate 110, including but not limited to: surface topography changes (e.g., terraces, depressions), use of materials with high adhesion and / or low adhesion, treatment with hydrophobic materials and / or self-assembled monolayers (SAMs), and / or surface activation techniques, among other examples. In addition, the bonding features or bonding areas 114 on the receptor substrate 110 may vary in size, shape, height, topography, pattern, and material. For example, an inorganic dielectric (e.g., silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON) and / or silicon carbon nitride (SiCN)), organic dielectrics (such as photoresists and adhesives), conductive materials (such as metals), and combinations thereof to form the bonding feature 114.

[0051] The donor substrate 100 and the acceptor substrate 110 may be (partially) joined using any suitable joining technique, including but not limited to hybrid joining, fusion joining, and adhesive joining. The donor substrate 100 and the acceptor substrate 110 may be debonded or released using any suitable debonding technique, including but not limited to IR and UV laser debonding. Furthermore, there may be additional cleaning steps before or after each selective layer transfer to the acceptor substrate 110, so that the donor substrate 100 can be reused.

[0052] In addition, in some embodiments, additional bonding and / or alignment features may be included at the wafer level and / or die level (e.g., on the donor die, donor wafer, acceptor wafer, and / or final product). For example, the donor and / or acceptor wafer may include ridges or cross structures for facilitating bonding, such as a single ridge (e.g., a line or strip of dielectric material) extending across and / or through the center of the wafer, or multiple orthogonal ridges forming a cross pattern. Alignment features for wafers, small dies, and / or die arrays may also be included to facilitate bonding with proper alignment. In addition, multiple dies may be connected by small (e.g., dielectric) bridges to facilitate their joint bonding and transfer together. For example, if some of the dies connected by the bridge are successfully bonded to the acceptor, the bridge may also facilitate bonding of other dies. Therefore, these inter-die bridges may exist on the donor before transfer and on the acceptor and final product after transfer.

[0053] Furthermore, in some cases the debonding process may cause some unique damage or delamination near the edge and / or on the backside of the die, which does not affect the process performance but may indicate that this solution is being used.

[0054] Figure 2A-2I An exemplary process flow for selective layer transfer using blanket laser exposure is shown. In the example shown, layer 204 of integrated circuit (IC) component 206 is selectively transferred from donor substrate 200 to receptor substrate 210. However, prior to transfer, the entire release layer 202b on donor 200 is mechanically weakened (e.g., using IR laser, visible light laser, UV laser, chemical etching, and / or thermal techniques), which can also be referred to as partial release. In this way, after the target IC component 206 on donor 200 is bonded to receptor 210, the target IC component 206 can be completely released from donor 200 by mechanically separating donor 200 from receptor 210. In some cases, the target IC component 206 can be completely released from donor 200 by mechanically separating donor 200 from receptor 210. Figure 1A-Figure 1I This can result in a simplified and faster bonding / debonding process compared to the bonding / selective release / debonding process in the conventional method. Figures 8A-14B Other variations of this process are described.Alternatively, rather than using blanket laser exposure, the respective materials used in donor release layer 202 and receptor bonding template 214 may be selected so that the bond to donor 200 is weaker than the bond subsequently formed to receptor 210.

[0055] exist Figure 2A In the embodiment of the present invention, a release layer 202 is formed on a donor substrate 200. A selectively transferred layer 204 is formed on the release layer 202 (e.g., by directly forming the layer 204 or blanket transferring the layer 204). In some embodiments, the selectively transferred layer 204 can be a layer of an IC component (e.g., an IC die, a chip, an interconnect, a bridge, a capacitor, a transistor, and / or other semiconductor device).

[0056] exist Figure 2B In the embodiment of the present invention, the selectively transferred layer 204 is cut above the donor substrate 200 without cutting through the donor substrate 200 , thereby partially singulating the IC components 206 in the layer 204 .

[0057] exist Figure 2C In the embodiment, before transfer, blanket laser exposure is performed on the donor release layer 202 to weaken the entire release layer 202. For example, in some embodiments, the blanket laser exposure can be performed using laser (e.g., IR or UV laser exposure), chemical and / or thermal techniques. In this way, the weakened release layer 202 has a lower bonding energy, which causes partial release of the IC component 206 bonded to the layer 202.

[0058] exist Figure 2D In the embodiment of the present invention, release layer 212 is optionally formed over receptor substrate 210. For example, if selectively transferred IC component 206 will be subsequently debonded from receptor substrate 210 after transfer, release layer 212 may be formed over receptor 210; otherwise, release layer 212 on receptor 210 may be omitted.

[0059] Next, a bonding template 214 is formed on the surface of the acceptor substrate 210 (e.g., over the release layer 212, if included). The bonding template 214 includes a pattern of bonding features or bonding areas 214 (e.g., mesas) that enable selective transfer of specific areas of the donor substrate 200 to the acceptor substrate 210. However, in various embodiments, any suitable surface treatment or other technique may be used to control the level of adhesion on different areas of the acceptor substrate 210 (e.g., to form bonding areas and non-bonding areas for selective transfer), including but not limited to: surface topography changes (e.g., mesas, depressions), use of materials with high adhesion and / or low adhesion, treatment with hydrophobic materials and / or self-assembled monolayers (SAMs), and / or surface activation techniques, among other examples.

[0060] exist Figure 2E In the process, the donor substrate 200 and the acceptor substrate 210 are brought into contact with each other with their top surfaces aligned face to face so that the target IC components 206 on the donor 200 are aligned with the corresponding bonding features 214 on the acceptor 210 .

[0061] exist Figure 2F In FIG. 1 , a donor substrate 200 and an acceptor substrate 210 are partially bonded together, wherein a region of the donor 200 having a target IC component 206 is bonded to a region of the acceptor 210 having a bonding mesa 214 .

[0062] exist Figure 2G , the donor substrate 200 and the acceptor substrate 210 are mechanically separated from each other. At this point, the IC components 206 that were selectively bonded to the acceptor 210 (e.g., via the bonding mesas 214) remain on the acceptor 210 and are debonded / separated from the donor 200 due to the blanket weakening of the donor release layer 202. All other IC components 206 that are not bonded to the acceptor 210 remain on the donor 200.

[0063] Alternatively, in some embodiments, the respective materials used in the donor release layer 202 and the receptor engagement template 214 may be selected without performing Figure 2C Blanket laser exposure in Figure 2CThe target IC component 206 may be formed by a laser beam (except for blanket laser exposure in the embodiment of the present invention) so that the target IC component 206 will have a stronger bond with the receptor 210 than with the donor 200. In this way, when the donor 200 and the receptor 210 are mechanically separated, the target IC component 206 will be debonded from the donor 200 and remain on the receptor 210 due to the difference in bond strength.

[0064] exist Figure 2H , the receptor substrate 210 is ready for continued processing, such as dielectric fill 216 around the transferred IC component 206, planarization, selective transfer or pick and place attachment of additional IC dies or other IC components, via formation, formation of interconnect / metallization layers, attachment of a structural substrate, debonding of the receptor substrate (e.g., via an optional receptor release layer 212), and / or any other processing required for the finished product (e.g., an IC package).

[0065] exist Fig.2I The donor substrate 200 is then reused to transfer the remaining IC components 206 (e.g., the remaining areas of the selectively transferred layer 204) to a new acceptor substrate 210'. The donor substrate 200 may continue to be reused in this manner until all IC components 206 or the entire layer 204 have been selectively transferred to any number of acceptor substrates 210.

[0066] Figure 2A-2I The elements marked with reference numerals in the Figure 1A-1I Furthermore, it should be understood that the illustrated process flow for selective layer transfer is presented as an example only, and that many other process variations are possible, including but not limited to those described throughout this disclosure.

[0067] Figure 3A-Figure 3I An exemplary process flow for selective layer transfer from a singulated donor substrate 300 is shown. For example, in some cases, if the percentage of integrated circuit (IC) components 306 transferred for each selective layer transfer is relatively small, it may be easier and more cost-effective to cut the donor substrate 300 and perform the transfer from singulated donor dies 301 containing a smaller subset of IC components 306 from the original donor substrate 300. Thus, in the example shown, the donor substrate 300 having a layer 304 of IC components 306 is cut, and the resulting layer of IC components 306 located on the singulated donor dies 301 is selectively transferred to an acceptor substrate 310. In this way, the transfer is performed at the donor die level rather than at the wafer level or panel level.

[0068] exist Figure 3A, a release layer 302 is formed on a donor substrate 300. A selectively transferred layer 304 is formed on the release layer 302 (e.g., by directly fabricating the layer 304 or blanket transferring the layer 304). In some embodiments, the selectively transferred layer 304 can be a layer of an IC component (e.g., an IC die, a chip, an interconnect, a bridge, a capacitor, a transistor, and / or other semiconductor device).

[0069] exist Figure 3B In the embodiment, the selective transfer layer 304 is cut above the donor substrate 300 without cutting through the donor substrate 300, thereby partially singulating the IC components 306 in the layer 304. In some embodiments, the release layer 302 can also be singulated (eg, cut or etched) together with the transfer layer 306.

[0070] exist Figure 3C , a donor substrate 300 is cut into singulated donor dies 301, each of which contains a subset of IC components 306 from the original donor substrate 300. For example, each donor die 301 may include one or more IC components 306 from a layer 304 on the original donor substrate 300.

[0071] exist Figure 3D In the embodiment, blanket laser exposure (as shown) or selective laser release is performed on the donor release layer 302 prior to transfer (e.g., using IR / UV laser exposure or thermal techniques) to weaken the entire release layer 302, thereby partially releasing the IC component 306 from the donor die 301.

[0072] exist Figure 3E , a release layer 312 is optionally formed over the acceptor substrate 310 (e.g., in the case where the selectively transferred IC component 306 will subsequently be debonded from the acceptor substrate 310 after transfer). Next, a bonding template 314 is formed on the surface of the acceptor substrate 310 (e.g., over the release layer 312, if included). The bonding template 314 includes a pattern of bonding features or bonding areas 314 (e.g., mesas) that enable specific areas of the donor die 301 to be selectively transferred to the acceptor substrate 310. However, in various embodiments, any suitable surface treatment or other technique may be used to control the level of adhesion on different areas of the acceptor substrate 310 (e.g., to form bonding areas and non-bonding areas for selective transfer), including but not limited to: surface topography changes (e.g., mesas, depressions), use of materials with high adhesion and / or low adhesion, treatment with hydrophobic materials and / or self-assembled monolayers (SAMs), and / or surface activation techniques, among other examples.

[0073] exist Figure 3F, a bond head 320 is used to pick up one of the donor dies 301 and place it face down on an acceptor substrate 310 such that a target IC component 306 located on the donor die 301 is aligned with a corresponding bonding mesa 314 located on the acceptor substrate 310. The donor die 301 and the acceptor substrate 310 are then partially bonded together (e.g., die-to-wafer bonding), wherein the target IC component 306 is bonded to the acceptor bonding mesa 314.

[0074] exist Figure 3G 3, the bond head 320 is raised and the donor die 301 is mechanically separated from the acceptor substrate 310. At this point, the IC components 306 that were selectively bonded to the acceptor 310 (e.g., via the bonding mesas 314) remain on the acceptor 310 and are debonded / separated from the donor die 301 (e.g., die-to-wafer debonding) due to the blanket weakening of the donor release layer 302. All other IC components 306 that are not bonded to the acceptor substrate 310 remain on the donor die 301.

[0075] Alternatively, in some embodiments, the target IC component 306 may be selectively released (e.g., as described with respect to Figure 1F ), instead of (or in addition to) executing Figure 3D Alternatively, the donor release layer 302 and the acceptor bonding template 314 may be formed using materials having different bonding strengths so that the target IC component 306 will have a stronger bond to the acceptor substrate 310 than to the donor die 301 .

[0076] exist Figure 3H and Fig. 3I In the process, the bonding head 320 translates and repeats the steps. For example, the bonding head 320 moves to a new position and repeats the steps respectively. Figure 3F and Figure 3G The process in to selectively transfer another set of IC components 306 from the donor die 301 to other areas of the acceptor substrate 310.

[0077] The process may be repeated in this manner until all IC components 306 on the donor die 301 have been transferred. At this point, the bond head 320 may pick up another donor die 301 and continue transferring the IC components 306 from the new donor die 301 to the same or a different receptor substrate 310.

[0078] After all transfers to the receptor substrate 310 are completed, the receptor 310 can be ready for continued processing, such as dielectric fill around the transferred IC components 306, planarization, selective transfer or pick and place attachment of additional IC dies or other IC components, via formation, formation of interconnect / metallization layers, attaching a structural substrate, debonding the receptor substrate (e.g., via an optional receptor release layer 312), and / or any other processing required for the finished product (e.g., an IC package).

[0079] Figure 3A-Figure 3I The elements marked with reference numerals in the Figure 1A-Figure 1I Furthermore, it should be understood that the illustrated process flow for selective layer transfer is presented as an example only, and that many other process variations are possible, including but not limited to those described throughout this disclosure.

[0080] Figure 4A-4C An exemplary process flow for selective layer transfer from multiple donor substrates is shown. In the example shown, integrated circuit (IC) components 414, 434 are selectively transferred from multiple donor substrates 410, 430 to an acceptor substrate 450 using intermediate carrier substrates 420, 440. In some embodiments, the respective donors 410, 430 may have different types of IC components 414, 434, such as different types of IC dies or core particles. In this way, selective layer transfer can be used to transfer multiple types of IC components (e.g., different types of dies or core particles) to the same acceptor substrate 450. Although the example shown depicts selective transfer from two types of donor substrates 410, 430 (e.g., having two types of IC components 414, 434), any number of donor substrates having any type of IC die or other components (including having different die sizes) are possible.

[0081] exist Figure 4A4. In the process of selectively transferring IC components 414 from a first donor substrate 410 to an intermediate carrier substrate 420, a layer of IC components 414 is selectively transferred from a first donor substrate 410 to an intermediate carrier substrate 420 (e.g., using any of the selective transfer processes described throughout this disclosure). For example, a release layer 412 is formed on the donor substrate 410. Then, the selectively transferred layer 414 is formed on the release layer 412 (e.g., by directly fabricating the layer 414 or blanket transferring the layer 414 from a wafer to the donor carrier 410) and cut into partially singulated IC components 414. Separately, a release layer 422 is formed on the intermediate carrier / receiver substrate 420, and a bonding template 424 is formed on a surface of the intermediate carrier 420 (e.g., above the release layer 422). The donor 410 and the intermediate carrier 420 are then partially bonded together (e.g., the target IC component 414 located on the donor 410 is bonded to a bonding feature or bonding area 424 located on the intermediate carrier 420). The donor 410 and the intermediate carrier 420 are then debonded and separated from each other using any of the techniques described throughout this disclosure (e.g., selective release, blanket laser exposure, etc.). As a result, the target IC component 414 is debonded / separated from the donor 410 and remains on the intermediate carrier 420.

[0082] exist Figure 4B 4, another layer of IC components 434 is selectively transferred from a second donor substrate 430 to another intermediate carrier substrate 440 (e.g., using any of the selective transfer processes described throughout this disclosure). For example, a release layer 432 is formed on the donor substrate 430. Then, the selectively transferred layer 434 is formed on the release layer 432 (e.g., by directly fabricating the layer 434 or blanket transferring the layer 434 from the wafer to the donor carrier 430) and cut into partially singulated IC components 434. Separately, a release layer 442 is formed on the intermediate carrier / acceptor substrate 440, and a bonding template 444 is formed on the surface of the intermediate carrier 440 (e.g., above the release layer 442). The donor 430 and the intermediate carrier 440 are then partially bonded together (e.g., the target IC component 434 located on the donor 430 is bonded to a bonding feature or bonding area 444 located on the intermediate carrier 440). The donor 430 and the intermediate carrier 440 are then debonded and separated from each other using any of the techniques described throughout this disclosure (e.g., selective release, blanket laser exposure, etc.). As a result, the target IC component 434 is debonded / separated from the donor 430 and remains on the intermediate carrier 440.

[0083] exist Figure 4C, IC components 414, 434 located on both intermediate carriers 420, 440 are selectively transferred to an acceptor substrate 450 (e.g., using any selective transfer process described throughout this disclosure). For example, optionally, a release layer 452 is formed over the acceptor substrate 450 (e.g., in the case where the selectively transferred IC components 414, 434 will subsequently be debonded from the acceptor substrate 450 after transfer). Then, a bonding layer 454 (e.g., having bonding areas / bonding features) is formed on the surface of the acceptor 450 (e.g., above the release layer 452, if included). Next, the IC component 414 located on the first intermediate carrier 420 is selectively transferred to the acceptor substrate 450 (e.g., using any selective transfer process described throughout this disclosure). Finally, the IC component 434 located on the second intermediate carrier 440 is selectively transferred to the acceptor substrate 450 (e.g., using any selective transfer process described throughout this disclosure).

[0084] Additional processing may then be performed on the receptor substrate 450, such as cleaning steps (e.g., removing residual bonding structures 424, 444 from the transferred IC components 414, 434), dielectric fill around the transferred IC components 414, 434, planarization, selective transfer or pick and place attachment of additional IC dies or other IC components, via formation, formation of interconnect / metallization layers, attaching a structural substrate, debonding the receptor substrate (e.g., via an optional receptor release layer 452), and / or any other processing required for the finished product (e.g., an IC package).

[0085] It should be understood that the illustrated process flow for selective layer transfer is presented by way of example only, and that numerous other process variations are possible, including but not limited to those described throughout this disclosure.

[0086] Figure 5A-5FAn exemplary process flow for forming an integrated circuit (IC) package 500 having a selectively transferred passive interposer 506 is shown. Selective transfer can be used for a variety of applications, including transfer of active components (e.g., IC die, transistors, diodes) and passive components (e.g., interconnects, metal-insulator-metal (MIM) cores, resistors, capacitors, inductors, transformers). In the example shown, the process flow is used to form an IC package 500 having a selectively transferred, low-cost passive interposer 506. For example, an interposer 506 having a high-density die-to-die (D2D) link 508 is created on a donor wafer 502 and then selectively transferred to a recipient wafer 512, which enables the same donor wafer 502 to be reused multiple times and the cost of the interconnect device to be amortized over multiple recipient wafers 512. In some embodiments, other components of the IC package 500, such as IC die 518a-518b, may also be selectively transferred. Selective transfer can also be used for other applications including, but not limited to, transfer of photonic / optical components, and localized transfer of III-V semiconductors for radio frequency (RF) and high power devices.

[0087] exist Figure 5A In the embodiment of the present invention, a repeating D2D interconnect pattern 506 is created on a release layer 504 of a donor substrate 502, and the resulting D2D interconnects are partially singulated (eg, cut to the donor substrate 502, but not through the donor substrate 502). The D2D interconnects 506 include high-density interconnect links 508 separated by dielectric layers 510.

[0088] exist Figure 5B , a transfer template 516 for selective transfer is created on a release layer 514 of an acceptor / carrier substrate 512. The transfer template 516 includes dielectric bonding protrusions 516 (referred to as mesas) located on the surface of the acceptor substrate 512. However, in various embodiments, any suitable surface treatment or other technique may be used to control the adhesion level on different areas of the acceptor substrate 512 (e.g., to form bonding areas and non-bonding areas for selective transfer), including but not limited to: surface topography changes (e.g., mesas, depressions), use of materials with high adhesion and / or low adhesion, treatment with hydrophobic materials and / or self-assembled monolayers (SAMs), and / or surface activation techniques, among other examples. In addition, in various embodiments, any number of buildup layers may be formed on the acceptor substrate 512 prior to forming the templated connection base or mesas 516 for selective transfer.

[0089] The bonding mesas 516 are used to selectively transfer the D2D interconnects 506 from the donor 502 to the receptor 512 (e.g., using any selective transfer process described throughout this disclosure). For example, the donor 502 and the receptor 512 are aligned face-to-face, stacked, and then partially bonded together so that one of the D2D interconnects 506 located on the donor 502 is bonded to the bonding mesas 516 located on the receptor 512.

[0090] exist Figure 5C In the embodiment, the D2D interconnect 506 bonded to the acceptor mesa 516 is debonded and / or released from the donor release layer 504 using any of the techniques described herein (e.g., selective release, blanket laser exposure, formation of a bond with intensity difference), and the donor 502 and the acceptor 512 are mechanically separated. As a result, the transferred D2D interconnect 506 is separated from the donor 502 and remains on the acceptor 512.

[0091] exist Figure 5D In the process, additional processing is performed to form the remaining interconnects, which additional processing includes dielectric (e.g., oxide) filling 510 and planarization, interconnect 508 patterning / metallization (e.g., forming through dielectric vias (TDVs) 508, top metal contacts 508 (e.g., hybrid bonding pads), dielectric layers 510), etc.

[0092] It is worth noting that since the D2D interposer 506 is selectively transferred and the surrounding dielectric layer 510 is directly fabricated on the receptor 512, Figure 5D As shown, there is a gap 511 between the transferred D2D interposer 506 and the surrounding layer 510. Generally speaking, since this type of gap or transition is not formed simultaneously with the surrounding layer, they may exist around any type of selectively transferred component.

[0093] exist Figure 5E In the embodiment, multiple IC dies 518a-518b are attached to a top metal pad 508 (e.g., via hybrid bonding), the area around the dies 518a-518b is filled with a dielectric material 510 (e.g., oxide) and planarized, and a structural substrate 520 (e.g., a structural silicon wafer) is attached.

[0094] The dies 518a-518b may be attached using standard assembly techniques (eg, pick and place) or using the selective transfer techniques described herein (eg, similar to the transferred D2D interconnect 506).

[0095] If the dies 518a-518b are attached using pick and place assembly, they are typically formed on a thick substrate for handling purposes and subsequently thinned after attachment.

[0096] However, if the die 518a-518b are selectively transferred, they can be formed on a very thin substrate and transferred directly from the very thin substrate. Therefore, selectively transferring the die 518a-518b not only eliminates the need for post-attachment thinning, but also enables the die 518a-518b to be much thinner than a die that is picked and placed for attachment and subsequently thinned. In addition, if the die 518a-518b are selectively transferred, there may be a gap 511 between the die 518a-518b and the portion of the layer 510 surrounding the die 518a-518b, similar to the gap 511 shown around the transferred D2D interconnect 506 as described above. In addition, since the die 518a-518b are selectively transferred, they can be different types of die, formed on separate substrate material sheets (e.g., separate wafers or panels) using separate processes, and then selectively transferred to the same layer of the IC device 500.

[0097] exist Fig. 5F In the process, receptor 512 is debonded and released from release layer 514 (eg, using any of the techniques described herein, such as IR or UV laser ablation).

[0098] At this point, IC package 500 may be completed, or alternatively, additional processing may be performed. For example, if processing is performed at the wafer level or panel level, the resulting IC package 500 on structural substrate 520 may be singulated.

[0099] Figure 6A-6B An example of selective layer transfer between a donor wafer 600 and an acceptor wafer 610 is shown. Specifically, Fig. 6A 6 shows wafers 600, 610 before transfer, and Figure 6B Wafers 600, 610 are shown after transfer. In the example shown, non-contiguous regions of the donor wafer 600 are selectively transferred to non-contiguous locations on the acceptor wafer 610. However, in other embodiments, the target region on the donor 600 and the target region on the acceptor 610 may be partially or completely contiguous.

[0100] like Fig. 6AAs shown, prior to transfer, the donor wafer 600 includes a layer of integrated circuit (IC) components 602 (e.g., dies, core particles, interconnects, capacitors, transistors, etc.), which may be partially singulated (e.g., cut down to the underlying wafer 600, but not through the underlying wafer 600). The acceptor wafer 610 includes bonding areas 612 (also referred to as a bonding template) patterned in non-contiguous locations on the surface, which is where the target IC components 602 from the donor 600 will be transferred. For example, in some embodiments, the bonding areas 612 can be raised structures or protrusions (referred to as "mesas") patterned on the surface of the acceptor 612. In addition, in some embodiments, the bonding areas 612 on the acceptor 610 can have a similar footprint as the target IC components 602 on the donor 600. However, in various embodiments, any suitable surface treatment or other technique may be used to control the adhesion levels on different areas of the receptor substrate 610 (e.g., to form adhesion areas and non-adhesion areas for selective transfer), including but not limited to: surface topography changes (e.g., terraces, depressions), use of materials with high adhesion and / or low adhesion, treatment with hydrophobic materials and / or self-assembled monolayers (SAMs), and / or surface activation techniques, among other examples.

[0101] like Figure 6B As shown, after transfer, the target IC components 602 have been transferred from the donor wafer 600 to the acceptor wafer 610. Therefore, the donor wafer 600 includes a blank area 603 where the transferred IC components 602 are located, and the acceptor wafer 610 includes the transferred IC components 602 at locations where the bonding areas 612 are patterned. Specifically, the individual IC components 602 from the donor wafer 600 are now bonded to the individual bonding areas 612 on the acceptor wafer 610.

[0102] Although the illustrated example depicts selective transfer between two wafers, selective transfer may be performed between panels or other substrates of any shape or size, including substrates having non-matching shapes and sizes.

[0103] Figure 7A flow chart 700 for performing a selective layer transfer is shown. In accordance with the present disclosure, it will be understood that the process flow shown is only an exemplary method for performing a selective layer transfer. In addition, the steps of the process flow shown can be performed using any suitable semiconductor fabrication technology. For example, film deposition - such as depositing a layer, filling portions of a layer (e.g., removed portions), and filling via openings - can be performed using any suitable deposition technology (e.g., including chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), atomic layer deposition (ALD), and / or physical vapor deposition (PVD)). In addition, patterning and removal - such as interconnect patterning, forming via openings, and shaping - can be performed using any suitable technology (e.g., lithography-based patterning / masking and / or etching).

[0104] The flow chart begins at block 702 with receiving a first substrate having a layer of integrated circuit (IC) components, which may be referred to as a donor substrate. In some embodiments, the donor substrate may include a base substrate, a release layer located on the base substrate, and a (partially singulated) layer of IC components located on the release layer.

[0105] In some embodiments, a donor substrate can be formed by receiving a base substrate, forming a release layer over the base substrate, forming layers of IC components over the release layer (e.g., by forming or transferring the layers of IC components onto the release layer), and partially singulating the layers of IC components (e.g., by cutting through the layers of IC components without cutting through the base substrate).

[0106] In various embodiments, a layer of an IC component may include one or more IC dies, interconnects, transistors, diodes, resistors, capacitors, inductors, transformers, optical components, and / or any other active or passive circuitry or components.

[0107] The base substrate may be made of one or more materials including elements such as silicon (Si), oxygen (O), carbon (C), hydrogen (H), and / or Group III-V elements (e.g., aluminum (Al), gallium (Ga), indium (In), nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb)), including but not limited to silicon (Si), silicon dioxide (SiO2 or SiO 2 ), silicon on insulator (SOI), quartz, glass, III-V materials (e.g., gallium nitride (GaN), aluminum gallium nitride (GaN), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium phosphide (InP)), and epoxies / resins (e.g., IR or UV transparent epoxies).

[0108] The release layer may include one or more layers of different materials, depending on the type of release or debonding technique used. For example, for IR laser debonding, the release layer may include one or more layers of materials that can absorb and / or reflect infrared (IR) electromagnetic radiation, such as a thin metal layer or multiple metal layers (e.g., aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN)). For UV laser debonding, the release layer may include one or more layers of materials that can absorb ultraviolet (UV) electromagnetic radiation (e.g., an organic polymer such as polyimide). In some embodiments, the release layer may additionally or alternatively include one or more layers of dielectric materials, such as silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), aluminum oxide (Al 2 O 3 ), low-k dielectrics such as carbon-doped oxide (CDO) or porous silicon dioxide (SiO 2 ), titanium dioxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 )) to buffer laser ablation and thermal energy, control thin film interference or adhesion, and / or provide residual adhesion after other materials and / or layers in the release layer are weakened, removed and / or ablated by the laser. Therefore, in some embodiments, the (multiple) release layers can be made of one or more materials, which include elements such as aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), silicon (Si), oxygen (O), nitrogen (N), hydrogen (H) and carbon (C), including but not limited to any of the materials cited above.

[0109] The flow chart then proceeds to block 704 to receive a second substrate having one or more bonding areas, which may be referred to as an acceptor substrate. In some embodiments, the acceptor substrate may include a base substrate having one or more bonding areas patterned on a surface (e.g., a layer of raised bonding structures or "mesas" located above the base substrate). The acceptor substrate may also optionally include a release layer located above the base substrate (e.g., to enable subsequent debonding of the base substrate after transfer) and / or one or more additional buildup layers and / or IC components.

[0110] In some embodiments, the acceptor substrate can be formed by receiving a base substrate, optionally forming a release layer over the base substrate, optionally forming additional buildup layers and / or IC components over the base substrate (e.g., over the optional release layer, if included), and forming bonding areas (e.g., bonding structures) on a surface of the acceptor substrate (e.g., over the layers cited above, if included). In some embodiments, the base substrate and optional release layer of the acceptor can be made of any of the materials cited above for the base substrate and release layer of the donor, respectively.

[0111] In some embodiments, the bonding area may include a mesa structure having a similar footprint as the corresponding IC component to be transferred from the donor (although in some cases, the mesa may be slightly larger or smaller than the IC component to accommodate alignment and manufacturing tolerances). The mesa structure may be made of different materials (e.g., dielectric materials, metals, or both), depending on the type of bonding and / or whether electrical connection through the bonding cross section is required for the subsequently bonded IC component. For example, the mesa structure may include a blanket dielectric structure without conductive contacts (e.g., for dielectric-to-dielectric bonding), a dielectric structure with conductive contacts (e.g., for mixed dielectric and metal bonding), and / or itself includes conductive contacts (e.g., for metal-to-metal bonding). Thus, in some embodiments, the mesa structure may be made of one or more materials including elements such as silicon (Si), oxygen (O), hydrogen (H), nitrogen (N), carbon (C), aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), including but not limited to: inorganic dielectrics (e.g., silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), and / or silicon carbon nitride (SiCN)), organic dielectrics (such as photoresists and adhesives), and / or conductive materials (such as metals and alloys (for example, any of the above-mentioned metal elements and / or their compounds / alloys)).

[0112] However, in various embodiments, any suitable technique(s) may be used to control the adhesion level on different regions of the receptor substrate. For example, various surface treatments (e.g., photolithography or additive manufacturing) may be used to enhance and / or reduce adhesion of selected regions of the receptor substrate, including, but not limited to: modifying the surface topography (e.g., raised regions versus recessed regions, smooth regions versus rough regions), using materials with high adhesion and / or low adhesion (e.g., forming a layer with adhesive material and non-adhesive material in the selected regions), using treatments with hydrophobic materials and / or self-assembled monolayers (SAMs), and / or surface activation techniques (e.g., plasma or wet activation), among other examples.

[0113] For example, the surface topography of the receptor substrate can be modified (e.g., using techniques such as deposition, lithography, etching, roughening) to form regions with different adhesion levels, such as raised (e.g., adhesion) regions and recessed (e.g., non-adhesion) regions, smooth (e.g., adhesion) regions and rough (e.g., non-adhesion) regions, etc.

[0114] As another example, the surface of the receptor substrate may be patterned with a material that has high adhesion and / or low adhesion in selected areas. For example, a layer patterned with different areas of adhesive material and non-adhesive material may be formed on the receptor substrate. In some embodiments, the adhesive material may include: silicon dioxide (SiO 2 ) or silicon nitride carbon (SiCN) to promote strong oxide fusion bonding, silicon carbide (SiC) to provide a higher strength than SiO 2 or SiCN for lower thermal contact resistance, and / or metal to form an electrical connection. In addition, in some embodiments, the non-adhesive material may include silicon nitride (Si 3 N 4 ) to form a weak bond or no bond.

[0115] As another example, treatment with a hydrophobic material and / or a self-assembled monolayer (SAM) can be used to enhance and / or reduce adhesion in selected areas of a receptor substrate (e.g., using a SAM treatment to create a monolayer with high adhesion and / or low adhesion in selected areas). In some embodiments, the hydrophobic material can include a SAM material, such as an alkyl or fluoroalkyl silane (e.g., ODS, FDTS), a thiol (e.g., hexadecyl mercaptan), a phosphoric acid (e.g., octadecyl or perfluorooctane phosphoric acid), or an alkanoic acid (e.g., heptadecanoic acid). However, non-SAM based materials or membranes can also be used. In some embodiments, the hydrophobic material can include a polymer film, such as a siloxane (e.g., PDMS and derivatives, HMDSO), a silazane (HMDS), a polyolefin (e.g., PP), or a fluorinated polymer (e.g., PTFE, PFPE, PFDA, C4F8 plasma polymerized membrane, etc.). In other embodiments, other hydrophobic materials can be used.

[0116] As another example, surface activation techniques may be used to enhance and / or reduce adhesion in selected areas of the receptor substrate, including but not limited to plasma or wet activation.

[0117] The flow chart then proceeds to block 706 to partially bond the donor substrate (e.g., face-to-face) to the acceptor substrate such that one or more target IC components located on the donor substrate are selectively bonded to one or more bonding regions located on the acceptor substrate. The donor substrate and the acceptor substrate may be partially bonded using any suitable bonding technique, including, but not limited to, hybrid bonding, fusion bonding, and / or adhesive bonding.

[0118] The flow chart then proceeds to block 708 to release the target IC component from the donor substrate and separate the donor substrate from the acceptor substrate. In this way, when the donor substrate and the acceptor substrate are separated, the target IC component is separated from the donor substrate and remains on the acceptor substrate.

[0119] In some embodiments, the donor substrate and the acceptor substrate can be debonded / separated from each other by at least partially releasing the target IC component from the release layer of the donor substrate and then mechanically separating the donor substrate from the acceptor substrate. For example, in some embodiments, the target IC component can be completely released from the donor substrate by selectively debonding the target IC component from the donor release layer using a laser (e.g., an IR or UV laser); or alternatively, the target IC component can be partially released from the donor substrate by weakening the donor release layer using a laser (e.g., an IR or UV laser). After fully or partially releasing the target IC component from the donor, the donor substrate and the acceptor substrate are mechanically separated, and after separation, the target IC component remains bonded to the acceptor and is no longer located on the donor.

[0120] Alternatively or additionally, the donor release layer and receptor bonding structure can be formed of corresponding materials having different bonding strengths so that the target IC component has a stronger bond with the receptor than with the donor, so that when the donor and receptor are mechanically separated, the target IC component is debonded from the donor and remains on the receptor.

[0121] The flowchart then proceeds to box 710 to perform any remaining processing, such as dielectric fill and planarization, attaching additional IC dies or components (e.g., via selective transfer or pick and place assembly), forming interconnects (e.g., vias, traces), attaching the structure substrate, debonding the receptor base substrate (e.g., via an optional receptor release layer), and / or any other processing required for the completed product (e.g., IC package, device, system, etc.).

[0122] The finished product may include a variety of components and circuit systems (some of which may have been selectively transferred), including electrical components (e.g., electronic integrated circuits (EICs), processors, XPUs, controllers, memories), optical components (e.g., optical interfaces, photonic integrated circuits (PICs), optical connectors, optical fibers), and / or radio frequency (RF) or high voltage components (e.g., high voltage electrostatic discharge (ESD) devices, power amplifiers (PAs), low noise amplifiers (LNAs), voltage controlled oscillators (VCOs), surface acoustic wave (SAW) / bulk acoustic wave (BAW) devices or filters, bandpass filters (BPFs), intermediate frequency (IF) amplifiers, frequency synthesizers, mixers, RF digital-to-analog converters (DACs), RF analog-to-digital converters (ADCs), thick gate oxide devices, III-V devices / chiplets, passive RF devices (e.g., interconnects, antennas, and inductors)).

[0123] Furthermore, in some embodiments, the resulting IC package or product can be electrically coupled to a circuit board and / or incorporated into an electronic device or system (eg, with other electronic components).

[0124] At this point, the flow chart can be completed. However, in some embodiments, the flow chart can be restarted, and / or some boxes can be repeated. For example, in some embodiments, the flow chart can be restarted at box 702 to continue to perform selective transfer.

[0125] Blanket wafer laser exposure for rapid selective transfer

[0126] As discussed above, transferring selective areas or dies from a donor substrate to a recipient substrate addresses the shortcomings of existing methods (e.g., full layer transfer, monolithic IC fabrication, die pick and place assembly) and enables multiple reuse of the donor substrate. For example, full wafer layer transfer requires removal of unwanted areas after the transfer, which results in higher costs and lower performance. In addition, pick and place die bonding has lower yields as dies become smaller and more dies are attached, and the ability to scale down die area and thickness is limited because dies / die with certain design parameters (e.g., high aspect ratio dies, sub-millimeter dies, thin dies / layers) cannot be attached using pick and place.

[0127] While selective transfer alleviates the aforementioned limitations of existing methods, it also faces its own unique challenges. For example, in some cases, especially when the transferred area is reduced in size (e.g., die size <1 mm 2 ), selective debonding (e.g., using laser debonding techniques to release only selective areas from the donor wafer) may be slow, and the percentage of donor wafer transferred to each acceptor wafer (%xfer) becomes lower.

[0128] Another challenge involves handling the wafers for selective debonding processing after bonding the donor and acceptor, which requires an in-plane offset between the wafers for all transfers after the first acceptor wafer. During transportation in a semiconductor factory, automated handling systems and the front opening wafer transfer box (Front Opening Unified Pod, FOUP) that holds the wafers cannot accept these non-circular offset bonded wafer pairs. In addition, existing equipment or tools cannot perform selective debonding on wafer pairs, and even if such equipment or tools are developed, it is impossible to transfer offset bonded wafer pairs between bonding tools and selective debonding tools. Solving the problem of offset bonded wafers requires integrating bonding, selective layer release and debonding into a single tool, which is complex and challenging, and also requires the development of new wafer handling robots to handle offset bonded wafers in the tool, which is even more challenging.

[0129] Thus, the present disclosure shows embodiments of rapid selective layer transfer using blanket wafer laser exposure, including processes, thin film architectures, and tools. For example, a thin structured film is made beneath the selectively transferred layer or die so that blanket laser exposure of the entire wafer is performed only once, after which a bonding / debonding process is used to selectively transfer regions from the donor wafer for each acceptor wafer. This eliminates the slow process of selectively debonding small regions of the wafer each time it is transferred to the acceptor wafer. In addition, the solution utilizes a novel bonding / debonding tool that eliminates any need to handle non-circular offset bonded wafer pairs.

[0130] The described solution provides various advantages. For example, the solution eliminates the slow process of selectively debonding small areas of the wafer each time a transfer is made to a recipient wafer - instead, only a blanket laser exposure of each donor wafer is required using a standard laser debonding tool. The selective transfer from the donor to each recipient wafer is controlled by selective bonding to a patterned bonding area (e.g., a table or other bonding mechanism) on the recipient wafer, which is a fast full-wafer process. Because the recipient wafer can be bonded to a pre-exposed donor wafer and then immediately debonded using selective transfer in the same module, the bonding / debonding tool eliminates any need to handle non-circular offset-bonded wafer pairs. In addition, the thin film release layer architecture can be designed to protect the die edges and corners from shock wave damage.

[0131] Figure 8A-8EAn exemplary process flow for selective transfer using blanket wafer laser exposure is shown. In the example shown, a blanket laser exposure of the donor wafer 800 is performed once (e.g., in a standard laser debonding tool) to weaken the release layer 802, after which the donor wafer 800 and the acceptor wafer 810 are selectively bonded / debonded (e.g., using Fig.11 Selective bonding / debonding tool 1100).

[0132] exist Fig. 8A In the embodiment of the present invention, a donor wafer 800 is formed, wherein the selective transfer layers 804a-804b are located on a release layer 802. The release layer 802 may include one or more thin film layers (e.g., a thin metal layer capable of absorbing infrared (IR) light) that enable laser debonding of the selective transfer layers 804a-804b, and / or structured dielectric and metal layers (e.g., similar to Figures 9A-10C The release layers 902, 1002 in FIG. Figure 8A-8E , a continuous blanket release layer 802 is shown, but in other embodiments, the release layer 802 may include a patterned layer etched through some or all of those layers located between the regions 804a-804b to be selectively transferred (e.g., Figures 9A-10C Multiple dielectric and metal layers in a “street pattern” (as shown).

[0133] The selective transfer layer 804a-804b may include any combination of one or more layers to be selectively transferred. In the example shown, the selective transfer layer 804a-804b includes a plurality of IC components 804a-804b, such as dies or core particles, and the plurality of IC components 804a-804b will be transferred to two different receptor wafers 810a-810b by two selective transfers (e.g., each transfer %xfer=50%). Specifically, a first group of IC components 804a will be transferred to a first receptor 810a, and a second group of IC components 804b will be transferred to a second receptor 810b. For example, in some embodiments, the two groups of IC components 804a-804b can be dies of the same type or dies of different types, transferred to different receptors 810a-810b by separate transfers.

[0134] exist Figure 8B In the embodiment, a laser debonding tool 820 is used to perform a blanket scan of the donor wafer 800 using laser exposure, which removes portions of the release layer 802 and / or weakens its structural integrity while still providing residual adhesion to the die / layers 804a-804b to be selectively transferred.

[0135] exist Figure 8C, a donor wafer 800 is partially or selectively bonded to a first acceptor wafer 810a (e.g., using a bonding / debonding tool 1100), having templated bonding areas 812 on its surface. For example, a target IC component 804a for a first transfer from the donor 810a is bonded to the bonding area 812 on the acceptor 810a, while other IC components 804b remain unbonded. In the illustrated embodiment, the bonding area 812 is a raised bonding mesa. However, in other embodiments, the bonding area 812 can be formed using any suitable surface treatment or other technique to control the bonding level in different areas of the acceptor substrate 810a-810b, including but not limited to: surface topography changes (e.g., mesas, depressions), the use of materials with high and / or low adhesion, the use of hydrophobic materials and / or self-assembled monolayer (SAM) treatments, and / or surface activation techniques, and other examples.

[0136] exist Fig.8D , the donor wafer 800 is mechanically separated and debonded from the acceptor wafer 810a (e.g., using the bonding / debonding tool 1100). Specifically, due to the weakened release layer 802, when the donor wafer 800 and the acceptor wafer 810a are mechanically separated, the target IC component 804a is debonded from the donor 800 and remains on the acceptor 810a. This is because the bond to the acceptor 810a is stronger than the residual bond to the donor 800 because the bonding energy provided by the mesa 812 is greater than the residual bonding energy provided by the weakened release layer 802.

[0137] exist Fig. 8E In the process, the first acceptor wafer 810a is transferred away and the second acceptor wafer 810b is transferred in for the next selective transfer, and the process is repeated. Figure 8C and Fig.8D The steps in the above step can be repeated to transfer another set of IC components 804b to a new receptor 810b (e.g., by selectively bonding / debonding the donor 800 and the receptor 810b). This method can be repeated for any number of receptor wafers 810 as needed. Figure 8C and Fig.8D Steps in .

[0138] Figure 9A-9DAn exemplary process flow for selective transfer using a structured release layer 902 having residual adhesion anchors 903 is shown. In general, the residual adhesion remaining in the release layer 902 after a blanket laser release process can be controlled by adjusting the pitch and pulse energy of the laser during exposure, but this approach may be unreliable with variations in products and wafer to wafer and wafer to wafer variations. As a result, some of the selectively transferred areas may accidentally debond from the donor wafer during or after performing the blanket laser release (e.g., during subsequent processing). Therefore, in the example shown, the laser release layer 902 is patterned with dielectric anchors 903 that do not absorb the laser light 920, which remain after the blanket laser release to maintain bonding between the die 904a-904b (or other components / regions / layers) and the donor wafer 900 over a relatively small percentage of the die area. In this way, during the transfer of the donor wafer 900 to the bonding / debonding tool 1100, the residual anchor 903 provides sufficient adhesion to the tube core 904a-904b, but the residual adhesion energy will still be less than the bonding energy with the acceptor wafer 910, thereby enabling the tube core 904a-904b to be selectively transferred to the templated acceptor wafer 910 using the bonding / debonding tool 1100.

[0139] exist Fig. 9A In the embodiment of the present invention, a donor wafer 900 is formed, wherein a layer of tube cores 904a-904b is located on a structured release layer 902. The structured release layer 902 includes a laser absorption layer 901, and the laser absorption layer 901 is patterned with a dielectric anchor 903 transparent to the laser 920. In some embodiments, the laser absorption layer 901 may include a thin metal layer capable of absorbing infrared (IR) light, and the dielectric anchor 903 may include one or more layers of dielectric bonding film transparent to IR light. In addition, the dielectric anchor 903 is patterned through the laser absorption layer 901 to provide adhesion between the donor wafer 900 and the tube cores 904a-904b.

[0140] exist Fig. 9B In the embodiment, a laser debonding tool 920 is used to perform a blanket scan of the donor wafer 900 using laser exposure, which removes or ablates the laser absorbing layer 901 while leaving the dielectric anchor 903 intact (eg, Fig. 9C shown).

[0141] exist Fig. 9C In FIG. 9 , the dielectric anchors 903 remaining after blanket laser exposure are designed to have a lower area percentage relative to the die 904a - 904b , which enables the anchors 903 to hold the die 904a - 904b to the donor 900 with lower residual adhesion.

[0142] exist Fig.9D In the process, a donor wafer 900 is selectively bonded to an acceptor wafer 910 patterned with a bonding mesa 912 (or other type of bonding area) and then debonded from the acceptor wafer 910, which causes certain dies 904a to be bonded to the acceptor mesa 912 and completely debonded from the patterned donor anchor 903, thereby selectively transferring the dies 904a from the donor 900 to the acceptor 910.

[0143] After debonding from donor 900, selectively transferred die 904a may retain some or all of the residue from patterned release layer anchor 903 thereon. Fig.9D As shown, all of the bonding dielectric in the patterned anchor structure 903 above the transferred die 904a is debonded from the donor 900 and remains on the selectively transferred die 904a. In this way, the transferred die 904a is completely covered by the bonding dielectric from the patterned anchor structure 903 above it.

[0144] However, in other cases, some of the bonding dielectric from the anchors 903 may remain on the donor wafer 900 (e.g., anchored to a smaller portion of the donor 900), while the remainder of the bonding dielectric may remain on the selectively transferred die 904a, thereby forming a negative pattern of the anchor in the bonding dielectric on the transferred die 904a (not shown). In these cases, a layer of dielectric residue from the anchors 903 remains on the transferred die 904a, but because some of the dielectric residue may remain on the donor 900, the dielectric residue may only partially cover each die 904a.

[0145] For example, relative to Fig. 10A, which is the same anchor pattern as this example, the anchor layer 1003 is bonded to the entire surface of the die 1004, but the anchor layer 1003 is only bonded to the donor 1000 via a small anchor structure located near the center of the die 1004. After transfer, in some cases, the entire anchor structure 1003 located above the transferred die 1004 can be debonded from the donor 1000 and remain on the die 1004, thereby covering the entire surface of the transferred die 1004. Alternatively, the small anchor structure in the anchor layer 1003 can remain on the donor 1000, while the rest of the anchor layer 1003 can remain on the transferred die 1004. Thus, the layer of dielectric residue 1003 may partially cover the surface of the transferred die 1004 (except for an area near the center of the die 1004) because this portion of the dielectric residue 1003 may remain on the donor 1000. For example, from a plan view, the dielectric residue 1003 located on the transferred die 1004 may have a similar footprint as the die 1004, but have a hole near the center (e.g., Fig. 10A 1003 shown in the plan view).

[0146] Relative to Fig. 10B 1004, but the anchor layer 1003 is only bonded to the donor 1000 via the anchor structures located along the edges of the die 1004. After transfer, in some cases, the entire anchor structure 1003 located above the transferred die 1004 can be debonded from the donor 1000 and remain on the die 1004, thereby covering the entire surface of the transferred die 1004. Alternatively, a portion of the anchor layer 1003 along the edge of the die can remain on the donor 1000, while the rest of the anchor layer 1003 can remain on the transferred die 1004. Thus, the layer of dielectric residue 1003 can partially cover the surface of the transferred die 1004 (except for the edge of the die 1004) because the portion of the dielectric residue 1003 can remain on the donor 1000. For example, the dielectric residue 1003 on the transferred die 1004 may be generally centered over the die 1004 from a plan view, but have a slightly smaller footprint that may not cover the edge of the die 1004 because that portion of the dielectric residue 1003 may remain on the donor 1000 (e.g., Fig. 10B 1003 shown in the plan view).

[0147] Back to Fig.9DIt is possible to remove the dielectric residue 903 from the transferred die 904a using photolithography and etching processing, but this increases the full wafer processing cost of removing the dielectric residue 903 from a small area of ​​the wafer. Therefore, in some embodiments, the dielectric residue 903 can simply be left on the die 904a and the remaining processing can be performed as usual.

[0148] Figure 10A-10C An example of a patterned release layer structure 1002 using anchors 1003 to control residual adhesion is shown. Specifically, Fig. 10A , Fig. 10B and Fig. 10C Depicted are cross-sectional and plan views of a donor wafer 1000 having dielectric anchors 1003 patterned in a release layer 1002 at the center of a die 1004, along the edge of the die 1004, and throughout the array of die 1004. In the example shown, the cross-sectional view is based on a cutting plane 1005 shown in the plan view.

[0149] exist Fig. 10A , a release layer 1002 on a donor wafer 1000 includes a laser absorbing layer 1001 patterned with a dielectric anchor 1003, which is attached to the donor 1000 at the center of a die 1004. In various embodiments, the portion of the anchor 1003 located at the center of the die 1004 can be any shape (e.g., square, rectangular, circular, etc.).

[0150] exist Fig. 10B In the embodiment of the present invention, the release layer 1002 includes a laser absorbing layer 1001 patterned with dielectric anchors 1003, which are attached to the donor 1000 along the edges of the tube core 1004 to protect the edges from shock wave damage. For example, the dielectric anchors 1003 help protect the edges of the tube core 1004 from mechanical damage caused by the laser-induced shock wave, which may cause the edges and corners of the tube core to break. The width and total area of ​​the anchors 1003 can be adjusted to balance the residual adhesion to obtain the best selective transfer performance and reliability. For example, in some embodiments, each anchor 1003 can be a coiled spring (viewed from the top) that is unsupported except at its starting point (e.g., where the anchor 1003 is connected to the donor wafer 1000) and the end point (e.g., where the anchor 1003 is connected to the tube core 1004) to increase compliance and reduce possible damage to the tube core 1004 after release.

[0151] exist Fig. 10C, a release layer 1002 on a donor wafer 1000 includes a laser absorbing layer 1001 patterned with an array of dielectric anchors 1003 attached to the donor 1000 in an array of locations on each die 1004. In various embodiments, the anchor array 1003 (and / or individual anchors within the array 1003) can have any number of anchors, shapes, sizes, or total areas within each die 1004 (or other selectively transferred region 1004), and the anchor pattern can include structures (e.g., Figure 10A-10B Any combination of those structures in .

[0152] Fig.11 An exemplary embodiment of a bonding / debonding tool 1100 designed for selective transfer according to certain embodiments is shown. A conventional wafer-to-wafer bonding tool receives two wafers, stacks them one on top of the other, bonds them, and then transfers out a single bonded wafer pair. However, for selective transfer, the bonded wafer pair needs to be debonded to complete the transfer, which means that it needs to be transferred to a separate debonding tool. However, none of the existing debonding tools can selectively debond a pair of donor wafers and acceptor wafers for selective transfer. In addition, for all transfers from the same donor wafer except the first transfer (e.g., for transfers from a donor to the 2nd to the nth acceptor), selective transfer typically requires the donor wafer and the acceptor wafer to be bonded with an offset. Therefore, the offset bonded wafer pair will need to be transferred from the conventional bonding tool to the (non-existent) debonding tool. However, existing wafer processing systems cannot handle non-circular offset bonded wafer pairs. Thus, in the example shown, the bonding / debonding tool 1100 is designed to perform the bonding and debonding steps of the selective transfer in the same module, thereby eliminating the need to transfer the offset bonded wafer pair to a separate and non-existent debonding tool. For example, as described below, the bonding / debonding tool 1100 performs a selective transfer from a donor wafer 1110 to an acceptor wafer 1120 by bonding the acceptor 1120 to the donor 1110 and then immediately debonding the wafers 1110, 1120.

[0153] In the illustrated embodiment, the bonding / debonding tool 1100 introduces the donor wafer 1110 and the acceptor wafer 1120 separately (e.g., via a robotic arm), holds the donor wafer 1110 in position on its own wafer chuck 1102, selectively bonds the wafers 1110, 1120 (e.g., bonding the donor die 1114a to the acceptor mesa 1122 (or other type of bonding area)), and then removes the acceptor wafer 1120 immediately after bonding (e.g., via vacuum lift-off), thereby debonding the acceptor 1120 from the donor 1110. In this way, the bonding and debonding functions are integrated into a single module.

[0154] Additionally, acceptor wafers 1120 are sequentially transferred in, bonded, mechanically separated, and then transferred out while the donor wafer 1110 is held in place on the chuck 1102. In this way, multiple acceptor wafers 1120 can be cycled through the bonding / debonding process while the donor wafer 1110 remains in the module.

[0155] Furthermore, because the bond / debond tool 1100 performs the bonding and debonding functions in the same module and then transfers the acceptor wafer 1120 by itself, offset bonded wafer pairs are not transferred, thereby eliminating the need to modify automated handling systems to support offset bonded wafer pairs.

[0156] In the example shown, the donor wafer 1110, the release layer 1112, the dies 1114a-1114b, the acceptor wafer 1120 and the bonding table 1122 can be similar to the elements with similar names in other figures. In addition, it should be understood that the bonding / debonding tool 1100 shown for selective transfer is shown only as an example, and numerous variations are possible. For example, in some embodiments, the acceptor wafer 1120 can be kept in the appropriate position on its own wafer chuck during the bonding process. In addition, any type of bonding can be used to bond the donor wafer 1110 and the acceptor wafer 1120 (e.g., hybrid bonding, fusion bonding, heat / pressure bonding). In addition, after the wafers 1110 and 1120 are bonded, any appropriate technology (e.g., vacuum lift-off) can be used to mechanically separate the acceptor wafer 1120 from the donor wafer.

[0157] Figure 12A-12C Various laser release techniques for selective transfer are shown. Specifically, Fig. 12A , Fig. 12B and Fig. 12C Cross-sectional views and plan views of the donor wafer 1200 are depicted when performing selective scanning and laser exposure, blanket scanning and selective laser exposure, and blanket scanning and laser exposure techniques, respectively.

[0158] In the example shown, various laser release techniques are performed on a donor wafer 1200 , wherein a layer of integrated circuit (IC) dies 1204 a - 1204 b is located above a release layer 1202 .

[0159] exist Fig. 12A In the method, laser release is performed using selective scanning and laser exposure techniques. As depicted by laser path 1222, the donor wafer 1200 is selectively scanned and exposed to the laser 1220 (e.g., using a galvanometer) over the areas of the release layer 1202 that are bonded to the target tube core 1204a to be transferred, thereby removing or weakening these areas of the release layer 1202 for subsequent transfer. Since the method has a very short scan length and each tube core 1204a requires multiple changes in direction, the method is relatively slow, where each change in direction requires approximately 1 millisecond (ms) and there are multiple translations between the selective release areas. As a result, as the tube core 1204a-1204b becomes smaller, the average scan speed becomes slower. In addition, for each transfer to the recipient wafer, the selective release process must be repeated on the donor wafer 1200. The method also requires complex integration of bonding, selective laser release, and transfer of wafer pairs that are debonded and offset bonded.

[0160] exist Fig. 12B In the embodiment of the present invention, laser release is performed using blanket scanning and selective laser exposure techniques. As depicted by laser path 1222, the entire donor wafer 1200 is blanket scanned, but only the area of ​​the release layer 1202 bonded to the target die 1204a is selectively exposed to the laser 1220. For example, during the blanket scan, the laser 1220 can be exposed when scanning over the target die 1204a and turned off when scanning over the unselected die 1204b. This method is more convenient than Fig. 12A The method in is faster because fewer directional changes are required to scan the entire donor wafer 1200. However, although the entire donor wafer 1200 is scanned, only the target die 1204a is released during the scan. Therefore, for each transfer to the recipient wafer, this method requires a full donor wafer scan. The transfer time per die of this method can be calculated as follows: Where "%xfer" represents the percentage of dies (or other selectively transferred components) on the donor wafer that are transferred to each recipient wafer. The transfer time per die increases as the transfer percentage (%xfer) decreases. For example, if only 1 die out of every 10 dies on the donor is transferred at a time, the transfer percentage (%xfer) is 10%, which increases the transfer time per die because more transfers are required. This method also requires complex integration of bonding, selective laser release, and debonding and transfer of offset bonded wafer pairs.

[0161] exist Fig. 12C In the embodiment of the present invention, laser release is performed using a blanket scan and laser exposure technique. As depicted by the laser path 1222, the entire donor wafer 1200 is blanket scanned and exposed to the laser 1220, thereby weakening the entire release layer 1202 while still providing residual adhesion for the dies 1204a-1204b. In this way, each donor wafer 1200 only needs to undergo a blanket wafer scan / exposure once. Therefore, this method is significantly faster than Figure 12A-12B As an example, for 1mm 2 For a die size of 1000 mm / s, this method may take approximately 3.6 ms per die. Laser release may be performed using a standard laser debonding tool, while subsequent bonding / debonding to a receptor wafer may be performed using the bonding / debonding tool 1100, which provides a much simpler construction than other methods and does not require wafer handling for offset bonding.

[0162] Fig.13 A graph 1300 showing laser debonding times for selective transfer using various laser debonding techniques is shown. Specifically, graph 1300 shows laser debonding times (minutes) for each donor wafer based on square die size (mm) (e.g., length / width of a square die, such as 1×1 mm, 2×2 mm, etc.). The laser debonding time represents the total time to debond or partially release all dies (or other components) on a donor wafer using a 40 μm pitch IR debonding laser (e.g., total laser release process scan time for each donor wafer, excluding the time required for the bonding / separation step with the recipient wafer). For other laser debonding tools (e.g., a UV debonder), the time values ​​will be different, but the relative comparison is generally applicable to all laser debonding tools.

[0163] For selective scanning / exposure 1301, the debonding time per donor wafer increases exponentially as die size decreases and is very low for wafers smaller than 3 mm. 2 For example, for 3-10mm 2 The debonding time ranges from 6 to 13 minutes for die sizes approaching 1 mm. 2 When , the decoupling time increases to more than 30 minutes.

[0164] The debonding time for each donor wafer is shown for 50% and 10% transfer percentages, respectively, for blanket scan / selective exposure 1302, 1303. For 50% transfer percentage, the process time 1302 is reasonable (~8.5 minutes), but as the transfer percentage is reduced to 10%, the process time 1303 for the entire donor wafer increases to over 40 minutes.

[0165] For blanket scan / exposure 1304, the process time is independent of die size and transfer percentage since only one full wafer blanket scan / exposure is required regardless of die size and transfer percentage. Therefore, this is the fastest method and requires less than 5 minutes per donor wafer.

[0166] Figure 14A-14B A selective transfer process flow for avoiding contact between the donor wafer surface and the wafer chuck during blanket laser release is shown. For example, if blanket laser release is performed on a donor wafer before it is bonded to a recipient wafer, the donor wafer will be mounted on the chuck of the laser tool with the bonding surface of the transfer layer (e.g., die or other selectively transferred component) facing down (e.g., see Figure 8B (Chuck not shown). Contact between the transfer layer and the chuck has the potential to damage the transfer layer, which could cause problems when the donor wafer is subsequently bonded to a recipient wafer. Various methods can be used to protect the transfer layer during blanket laser release, such as a customized chuck design or a sacrificial protective layer, but these methods require new tooling (e.g., customized chuck) or additional processing (e.g., deposition / removal of protective layer). Therefore, in the example shown, an alternative process flow is demonstrated that avoids contact between the donor wafer surface and the chuck during blanket laser release without the need for modified tooling or additional processing.

[0167] In the process flow shown, the transfer from the donor wafer 1400 to the first acceptor wafer 1410a is performed using standard tools. Fig.14A As shown, prior to the laser release process, a first acceptor wafer 1410a is bonded to a donor wafer 1400 using a standard bonding tool (e.g., a target die 1404a on the donor 1400 is selectively bonded to a bonding mesa 1412 (or other type of bonding area) on the acceptor 1410a). Since no offset is required between the bonded donor wafer / acceptor wafer pair for the first transfer from the donor 1400, the bonded wafer pair can be transported between tools using a standard handling system. In this way, the bonded wafer pair can be transferred to a standard laser debonding tool to perform a blanket laser release (e.g., using a laser 1420 to weaken the entire release layer 1402 on the donor 1400). After the blanket release, the donor wafer 1400 and the acceptor wafer 1410a are mechanically separated, so that the target die 1404a is completely debonded from the donor 1400 and remains on the acceptor 1410a.

[0168] All subsequent transfers from the donor wafer 1400 to the remaining acceptor wafers (e.g., the 2nd acceptor to the nth acceptor) are performed using the new bonding / debonding tool 1100. For example, Fig. 14B As shown, the second acceptor wafer 1410b is bonded to the donor wafer 1400 with an offset and then immediately separated and debonded from the donor wafer 1400, such that the target die 1404b is completely debonded from the donor 1400 and remains on the acceptor 1410b.

[0169] Exemplary Embodiments

[0170] Fig.15 1 is a top view of a wafer 1500 and die 1502 that may be included in any of the embodiments disclosed herein. Wafer 1500 may be comprised of semiconductor material and may include one or more die 1502 having integrated circuit structures formed on a surface of wafer 1500. A single die 1502 may be a repeating unit of an integrated circuit product including any suitable integrated circuit. After fabrication of the semiconductor product is completed, wafer 1500 may undergo a singulation process in which die 1502 are separated from one another to provide discrete “chips” of an integrated circuit product. Die 1502 may be any of the dies disclosed herein. Die 1502 may include one or more transistors (e.g., the transistors discussed below). Fig.16 1640), supporting circuitry for routing electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other integrated circuit components. In some embodiments, wafer 1500 or die 1502 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 1502. For example, a memory array formed by multiple memory devices may be coupled to a processor unit (e.g., Fig.19 The microelectronic components disclosed herein may be fabricated using die-to-wafer assembly techniques in which some of the dies are attached to a wafer 1500 that includes other of the dies, and the wafer 1500 is subsequently singulated.

[0171] Fig.161600 may be included in any of the embodiments disclosed herein (eg, in any of the dies). One or more integrated circuit devices in the integrated circuit device 1600 may be included in one or more dies 1502 ( Fig.15 ). The integrated circuit device 1600 may be formed on a die substrate 1602 (eg, Fig.15 1500) and may be included in a die (e.g., Fig.15 1502 in the die). The die substrate 1602 can be a semiconductor substrate composed of a semiconductor material system including, for example, an n-type or p-type material system (or a combination of the two). For example, the die substrate 1602 can include a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate 1602 can be formed using alternative materials that may or may not be combined with silicon, including but not limited to: germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as II-VI, III-V, or IV groups can also be used to form the die substrate 1602. Although some examples of materials that can form the die substrate 1602 are described herein, any material that can serve as the basis for the integrated circuit device 1600 can be used. The die substrate 1602 can be a singulated die (for example, Fig.15 1502) or a wafer (e.g., Fig.15 A portion of wafer 1500).

[0172] The integrated circuit device 1600 may include one or more device layers 1604 disposed on a die substrate 1602. The device layer 1604 may include features of one or more transistors 1640 (e.g., metal oxide semiconductor field effect transistors (MOSFETs)) formed on the die substrate 1602. The transistor 1640 may include, for example, one or more source and / or drain (S / D) regions 1620, a gate 1622 for controlling the flow of current between the S / D regions 1620, and one or more S / D contacts 1624 for routing electrical signals to / from the S / D regions 1620. The transistor 1640 may include additional features that are not depicted for clarity, such as device isolation regions, gate contacts, etc. The transistor 1640 is not limited to Fig.16 The types and configurations described in the drawings and may include a variety of other types and configurations (e.g., planar transistors, non-planar transistors, or a combination of both). Non-planar transistors may include FinFET transistors (e.g., dual-gate transistors or tri-gate transistors), and all-around gate transistors or all-around gate transistors (e.g., nanoribbon, nanosheet, or nanowire transistors).

[0173] Figures 17A-17D are simplified perspective views of exemplary planar transistors, FinFET transistors, gate-all-around transistors, and stacked gate-all-around transistors that may be included in any of the embodiments disclosed herein (eg, in any of the dies). Figures 17A-17D The transistor shown in FIG. 17 is formed on a substrate 1716 having a surface 1708. Isolation regions 1714 separate the source and drain regions of the transistor from other transistors and a body region 1718 of the substrate 1716.

[0174] Fig.17A is a perspective view of an exemplary planar transistor 1700 including a gate 1702 that controls current flow between a source region 1704 and a drain region 1706. Transistor 1700 is planar because source region 1704 and drain region 1706 are planar relative to substrate surface 1708.

[0175] Fig. 17B is a perspective view of an exemplary FinFET transistor 1720 that includes a gate 1722 that controls current flow between a source region 1724 and a drain region 1726. Transistor 1720 is non-planar because source region 1724 and drain region 1726 include a "fin" that extends upward from substrate surface 1728. Because gate 1722 surrounds three sides of the semiconductor fin extending from source region 1724 to drain region 1726, transistor 1720 can be considered a tri-gate transistor. Fig. 17B One S / D fin is shown extending through the gate 1722 , but multiple S / D fins may extend through the gate of the FinFET transistor.

[0176] Fig. 17C is a perspective view of a gate all around (GAA) transistor 1740 including a gate 1742 that controls current flow between a source region 1744 and a drain region 1746. Transistor 1740 is non-planar because source region 1744 and drain region 1746 are elevated from substrate surface 1728.

[0177] Fig.17D1760 includes a gate 1762 that controls current flow between multiple elevated source regions 1764 and multiple elevated drain regions 1766. Transistor 1760 is a stacked GAA transistor because the gate controls current flow between multiple elevated S / D regions stacked on top of each other. Transistors 1740 and 1760 are considered to be all-around gate transistors because the gate surrounds all sides of the semiconductor portion extending from the source region to the drain region. Depending on the width of the semiconductor portion extending through the gate (e.g., widths 1748 and 1768 of transistors 1740 and 1760, respectively), transistors 1740 and 1760 may alternatively be referred to as nanowire, nanosheet, or nanoribbon transistors.

[0178] Back to Fig.16 , transistor 1640 may include a gate 1622 formed of at least two layers (i.e., a gate dielectric and a gate electrode). The gate dielectric may include one layer or a stack of layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or a high-k dielectric material.

[0179] High-k dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in gate dielectrics include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be performed on the gate dielectric to improve its quality when a high-k material is used.

[0180] The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1640 will be a p-type metal oxide semiconductor (PMOS) transistor or an n-type metal oxide semiconductor (NMOS) transistor. In some embodiments, the gate electrode may be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Other metal layers may be included for other purposes, such as barrier layers.

[0181] For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to NMOS transistors (e.g., for work function adjustment). For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to PMOS transistors (e.g., for work function adjustment).

[0182] In some embodiments, when viewed from a cross section of transistor 1640 along the source-channel-drain direction, the gate electrode may be composed of a U-shaped structure including a bottom portion substantially parallel to the surface of die substrate 1602 and two sidewall portions substantially perpendicular to the top surface of die substrate 1602. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of die substrate 1602 and does not include a sidewall portion substantially perpendicular to the top surface of die substrate 1602. In other embodiments, the gate electrode may be composed of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be composed of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0183] In some embodiments, a pair of sidewall spacers may be formed on opposite sides of the gate stack to sandwich the gate stack therebetween. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, multiple pairs of spacers may be used; for example, two, three, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0184] The S / D region 1620 may be formed within the die substrate 1602 and adjacent to the gate 1622 of the single transistor 1640. The S / D region 1620 may be formed using, for example, an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion implanted into the die substrate 1602 to form the S / D region 1620. An annealing process may follow the ion implantation process, which activates the dopant and diffuses it further into the die substrate 1602. In the latter process, the die substrate 1602 may first be etched to form a recess at the location of the S / D region 1620. Then, an epitaxial deposition process may be performed to fill the recess with a material for making the S / D region 1620. In some embodiments, the S / D region 1620 may be made using a silicon alloy (e.g., silicon germanium or silicon carbide). In some embodiments, the epitaxially deposited silicon alloy may be in-situ doped with a dopant such as boron, arsenic, or phosphorus. In some embodiments, one or more alternative semiconductor materials (eg, germanium or III-V materials or alloys) may be used to form S / D region 1620. In further embodiments, S / D region 1620 may be formed using one or more layers of metal and / or metal alloys.

[0185] The device layer 1604 may be provided with one or more interconnect layers (in Fig.16 1606-1610) to route electrical signals (e.g., power and / or input / output (I / O) signals) to and / or from devices (e.g., transistors 1640) of device layer 1604. For example, conductive features (e.g., gates 1622 and S / D contacts 1624) of device layer 1604 can be electrically coupled to interconnect structures 1628 of interconnect layers 1606-1610. One or more interconnect layers 1606-1610 can form a metallization stack (also referred to as an "ILD stack") 1619 of integrated circuit device 1600.

[0186] Interconnect structure 1628 can be arranged within interconnect layers 1606-1610 to route electrical signals according to a variety of designs; in particular, the arrangement is not limited to Fig.16 The specific configuration of interconnect structure 1628 is depicted in FIG. Fig.16 A particular number of interconnect layers 1606 - 1610 are depicted in FIG. 1 , but embodiments of the present disclosure include integrated circuit devices having more or fewer interconnect layers than depicted.

[0187] In some embodiments, the interconnect structure 1628 may include wires 1628a and / or vias 1628b filled with a conductive material (e.g., metal). The wires 1628a may be arranged to route electrical signals in a direction substantially parallel to a surface of the die substrate 1602 on which the device layer 1604 is formed. For example, the wires 1628a may be arranged to route electrical signals in a direction substantially parallel to a surface of the die substrate 1602 on which the device layer 1604 is formed. Fig.16 The vias 1628b may be arranged to route electrical signals in a direction that is substantially perpendicular to the surface of the die substrate 1602 on which the device layer 1604 is formed. In some embodiments, the vias 1628b may electrically couple together the lines 1628a of different interconnect layers 1606-1610.

[0188] like Fig.16 As shown, interconnect layers 1606-1610 may include dielectric material 1626 disposed between interconnect structures 1628. In some embodiments, dielectric material 1626 disposed between interconnect structures 1628 in different ones of interconnect layers 1606-1610 may have different compositions; in other embodiments, the composition of dielectric material 1626 between different ones of interconnect layers 1606-1610 may be the same. Device layer 1604 may also include dielectric material 1626 disposed between transistor 1640 and the bottom layer of the metallization stack. Dielectric material 1626 included in device layer 1604 may have a different composition than dielectric material 1626 included in interconnect layers 1606-1610; in other embodiments, the composition of dielectric material 1626 in device layer 1604 may be the same as dielectric material 1626 included in any one of interconnect layers 1606-1610.

[0189] A first interconnect layer 1606 (referred to as metal 1 or "M1") can be formed directly on the device layer 1604. In some embodiments, as shown, the first interconnect layer 1606 can include lines 1628a and / or vias 1628b. The lines 1628a of the first interconnect layer 1606 can be coupled to contacts (e.g., S / D contacts 1624) of the device layer 1604. The vias 1628b of the first interconnect layer 1606 can be coupled to the lines 1628a of the second interconnect layer 1608.

[0190] A second interconnect layer 1608 (referred to as metal 2 or "M2") may be formed directly on the first interconnect layer 1606. In some embodiments, the second interconnect layer 1608 may include vias 1628b to couple the wires 1628 of the second interconnect layer 1608 with the wires 1628a of the third interconnect layer 1610. Although the wires 1628a and the vias 1628b are structurally depicted with lines within a single interconnect layer for clarity, in some embodiments, the wires 1628a and the vias 1628b may be structurally and / or materially continuous (e.g., filled simultaneously during a dual damascene process).

[0191] A third interconnect layer 1610 (referred to as metal 3 or "M3") (and additional interconnect layers, as desired) may be formed successively on the second interconnect layer 1608 according to similar techniques and constructions described in connection with the second interconnect layer 1608 or the first interconnect layer 1606. In some embodiments, interconnect layers that are "higher up" (i.e., farther from the device layer 1604) in the metallization stack 1619 in the integrated circuit device 1600 may be thicker than interconnect layers lower in the metallization stack 1619, wherein the lines 1628a and vias 1628b in the higher interconnect layers are thicker than the lines 1628a and vias 1628b in the lower interconnect layers.

[0192] The integrated circuit device 1600 may include a solder resist material 1634 (eg, polyimide or similar material) formed on the interconnect layers 1606-1610 and one or more conductive contacts 1636. Fig.16 , the conductive contact 1636 is shown as taking the form of a bonding pad. The conductive contact 1636 can be electrically coupled to the interconnect structure 1628 and configured to route electrical signals of the (multiple) transistors 1640 to an external device. For example, a solder joint can be formed on one or more conductive contacts 1636 to mechanically and / or electrically couple the integrated circuit die including the integrated circuit device 1600 to another component (e.g., a printed circuit board). The integrated circuit device 1600 may include additional or alternative structures to route electrical signals from the interconnect layers 1606-1610; for example, the conductive contact 1636 may include other similar features (e.g., columns) that route electrical signals to external components. The conductive contact 1636 may serve as any of the conductive contacts described throughout the present disclosure.

[0193] In some embodiments where the integrated circuit device 1600 is a double-sided die, the integrated circuit device 1600 may include another metallization stack (not shown) located on the opposite side of the device layer(s) 1604. The metallization stack may include multiple interconnect layers as discussed above with reference to the interconnect layers 1606-1610 to provide conductive paths (e.g., including conductive lines and vias) between the device layer(s) 1604 and additional conductive contacts (not shown) located on the side of the integrated circuit device 1600 opposite the conductive contacts 1636. These additional conductive contacts may serve as any of the conductive contacts described throughout the present disclosure.

[0194] In other embodiments where the integrated circuit device 1600 is a double-sided die, the integrated circuit device 1600 may include one or more through silicon vias (TSVs) through the die substrate 1602; these TSVs may contact the device layer(s) 1604 and may provide a conductive path between the device layer(s) 1604 and additional conductive contacts (not shown) located on the side of the integrated circuit device 1600 opposite the conductive contacts 1636. These additional conductive contacts may serve as any of the conductive contacts described throughout this disclosure. In some embodiments, the TSVs extending through the substrate may be used to route power and ground signals from the conductive contacts located on the side of the integrated circuit device 1600 opposite the conductive contacts 1636 to the transistor 1640 and any other components integrated into the die 1600, and the metallization stack 1619 may be used to route I / O signals from the conductive contacts 1636 to the transistor 1640 and any other components integrated into the die 1600.

[0195] A plurality of integrated circuit devices 1600 may be stacked, wherein one or more TSVs in a single stacked device provide a connection between one device in the device and any device in the other devices in the stack. For example, one or more high bandwidth memory (HBM) integrated circuit dies may be stacked on top of a substrate integrated circuit die, and the TSVs in the HBM die may provide a connection between a single HBM and the substrate integrated circuit die. The conductive contacts may provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts may be fine pitch solder bumps (microbumps).

[0196] Fig.181800, which may include any of the embodiments disclosed herein (e.g., IC components, such as dies, selectively transferred from a donor wafer). In some embodiments, the integrated circuit device assembly 1800 may be a microelectronic assembly. The integrated circuit device assembly 1800 includes a plurality of components disposed on a circuit board 1802 (which may be a motherboard, a system board, a mainboard, etc.). The integrated circuit device assembly 1800 includes components disposed on a first side 1840 of the circuit board 1802 and an opposing second side 1842 of the circuit board 1802; in general, the components may be disposed on one or both of the sides 1840 and 1842. Any of the integrated circuit components discussed below with reference to the integrated circuit device assembly 1800 may take the form of any suitable embodiment of the embodiments of the microelectronic assembly disclosed herein.

[0197] In some embodiments, circuit board 1802 may be a printed circuit board (PCB) that includes multiple metal (or interconnect) layers separated from each other by layers of dielectric material and interconnected by conductive vias. A single metal layer includes conductive traces. Any one or more of the metal layers may be formed in accordance with a desired circuit pattern to route electrical signals between components coupled to circuit board 1802 (optionally, in conjunction with other metal layers). In other embodiments, circuit board 1802 may be a non-PCB substrate. Fig.18 The integrated circuit device assembly 1800 shown in FIG. 1 includes a package structure on an interposer 1836 coupled to a first side 1840 of a circuit board 1802 via a coupling component 1816. The coupling component 1816 can electrically and mechanically couple the package structure on the interposer 1836 to the circuit board 1802 and can include solder balls (e.g., Fig.18 ), pins (e.g., as part of a pin grid array (PGA)), contacts (e.g., as part of a land grid array (LGA)), male and female portions of a socket, adhesives, underfill materials, and / or any other suitable electrical and / or mechanical coupling structures. Coupling component 1816 may optionally function as a coupling component as shown or described for any substrate assembly or substrate assembly component described herein.

[0198] The package-on-interposer structure 1836 may include an integrated circuit component 1820 coupled to the interposer 1804 via a coupling component 1818. The coupling component 1818 may take any appropriate form for the application, such as those discussed above with reference to the coupling component 1816. Fig.18A single integrated circuit component 1820 is shown in FIG. 1 , but multiple integrated circuit components may be coupled to interposer 1804; indeed, additional interposers may be coupled to interposer 1804. Interposer 1804 may provide an intermediate substrate for bridging circuit board 1802 and integrated circuit components 1820.

[0199] Integrated circuit component 1820 may be a packaged or unpackaged integrated circuit product that includes one or more integrated circuit dies (eg, Fig.15 The tube core 1502, Fig.16 The integrated circuit device 1600 in the package includes one or more integrated circuit dies mounted on a packaging substrate, wherein the integrated circuit die and the packaging substrate are encapsulated in a housing material such as metal, plastic, glass or ceramic. In one example of an unpackaged integrated circuit component 1820, a single monolithic integrated circuit die includes solder bumps attached to contacts on the die. The solder bumps allow the die to be directly attached to the interposer 1804. The integrated circuit component 1820 may include one or more computing system components, such as one or more processor units (e.g., a system on a chip (SoC), a processor core, a graphics processor unit (GPU), an accelerator, a chipset processor), an I / O controller, a memory, or a network interface controller. In some embodiments, the integrated circuit component 1820 may include one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.

[0200] In embodiments where integrated circuit component 1820 includes multiple integrated circuit dies, the dies may be of the same type (homogeneous multi-die integrated circuit component) or of two or more different types (heterogeneous multi-die integrated circuit component). A multi-die integrated circuit component may be referred to as a multi-chip package (MCP) or a multi-chip module (MCM).

[0201] In addition to including one or more processor units, the integrated circuit component 1820 may also include additional components, such as embedded DRAM, stacked high bandwidth memory (HBM), shared cache memory, input / output (I / O) controllers, or memory controllers. Any of these additional components may be located on the same integrated circuit die as the processor unit, or on one or more integrated circuit dies separate from the integrated circuit die that includes the processor unit. These separate integrated circuit dies may be referred to as "chiplets." In embodiments where the integrated circuit component includes multiple integrated circuit dies, the integrated circuit dies may be formed by a packaging substrate, one or more silicon interposers, one or more silicon bridges (e.g., embedded in the packaging substrate), or a plurality of silicon interposers. Embedded multi-die interconnect bridge (EMIB)) or a combination thereof to provide interconnection between dies.

[0202] In general, interposer 1804 can extend connections to a wider pitch or reroute connections to different connections. For example, interposer 1804 can couple integrated circuit component 1820 to a set of ball grid array (BGA) conductive contacts of coupling component 1816 for coupling to circuit board 1802. Fig.18 In the embodiment shown in FIG. 1 , integrated circuit component 1820 and circuit board 1802 are attached to opposite sides of interposer 1804; in other embodiments, integrated circuit component 1820 and circuit board 1802 can be attached to the same side of interposer 1804. In some embodiments, three or more components can be interconnected through interposer 1804.

[0203] In some embodiments, the interposer 1804 may be formed as a PCB including multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. In some embodiments, the interposer 1804 may be formed of epoxy, glass fiber reinforced epoxy, epoxy with inorganic fillers, ceramic material, or polymer material such as polyimide. In some embodiments, the interposer 1804 may be formed of alternative rigid or flexible materials, which may include the same materials as those described above for use in semiconductor substrates, such as silicon, germanium, and other III-V and IV materials. The interposer 1804 may include metal interconnects 1808 and vias 1810, including but not limited to through-hole vias 1810-1 (which extend from the first side 1850 of the interposer 1804 to the second side 1854 of the interposer 1804), blind vias 1810-2 (which extend from the first side 1850 or the second side 1854 of the interposer 1804 to the internal metal layer), and buried vias 1810-3 (which connect the internal metal layer).

[0204] In some embodiments, interposer 1804 may include a silicon interposer. Through silicon vias (TSVs) extending through the silicon interposer may connect connectors on a first side of the silicon interposer to an opposite second side of the silicon interposer. In some embodiments, interposer 1804 including a silicon interposer may also include one or more routing layers to route connectors on a first side of interposer 1804 to an opposite second side of interposer 1804.

[0205] The interposer 1804 may also include embedded devices 1814, which include both passive devices and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices, may also be formed on the interposer 1804. The package structure 1836 on the interposer may take the form of any package structure on the interposer known in the art. In some embodiments, the interposer is a non-printed circuit board.

[0206] The integrated circuit device assembly 1800 may include an integrated circuit component 1824 coupled to the first side 1840 of the circuit board 1802 via a coupling component 1822. The coupling component 1822 may take the form of any of the embodiments discussed above with reference to the coupling component 1816, and the integrated circuit component 1824 may take the form of any of the embodiments discussed above with reference to the integrated circuit component 1820.

[0207] Fig.18 The integrated circuit device assembly 1800 shown in FIG. 1 includes a package-on-package structure 1834 coupled to a second side 1842 of a circuit board 1802 via a coupling component 1828. The package-on-package structure 1834 may include an integrated circuit component 1826 and an integrated circuit component 1832 coupled together via a coupling component 1830, such that the integrated circuit component 1826 is disposed between the circuit board 1802 and the integrated circuit component 1832. The coupling components 1828 and 1830 may take the form of any embodiment of the coupling component 1816 discussed above, and the integrated circuit components 1826 and 1832 may take the form of any embodiment of the integrated circuit component 1820 discussed above. The package-on-package structure 1834 may be constructed according to any package-on-package structure known in the art.

[0208] Fig.19 1 is a block diagram of an exemplary electrical device 1900 that may include one or more of the embodiments disclosed herein. For example, any suitable component of the components of the electrical device 1900 may include one or more selectively transferred IC components (e.g., dies) disclosed herein, the integrated circuit device assembly 1800, the integrated circuit component 1820, the integrated circuit device 1600, or the integrated circuit die 1502. Fig.191900, but any one or more of these components may be omitted or duplicated to suit the application. In some embodiments, some or all of the components included in the electrical device 1900 may be attached to one or more motherboards, mainboards, or system boards. In some embodiments, one or more of these components are fabricated on a single system-on-chip (SoC) die.

[0209] Additionally, in various embodiments, the electrical device 1900 may not include Fig.19 , but the electrical device 1900 may include interface circuitry for coupling to one or more of the components. For example, the electrical device 1900 may not include the display device 1906, but may include display device interface circuitry (e.g., connector and driver circuitry) to which the display device 1906 may be coupled. In another set of examples, the electrical device 1900 may not include the audio input device 1924 or the audio output device 1908, but may include audio input or output device interface circuitry (e.g., connector and supporting circuitry) to which the audio input device 1924 or the audio output device 1908 may be coupled.

[0210] The electrical device 1900 may include one or more processor units 1902 (e.g., one or more processor units). As used herein, the term "processor unit", "processing unit" or "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that can be stored in registers and / or memory. The processor unit 1902 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general purpose GPUs (GPGPUs), accelerated processing units (APUs), field programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller cryptographic processors (dedicated processors that execute cryptographic algorithms in hardware), server processors, controllers, or any other suitable type of processor unit. In this way, the processor unit may be referred to as an XPU (or xPU).

[0211] The electrical device 1900 may include a memory 1904, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase change non-voltage memory), solid-state memory, and / or a hard disk drive. In some embodiments, the memory 1904 may include memory located on the same integrated circuit die as the processor unit 1902. The memory may be used as a cache memory (e.g., level 1 (L1), level 2 (L2), level 3 (L3), level 4 (L4), last level cache (LLC)), and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0212] In some embodiments, the electrical device 1900 may include one or more processor units 1902 that are heterogeneous or asymmetric with another processor unit 1902 in the electrical device 1900. There may be a variety of differences between the processor units 1902 in the system in terms of a range of quality criteria including architectural, microarchitectural, thermal, power consumption characteristics, etc. These differences can effectively manifest themselves as asymmetry and heterogeneity between the processor units 1902 in the electrical device 1900.

[0213] In some embodiments, the electrical device 1900 may include a communication component 1912 (e.g., one or more communication components). For example, the communication component 1912 may manage wireless communications that transmit data to and from the electrical device 1900. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that may transmit data through a non-solid medium using modulated electromagnetic radiation. The term "wireless" does not imply that the associated devices do not contain any wires, although in some embodiments they may not contain wires.

[0214] The communication component 1912 can implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 revision), Long Term Evolution (LTE) project and any revisions, updates and / or amendments (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). Broadband wireless access (BWA) networks compatible with IEEE 802.16 are generally referred to as WiMAX networks, which is an acronym standing for Worldwide Interoperability for Microwave Access and is a certification mark for products that have passed conformance and interoperability testing for the IEEE 802.16 standard. The communication component 1912 can operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication component 1912 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication component 1912 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher. In other embodiments, the communication component 1912 may operate in accordance with other wireless protocols. The electrical device 1900 may include an antenna 1922 to facilitate wireless communication and / or receive other wireless communications (e.g., AM or FM radio transmissions).

[0215] In some embodiments, the communication component 1912 can manage wired communications, such as electrical, optical, or any other appropriate communication protocol (e.g., IEEE 802.3 Ethernet standard). As described above, the communication component 1912 can include multiple communication components. For example, the first communication component 1912 can be dedicated to shorter-range wireless communications, such as Wi-Fi or Bluetooth, and the second communication component 1912 can be dedicated to longer-range wireless communications, such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO or other. In some embodiments, the first communication component 1912 can be dedicated to wireless communications, and the second communication component 1912 can be dedicated to wired communications.

[0216] The electrical device 1900 may include a battery / power circuit system 1914. The battery / power circuit system 1914 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuit systems for coupling components of the electrical device 1900 to an energy source separate from the electrical device 1900 (e.g., AC line power).

[0217] The electrical device 1900 may include a display device 1906 (or corresponding interface circuitry as discussed above). The display device 1906 may include one or more embedded or wired or wirelessly connected external visual indicators, such as a head-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0218] The electrical device 1900 may include an audio output device 1908 (or corresponding interface circuitry as discussed above). The audio output device 1908 may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such as a speaker, headphones, or earbuds.

[0219] The electrical device 1900 may include an audio input device 1924 (or a corresponding interface circuit system as discussed above). The audio input device 1924 may include any embedded or wired or wirelessly connected device that produces a signal representing sound, such as a microphone, a microphone array, or a digital musical instrument (e.g., a musical instrument with a musical instrument digital interface (MIDI) output). The electrical device 1900 may include a global navigation satellite system (GNSS) device 1918 (or a corresponding interface circuit system as discussed above), such as a global positioning system (GPS) device. As is known in the art, the GNSS device 1918 can communicate with a satellite-based system and can determine the geographic location of the electrical device 1900 based on information received from one or more GNSS satellites.

[0220] The electrical device 1900 may include other output device(s) 1910 (or corresponding interface circuitry as discussed above). Examples of other output device(s) 1910 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage.

[0221] The electronic device 1900 may include other input device(s) 1920 (or corresponding interface circuitry as discussed above). Examples of other input device(s) 1920 may include an accelerometer, a gyroscope, a compass, an image capture device (e.g., a monoscopic or stereoscopic camera), a trackball, a trackpad, a touchpad, a keyboard, a cursor control device (e.g., a mouse, a stylus), a touch screen, a proximity sensor, a microphone, a barcode reader, a quick response (QR) code reader, an electrocardiogram (ECG) sensor, a PPG (photoplethysmogram) sensor, a galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader.

[0222] The electrical device 1900 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a cell phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a 2-in-1 convertible computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, a portable game console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., a blade, tray or sled computing system), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a fixed game console, a smart TV, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device, or an embedded computing system (e.g., a computing system as part of a vehicle, a smart home appliance, a consumer electronic product or device, a manufacturing device). In some embodiments, the electrical device 1900 may be any other electronic device that processes data. In some embodiments, the electrical device 1900 may include multiple discrete physical components. Considering the range of devices that the electrical device 1900 may appear in various embodiments, in some embodiments, the electrical device 1900 may be referred to as a computing device or a computing system.

[0223] Example

[0224] Illustrative examples of the techniques described throughout this disclosure are provided below. Embodiments of these techniques may include any one or more of the examples described below and any combination thereof. In some embodiments, at least one of the systems or components described in one or more of the drawings in the above-mentioned figures may be configured to perform one or more operations, techniques, processes, and / or methods described in the following examples.

[0225] Example 1 includes a microelectronic component comprising: a layer comprising a dielectric material; and an integrated circuit (IC) die at least partially located within the layer, wherein the IC die has a thickness of 5 microns (μm) or less, and wherein a gap exists between the IC die and a portion of the layer surrounding the IC die.

[0226] Example 2 includes the microelectronic assembly of Example 1, further comprising a mesa structure beneath the IC die, wherein the mesa structure has a similar footprint as the IC die.

[0227] Example 3 includes a microelectronic assembly according to any of Examples 1-2, wherein: the layer is a first layer; and the microelectronic assembly further includes a second layer located below the IC die, wherein the IC die is bonded to the second layer via a bonding interface, wherein the bonding interface includes a dielectric bonding portion, or a hybrid dielectric and metal bonding portion.

[0228] Example 4 includes a microelectronic assembly according to any of Examples 1-3, wherein: the IC die is a first IC die; the microelectronic assembly further includes a second IC die at least partially located within the layer; and the first IC die and the second IC die each include a substrate formed from a separate sheet of substrate material.

[0229] Example 5 includes a microelectronic assembly according to any of Examples 1-4, wherein an edge of the IC die is unchipped.

[0230] Example 6 includes a microelectronic assembly according to any of Examples 1-5, wherein the IC die has an area of ​​less than 1 square millimeter (mm 2 ) area.

[0231] Example 7 includes a microelectronic assembly according to any of Examples 1-6, wherein the IC die has an asymmetric shape, a non-convex shape, or a shape having an aspect ratio of at least 8:1.

[0232] Example 8 includes an electronic device comprising: a layer comprising one or more materials; an integrated circuit (IC) component, the integrated circuit (IC) component being at least partially located within the layer; and a mesa structure, the mesa structure being located below the IC component, wherein the mesa structure has a similar footprint as the IC component, and wherein the IC component is bonded to the mesa structure.

[0233] Example 9 includes an electronic device according to Example 8, wherein: the mesa structure includes at least one of a dielectric material or a metal; and the IC component is bonded to the mesa structure via a dielectric bond, a metal bond, or a hybrid dielectric and metal bond.

[0234] Example 10 includes the electronic device of any of Examples 8-9, wherein a gap exists between the IC component and the portion of the layer surrounding the IC component.

[0235] Example 11 includes the electronic device of any of Examples 8-10, wherein the IC component includes an IC die, an interconnect, a transistor, a diode, a resistor, a capacitor, an inductor, or a transformer.

[0236] Example 12 includes a method comprising: receiving a first substrate, wherein the first substrate includes a layer of integrated circuit (IC) components; receiving a second substrate, wherein the second substrate includes one or more bonding areas; partially bonding the first substrate to the second substrate, wherein one or more IC components located on the first substrate are bonded to the one or more bonding areas located on the second substrate, wherein the one or more IC components are from the layer of IC components; and separating the first substrate from the second substrate, wherein the one or more IC components are separated from the first substrate and remain on the second substrate.

[0237] Example 13 includes the method of Example 12, wherein the layer of the IC component includes one or more IC dies, interconnects, transistors, diodes, resistors, capacitors, inductors, or transformers.

[0238] Example 14 includes the method of any of Examples 12-13, wherein the first substrate further comprises a base substrate and a release layer, wherein the release layer is located over the base substrate, and wherein the layer of the IC component is located over the release layer.

[0239] Example 15 includes a method according to Example 14, wherein receiving the first substrate includes: forming the first substrate, wherein forming the first substrate includes: receiving a base substrate; forming a release layer over the base substrate; forming a layer of IC components over the release layer; and partially singulating the layer of IC components.

[0240] Example 16 includes the method of Example 15, wherein forming the layer of the IC component on the release layer includes: fabricating the layer of the IC component on the release layer; or transferring the layer of the IC component onto the release layer.

[0241] Example 17 includes the method of any of Examples 14-16, wherein separating the first substrate from the second substrate includes: at least partially releasing one or more IC components from a release layer of the first substrate; and mechanically separating the first substrate from the second substrate.

[0242] Example 18 includes the method of Example 17, wherein at least partially releasing the one or more IC components from the release layer of the first substrate comprises: debonding the one or more IC components from the release layer using a laser; or weakening the release layer using a laser.

[0243] Example 19 includes the method of any of Examples 14-18, wherein the release layer includes a metal.

[0244] Example 20 includes the method of any of Examples 12-19, wherein the one or more adhesion regions include one or more raised structures, wherein the one or more raised structures include at least one of a dielectric material or a metal.

[0245] Although the concepts of the present disclosure are susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are described in detail herein. However, it should be understood that it is not intended to limit the concepts of the present disclosure to the specific forms disclosed, but on the contrary, the purpose is to cover all modifications, equivalents and alternatives consistent with the present disclosure and the appended claims.

[0246] In the accompanying drawings, some structural or method features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be necessary. On the contrary, in some embodiments, such features may be arranged in a different manner and / or order than shown in the illustrative figures. In addition, the inclusion of structural or method features in a particular figure does not mean that such features are required in all embodiments, and in some embodiments, such features may not be included, or such features may be combined with other features. In addition, it should be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

[0247] In addition, for ease of understanding, the illustrations and / or descriptions of various embodiments may be simplified or approximated, and therefore, they may not necessarily reflect the precise level or variations that may exist in actual embodiments. For example, although some of the drawings generally indicate straight lines, right angles, and smooth surfaces, given the real-world limitations of manufacturing processes, actual implementations of the disclosed embodiments may have less than ideal straight lines and right angles, and some features may have surface topography or be non-smooth in other cases. Similarly, for ease of understanding, the illustrations and / or descriptions of how to arrange components may be simplified or approximated, and may vary with a certain margin of error in actual embodiments (e.g., due to manufacturing processes, etc.).

[0248] Unless otherwise stated, the use of ordinal adjectives "first," "second," and "third," etc. to describe common objects merely indicates different instances of similar objects being referenced, and is not intended to imply that the objects so described must be in a given order temporally, spatially, hierarchically, or in any other manner.

[0249] The terms "substantially," "close," "approximately," "almost," and "about" generally refer to being within + / - 10% of a target value (unless otherwise indicated). Similarly, terms describing spatial relationships (e.g., "perpendicular," "orthogonal," or "coplanar") can mean being substantially within the described spatial relationship (e.g., within + / - 10 degrees of orthogonal).

[0250] Certain terms may also be used in the foregoing description for purposes of reference only, and are therefore not intended to be limiting. For example, terms such as "upper," "lower," "above," "below," "bottom," and "top" refer to directions in the drawings to which reference is made. Terms such as "front," "rear," "back," and "side" describe the orientation and / or position of portions of a component within a consistent but arbitrary reference system, which orientation and / or position can be clearly understood by reference to the text describing the component in question and the associated drawings. Such terms may include the words specifically mentioned above, their derivatives, and words of similar meaning.

[0251] As used herein, the terms "above," "below," "between," "adjacent to," "to," and "on" refer to the relative position of one layer or component with respect to other layers or components. For example, a layer that is "above," "below," or "on," "adjacent to," or joined "to" another layer may be directly in contact with the other layer, or may have one or more intervening layers. A layer that is "between" layers may be directly in contact with the layers, or may have one or more intervening layers.

[0252] The meanings of "a", "an" and "the" include plural references. The meaning of "in" includes "in" and "on".

[0253] For purposes of this disclosure, the phrases "A and / or B" and "A or B" mean (A), (B), or (A and B). For purposes of this disclosure, the phrases "A, B, and / or C" mean (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0254] The views labeled "Section," "Profile," and "Plan" correspond to orthogonal planes within a Cartesian coordinate system. Thus, section and profile views are taken in the xz plane, and plan views are taken in the xy plane. Typically, a profile view in the xz plane is a section view.

[0255] The term "package" generally refers to a self-contained carrier of one or more dies, wherein the die is attached to or embedded in a package substrate and may be encapsulated for protection, with integrated or wire-bonded interconnects between the die and leads, pins, or bumps on the external portion of the package substrate. A package may contain a single die or multiple dies, thereby providing the corresponding functionality. A package may be mounted on a printed circuit board for interconnection with other packaged integrated circuits and discrete components to form a larger circuit.

[0256] The term "core" generally refers to the substrate of an integrated circuit package built on a board, card or wafer comprising a non-flexible rigid material. Typically, a small printed circuit board is used as the core, and the integrated circuit devices and discrete passive components can be soldered to the core. Typically, the core has vias extending from one side to the other, allowing the circuit system located on one side of the core to be directly coupled to the circuit system located on the other side of the core. The core can also serve as a platform for stacking layers of conductors and dielectric materials.

[0257] The term "coreless" generally refers to the substrate of the integrated circuit package being devoid of a core. The lack of a core can allow for a higher density packaging architecture, as through vias can have relatively larger sizes and pitches compared to high density interconnects.

[0258] The term "land side" generally refers to the side of the substrate of an integrated circuit package that is closest to the attachment plane to a printed circuit board, motherboard, or other package. This is in contrast to the term "die side," which generally refers to the side of the substrate of an integrated circuit package to which one or more dies are attached.

[0259] The terms "dielectric" and "dielectric material" generally refer to any type or amount of non-conductive material. In some cases, dielectric materials can be used to form the structure of a package substrate. For example, dielectric materials can be incorporated into an integrated circuit package as a layer of a laminate film or as a resin molded over an integrated circuit die mounted on a substrate.

[0260] The term "metallization" generally refers to a metal layer formed on, over, and / or through a dielectric material of a package substrate. The metal layer is generally patterned to form metal structures (e.g., traces and bonding pads). The metallization of a package substrate may be limited to a single layer or to multiple layers separated by dielectric layers.

[0261] The term "bonding pad" generally refers to a metallization structure that terminates integrated traces and vias in integrated circuit packages and dies. The term "solder pad" may sometimes be substituted for "bonding pad" and may have the same or similar meaning.

[0262] The term “bump” generally refers to a conductive layer or structure formed on a bonding pad, which is typically made of solder or metal and has a circular or arc shape, and is therefore called a “bump”.

[0263] The term "substrate" generally refers to a planar platform including dielectric and / or metallization structures. The substrate can mechanically support and electrically couple one or more IC die on a single platform, wherein the one or more IC die are encapsulated by a moldable dielectric material. The substrate can include bumps or pads as bonding interconnects on one or both sides. For example, one side of the substrate (generally referred to as the "die side") may include bumps or pads for chip or die bonding. The opposite side of the substrate (generally referred to as the "pad side") may include bumps or pads for bonding the package to a printed circuit board.

[0264] The term "assembly" generally refers to a group of parts that form a single functional unit. For example, certain parts can be permanently joined together, integrated together, and / or mechanically assembled (e.g., where the parts can be removable) into a functional unit.

[0265] The terms "coupled" or "connected" mean a direct or indirect connection such as a direct electrical, mechanical, magnetic or fluid connection between the things connected, or an indirect connection through one or more passive or active intermediary devices.

[0266] The term "circuit" or "module" may refer to one or more passive and / or active components arranged to cooperate with each other to provide the desired functionality. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal or data / clock signal.

Claims

1. A microelectronic assembly comprising: a layer comprising a dielectric material; as well as An integrated circuit (IC) die is at least partially located within the layer, wherein the IC die has a thickness of 5 micrometers (μm) or less, and wherein a gap exists between the IC die and a portion of the layer surrounding the IC die.

2. The microelectronic assembly of claim 1 further comprising a mesa structure beneath the IC die, wherein: The mesa structure has a similar footprint as the IC die.

3. The microelectronic assembly of claim 1 , wherein: The layer is a first layer; and The microelectronic assembly also includes a second layer underlying the IC die, wherein the IC die is bonded to the second layer via a bonding interface, wherein the bonding interface includes a dielectric bond, or a hybrid dielectric and metal bond.

4. The microelectronic assembly of claim 1 , wherein: The IC die is a first IC die; The microelectronic assembly also includes a second IC die located at least partially within the layer; and The first IC die and the second IC die each include a substrate formed from a separate sheet of substrate material.

5. The microelectronic assembly according to any one of claims 1 to 4, wherein: The edges of the IC die are unchipped.

6. A microelectronic assembly according to any one of claims 1 to 4, wherein: The IC die has an area less than 1 square millimeter (mm 2 ) area.

7. A microelectronic assembly according to any one of claims 1 to 4, wherein: The IC die has an asymmetric shape, a non-convex shape, or a shape having an aspect ratio of at least 8:

1.

8. An electronic device comprising: a layer comprising one or more materials; an integrated circuit (IC) component located at least partially within the layer; as well as A mesa structure is located below the IC component, wherein the mesa structure has a similar footprint as the IC component, and wherein the IC component is bonded to the mesa structure.

9. The electronic device according to claim 8, wherein: The mesa structure comprises at least one of a dielectric material or a metal; and The IC components are bonded to the mesa structures via dielectric bonds, metal bonds, or hybrid dielectric and metal bonds.

10. The electronic device according to any one of claims 8 to 9, wherein: There is a gap between the IC component and the portion of the layer surrounding the IC component.

11. The electronic device according to any one of claims 8 to 9, wherein: The IC components include an IC die, an interconnect, a transistor, a diode, a resistor, a capacitor, an inductor, or a transformer.

12. A method comprising: receiving a first substrate, wherein the first substrate comprises a layer of integrated circuit (IC) components; receiving a second substrate, wherein the second substrate comprises one or more bonding areas; partially bonding the first substrate to the second substrate, wherein one or more IC components located on the first substrate are bonded to the one or more bonding areas located on the second substrate, wherein the one or more IC components are from a layer of the IC components; and The first substrate is separated from the second substrate, wherein the one or more IC components are separated from the first substrate and remain on the second substrate.

13. The method according to claim 12, wherein: The layers of the IC components include one or more IC dies, interconnects, transistors, diodes, resistors, capacitors, inductors, or transformers.

14. The method according to claim 12, wherein: The one or more adhesion regions include one or more raised structures, wherein the one or more raised structures include at least one of a dielectric material or a metal.

15. The method according to any one of claims 12 to 14, wherein: The first substrate further includes a base substrate and a release layer, wherein the release layer is located over the base substrate, and wherein a layer of the IC component is located over the release layer.

16. The method according to claim 15, wherein: Receiving the first substrate includes: forming the first substrate, wherein forming the first substrate includes: receiving the base substrate; forming the release layer over the base substrate; forming a layer of the IC component over the release layer; and The layers of the IC component are partially singulated.

17. The method according to claim 16, wherein: The layer forming the IC component on the release layer includes: fabricating a layer of the IC component on top of the release layer; or The layer of IC components is transferred onto the release layer.

18. The method according to claim 15, wherein: Separating the first substrate from the second substrate comprises: at least partially releasing the one or more IC components from the release layer of the first substrate; and The first substrate is mechanically separated from the second substrate.

19. The method according to claim 18, wherein: At least partially releasing the one or more IC components from the release layer of the first substrate comprises: debonding the one or more IC components from the release layer using a laser; or A laser is used to weaken the release layer.

20. The method according to claim 15, wherein: The release layer includes metal.

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