Power semiconductor device packaging structure, method, power device and electronic device

Abstract

The present application provides a power semiconductor device packaging structure, method, power device and electronic device, relating to the technical field of semiconductor manufacturing. The packaging structure includes a wafer, a cathode electrode, an anode electrode, a cathode case electrode and a case; the cathode electrode and the anode electrode are respectively located on opposite sides of the wafer; wherein, one surface of the anode electrode is in direct contact with the first main surface of the wafer, and the other surface is exposed to the outside of the packaging structure; one surface of the cathode electrode is in direct contact with the second surface of the wafer, and the other surface is connected to the cathode case electrode through an elastic structure. Through the present application, the thermal resistance optimization effect on the anode side can be achieved, and the current-carrying capacity of the device can be improved.

Description

Technical Field

[0001] This application relates to the technical field of semiconductor devices, and particularly to a power semiconductor device packaging structure, method, power device, and electronic device.

Background Art

[0002] As a fully controlled power device with the largest single-tube capacity, the Integrated Gate Commutated Thyristors (IGCT) device has excellent performance such as large capacity, fast switching speed, low switching loss, and high di / dt (current change rate) tolerance. It is widely used in fields such as DC power transmission, smart grid, power converters, and power inverters, with broad prospects and huge future development space.

[0003] In the prior art, the packaging structure is a five-layer structure of anode copper electrode - anode molybdenum sheet - silicon chip - cathode molybdenum sheet - cathode copper electrode, and the electrical connection is achieved through rigid contact by mechanical pressure. With the continuous improvement of the power level of IGCT devices, higher requirements are put forward for the packaging thermal resistance of the devices.

[0004] However, in the prior art, the following main problems exist:

[0005] 1) The existing IGCT device packaging structure is a five-layer structure of anode copper electrode - anode molybdenum sheet - silicon chip - cathode molybdenum sheet - cathode copper electrode, with too large bulk thermal resistance and contact thermal resistance, which affects the improvement of the current-carrying capacity of the device;

[0006] 2) The existing IGCT packaging structure is a rigid press connection, which has high requirements for the processing of packaging materials and device applications, and the device is prone to mechanical stress failure.

[0007] 3) The existing IGCT packaging structure is a ceramic shell, cold pressure welding seal, and gas insulation, with poor explosion-proof characteristics, which limits the application of the device in special working conditions such as short-circuit aging.

Summary of the Invention

[0008] Embodiments of the present invention provide a power semiconductor device packaging structure, method, power device, and electronic device, which improve the current-carrying capacity of the device.

[0009] In a first aspect, this application provides a power semiconductor device packaging structure, including:

[0010] A wafer, a cathode electrode, an anode electrode, a cathode housing electrode, and a housing;

[0011] The cathode electrode and the anode electrode are respectively located on opposite sides of the wafer;

[0012] One of the surfaces of the anode electrode is in direct contact with the first main surface of the wafer, and the other surface is exposed to the outside of the packaging structure;

[0013] One of the surfaces of the cathode electrode is in direct contact with the second surface of the wafer, and the other surface is connected to the cathode tube shell electrode through an elastic structure.

[0014] In this application, by improving the optimization effect of the anode-side thermal resistance, the current-carrying capacity of the device is improved. At the same time, an elastic component is provided on the cathode side, which improves the stress that the electrode side can withstand, and solves the problem that the device in the prior art is prone to mechanical stress failure.

[0015] A possible way is that it further includes a gate assembly, and the gate assembly includes: a gate insulating base, a gate lead-out ring, and a gate gasket;

[0016] The gate lead-out ring corresponds to the gate of the wafer;

[0017] The gate insulating base is used for insulating the gate and the cathode, and the gate insulating base is provided with a groove, and the size of the groove corresponds to the gate lead-out ring;

[0018] The gate lead-out ring is located between the wafer and the gate gasket.

[0019] A possible way is that the anode electrode and the wafer are interconnected by welding or sintering, and there is a positioning relationship between the gate insulating base and the cathode electrode. Based on the positioning relationship, the positions of the cathode electrode and the gate assembly and the cathode electrode are determined.

[0020] A possible way is that the anode electrode and / or the cathode electrode and / or the gate electrode adopt a composite material, and the thermal conductivity of the composite material ≥ 200 K / kW.

[0021] A possible way is that the composite material is one of molybdenum copper alloy, copper tungsten alloy, and copper diamond composite material.

[0022] A possible way is that the elastic component includes: an insulating plate, a current-carrying metal gasket, a cathode elastic component, and a gate elastic component;

[0023] The cathode elastic component is located above the cathode electrode;

[0024] The cathode elastic component includes a first elastic body and a first positioning frame;

[0025] The first positioning frame is used to position the first elastic body.

[0026] One possible way is that the first positioning frame is a porous copper block, and the first elastic body is a disc spring.

[0027] One possible way is that it further includes: a gate lead flange provided with grid bars, and a comb bar positioning groove is arranged on the top surface of the cathode electrode, and the grid bars are adapted to the comb bar positioning groove.

[0028] One possible way is that an insulating sleeve is sleeved outside the grid bars, and the insulating sleeve is used for insulating the gate and the cathode.

[0029] One possible way is that the gate lead flange and the tube shell are integrally formed.

[0030] One possible way is that the tube shell is made of a polymer composite material, and the insulation grade of the polymer composite material is ≥20 kV / mm, and the temperature resistance grade is ≥150 °C.

[0031] One possible way is that the tube shell and the anode electrode are sealed with a first insulating sealant, and the insulation grade of the first insulating sealant is ≥20 kV / mm, and the temperature resistance grade is ≥150 °C;

[0032] The cathode tube shell electrode and the tube shell are sealed with a second insulating sealant, and the insulation grade of the second insulating sealant is ≥20 kV / mm, and the temperature resistance grade is ≥150 °C.

[0033] In a second aspect, the present application provides a power semiconductor device packaging method, which is characterized in that it includes the packaging structure described in the first aspect, and specifically includes the following steps:

[0034] Install the anode electrode and the cathode electrode on opposite sides of the wafer, and install the gate assembly;

[0035] Bond the tube shell and the anode electrode with a first insulating sealant, and the tube shell is connected to the gate lead flange;

[0036] Install the elastic component, and use a customized pressing block and fixture to complete the silicone sealing of the wafer, the cathode electrode, the gate assembly, the elastic component, and the tube shell under the installation pressure condition;

[0037] Bond and seal the cathode tube shell electrode and the tube shell with a second insulating strength sealant.

[0038] One possible way is that in the step of asymmetrically installing the anode electrode and the cathode electrode on opposite sides of the wafer and installing the gate assembly,

[0039] Determine the positions of the cathode electrode and the gate assembly relative to the cathode electrode based on the positioning relationship between the gate insulating base and the cathode electrode.

[0040] One possible way is to install the elastic component, and use a customized pressing block and fixture to complete the silicone sealing step for the wafer, cathode electrode, gate component, elastic component, and shell under the installation pressure condition.

[0041] The silicone sealing strength is as follows:

[0042] The silicone gel is required to have an insulation strength ≥ 25 kV / mm, a temperature resistance ≥ 150 °C, and an operating time ≥ 2 h;

[0043] Before potting, the device is required to be dehumidified: 100 °C / 30 min;

[0044] The thickness of the silicone gel potting is 1 - 2 mm covering the cathode surface of the chip;

[0045] During the silicone gel potting process, the cavity vacuum is maintained at 100 - 120 mbar, and the whole process adopts multiple pressure holding - vacuum breaking - vacuum pumping - pressure holding until the silicone gel bubbles are completely removed.

[0046] In a third aspect, the present application provides a power device, including the packaging structure as described in the first aspect, and the power device is one of IGBT, GTO, Thyristor, and IGCT.

[0047] In a fourth aspect, the present application provides an electronic device, using the power device as described in the first aspect as the control element and / or current / voltage switching element of the electronic device.

[0048] It should be understood that the technical solutions of the second to third aspects of the embodiments of the present invention are consistent with those of the first aspect of the embodiments of the present invention, and the beneficial effects obtained by each aspect and the corresponding feasible implementation manners are similar, and will not be elaborated herein.

Description of the Drawings

[0049] Figure 1 It is the IGCT packaging structure diagram in the related art;

[0050] Figure 2 It is the schematic diagram of the power semiconductor device packaging structure provided by the embodiment of the present application;

[0051] Figure 3(a) is the three - dimensional view of the gate insulating base provided by the embodiment of the present application;

[0052] Figure 3(b) is the three - dimensional view of the gate lead - out ring provided by the embodiment of the present application;

[0053] Figure 3(c) is the schematic assembly diagram of the gate component provided by the embodiment of the present application;

[0054] Figure 4(a) is the schematic assembly diagram of the elastic component provided by the embodiment of the present application;

[0055] Figure 4(b) is a top view of the elastic component provided by the embodiment of the present application;

[0056] Figure 4(c) is a bottom view of the elastic component provided by the embodiment of the present application;

[0057] Figure 5(a) is a three-dimensional view of the gate lead-out flange provided by the embodiment of the present application;

[0058] Figure 5(b) is a three-dimensional view of the cathode electrode provided by the embodiment of the present application;

[0059] Figure 6 It is a three-dimensional view of the integral molding of the gate lead-out flange and the shell provided by the embodiment of the present application;

[0060] Figure 7 It is a three-dimensional view of the cathode shell electrode provided by the embodiment of the present application;

[0061] Figure 8 It is an exploded view of the power semiconductor device provided by the embodiment of the present application.

[0062] 101 - upper shell cover; 102 - anode molybdenum sheet; 103 - GCT chip; 104 - cathode molybdenum sheet, 105 gate lead-out ring; 106 - gate insulating seat; 107 - gate disc spring, 108 - lining tape, 109 - shell base; 110 - spokes and insulating sleeves;

[0063] 201 - anode electrode; 202 - wafer; 203 - cathode electrode; 204 - shell; 205 - cathode shell electrode;

[0064] 301 - gate insulating base; 302 - gate lead-out ring; 303 - gate spacer;

[0065] 401 - insulating board; 402 - current-carrying metal gasket; 403 - first elastomer; 404 - first positioning frame; 405 - second elastomer; 406 - second positioning frame;

[0066] 501 - grid bar; 502 - cathode electrode; 503 - comb bar positioning groove;

[0067] 801 - anode electrode; 802 - wafer; 803 - cathode electrode; 804 - insulating board; 805 - current-carrying metal gasket; 806 - gate insulating base; 807 - gate elastic component and cathode elastic component; 808 - positioning frame for gate elastic component and cathode elastic component; 809 - shell; 810 - gate lead-out flange; 811 - cathode shell electrode.

Detailed Implementation Manner

[0068] In order to better understand the technical solution of the embodiment of the present invention, the embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

[0069] It should be clear that the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments in the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope protected by the embodiments of the present invention.

[0070] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the embodiments of the present invention. The singular forms of "a", "the" and "said" used in the embodiments of the present invention and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0071] As a fully controlled power device with the largest single-tube capacity, the integrated gate commutated thyristor (IGCT) device is widely used in fields such as DC power transmission, smart grid, power converters, and power inverters due to its superior performance such as large capacity, fast switching speed, low switching loss, and high di / dt (current change rate) tolerance. It has broad prospects and huge future development space.

[0072] In the prior art, the packaging structure is a five-layer structure of anode copper electrode - anode molybdenum sheet - silicon chip - cathode molybdenum sheet - cathode copper electrode. Specifically, refer to Figure 1 , Figure 1 which is the IGCT packaging structure diagram in the prior art. Specifically, it includes: the upper cover 101 of the shell, the anode molybdenum sheet 102, the GCT chip 103, the cathode molybdenum sheet 104, the gate lead ring 105, the gate insulating seat 106, the gate disc spring 107, the lining tape 108, the base 109 of the shell, and the spokes and insulating sleeves 110. The electrical connection is realized through rigid contact by mechanical pressure. With the continuous improvement of the power level of IGCT devices, higher requirements are put forward for the packaging thermal resistance of the devices.

[0073] However, in the prior art, the following problems mainly exist:

[0074] 1) The existing IGCT device packaging structure is a five-layer structure of anode copper electrode - anode molybdenum sheet - silicon chip - cathode molybdenum sheet - cathode copper electrode, and the volumetric thermal resistance and contact thermal resistance are too large, which affects the improvement of the current-carrying capacity of the device;

[0075] 2) The existing IGCT packaging structure is a rigid press connection, which has high requirements for the processing of packaging materials and the application of devices, and the device is prone to mechanical stress failure.

[0076] 3) The existing IGCT packaging structure is a ceramic shell, cold pressure welding seal, and gas insulation, with poor explosion-proof characteristics, which limits the application of the device in special working conditions such as short-circuit failure.

[0077] In view of this, please refer to Figure 2 , the present application provides a power semiconductor device packaging structure, including:

[0078] a wafer 202, a cathode electrode 203, an anode electrode 201, and a package 204;

[0079] The cathode electrode 203 and the anode electrode 201 are respectively located on opposite sides of the wafer 202;

[0080] Wherein, one surface of the anode electrode 201 is in direct contact with the first main surface of the wafer 202, and the other surface is exposed to the outside of the packaging structure;

[0081] One surface of the cathode electrode 203 is in direct contact with the second surface of the wafer 202, and the other surface is connected to the cathode package electrode through an elastic structure (not marked in the figure).

[0082] The package 204 and the anode electrode are connected on the side close to the wafer 202, and the side of the anode electrode away from the wafer is exposed to the outside.

[0083] Compared with the prior art, in the embodiment provided by the present application, there is no package base at the bottom of the anode, the thermal resistance of the anode side of the device is optimized to the extreme, the optimization effect of the thermal resistance of the cathode side is abandoned, the current-carrying capacity of the device is improved, and at the same time, an elastic component is provided on the cathode side, which improves the stress that can be borne on the electrode side and solves the problem of mechanical stress failure of the device in the prior art.

[0084] At the same time, for the anode electrode, in order to better achieve contact with the wafer, welding, sintering and other technologies can be specifically used to achieve the whole-wafer interconnection of the wafer and the metal electrode through metallurgical bonding and diffusion.

[0085] For the anode electrode material, for the material selection, molybdenum-copper alloy, copper-tungsten alloy, copper-diamond composite material can be specifically used, and the thermal conductivity ≥ 200 K / kW.

[0086] Specifically, in the anode electrode, in order to ensure conductivity, the proportion of copper metal is greater than or equal to 60%.

[0087] At the same time, the anode electrode is provided with a boss, and the height of the boss ≥ the thickness of the red glue at the terminal of the IGCT wafer (generally exceeding 0.5 - 1 μm).

[0088] The cathode electrode can also be made of composite materials such as molybdenum-copper alloy, copper-tungsten alloy, and copper-diamond, and the thermal conductivity ≥ 200 K / kW.

[0089] Specifically, in the cathode electrode, in order to ensure conductivity, the proportion of copper metal is greater than or equal to 60%.

[0090] The gate components in the present application will be described below:

[0091] The gate components in the present application include: a gate insulating base, a gate lead-out ring, and a gate gasket;

[0092] The gate lead-out ring corresponds to the gate size in the wafer;

[0093] The gate insulating base is used for insulating the gate and the cathode, and the gate insulating base is provided with a groove, and the size of the groove corresponds to the gate lead-out ring;

[0094] The gate lead-out ring is located between the gate of the wafer and the gate gasket.

[0095] Specifically, the shape of the gate insulating base is shown in Fig. 3(a), the shape of the gate lead-out ring is shown in Fig. 3(b), and the assembly schematic diagram is shown in Fig. 3(c). In Fig. 3(c), it can be seen that the gate lead-out ring 302 needs to correspond to the size of the gate electrode of the wafer 202, the gate spacer 303 is located above the gate lead-out ring 302, and the gate lead-out ring 302 and the gate spacer 303 are embedded in the bottom of the groove of the gate insulating base 301. At this time, there is no cover under the anode electrode 201 (that is, there is no upper cover of the package in the prior art).

[0096] Based on this existing formula, wherein, R 阳极 , R 阴极 are the resistances of the anode electrode and the cathode electrode respectively, and R 器件 is the thermal resistance of the IGCT device. Thus, R 器件 ≤Min(R 阳极 , R 阴极 ).

[0097] Therefore, in this solution, the device thermal resistance is reduced by eliminating the contact thermal resistance between the anode electrode and the wafer and reducing the bulk thermal resistance of the anode electrode.

[0098] At the same time, when the junction temperature, the case temperature, and the voltage drop are certain, the current-carrying capacity of the device is linearly related to the thermal resistance of the device. By reducing the thermal resistance of the device, the current-carrying capacity of the device can be improved.

[0099] It can be understood that in the embodiment provided in the present application, there is a mutual positioning relationship between the gate insulating base and the cathode electrode. Using this positioning relationship, the positions of the cathode electrode, the gate component, and the cathode electrode can be determined.

[0100] Regarding the material of the gate electrode, a composite material can be used, specifically including but not limited to: molybdenum copper alloy, copper tungsten alloy, copper diamond, and its thermal conductivity ≥ 200 K / kW.

[0101] Specifically, in the gate electrode, in order to ensure conductivity, the proportion of copper metal is greater than or equal to 60%.

[0102] Regarding the material of the gate insulating seat, high-temperature resistant materials such as PI and PEEK can be specifically used, with the insulation level ≥ 50V and the temperature resistance level ≥ 150°C.

[0103] At the same time, one side of the gate lead-out ring is a stepped structure, and the width of the stepped surface is 80%-90% of the width of the electrode ring, which can prevent the gate cathode from short-circuiting while ensuring good contact.

[0104] Thus, the installation of the gate is completed. The following will elaborate on the elastic component in this application:

[0105] In the prior art, an elastic component is provided on the gate side. However, for semiconductor components installed in this way, the stress that can be borne on the electrode side is limited, which affects the reliability of the semiconductor device. To solve this problem, in this application, in addition to providing an elastic device on the gate side, an elastic device is also provided on the cathode side.

[0106] Specifically, referring to Fig. 4(a), the elastic component in this application includes:

[0107] It includes an insulating plate 401, a current-carrying metal gasket 402, a cathode elastic component, and a gate elastic component;

[0108] The cathode elastic component is located above the cathode electrode;

[0109] The cathode elastic component includes a first elastic body 403 and a first positioning frame 404;

[0110] The first positioning frame 404 is used to position the first elastic body 403.

[0111] Regarding the insulating plate 401, it is required to have the same shape as the cathode electrode, with the insulation level ≥ (device voltage level) and the temperature resistance level ≥ 150°C. It can be made of high-temperature resistant and insulating materials such as PI and PEEK.

[0112] Regarding the current-carrying metal gasket 402, its size and shape are the same as those of the cathode electrode, but openings are made at relevant positions of the elastic component. The device is electrically well-conducted by deforming the current-carrying metal gasket 402 through pressure. At this time, the anode and cathode currents of the device pass through the current-carrying metal gasket 402. Therefore, it is required that the current-carrying metal gasket has a certain large current-carrying capacity, with the large current tolerance ≥ 5kA, the fatigue life ≥ 100 times, and the temperature resistance capacity ≥ 150°C.

[0113] For the cathode elastic component, specifically referring to Fig. 4(a), its positioning frame (i.e., corresponding to the first positioning frame 404) is a porous copper block structure, and the elastic body is a disc spring component. The selection and design of the disc spring are determined according to the press-fitting force of the device; at the same time, the formation of the copper pressing block needs to be less than the deformation amount of the disc spring.

[0114] Correspondingly, for the gate elastic component, the cathode elastic component is located above the cathode electrode;

[0115] The gate elastic component includes a second elastic body 405 and a second positioning frame 406;

[0116] The second positioning frame 406 is used to position the second elastic body 405.

[0117] For the gate elastic component, the elastic component (i.e., the second elastic body 405) is composed of a copper pressing block, upper and lower gaskets, and disc springs. The selection and design of the disc springs are determined according to the press-fitting force of the device. At the same time, the formation of the copper pressing block needs to be less than the deformation amount of the disc spring. Thus, the top view of the elastic component is shown in Fig. 4(b) and the bottom view is shown in Fig. 4(c).

[0118] By setting the elastic component on the cathode side, the stress that the electrode side can withstand can be increased, and the safety of the overall power device can be improved.

[0119] On the basis of the foregoing embodiments, in the embodiments provided in the present application, specifically, the gate electrode is led out by a gate lead-out flange. Referring to Fig. 5(a), the gate lead-out flange is provided with grid bars. Combining with Fig. 5(b), a comb bar positioning groove 503 is provided on the top surface of the cathode electrode 502, and the grid bars are adapted to the comb bar positioning groove 503.

[0120] At the same time, in order to achieve insulation between the gate and the cathode, in the embodiments provided in the present application, an insulating sleeve is sleeved outside the grid bars, and the insulating sleeve is used for insulation between the gate and the cathode.

[0121] Regarding the selection of the insulating sleeve, the insulating sleeve is required to have an insulation grade ≥ 50V and a temperature resistance grade ≥ 150°C, and can be a high-temperature resistant material such as PI or PEEK.

[0122] By selecting such an insulating material, the requirements for the insulation grade of the semiconductor power device can be met.

[0123] At the same time, in the embodiments provided in the present application, specifically, the gate lead-out flange and the tube shell are integrally formed, and specifically, it can be formed by embedding / injection molding Figure 6 The structure shown.

[0124] On the basis of the foregoing embodiments, combined with related technologies, the semiconductor device can be packaged in the form of mechanical press-fitting. However, the following problems will occur through the mechanical packaging method:

[0125] The existing IGCT packaging structure is a rigid press connection, which has high requirements for the processing of packaging materials and device applications, and the device is prone to mechanical stress failure.

[0126] To solve the above problems, in this application, the tube shell and the anode electrode are sealed with a first insulating sealant, and the insulation grade of the first insulating sealant is ≥20 kV / mm, and the temperature resistance grade is ≥150 °C;

[0127] The cathode tube shell electrode and the tube shell are sealed with a second insulating sealant, and the insulation grade of the first insulating sealant is ≥20 kV / mm, and the temperature resistance grade is ≥150 °C.

[0128] Here, the difference between the first insulating sealant and the second insulating sealant is only the different usage scenarios. In some embodiments, the first insulating sealant and the second insulating sealant can be the same sealant, and those skilled in the art can select the insulating sealant by themselves according to the insulation grade and the temperature resistance grade.

[0129] On the basis of the foregoing embodiments, in some other embodiments, the rigid press connection in the prior art is replaced by a bonding method, which solves the problem that the mechanical press connection in the prior art is prone to stress failure, and further improves the explosion-proof ability of the semiconductor power device.

[0130] At the same time, in the related art, the material of the tube shell generally uses ceramics, and the explosion-proof performance of ceramics is poor, so the expansion application of semiconductor power devices in short-circuit failure conditions is greatly limited.

[0131] To solve this problem, in the embodiments provided in this application, the material of the tube shell is improved. Specifically, the tube shell uses a polymer composite material. Exemplarily, it can be a SMC glass fiber composite material. Regarding the requirements for the insulation grade and temperature resistance grade of the polymer material, specifically, the insulation grade is ≥20 kV / mm, and the temperature resistance grade is ≥150 °C. Thus, the explosion-proof performance of the device is improved by improving the material of the tube shell.

[0132] The following details the cathode tube shell electrode:

[0133] Refer to Figure 7 , the cathode tube shell electrode is composed of a skirt and a copper block. The skirt is made of oxygen-free copper material, and a deformation buffer step is designed, with a step height of 1-5 mm, to release the deformation during the device pressing process.

[0134] The copper block is made of oxygen-free copper material, and a step is designed, with a step width of 1-5 mm, for brazing and overlapping between the skirt and the copper block.

[0135] As described above, the cathode tube shell electrode abuts against the aforementioned elastic structure, that is, it contacts the aforementioned positioning frame (including the first positioning frame and the second positioning frame).

[0136] The above is the packaging structure of the power semiconductor device of the present application. Based on the foregoing, the present application has the following advantages:

[0137] 1) Compared with the prior art, the tube shell base is omitted, the thermal resistance on the anode side of the device is optimized to the extreme, the optimization effect of the thermal resistance on the cathode side is abandoned, and the current-carrying capacity of the device is improved.

[0138] 2) An elastic component is provided above the cathode electrode, increasing the stress threshold that the electrode side can withstand, solving the problem of easy stress failure in mechanical crimping in the prior art, and improving the safety of the overall power device.

[0139] 3) The adhesive structure is adopted to further improve the explosion-proof ability of the semiconductor power device, and at the same time reduce the requirements for the processing accuracy of the structural parts, reducing the cost.

[0140] 4) Using polymer composite materials to replace ceramics improves the explosion-proof performance of the device.

[0141] Based on the foregoing embodiments, the present application also provides a method for packaging a power semiconductor device, which specifically includes the following steps:

[0142] S101: Install the anode electrode and the cathode electrode on opposite sides of the wafer, and install the gate assembly;

[0143] Specifically, in this step, based on the positioning relationship between the gate insulating base 806 and the cathode electrode 803, the positions of the cathode electrode and the gate assembly and the cathode electrode 804 are determined.

[0144] Regarding the positioning relationship between the gate insulating base and the cathode electrode 803, reference can be specifically made to the foregoing embodiments. To avoid repetition, it will not be elaborated here.

[0145] Combined with Figure 8 and the foregoing embodiments, at this time, the anode electrode 801 and the wafer 802 can be connected by sintering or welding, and the cathode electrode 803 and the gate assembly are installed.

[0146] Specifically, first install the insulating plate 804, and then install the current-carrying metal gasket 805, the gate elastic component and the cathode elastic component 807 (including the aforementioned first elastic body and the second elastic body). Combining the foregoing, the gate elastic component and the cathode elastic component positioning frame 808 (including the aforementioned first positioning frame and the second positioning frame).

[0147] S102: Bond the package case and the anode electrode with a first insulating sealant, and connect the package case to the gate lead ring.

[0148] In Figure 8 In the illustrated embodiment, the package case 809 is integrally connected to the gate lead flange 810.

[0149] Regarding the relevant description of the first insulating sealant, reference can be made to the foregoing, and details will not be elaborated here.

[0150] S103: Install the elastic component, and use a customized pressing block and fixture to complete the silicone seal for the wafer, cathode electrode, gate component, elastic component, and package case under the installation pressure condition;

[0151] Regarding the silicone seal, the silicone seal strength is as follows:

[0152] The silicone gel is required to have an insulation strength ≥ 25 kV / mm, a temperature resistance ≥ 150 °C, and an operating time ≥ 2 h;

[0153] Before potting, the device is required to be dehumidified: 100 °C / 30 min;

[0154] The thickness of the silicone gel potting is 1 - 2 mm covering the cathode surface of the chip;

[0155] During the silicone gel potting process, the cavity vacuum degree is maintained at 100 - 120 mbar, and the whole process adopts multiple pressure holding - vacuum breaking - vacuum pumping - pressure holding until the silicone gel bubbles are completely removed.

[0156] Here, the gate lead flange is provided with a glue injection port for silicone seal.

[0157] S104: Bond and seal the cathode package case electrode 811 and the package case with a second insulating strength sealant.

[0158] Regarding the relevant description of the second insulating sealant, reference can be made to the foregoing, and details will not be elaborated here.

[0159] Meanwhile, the present application also provides a power device. The power device includes the packaging structure provided in the foregoing embodiment. The power device is one of IGBT, GTO, Thyristor, and IGCT, and the power device serves as a control element and / or a current / voltage switching element of the electronic device.

[0160] In all the examples shown and described here, any specific value should be construed as merely exemplary, not as a limitation. Therefore, other examples of the exemplary embodiments may have different values.

[0161] In addition, in the description of the embodiments of the present invention, unless otherwise clearly specified and limited, the terms "installation", "connection", and "coupling" shall be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0162] In the description of the embodiments of the present invention, the descriptions referring to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the embodiments of the present invention. In the embodiments of the present invention, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in the embodiments of the present invention and the features of different embodiments or examples.

[0163] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the embodiments of the present invention, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0164] Any process or method description shown in the flowchart or described in other ways herein can be understood as representing a module, segment, or part of code including one or more executable instructions for implementing a customized logical function or process. The scope of the preferred embodiments of the embodiments of the present invention includes additional implementations, where the functions can be executed in a substantially simultaneous manner or in the reverse order according to the involved functions, rather than in the order shown or discussed, which should be understood by those skilled in the art of the embodiments of the present invention.

[0165] The above are only the preferred embodiments of the embodiments of the present invention and are not intended to limit the embodiments of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the embodiments of the present invention shall be included within the scope of protection of the embodiments of the present invention.

Claims

1. A power semiconductor device packaging structure, characterized in that: include: Wafer, cathode electrode, anode electrode, cathode tube shell electrode and tube shell; The cathode electrode and the anode electrode are respectively located on two opposite sides of the wafer; the anode electrode and the cathode electrode are composite materials; The proportion of copper metal in the anode electrode is greater than or equal to 60%, one surface of the anode electrode is in direct contact with the first main surface of the wafer, and the other surface is exposed to the outside of the packaging structure; The proportion of copper metal in the cathode electrode is greater than or equal to 60%, one surface of the cathode electrode is in direct contact with the second surface of the wafer, and the other surface is connected to the cathode tube shell electrode through an elastic component; The elastic component comprises: an insulating plate, a current-carrying metal gasket, a cathode elastic component and a gate elastic component; The cathode elastic component is located above the cathode electrode; The cathode elastic component includes a first elastic body and a first positioning frame; The first positioning frame is used to position the first elastic body; The first positioning frame is a through-hole copper block, and the first elastic body is a disc spring; Grooves are arranged on both sides of the wafer, and the anode electrode and the cathode electrode cooperate with the grooves.

2. The packaging structure according to claim 1, characterized in that: Also included is a gate assembly, the gate assembly comprising: a gate insulating base, a gate lead ring and a gate gasket; The gate lead-out ring corresponds to the gate of the wafer; The gate insulating base is used for insulating the gate and the cathode, and the gate insulating base is provided with a groove, the size of which corresponds to the gate lead-out ring; The gate lead-out ring is located between the wafer and the gate gasket.

3. The packaging structure according to claim 2, characterized in that: The anode electrode and the wafer are interconnected by welding or sintering, and a positioning relationship exists between the gate insulating base and the cathode electrode. The positions of the cathode electrode and the gate assembly are determined based on the positioning relationship.

4. The packaging structure according to claim 3, characterized in that: The gate electrode is a composite material, and the thermal conductivity of the composite material is ≥200K / kW.

5. The packaging structure according to claim 4, characterized in that: The composite material is a molybdenum-copper alloy, a copper-tungsten alloy, or a copper-diamond composite material.

6. The packaging structure according to claim 1, characterized in that: Also includes: The gate lead-out flange is provided with grid bars, the top surface of the cathode electrode is provided with comb bar positioning grooves, and the grid bars are adapted to the comb bar positioning grooves.

7. The packaging structure according to claim 6, characterized in that: An insulating sleeve is sleeved outside the grid bar, and the insulating sleeve is used for insulating the gate and the cathode.

8. The packaging structure according to claim 6, characterized in that: The gate lead flange is integrally formed with the tube shell.

9. The packaging structure according to claim 1, characterized in that: The tube shell is made of a polymer composite material, and the insulation level of the polymer composite material is ≥20kV / mm and the temperature resistance level is ≥150°C.

10. The packaging structure according to claim 9, characterized in that: The tube shell and the anode electrode are sealed by a first insulating sealant, wherein the insulation level of the first insulating sealant is ≥20kV / mm and the temperature resistance level is ≥150°C; The cathode tube shell electrode and the tube shell are sealed with a second insulating sealant, and the insulation level of the second insulating sealant is ≥20kV / mm and the temperature resistance level is ≥150°C.

11. A method for packaging a power semiconductor device, characterized in that: The packaging structure according to any one of claims 1 to 10 comprises the following steps: Anode electrodes and cathode electrodes are asymmetrically installed on opposite sides of the wafer, and gate components are installed; The tube shell and the anode electrode are bonded with a first insulating sealant, and the tube shell is connected to the gate lead flange; Install the elastic component, and use a customized pressing block and fixture to complete the silicone sealing of the wafer, cathode electrode, gate component, elastic component and tube shell under the installation pressure condition; The cathode tube shell electrode is bonded and sealed with the tube shell by using a sealant with a second insulating strength.

12. The packaging method according to claim 11, characterized in that: In the step of asymmetrically installing anode electrodes and cathode electrodes on opposite sides of the wafer and installing gate components, The positions of the cathode electrode and the gate assembly are determined based on the positioning relationship between the gate insulating base and the cathode electrode.

13. The packaging method according to claim 11, characterized in that: In the step of installing the elastic component and using a customized pressing block and fixture to seal the wafer, cathode electrode, gate component, elastic component and tube shell under installation pressure conditions to complete silicone sealing, The silicone seal strength is as follows: Silicone gel requires insulation strength ≥25KV / mm, temperature resistance ≥150℃, and operating time ≥2h; The device must be dehumidified before potting: 100℃ / 30min; The thickness of silicone gel encapsulation is 1-2mm above the cathode surface of the chip; The silicone gel potting process maintains the cavity vacuum degree at 100-120mbar, and the whole process adopts multiple pressure maintenance-vacuum breaking-vacuum extraction-pressure maintenance until the silicone gel bubbles are completely removed.

14. A power device, characterized in that: Comprising the packaging structure according to any one of claims 1 to 10, the power device is one of IGBT, GTO and IGCT.

15. A power device, characterized in that: Comprising the packaging structure according to any one of claims 1 to 10, the power device is a Thyristor.

16. An electronic device, characterized in that: The power device according to claim 14 or 15 is used as a control element and / or a current / voltage switching element of the electronic device.

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