Compound semiconductor device packaging structure
By setting and sorting the package pins of gate electrode, source electrode and drain electrode on the integrated circuit structure layer of compound semiconductor devices, the coupling interference problems caused by traditional device packaging are solved, and the performance and reliability of the device are improved.
Patent Information
- Application Number
- CN202411945988.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-27
- Publication Date
- 2025-03-28
AI Technical Summary
During the packaging process, traditional power devices cause parasitic capacitance due to pin sorting, which causes coupling interference and affects product performance.
By providing the gate electrode, source electrode and drain electrode on the integrated circuit structure layer of the compound semiconductor device, and making the drive circuit and the power circuit do not intersect, ensure that the package pins of the gate electrode, source electrode and drain electrode are sorted by GSD.
It effectively reduces coupling interference, improves the performance and reliability of the device, and avoids the negative impact of parasitic capacitors on product performance.
Smart Images
Figure CN119725293A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a compound semiconductor device packaging structure. Background Art
[0002] Traditional power devices are generally vertical structures, with the gate electrode G and source electrode S on the front of the chip and the drain electrode D on the back. During packaging, the conductive adhesive patch is directly adhered to the packaging frame, so that the package pins are arranged in GDS order. For horizontal structure devices of compound semiconductors, the pin order can be freely defined and will not be restricted by the device structure. However, the current device structure with GDS arrangement of package pins will cause parasitic capacitance in the device, which will form coupling interference when the device is coupled, affecting product performance. Summary of the invention
[0003] An object of an embodiment of the present application is to provide a compound semiconductor device packaging structure that can effectively reduce coupling interference.
[0004] According to one aspect of an embodiment of the present application, a compound semiconductor device packaging structure is provided, comprising a packaging frame and a chip arranged on the packaging frame, wherein at least a gate electrode, a source electrode and a drain electrode are arranged on the integrated circuit structure layer of the chip, a drive circuit is formed between the gate electrode and the source electrode, a power circuit is formed between the source electrode and the drain electrode, and the drive circuit does not intersect with the power circuit.
[0005] The driving circuit and the power circuit do not intersect, so that the packaging pins of the gate electrode, source electrode and drain electrode are arranged according to GSD. In this way, the driving circuit and the power circuit formed by the gate electrode and the source electrode, and the source electrode and the drain electrode respectively do not intersect, thereby solving the problem of coupling interference and preventing the product performance from being affected by parasitic capacitance, thereby improving the performance and reliability of the device.
[0006] Optionally, the gate electrode, the source electrode and the drain electrode are all arranged on the front side of the chip, and pins are also formed on the packaging frame, and the pins include a drain pin electrically connected to the drain electrode, a gate pin electrically connected to the gate electrode, and a source pin electrically connected to the source electrode.
[0007] Optionally, there are multiple chips, and the multiple chips are connected through the source electrode.
[0008] Optionally, there are multiple pins, and the multiple pins are electrically connected to corresponding electrodes.
[0009] Optionally, a base island is further provided on the packaging frame, and the base island is connected to the source electrode of the chip.
[0010] Optionally, the base island at least includes a circuit board, a ceramic substrate and a bridge base island.
[0011] Optionally, the back side of the chip is attached to the packaging frame, the gate electrode and the source electrode are arranged on the back side of the chip, the drain electrode is arranged on the front side of the chip, the back side of the chip is attached to the packaging frame, and the drain electrode is connected to an external device through a connecting wire or a connecting board.
[0012] Optionally, the source electrode of the chip is connected to the packaging frame by means of wire bonding or copper jumper wires.
[0013] Optionally, the chip is welded on the packaging frame via a chip mounting material.
[0014] The compound semiconductor device packaging structure provided in the embodiment of the present application has at least a gate electrode, a source electrode and a drain electrode arranged on the integrated circuit structure layer of the chip, a drive circuit is formed between the gate electrode and the source electrode, a power circuit is formed between the source electrode and the drain electrode, the drive circuit and the power circuit do not intersect, and the packaging pins of the gate electrode, the source electrode and the drain electrode are arranged according to GSD, so as to solve the problem of coupling interference, so that the product performance will not be affected by the parasitic capacitance, thereby improving the performance and reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0016] Figure 1 It is a schematic diagram of the structure of the existing device;
[0017] Figure 2 This is one of the schematic diagrams of the compound semiconductor device packaging structure provided in this embodiment;
[0018] Figure 3 This is the second schematic diagram of the compound semiconductor device packaging structure provided in this embodiment;
[0019] Figure 4 This is the third schematic diagram of the compound semiconductor device packaging structure provided in this embodiment;
[0020] Figure 5 This is the fourth schematic diagram of the compound semiconductor device packaging structure provided in this embodiment;
[0021] Figure 6 This is the fifth schematic diagram of the compound semiconductor device packaging structure provided in this embodiment;
[0022] Figure 7 This is the sixth schematic diagram of the compound semiconductor device packaging structure provided in this embodiment;
[0023] Figure 8a This is the seventh schematic diagram of the compound semiconductor device packaging structure provided in this embodiment;
[0024] Figure 8b yes Figure 8a Schematic diagram of the packaging framework;
[0025] Figure 8c yes Figure 8a One of the perspective diagrams of the package;
[0026] Figure 8d yes Figure 8a The second perspective diagram of the package.
[0027] Icons: 10-packaging frame; 11-chip; 12-source electrode; 121-source pin; 13-gate electrode; 131-gate pin; 14-drain electrode; 141-drain pin; 151-connecting wire; 152-connecting belt; 161-circuit board; 162-bridge base island. DETAILED DESCRIPTION
[0028] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.
[0029] In the description of this application, it should be noted that the terms "inside", "outside", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the application is usually placed when in use, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.
[0030] It should also be noted that, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0031] In the prior art, such as Figure 1As shown, the packaging pins of the gate electrode (G), source electrode (S) and drain electrode (D) form a GDS arrangement. In this way, the driving circuit formed between the gate electrode and the source electrode and the power circuit formed between the source electrode and the drain electrode intersect, causing waveform oscillation and coupling interference during application.
[0032] To solve the above problems, refer to Figure 2 As shown, an embodiment of the present application provides a compound semiconductor device packaging structure, including: a packaging frame 10 and a chip 11 arranged on the packaging frame 10, wherein at least a gate electrode 13, a source electrode 12 and a drain electrode 14 are arranged on the integrated circuit structure layer of the chip 11, a driving circuit is formed between the gate electrode 13 and the source electrode 12, a power circuit is formed between the source electrode 12 and the drain electrode 14, and the driving circuit and the power circuit do not intersect.
[0033] The chip 11 is placed on the packaging frame 10, and at least a gate electrode 13, a source electrode 12 and a drain electrode 14 are formed on the integrated circuit structure layer of the chip 11; wherein the driving circuit formed between the gate electrode 13 and the source electrode 12 does not intersect with the power circuit formed between the source electrode 12 and the drain electrode 14.
[0034] For example, if the drive circuit and the power circuit do not intersect, the package pins of the gate electrode (G) 13, the source electrode (S) 12 and the drain electrode (D) 14 can be arranged in the same manner. Figure 2 As shown in the GSD arrangement, the driving circuit and the power circuit formed by the gate electrode (G) 13 and the source electrode (S) 12, and the source electrode (S) 12 and the drain electrode (D) 14 respectively do not intersect, thereby solving the problem of coupling interference, so that the product performance will not be affected by the parasitic capacitance, thereby improving the performance and reliability of the device.
[0035] Furthermore, the electrode surface of the source electrode 12 is larger than the electrode surface of the gate electrode 13 and the electrode surface of the drain electrode 14. In other words, the electrode surface of the source electrode 12 has the largest area on the package frame 10, so that in practical applications, the source electrode 12 can be directly used as a heat dissipation surface, and there is no need to design an insulation structure on the PCB circuit board, saving additional insulation costs.
[0036] The compound semiconductor device packaging structure of the present application can be applied to different product structures. Specifically, in the first embodiment, Figure 3 As shown, the gate electrode 13, the source electrode 12 and the drain electrode 14 are all arranged on the front side of the chip 11, and the back side of the chip 11 is attached to the package frame 10. Pins are also formed on the package frame 10, and the pins include a drain pin 141 electrically connected to the drain electrode 14, a gate pin 131 electrically connected to the gate electrode 13, and a source pin 121 electrically connected to the source electrode 12.
[0037] Figure 3 The diagram illustrates the structure of a single device in which only one chip 11 is arranged on the packaging frame 10. For such a single device, the chip 11 is directly soldered to the surface of the packaging frame 10 by means of solder paste or other mounting materials, and the source electrode 12 is directly electrically connected to the largest area of the packaging frame 10 by means of wire bonding or C l ip (copper jumper). Subsequently, conventional plastic sealing and separation are performed to complete the device packaging.
[0038] exist Figure 3 In the example, a plurality of source electrodes 12, a plurality of gate electrodes 13 and a plurality of drain electrodes 14 are formed on the chip 11, each source electrode 12 is electrically connected to a source pin 121, each gate electrode 13 is electrically connected to a gate pin 131, and each drain electrode 14 is electrically connected to a drain pin 141; and the package pins of the gate electrode (G) 13, the source electrode (S) 12 and the drain electrode (D) 14 are still arranged according to GSD, so that the driving circuit between the gate electrode (G) 13 and the source electrode (S) 12 and the power circuit between the source electrode (S) 12 and the drain electrode (D) 14 do not intersect.
[0039] On the basis of the single device in the first embodiment, a plurality of chips 11 may be arranged on the packaging frame 10 , that is, a device in which a plurality of chips 11 are sealed together is formed, and the plurality of chips 11 are connected via source electrodes 12 .
[0040] Specifically, in Example 2, refer to Figure 2 As shown, two chips 11 are arranged on the packaging frame 10 , wherein the source electrode 12 on the left chip 11 is electrically connected to its source pin 121 , and the gate electrode 13 is electrically connected to its gate pin 131 .
[0041] Part of the source electrode 12 on the right chip 11 is electrically connected to its source pin 121 , and part of the source electrode 12 is electrically connected to the left chip 11 ; the drain electrode 14 on the right chip 11 is electrically connected to its drain pin 141 .
[0042] For this type of multi-packaged device, the packaging process is the same as that of the aforementioned embodiment 1, that is, the chip 11 is directly soldered to the frame surface through mounting materials such as solder paste, and the device source electrode 12 is directly electrically connected to the largest area of the packaging frame 10 through wire bonding or Clip, followed by conventional plastic packaging and separation to complete the device packaging.
[0043] In Example 3, refer to Figure 4 As shown, there are multiple pins, and the multiple pins are electrically connected to corresponding electrodes.
[0044] In the third embodiment, the packaging frame 10 can be reshaped and designed to have eight pins or more pins.
[0045] The chip 11 can be set to multiple or single, and is connected in the same way that the source electrode 12 is electrically connected to the source pin 121, the gate electrode 13 is electrically connected to the gate pin 131, and the drain electrode 14 is electrically connected to the drain pin 141. The source electrode 12 is wired or electrically connected to the maximum area of the frame electrode in a Clip manner.
[0046] In the fourth embodiment, a base island may be further provided on the packaging frame 10 , and the base island is connected to the source electrode 12 of the chip 11 .
[0047] For example Figure 5 The base island is a PCB circuit board 161 or a ceramic substrate, the source electrode 12 of the chip 11 is electrically connected to the PCB circuit board or the ceramic substrate, and the connection method between the source, drain and gate of the chip 11 and its introduction is performed with reference to the above implementation, and the source electrode 12 is transferred to the largest area of the packaging frame 10 by wire bonding or Clip.
[0048] Alternatively, the base island can also be Figure 6 The bridge base island 162 is electrically bonded on the upper and lower surfaces of the bridge base island 162 through vias, and then the source electrode 12 of the device is connected to the source pin 121 of the packaging frame 10 by wire bonding or Clip.
[0049] Refer to Figure 7 The fifth embodiment can also be a non-SMD packaged device, with each pin extending outside the package frame 10, and can also be applied to direct plug-in or other package shapes.
[0050] Depend on Figure 7 It can be more clearly seen that the gate pin 131 , the source pin 121 and the drain pin 141 on the packaging frame 10 of the present application are arranged in the order of GSD.
[0051] The sixth embodiment is different from the above five embodiments. The sixth embodiment is a vertical structure device. Figure 8a , Figure 8b As shown, the back side of the chip 11 is attached to the packaging frame 10, the gate electrode 13 and the source electrode 12 are arranged on the back side of the chip 11, and the drain electrode 14 is arranged on the front side of the chip 11 ( Figure 8a The back side of the chip 11 is attached to the packaging frame 10, and the drain electrode 14 on the front side is connected to the packaging frame 10. Figure 8c The connection line 151 or Figure 8d The connecting strip 152 is electrically connected to the drain pin 141 .
[0052] The front side of the chip 11 is welded to the frame surface, and the back side of the chip 11 is directly connected to the device source electrode 12 by wire bonding or clipping to the largest area of the packaging frame 10, followed by conventional plastic encapsulation and separation to complete the device packaging.
[0053] At this time, since the back side of the chip 11 is directly attached to the surface of the package frame 10, the gate electrode 13 and the source electrode 12 on the back side of the chip 11 are directly in contact with the package frame 10 and electrically connected, eliminating the need for the wire connection method in the previous embodiment. Figure 8c The connection line 151 or Figure 8d The connecting strip 152 is electrically connected to the drain pin 141 .
[0054] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A compound semiconductor device packaging structure, characterized in that: include: A packaging frame and a chip arranged on the packaging frame, wherein the integrated circuit structure layer of the chip is at least provided with a gate electrode, a source electrode and a drain electrode, a driving circuit is formed between the gate electrode and the source electrode, a power circuit is formed between the source electrode and the drain electrode, and the driving circuit does not intersect with the power circuit.
2. The compound semiconductor device packaging structure according to claim 1, characterized in that: The gate electrode, the source electrode and the drain electrode are all arranged on the front side of the chip, and pins are also formed on the packaging frame, and the pins include a drain pin electrically connected to the drain electrode, a gate pin electrically connected to the gate electrode, and a source pin electrically connected to the source electrode.
3. The compound semiconductor device packaging structure according to claim 2, characterized in that: There are multiple chips, and the multiple chips are connected through the source electrode.
4. The compound semiconductor device packaging structure according to claim 3, characterized in that: There are multiple pins, and the multiple pins are electrically connected to corresponding electrodes.
5. The compound semiconductor device packaging structure according to claim 2, characterized in that: A base island is also provided on the packaging frame, and the base island is connected to the source electrode of the chip.
6. The compound semiconductor device packaging structure according to claim 5, characterized in that: The base island at least includes a circuit board, a ceramic substrate and a bridge base island.
7. The compound semiconductor device packaging structure according to claim 2, characterized in that: The back side of the chip is attached to the packaging frame, the gate electrode and the source electrode are arranged on the back side of the chip, the drain electrode is arranged on the front side of the chip, and the drain electrode is electrically connected to the drain pin through a connecting wire or a connecting belt.
8. The compound semiconductor device packaging structure according to any one of claims 1 to 6, characterized in that: The source electrode of the chip is connected to the packaging frame by means of bonding wires or copper jumpers.
9. The compound semiconductor device packaging structure according to any one of claims 1 to 7, characterized in that: The chip is welded on the packaging frame through chip mounting material.