Microelectronic structure including glass substrate with dielectric-based liner material

Abstract

The invention relates to a microelectronic structure including a glass substrate having a dielectric-based liner material. A microelectronic integrated circuit package structure includes a device having a substrate including a glass layer, the substrate including one or more through-glass vias (TGVs) extending through the glass layer. The individual TGV includes a TGV sidewall, an organic dielectric layer on the TGV sidewall, and a conductive layer on the organic dielectric layer.

Description

Background Art

[0001] In electronics manufacturing, integrated circuit (IC) packaging is the manufacturing stage where an IC, which has been fabricated on a die or chip comprising semiconductor material, is coupled to a supporting housing or "package" that protects the IC from physical damage and supports electrical interconnections suitable for further connection to a host component such as a printed circuit board (PCB). In the IC industry, the process of manufacturing a package is often referred to as packaging or assembly.

[0002] Some multi-die packaging architectures may include an IC die attached to a glass substrate and coupled to conductive through-glass vias (TGVs) extending through the glass substrate. However, the glass substrate has a much lower coefficient of thermal expansion (CTE) than many conductive materials. Therefore, thermal cycling during the manufacture and operation of the TGVs may generate thermal stresses in and around the TGVs, which may lead to reliability issues and reduced device yields. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The subject matter described herein is illustrated by way of example and not limitation in the accompanying drawings. For simplicity and clarity of illustration, the elements shown in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Furthermore, where considered appropriate, reference numerals have been repeated between the drawings to indicate corresponding or similar elements. In the drawings:

[0004] Figures 1A-1E is a cross-sectional view of an IC package structure including a dielectric-based liner material according to some embodiments.

[0005] Figures 2A-2F is a cross-sectional view of an IC package structure including a dielectric-based liner material according to some embodiments.

[0006] Figures 3A-3D is a cross-sectional view of an IC package structure including a dielectric-based liner material according to some embodiments.

[0007] Figures 4A-4C is a cross-sectional view of an IC package structure including a dielectric-based liner material according to some embodiments.

[0008] Figures 5A-5D is a cross-sectional view of an IC package structure including a dielectric-based liner material according to some embodiments.

[0009] Figures 6A-6C is a cross-sectional view of an IC package structure including a dielectric-based liner material according to some embodiments.

[0010] Figure 7is a cross-sectional view of an IC package structure including a dielectric-based liner material according to some embodiments.

[0011] Figures 8A-8B A flow chart of a process for fabricating an IC package structure having a dielectric-based liner material is shown in accordance with some embodiments.

[0012] Fig. 9 is a functional block diagram of an electronic computing device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0013] Embodiments are described with reference to the accompanying drawings. Although specific configurations and arrangements are described and discussed in detail, it should be understood that this is done for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of this specification. It will be apparent to those skilled in the relevant art that the techniques and / or arrangements described herein can be employed in a variety of other systems and applications in addition to the systems and applications described in detail herein.

[0014] Reference is made to the accompanying drawings in the following detailed description, which form a part of the detailed description and illustrate exemplary embodiments. In addition, it should be understood that other embodiments may be utilized and structural and / or logical changes may be made without departing from the scope of the claimed subject matter. It should also be noted that directions and references (e.g., up, down, top, bottom, etc.) may be used only to facilitate the description of features in the accompanying drawings. Therefore, the following detailed description should not be considered to have a limiting meaning, and the scope of the claimed subject matter is limited only by the attached claims and their equivalents.

[0015] In the following description, many details are set forth. However, it will be apparent to those skilled in the art that embodiments may be practiced without these specific details. In some cases, known methods and apparatus are shown in block diagram form rather than in detail to avoid making the embodiments difficult to understand. References throughout this specification to "embodiment" or "one embodiment" or "some embodiments" indicate that the specific features, structures, functions or characteristics described in conjunction with the embodiment are included in at least one embodiment. Therefore, the phrases "in an embodiment" or "in an embodiment" or "some embodiments" that appear in various positions throughout this specification do not necessarily refer to the same embodiment. In addition, specific features, structures, functions or characteristics may be combined in any suitable manner in one or more embodiments. For example, the first embodiment may be combined with the second embodiment anywhere where the specific features, structures, functions or characteristics associated with the two embodiments are not mutually exclusive.

[0016] As used in the specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0017] The terms "coupling" and "connection" and their derivatives may be used in this article to describe the functional or structural relationship between components. It should be understood that these terms are not intended to be synonymous with each other. On the contrary, in a particular embodiment, "connection" may be used to indicate that two or more elements are in direct physical, optical or electrical contact with each other. "Coupling" may be used to indicate that two or more elements are in direct or indirect (with other intermediate elements between them) physical or electrical contact with each other, and / or that two or more elements cooperate or interact with each other (e.g., as in a cause-and-effect relationship).

[0018] As used herein, the terms "above," "below," "between," and "on" refer to the relative position of one component or material with respect to other components or materials where such physical relationship is noteworthy. For example, in the context of materials, a material or layer above or below another material or layer may be in direct contact or may have one or more intervening materials or layers. Additionally, a material between two materials or layers may be in direct contact with both materials / layers or may have one or more intervening materials / layers. Conversely, a first material or layer "above" a second material or layer is in direct physical contact with the second material / layer. Similar distinctions are made in the context of component assemblies.

[0019] As used throughout the specification and claims, a list of items connected by the term "at least one of" or "one or more of" may mean any combination of the listed terms. For example, the phrase "at least one of A, B, or C" may mean A; B; C; A and B; A and C; B and C; or A, B, and C.

[0020] Unless otherwise indicated in the context of explicit use, the term "predominantly" means greater than 50% or greater than half. For example, a composition having predominantly a first component means that more than half of the composition is the first component (e.g., <50 atomic %). The term "predominantly" means the majority or largest portion. For example, a composition having predominantly the first component means that the composition has more of the first component than any other component.

[0021] The term "package" generally refers to a self-contained carrier of one or more dies, wherein the die is attached to a package substrate and may be encapsulated for protection, with integrated or wire-bonded interconnections between the die and leads, pins, or bumps located on an external portion of the package substrate. A package may contain a single die or multiple dies that provide a specific function. Packages are typically mounted on a printed circuit board for interconnection with other packaged integrated circuits and discrete components to form a larger circuit.

[0022] The term "dielectric" generally refers to any number of non-conductive materials that make up the structure of a package substrate.

[0023] The term "metallization" generally refers to a metal layer formed over and through the dielectric material of a package substrate. The metal layer is typically patterned to form metal structures, such as traces and bond pads. The metallization of a package substrate may be limited to a single layer or multiple layers separated by dielectric layers.

[0024] The term "bond pad" generally refers to the metallization structure that terminates integrated traces and vias in integrated circuit packages and dies. The term "pad" may occasionally replace "bond pad" and has the same meaning.

[0025] The term "solder bump" generally refers to a solder layer formed on a bonding pad. The solder layer generally has a circular shape, hence the term "solder bump".

[0026] The term "substrate" generally refers to a planar platform including dielectric and metallization structures. The substrate mechanically supports and electrically couples one or more IC die on a single platform, wherein one or more IC die are encapsulated by a moldable dielectric material. The substrate generally includes solder bumps as bonding interconnects on both sides. One side of the substrate (commonly referred to as the "die side") includes solder bumps for chip or die bonding. The opposite side of the substrate (commonly referred to as the "land side") includes solder bumps for bonding the package to a printed circuit board.

[0027] Vertical orientation is in the z direction, and it should be understood that the descriptions of "top", "bottom", "above" and "below" refer to relative positions in the z dimension with common meanings. However, it should be understood that the embodiments are not necessarily limited to the orientations or configurations shown in the figures.

[0028] The terms "substantially," "close," "approximately," "near," and "about" generally mean within + / -10% of a target value (unless otherwise specified). Unless otherwise specified, the use of ordinal adjectives "first," "second," and "third," etc. to describe common objects merely indicates different instances of the similar objects being referred to, and is not intended to imply that the objects so described must be in a given order in time, space, order, or in any other manner.

[0029] The views labeled "Section," "Profile," and "Plan" correspond to orthogonal planes within a Cartesian coordinate system. Thus, section and profile views are taken in the xz plane, and plan views are taken in the xy plane. Typically, profile views in the xz plane are section views. The figures are labeled with axes to indicate the orientation of the figure, where appropriate.

[0030] Embodiments discussed herein address issues associated with packaging architectures and methods employing glass substrates. Such methods include using through-glass vias (TGVs) to produce high input / output (I / O) density devices with minimal warpage. Glass substrates with adjustable CTE, small total thickness variation (TTV), and adjustable optical properties can be formed. Glass-based substrates or interposers can provide better interconnect performance in advanced 2.5D and 3D packaging structures. Copper-filled TGVs provide vertical electrical connections and facilitate heat dissipation in advanced packaging structures.

[0031] However, due to the CTE mismatch between the conductive material and the glass, thermal cycling during the manufacture and operation of the TGV can generate thermal stress in and around the TGV. To relieve thermal stress, an organic dielectric liner or buffer layer can be introduced between the conductive material and the glass in the TGV. The glass strength can be restored to its original level by separating the conductive material from the glass sidewall using a low modulus liner. Such a low modulus liner can include a metal liner, a parylene liner, or a combination of a metal and an organic dielectric liner.

[0032] Embodiments describe a substrate including a glass layer including one or more TGVs extending through the glass layer. The glass substrate may include an interposer or core. One or more TGVs include TGV sidewalls. An organic dielectric layer may be formed on the TGV sidewalls, wherein in embodiments, the organic dielectric material may be molded into the TGV of the glass substrate. A wide range of organic dielectric materials having suitable CTE and modulus values ​​may be selected to buffer stresses that occur during thermal cycling of, for example, conductive materials that are plated to fill the TGVs. After the molding process, the organic dielectric material may be inserted into the TGV.

[0033] The organic dielectric molding material within the TGV can then be drilled by utilizing mechanical drilling, laser drilling, or ultraviolet (UV) lithography processes to form openings in the organic dielectric material. In an embodiment, for example, a conductive layer can be formed on the organic dielectric layer by utilizing a plating process. In an embodiment, the conductive material can fill the openings in the organic dielectric material. The basic component that enables the glass interposer or core is a TGV filled with a conductive material, which provides a vertical electrical connection and promotes heat dissipation. The conductive material provides an interconnect path, which is used to conductively couple the glass substrate to the device within the packaging structure. An electrical wiring structure including a redistribution layer (RDL) metallization portion can be constructed on at least one side of the glass substrate, and (multiple) IC dies can be assembled to the wiring structure. The method improves TGV reliability with a dielectric-based liner material.

[0034] Embodiments herein enable a cost-effective process that can prevent TGV failure.Molding equipment used according to embodiments herein facilitates the insertion of organic dielectrics into TGVs.

[0035] The architecture described herein can be assembled and / or manufactured with one or more of the features or properties provided according to various embodiments. According to one or more of the features or properties described herein, many different assembly and / or manufacturing methods can be implemented for the TGV with an organic dielectric liner in a glass packaging structure.

[0036] Figures 1A-1E An embodiment of a package structure including a TGV with an organic dielectric liner is shown. The package structure is formed using standard deposition and lithography processing techniques. The fabrication methods described herein produce improved interconnect performance in advanced 2.5D and 3D packages.

[0037] Figure 1A 1 is a cross-sectional view of a portion of an integrated circuit (IC) package structure 100 according to some embodiments. As shown, a substrate 102 includes a glass layer 102, wherein the glass layer 102 includes one or more of aluminosilicate, borosilicate, aluminoborosilicate, silicon dioxide, or fused silicon dioxide. The glass layer 102 may include one or more additives, such as Al2O3, B2O3, MgO, CaO, SrO, BaO, SnO2, Na2O, K2O, SrO, P2O3, ZrO2, Li2O, Ti, or Zn. In an embodiment, the glass may include silicon and oxygen, and any one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and zinc.

[0038] In an embodiment, the glass layer 102 may include at least 23 wt% silicon and at least 26 wt% oxygen, and may also include at least 5 wt% aluminum. In an embodiment, the glass layer 102 may include a solid glass layer that is rectangular in shape in a plan view. In an embodiment, the glass layer 102 does not include an organic binder or an organic material. The substrate 102 may include a glass core or a glass interposer that provides mechanical benefits such as reduced warping, less thickness variation, and design flexibility by providing tighter via spacing and finer core routing.

[0039] The organic dielectric layer 112 may be on the sidewalls 113 and on the first surface 101 and the second surface 107 of the substrate 102. The organic dielectric material 112 may include an organic material such as an epoxy molding compound, a build-up dielectric (ABF), or a photoimageable dielectric (PID) material such as a polyimide material. In an embodiment, the organic dielectric material 112 may have micron or nanometer-sized particle fillers therein, or a mixture of fiber and particle fillers. The filler in the organic dielectric material 112 may include silicates, quartz, mica, silicates, titanium dioxide, amorphous silicon dioxide, magnesium carbonate, aluminum nitride, aluminum oxide, boron nitride, magnesium hydroxide, chalk, limestone, feldspar, barium sulfate, solid or hollow fillers, permanent magnetic metal compounds, and / or alloys or mixtures thereof.

[0040] A wide range of organic dielectric materials having suitable coefficients of thermal expansion (CTE) and moduli may be selected to buffer the stress of the conductive material 114 within the TGV 103a during thermal cycling of the package structure. For example, in the case where the substrate comprises a CTE of 4-9 ppm / K, the CTE of the organic dielectric material 112 may be less than about 25 ppm / K. In an embodiment, the organic dielectric material 112 may comprise an elastic modulus of less than about 15 GPa. In an embodiment, the thickness 117 of the organic dielectric layer 112 on the sidewalls 113 of the substrate 102 may comprise less than about 25% of the lateral width 109 of the TGV 103a.

[0041] Conductive layer 114 may be on organic dielectric material 112. In an embodiment, thickness 119 of conductive layer 114 on organic dielectric layer 112 may include less than about 25% of lateral width 109 of TGV 103a. In an embodiment, conductive layer 114 may include copper material or copper alloy, but may include any suitable conductive material. Conductive layer 114 forms an interconnect path with which any device coupled within or to package structure 100 is conductively coupled.

[0042] The additional organic dielectric material 115 may be within the TGV 103a, wherein the TGV 103a includes an organic dielectric material 112 on a sidewall 113 of the substrate 102, a conductive material 114 on the organic dielectric material 112, and an additional organic dielectric material 115 on the conductive material 114. In an embodiment, the TGV 103a includes a via structure 103a filled with an organic dielectric material. In an embodiment, the additional organic dielectric material 115 may include a material different from the organic dielectric material 112. In other embodiments, the additional organic dielectric material 115 may include the same material as the organic dielectric material 112. The additional organic dielectric material 115 may include an organic dielectric plug for the TGV 103a. In an embodiment, the organic dielectric layer 112 includes a first organic dielectric layer, and the additional organic dielectric layer 115 includes a second dielectric layer, wherein the second organic dielectric layer is on a conductive layer opposite to the first organic dielectric layer.

[0043] Figure 1B 1 is a cross-sectional view of a portion of an integrated circuit (IC) package structure 121 according to some embodiments. As shown, the substrate 102 includes a glass layer, wherein the glass layer includes aluminosilicate, borosilicate, aluminoborosilicate, silicon dioxide and molten silica. The glass layer may include one or more additives, such as Al2O3, B2O3, MgO, CaO, SrO, BaO, SnO2, Na2O, K2O, SrO, P2O3, ZrO2, Li2O, Ti and Zn. The glass layer may include silicon and oxygen, as well as any one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium and zinc, and may include at least 23% by weight of silicon and at least 26% by weight of oxygen.

[0044] The organic dielectric layer 112 may be on the sidewalls 113 and on the first surface 101 and the second surface 107 of the substrate 102. The organic dielectric material 112 may include an organic material such as an epoxy molding compound, a build-up dielectric (ABF), a photoimageable dielectric (PID) such as a polyimide. In an embodiment, the organic dielectric material 112 may have micron or nanometer-sized particle fillers therein, or a mixture of fiber and particle fillers. The filler in the material may include silicates, quartz, mica, silicates, titanium dioxide, amorphous silicon dioxide, magnesium carbonate, aluminum nitride, aluminum oxide, boron nitride, magnesium hydroxide, chalk, limestone, feldspar, barium sulfate, solid or hollow fillers, permanent magnetic metal compounds and / or alloys or mixtures thereof.

[0045] In an embodiment, a thickness 117 of the organic dielectric layer 112 on the sidewalls 113 of the substrate 102 may include less than about 25% of the lateral width 109 of the TGV 103 opening. A conductive material 114 may be on the organic dielectric material 112. In an embodiment, the conductive material 114 may fill one or more TGVs 103b, wherein the one or more TGVs may include the organic dielectric material 112 on the sidewalls 113 of the substrate 102 and a conductive material on the organic dielectric material 112. A thickness 119 of the conductive layer 114 on the organic dielectric layer 112 may include more than about 30% of the lateral width 109 of the TGV / via structure 103b.

[0046] In an embodiment, the conductive material 114 may include a copper material or a copper alloy, but may include any suitable conductive material. The conductive material 114 forms an interconnect path with which any device coupled within or to the package structure 100 is conductively coupled, wherein the conductive material 114 includes a conductive TGV 103b plug. In an embodiment, the conductive material 114 may be on the surface 101 of the substrate 102, wherein the individual TGVs 103b are conductively coupled to each other.

[0047] Figure 1C FIG. 1 is a cross-sectional view of a portion of an integrated circuit (IC) package structure 122 according to some embodiments. As shown, the substrate 102 includes a glass layer, such as a glass layer similar to FIG. Figure 1A The glass layer 102. In an embodiment, the substrate 102 may include a glass core or interposer and may provide mechanical benefits such as reduced warping, less thickness variation, and design flexibility (tighter via pitch, finer core routing).

[0048] The thin layer 116 may be on the sidewall 113 and on the first surface 101 and the second surface 107 of the substrate 102. The thin layer 116 may include a polyparaxylene material or a conductive material such as aluminum. In an embodiment, the thin layer 116 may include a thickness less than 25% of the lateral width of one or more TGVs 103c. The conductive material 114 may be on the thin layer 116. The conductive material 114 may include any suitable conductive material, such as copper or a copper alloy. In an embodiment, the organic dielectric material 112 may be on the conductive material 114. The organic dielectric material 112 may include an organic dielectric material such as the following materials: epoxy molding compound, build-up dielectric (ABF), photoimageable dielectric (PID) such as polyimide. In an embodiment, the organic dielectric material 112 may have micron or nanometer-sized particle fillers therein, or a mixture of fibers and particle fillers. The filler in the material may include silicate, quartz, mica, silicate, titanium dioxide, amorphous silicon dioxide, magnesium carbonate, aluminum nitride, aluminum oxide, boron nitride, magnesium hydroxide, chalk, limestone, feldspar, barium sulfate, solid or hollow fillers, permanent magnetic metal compounds and / or alloys or mixtures thereof.

[0049] The CTE of the organic dielectric material 112 may be less than about 25 ppm / K. In an embodiment, the organic dielectric material may include an elastic modulus less than about 15 GPa. In an embodiment, the thickness of the organic dielectric layer 112 on the conductive layer 114 may include more than about 25% of the lateral width 109 of the one or more TGVs 103c, in an embodiment, wherein the organic dielectric layer may be a plug of the TGV 103c. In an embodiment, the one or more TGVs 103c may include a thin layer 116 on the sidewalls 113 of the substrate 102, a conductive layer 114 on the thin layer 116, and an organic dielectric material 112 on the thin layer 116.

[0050] Figure 1D-1E FIG. 1 shows a portion of the glass substrate 102 of the encapsulation structures 123 and 124, wherein the organic dielectric material 112 in the via structure 103b includes a plurality of hollow filling materials. Figure 1D In the embodiment, the organic dielectric material 112 of the portion of the integrated circuit (IC) package structure 122 includes a hollow filling material 120. The organic dielectric material 112 is on the sidewall 113 of the glass substrate 102. In an embodiment, the concentration of the hollow filling material 120 in the organic dielectric material 112 includes about 1-85% by weight. The conductive material 114 fills the via 103b. Figure 1E , a portion of an integrated circuit (IC) package structure 124 is shown, wherein a conductive material 114 is on a sidewall 113 of a glass substrate 102. An organic dielectric material 112 including a void-filling material 120 fills the via 103a.

[0051] Figures 2A-2F The formation of an IC package structure (eg Figures 1A-1E An embodiment of an IC packaging structure). Figure 2A A cross-sectional view of a portion of a substrate 102 according to some embodiments is shown. As shown, the substrate 102 may include a glass layer 102. An IC device packaging structure may be manufactured on the substrate 102. The substrate 102 includes a flatness and / or thickness control for a glass preform that is superior to the flatness and / or thickness control of a starting substrate based on an organic material (e.g., epoxy resin), and the cost may be significantly lower than the cost of a single crystal material (e.g., silicon). The substrate 102 may include a solid bulk material layer that may be preformed into any shape suitable for a plan view (e.g., an xy plane) of a packaged workpiece, such as a rectangular shape. The substrate 102 includes a thickness 110 that may be optimized according to specific design requirements, such as to limit warping while remaining thin enough to allow through-glass vias (TGVs) to be formed at a spacing optimized for specific design requirements. In an exemplary embodiment, the thickness 110 may include between about 200 microns and about 2000 microns.

[0052] Advantageously, silicon and oxygen predominate in the substrate 102. In some embodiments, the substrate 102 includes at least 23 weight percent (i.e., weight %) silicon and at least 26 weight percent oxygen. The substrate 102 may also include one or more additives, such as aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, or zinc. In some embodiments in which the substrate 102 includes at least 23 weight percent Si and at least 26 weight percent O, the substrate 102 also includes at least 5 weight percent Al. The additives within the substrate 102 may form suboxides (A2O), monoxides (AO), binary oxides (AO2), ternary oxides (ABO3), and mixtures thereof. For example, the substrate 102 may include AlO x (e.g. Al2O3), BO x (e.g. B2O3), MgO x (e.g. MgO), CaO x (e.g. CaO), SrO x (e.g. SrO), BaO x (e.g. BaO), SnO x (e.g. SnO2), NaO x (such as Na2O), KO x (e.g. K2O), PO x (e.g. P2O3), ZrO x (such as ZrO2), LiO x (e.g. Li2O), TiO x (such as TiO2) or ZnO x(eg, ZnO2). Depending on the chemical composition, the substrate 102 may therefore be referred to as, for example, silicon dioxide, fused silica, aluminosilicate, borosilicate, or aluminoborosilicate.

[0053] Compared to composite materials that may include only glass fillers and / or fibers, substrate 102 is advantageously a bulk material having a substantially uniform composition. Although in some embodiments substrate 102 is substantially amorphous, substrate 102 may also have other morphologies or microstructures, such as polycrystalline (eg, nanocrystalline).

[0054] Although not shown, one or more material layers may be coated on either or both of the first surface 101 or the second surface 107, wherein the first surface 101 is opposite to the second surface 107, so that in an embodiment, the substrate 102 may include a bulk layer or a core layer of a multi-layer substrate 102. Exemplary coating materials include inorganic materials such as silicon nitride (SiN x ) or silicon oxynitride (SiO x N y In other embodiments, a silicon layer (polycrystalline or single crystal) may cover the first surface 101 and / or the second surface 107 of the substrate 102. An organic material layer (such as a polymer dielectric material) may also cover the first surface 101 and / or the second surface 107 of the substrate 102.

[0055] exist Figure 2B In the embodiment, one or more TGVs 103a may be formed in and through the substrate 102 using process 151. Process 151 may include processes such as drilling or chemical etching processes. In embodiments, any process known to be suitable for forming TGVs 103a in bulk glass may be used. In some embodiments, a laser ablation process, a glass etching process (laser assisted or otherwise), or any other such technique known to be suitable for forming features (e.g., holes) through the thickness of a substrate may be used to achieve the desired diameter and feature spacing of one or more TGVs 103a.

[0056] In an embodiment, the length 111 of the sidewall 113 of an individual TGV 103a may include substantially the same size as the thickness 110 of the substrate 102. That is, one or more TGVs 103a extend through the thickness 110 of the substrate 102. In an embodiment, the width 109 of one or more TGVs 103a may include between approximately 50 microns and 100 microns, but may be optimized depending on the particular application.

[0057] A process 153 may be employed in which an organic dielectric material 112 may be formed on a substrate 102 and at least partially within one or more TGVs 103 ( Figure 2C). In an embodiment, process 153 may include processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), slit coating, lamination, or molding methods. The molding process may include, but is not limited to, compression molding, lamination, hot pressing, or transfer molding.

[0058] The organic dielectric material 112 may include organic materials such as epoxy molding compounds, build-up dielectrics (ABF), photoimageable dielectrics (PID) such as polyimide. In an embodiment, the organic dielectric material 112 may have micron or nanometer-sized particle fillers therein, or a mixture of fiber and particle fillers. The fillers in the material may include silicates, quartz, mica, silicates, titanium dioxide, amorphous silicon dioxide, magnesium carbonate, aluminum nitride, aluminum oxide, boron nitride, magnesium hydroxide, chalk, limestone, feldspar, barium sulfate, solid or hollow fillers, permanent magnetic metal compounds, and / or alloys or mixtures thereof.

[0059] The organic dielectric material 112 may be selected to have a wide range of suitable coefficients of thermal expansion (CTE) and moduli to buffer stress of conductive materials subsequently formed within the TGV 103 during thermal cycling of the package structure. For example, where the substrate 102 includes a CTE of 4-9 ppm / K, the CTE of the organic dielectric material 112 may be less than about 25 ppm / K. In an embodiment, the organic dielectric material 112 may include an elastic modulus of less than about 15 GPa.

[0060] Process 155 may be employed after forming an organic dielectric material 112 on substrate 102, wherein the organic dielectric material 112 may be inserted into one or more substrate 102 TGVs 103 ( Figure 2D ). The organic dielectric material 112 may be drilled by mechanical drilling or laser drilling, or may be subjected to ultraviolet (UV) lithography to form the organic dielectric layer 112 on the sidewalls of the TGV 103a. In this manner, one or more TGVs 103b including the organic dielectric layer 12 on the sidewalls of the TGV 103b include a polymer via 103b in a glass via (via in a via structure) that enhances the mechanical strength of the glass substrate 102 and prevents crack propagation within the substrate 102. In an embodiment, the thickness 117 of the organic dielectric layer 112 on the sidewall 113 of the TGV 103b may include less than about 25% of the lateral width 109 of the TGV 103b sidewall 113 opening.

[0061] This can be accomplished by using the forming process 157 ( Figure 2E)A conductive material 114 is formed on the organic dielectric layer 112. In an embodiment, the conductive material 114 may be formed by first forming a conductive seed layer on the organic dielectric layer 112 and then plating the conductive material 114 on the conductive seed layer so that the via 103 is filled with the conductive material 114. In an embodiment, the conductive material 114 may include a copper material 114 or a copper alloy, but may also include any suitable conductive material. The conductive material forms an interconnect path, by which any device coupled within or to the package structure 100 is conductively coupled. The conductive material 114 includes a conductive TGV 103b plug. In an embodiment, the first surface 101 and / or the second surface 107 of the substrate 102 may be ground or polished 159 to form a flat planarized surface 101, 107. ( Figure 2F ).

[0062] Figures 3A-3D The formation of a package structure according to an embodiment of the present disclosure is shown. Figure 3A shows, for example, something like Figure 2A-2E The substrate 102 of the substrate 102 may include a glass layer 102. The IC device packaging structure / device may be manufactured on the substrate 102. One or more TGVs 103 are within the substrate 102 and pass through the substrate 102. Similar to Figures 2A-2F The organic dielectric layer 112 of the organic dielectric layer 112 may be on the sidewall 113 of the TGV 103a. In an embodiment, the thickness 117 of the organic dielectric layer 112 on the sidewall 113 of the TGV 103a may include less than about 25% of the lateral width 109 of the TGV 103 sidewall 113 opening.

[0063] exist Figure 3B In the embodiment of the present invention, the conductive layer 114 can be formed on the organic dielectric layer 112 using the formation process 157, for example, similar to Figure 2E In an embodiment, the thickness 119 of the conductive layer 114 on the organic dielectric layer 112 can be formed to include less than about 25% of the lateral width 109 of the TGV 103 opening. In another embodiment, the conductive material 114 can be formed to initially fill the TGV 103 and can then be drilled to leave the center of the via 103 open.

[0064] exist Figure 3C In the embodiment of the present invention, an additional organic dielectric layer 115 may be formed on the conductive layer 114 using a forming process 153, for example, similar to Figure 2CIn an embodiment, the additional organic dielectric material 115 may include the same material as the organic dielectric material 112, or may include a different organic dielectric material. In an embodiment, the organic dielectric layer 115 material may include an organic material such as an epoxy molding compound, a build-up dielectric (ABF), or a photoimageable dielectric (PID) such as polyimide.

[0065] In an embodiment, the additional organic dielectric material 115 may have micron or nanometer sized particle fillers therein, or a mixture of fiber and particle fillers. The fillers in the material may include silicates, quartz, mica, silicates, titanium dioxide, amorphous silicon dioxide, magnesium carbonate, aluminum nitride, aluminum oxide, boron nitride, magnesium hydroxide, chalk, limestone, feldspar, barium sulfate, solid or hollow fillers, permanent magnetic metal compounds and / or alloys or mixtures thereof.

[0066] The additional organic dielectric material 115 may be selected to have a suitable coefficient of thermal expansion (CTE) and modulus to buffer the stress of the conductive material subsequently formed within the TGV 103 during thermal cycling of the package structure. For example, in the case where the substrate includes a CTE of 4-9 ppm / K, the CTE of the organic dielectric material may be less than about 25 ppm / K. In an embodiment, the additional organic dielectric material 115 may include an elastic modulus of less than about 15 GPa. In this way, a glass-organic dielectric-conductive layer-organic dielectric via structure is formed to improve the reliability of the entire substrate 102. Figure 3D Another embodiment is shown, wherein the conductive material 114 of the package structure 100 may be formed on a surface of the substrate 102 , wherein individual TGVs are electrically coupled to each other through the surface conductive layer 114 .

[0067] Figures 4A-4C The formation of a package structure according to an embodiment of the present disclosure is shown. Figure 4A In the embodiment, a glass substrate 102 is provided, wherein one or more TGVs 103 extend through the glass substrate 102. A conductive layer 114 ( Figure 4B ). In an embodiment, conductive layer 114 may include thickness 119, which may be formed to include less than about 25% of lateral width 109 of TGV 103 opening. In another embodiment, conductive material 114 may be formed to initially fill TGV 103b, and may then be drilled, leaving the center of via 103c open.

[0068] A forming process 153 may then be employed, wherein an organic dielectric material 112 may be formed on the conductive layer 114 using the forming process 153, for example, similar to Figure 2C The formation process ( Figure 4C In an embodiment, the organic dielectric material 112 material may include an organic material such as epoxy molding compound, build-up dielectric (ABF), or a photo-imageable dielectric (PID) such as polyimide.

[0069] A molding process may be performed to insert the organic dielectric material 112 into the center of the TGV 103. The organic dielectric plug of the TGV exhibits good adhesion to the conductive material 114, has a low modulus (which may reduce thermal shrinkage of the conductive material 114), and provides thermal stress reduction while preventing delamination of the conductive material from the glass substrate 102.

[0070] Figures 5A-5D The formation of a package structure according to an embodiment of the present disclosure is shown. Figure 5A In the embodiment, a glass substrate 102 is provided, wherein one or more TGVs 103 extend through the glass substrate 102. A thin layer 116 may be formed on the sidewalls 113 of the TGVs 103 ( Figure 5B ). In an embodiment, thin layer 116 may include polyparaxylene material or a thin conductive material, such as aluminum. Thin layer 116 may be formed using any suitable formation process, such as a physical vapor deposition process, wherein thin layer 116 may serve as a stress buffer layer. Conductive layer 114 may be formed directly on thin layer 116 ( Figure 5C ). Conductive layer 114 may include a thickness that may be formed to include less than about 25% of the lateral width of the TGV 103 opening, in an embodiment, leaving TGV 103 open. Organic dielectric material 112 is then inserted into TGV 103 by using, for example, a molding process ( Figure 5D ).

[0071] Figures 6A-6C The formation of a package structure according to an embodiment of the present disclosure is shown. Fig. 6A In the embodiment, a glass substrate 102 is provided, wherein one or more TGVs 103 extend through the glass substrate 102. In an embodiment, a laser induced direct etching (LIDE) technique is used to sensitize and etch the glass substrate 102 according to the desired size of the TGV structure. The glass substrate 102 is then preferentially etched at the laser sensitized area using hydrofluoric acid to form a TGV opening structure.

[0072] Similar to Figures 2A-2FThe organic dielectric layer 112 of the organic dielectric layer 112 may be formed 153 on the sidewall 113 of the TGV 103. In an embodiment, the organic dielectric material 112 may include a plurality of hollow fillers. In an embodiment, the organic dielectric material 112 may be formed inside the TGV 103 using a slit coating process or a lamination process or a molding method. In an embodiment, the organic dielectric material 112 may include a plurality of hollow SiO2 fillers 120 in a resin material such as ABF. In an embodiment, the hollow fillers 120 may be filled with an ambient gas. In an embodiment, the thickness of the organic dielectric layer 112 on the sidewall 113 of the substrate 102 may include less than about 25% of the lateral width of the TGV 103 opening. The filled vias 103 are then drilled and metallized with a conductive material (e.g., copper or a copper alloy) to form high-speed interconnect vias ( Figure 6B ). In an embodiment, the surface metal and organic dielectric material 112 may be planarized and metallized to form conductive traces and pads on the substrate 102 .

[0073] Instead of implementing the hollow filler containing organic dielectric as a liner, it can also be integrated into the core TGV as a plug material. In an embodiment, the conductive layer 114 can be formed on the sidewalls of the substrate 102, and then a via is drilled at the center portion of the TGV 103, and then plugged with the hollow filler containing organic dielectric material 112 using a molding or slit coating or lamination process to produce a package structure 124 ( Figure 6C ).

[0074] Figure 7 An IC package structure 200 is shown, wherein the dies 126a, 126b are, for example, on a substrate 102 (such as Figure 1A In some embodiments, the die 126a, 126b may include chiplet structures 126a, 126b, which may include components of a system-on-chip (SOC) structure. According to any of the embodiments disclosed herein, the die 126a, 126b are coupled to each other and to the glass substrate 102 (e.g., including the TGV vias 103) through a redistribution layer (RDL) metallization 130. Figures 2A-2F 126a, 126b.

[0075] The discussion now turns to the operations for assembling and / or manufacturing the discussed structures.

[0076] Fig. 8A is a flow chart of a process 800 for manufacturing a package structure according to some embodiments. For example, the process 800 can be used to manufacture Figures 2A-2F Any one of the microelectronic IC packaging structures.

[0077] As described in block 802, a substrate may be provided, wherein the substrate includes a glass layer. In an embodiment, the glass layer may include aluminosilicates, borosilicates, aluminoborosilicates, silicon dioxide, and molten silica. The glass layer may include one or more additives, such as Al2O3, B2O3, MgO, CaO, SrO, BaO, SnO2, Na2O, K2O, SrO, P2O3, ZrO2, Li2O, Ti, and Zn. The glass layer may include silicon and oxygen, and any one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and zinc. The glass layer may include at least 23% by weight of silicon and at least 26% by weight of oxygen, and also include at least 5% by weight of aluminum. The glass layer may be a solid bulk material layer that may be preformed into any shape, such as a rectangle, suitable for a plan view (e.g., an xy plane) of a packaged workpiece. In an embodiment, the glass layer has a thickness that can vary depending on the implementation, for example to limit warping while remaining thin enough to allow formation of vias at a pitch as small as that achieved by the surface flatness of the glass layer. In an embodiment, the glass layer is advantageously 200 microns to 2000 microns thick.

[0078] Advantageously, the glass layer is dominated by silicon and oxygen. In some embodiments, the glass layer includes at least 23 weight percent (i.e., weight %) silicon and at least 26 weight percent oxygen. In some embodiments where the glass layer includes at least 23 weight percent Si and at least 26 weight percent O, the glass layer also includes at least 5 weight percent Al. Additives within the glass can form suboxides (A2O), monoxides (AO), binary oxides (AO2), ternary oxides (ABO3), and mixtures thereof. For example, the glass may include AlO x (e.g. Al2O3), BO x (e.g. B2O3), MgO x (e.g. MgO), CaO x (e.g. CaO), SrO x (e.g. SrO), BaO x (e.g. BaO), SnO x (e.g. SnO2), NaO x (such as Na2O), KO x (e.g. K2O), PO x (e.g. P2O3), ZrOx (such as ZrO2), LiO x (e.g. Li2O), TiO x (such as TiO2) or ZnO x (eg ZnO2). Depending on the chemical composition, the glass may therefore be referred to as, for example, silicon dioxide, fused silica, aluminosilicate, borosilicate or aluminoborosilicate.

[0079] In step 804, a plurality of through glass vias (TGVs) are formed in the glass substrate. The conductively filled TGVs provide vertical electrical connections and facilitate heat dissipation. The plurality of TGVs may be formed using a drilling or chemical etching process. In an embodiment, any process known to be suitable for forming TGVs in bulk glass may be used. In some embodiments, a laser ablation process, a glass etching process (laser assisted or otherwise), or any other such technique known to be suitable for forming features (e.g., holes) through the thickness of the glass may be used to achieve the desired diameter and feature spacing. Laser induced direct etching (LIDE) techniques may be used to initially sensitize the etched glass. The glass substrate is then preferentially etched in the laser sensitized area using hydrofluoric acid to form the TGV opening structure.

[0080] In step 806, an organic dielectric layer may be formed on the sidewalls of the TGV. In an embodiment, the organic dielectric layer may be formed on the sidewalls of the TGV using a process such as slit coating, lamination, or molding. The molding process may include, but is not limited to, compression molding, lamination, hot pressing, or transfer molding. The organic dielectric layer may include an organic material such as an epoxy molding compound, an build-up dielectric (ABF), a photoimageable dielectric (PID) such as a polyimide. The organic dielectric material may have a micron or nanometer sized particle filler, or a mixture of fiber and particle filler. The filler in the material may include silicates, quartz, mica, silicates, titanium dioxide, amorphous silicon dioxide, magnesium carbonate, aluminum nitride, aluminum oxide, boron nitride, magnesium hydroxide, chalk, limestone, feldspar, barium sulfate, solid or hollow fillers, permanent magnetic metal compounds, and / or alloys or mixtures thereof. In an embodiment, the thickness of the organic dielectric layer may include less than about 25% of the diameter of the TGV opening.

[0081] After the molding process, an organic dielectric material (which may include a polymer organic dielectric material) may be inserted into the plurality of TGVs. The organic dielectric material may then be drilled by mechanical drilling, laser drilling, ultraviolet (UV) lithography to form vias lined with organic dielectric material. In an embodiment, the organic dielectric layer on the sidewall of the glass substrate may include a polymer via within a glass via (via in via), which enhances the mechanical strength of the glass and prevents stress crack formation and propagation.

[0082] In an embodiment, the organic dielectric layer may include a plurality of hollow filler structures. In an embodiment, the hollow filler structures may include substantially spherical hollow structures and may comprise about 1-85% by weight within the organic dielectric layer.

[0083] In step 808, a conductive layer may be formed on the organic dielectric layer. In an embodiment, the conductive layer may include copper or a copper alloy material. In an embodiment, a copper seed layer may be initially deposited (using any suitable deposition process) on the organic dielectric layer, and copper may then be plated on the seed layer so that the TGVs are filled with the conductive layer. After the TGVs are filled with the conductive layer, the top or bottom surface of the substrate may be ground or polished to form a flat surface. In an embodiment, a conductive material layer may be formed on the surface of the substrate to conductively couple each TGV to each other, such as Figure 1B shown.

[0084] In an alternative embodiment, after the conductive seed layer is deposited, a thin layer of a conductive layer is plated on the surface of the TGV to form a conductive path, or the TGV can be plated and then drilled, leaving the center portion of the TGV open. An additional amount of organic dielectric material can then be placed inside the TGV (using a molding process or any other suitable process) to fill the center portion of the TGV with additional organic dielectric material. Thus, a glass-organic dielectric layer-conductive layer-organic dielectric layer structure can be formed to improve the reliability of the substrate.

[0085] Figure 8B is a flow chart of a process 810 for manufacturing a package structure according to some embodiments. For example, process 810 can be used to manufacture Figures 4A-4C Any one of the microelectronic IC packaging structures.

[0086] As described in block 812, a substrate may be provided, wherein the substrate includes a glass layer. In an embodiment, the glass layer may include aluminosilicate, borosilicate, aluminoborosilicate, silicon dioxide, and molten silica. The glass layer may include one or more additives, such as Al2O3, B2O3, MgO, CaO, SrO, BaO, SnO2, Na2O, K2O, SrO, P2O3, ZrO2, Li2O, Ti, and Zn. The glass layer may include silicon and oxygen, and any one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and zinc. The glass layer may include at least 23% by weight of silicon and at least 26% by weight of oxygen, and also include at least 5% by weight of aluminum. In an exemplary embodiment, the thickness of the glass layer is advantageously 200 microns to 2000 microns.

[0087] At step 814, a plurality of through glass vias (TGVs) are formed in the glass substrate. The plurality of TGVs may be formed using a drilling or chemical etching process. In embodiments, any process known to be suitable for forming TGVs in bulk glass may be used. In some embodiments, a laser ablation process, a glass etching process (laser assisted or otherwise), or any other such technique known to be suitable for forming features (e.g., holes) through the thickness of glass may be used to achieve the desired diameter and feature spacing.

[0088] At step 816, a conductive layer may be formed on the organic dielectric layer. In an embodiment, the conductive layer may include copper or a copper alloy material. In an embodiment, a copper seed layer may be initially deposited on the organic dielectric layer (using any suitable deposition process), and then the conductive layer may be plated on the seed layer. The conductive layer is plated only on the surface of the TGV to form a conductive path. The center of the TGV remains open.

[0089] In another embodiment, before forming the conductive layer, a material such as parylene (C|C16H14Cl2) or a thin metal liner with a different composition from the conductive layer is deposited directly on the TGV glass sidewalls, where the parylene or thin metal layer acts as a stress buffer. The conductive layer is then plated onto the parylene or thin metal liner sidewalls, leaving the center of the TGV open.

[0090] At step 818, a molding process is then performed to coat the substrate with an organic dielectric material such as Fig. 8A In an embodiment, the conductive material is in direct contact with the glass substrate, but the organic dielectric plug in the center exhibits good adhesion to the conductive layer, and its low modulus can reduce thermal shrinkage of the conductive layer, as well as balance thermal stress and prevent delamination of the conductive layer from the glass substrate. After filling the TGV with the conductive layer, the top or bottom surface of the substrate can be ground or polished to form a flat surface. In an embodiment, the organic dielectric layer can include a plurality of hollow filler structures. In an embodiment, the hollow filler structure can include a generally spherical hollow structure and can include about 1-85% by weight within the organic dielectric layer.

[0091] Embodiments described herein enable the fabrication of improved TGV structures for 2.5 to 3D devices. The disclosed structures and methods increase the reliability of packaging structures combining TGVs with organic dielectric-based liner materials. The cost-effective methods described herein prevent TGV failures. The molding equipment used in the present disclosure facilitates the insertion of dielectrics into TGV structures. A wide range of organic dielectric materials with suitable CTE and modulus can be selected to buffer the stress of conductively plated TGVs during thermal cycling.

[0092] Fig. 9An electronic or computing device 900 according to one or more embodiments of the present specification is shown. The computing device 900 may include a housing 901 in which a board 902 is disposed. The computing device 900 may include a plurality of integrated circuit components, including but not limited to a processor 904, at least one communication chip 906a, 906b, a volatile memory 908 (e.g., DRAM), a non-volatile memory 910 (e.g., ROM), a flash memory 912, a graphics processor or CPU 914, a digital signal processor (not shown), a cryptographic processor (not shown), a chipset 916, an antenna, a display (touch screen display), a touch screen controller, a battery, an audio codec (not shown), a video codec (not shown), a power amplifier (AMP), a global positioning system (GPS) device, a compass, an accelerometer (not shown), a gyroscope (not shown), a speaker, a camera, and a mass storage device (not shown) (such as a hard drive, a compact disk (CD), a digital versatile disk (DVD), etc.). Any integrated circuit component may be physically and electrically coupled to the board 902. In some embodiments, at least one of the integrated circuit components may be part of the processor 904.

[0093] The communication chip implements wireless communication for transmitting data to and from the computing device. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, technologies, communication channels, etc. that can transfer data via non-solid media using modulated electromagnetic radiation. The term does not mean that the associated device does not include any wires, although in some embodiments they may not. The communication chip can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and thereafter. The computing device may include multiple communication chips. For example, the first communication chip can be dedicated to shorter-range wireless communications such as Wi-Fi and Bluetooth, and the second communication chip can be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0094] The term "processor" may refer to any device or portion of a device that processes electronic data from a register and / or memory to convert the electronic data into other electronic data that may be stored in the register and / or memory. At least one of the integrated circuit components may include a device having a substrate including a glass layer, the substrate including one or more through-glass vias (TGVs) extending through the glass layer, the one or more TGVs including TGV sidewalls, an organic dielectric layer on the sidewalls; and a conductive layer on the organic dielectric layer.

[0095] In various embodiments, the computing device may be a laptop computer, a netbook, a notebook, an ultrabook, a smart phone, a tablet computer, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video camera. In other embodiments, the computing device may be any other electronic device that processes data.

[0096] Although certain features set forth herein have been described with reference to various embodiments, the description is not intended to be construed in a limiting sense. Therefore, various modifications of the embodiments described herein and other embodiments that are apparent to those skilled in the art to which the present disclosure pertains are considered to fall within the spirit and scope of the present disclosure. It should be understood that the subject matter of the present specification is not necessarily limited to the specific applications shown in Figures 1-9. The present subject matter may be applied to other integrated circuit device and component applications, as well as any appropriate electronic applications, as will be appreciated by those skilled in the art.

[0097] The following examples relate to additional embodiments, and the details in the examples can be used anywhere in one or more embodiments, wherein the first example is a device comprising a substrate, the substrate comprising a glass layer. The substrate comprises one or more through-glass vias (TGVs) extending through the glass layer, wherein individual TGVs in the one or more TGVs comprise a TGV sidewall, the TGV sidewall comprising a TGV length equal to the thickness of the substrate. An organic dielectric layer is on the TGV sidewall, and a conductive layer is on the organic dielectric layer.

[0098] In a second example, wherein the first example further includes wherein the conductive layer includes at least one of copper or a copper alloy.

[0099] In a third example, for any of Examples 1-2, further including, wherein the organic dielectric layer includes one or more of an epoxy molding compound, a build-up dielectric, or a photoimageable dielectric (PID).

[0100] In a fourth example, for any one of Examples 1-3, the organic dielectric layer includes a filling material, and the filling material includes one or more of silicate, quartz, mica, titanium dioxide, amorphous silica, magnesium carbonate, aluminum nitride, aluminum oxide, boron nitride, magnesium hydroxide, chalk, limestone, feldspar or barium sulfate.

[0101] In a fifth example, wherein the fourth example further includes wherein the filling material comprises a hollow filling material.

[0102] In a sixth example, the fifth example further includes wherein a concentration of the hollow filling material in the organic dielectric layer includes 1 to 85 weight percent.

[0103] In a seventh example, for any of Examples 1-6, wherein the organic dielectric layer includes a first organic dielectric layer, and wherein a second organic dielectric layer is on the conductive layer and opposite the first organic dielectric layer.

[0104] In an eighth example, for any of Examples 1-7, wherein individual TGVs of the one or more TGVs are filled with a conductive layer.

[0105] In a ninth example, for any of Examples 1-8, wherein the conductive layer comprises a lateral width greater than twice a lateral width of the organic dielectric layer.

[0106] In a tenth example, for any of Examples 1-9, wherein a surface conductive layer is on a surface of the substrate and contacts the one or more TGVs.

[0107] In an eleventh example, for any one of Examples 1-10, wherein the substrate includes a glass interposer or a glass core structure, the glass interposer or the glass core structure having a rectangular shape in a plan view.

[0108] In a twelfth example, for any of Examples 1-11, further including a die coupled to the substrate.

[0109] The thirteenth example is a device comprising: a substrate, the substrate comprising a glass layer, the substrate comprising one or more through-glass vias (TGVs) extending through the glass layer, wherein an individual TGV of the one or more TGVs comprises: a TGV sidewall, the TGV sidewall comprising a TGV length equal to the thickness of the substrate; a conductive layer, the conductive layer adjacent to the TGV sidewall; and an organic dielectric layer, the organic dielectric layer on the conductive layer.

[0110] In a fourteenth example, the thirteenth example also includes wherein a parylene layer is between the conductive layer and the TGV sidewall.

[0111] In a fifteenth example, for any of Examples 13-14, wherein the organic dielectric layer comprises a thickness greater than twice a thickness of the conductive layer, and wherein the organic dielectric layer fills individual TGVs of the one or more TGVs.

[0112] In a sixteenth example, for any one of Examples 13-15, the organic dielectric layer includes a filling material, and the filling material includes one or more of silicate, quartz, mica, titanium dioxide, amorphous silica, magnesium carbonate, aluminum nitride, aluminum oxide, boron nitride, magnesium hydroxide, chalk, limestone, feldspar or barium sulfate.

[0113] In a seventeenth example, for any of Examples 13-16, further including a die coupled to the substrate.

[0114] An eighteenth example is a method comprising: providing a substrate comprising a glass layer; forming one or more through-glass vias (TGVs) in the substrate; forming an organic dielectric layer on TGV sidewalls of individual TGVs in the one or more TGVs; and forming a conductive layer on the organic dielectric layer.

[0115] In the nineteenth example, the eighteenth example further includes forming an additional organic dielectric layer on the conductive layer.

[0116] In a twentieth example, for any one of Examples 18-19, further comprising forming a polyparaxylene layer between the organic dielectric layer and the conductive layer, wherein the organic dielectric layer includes a plurality of hollow filling materials.

[0117] It will be appreciated that the principles of the present disclosure are not limited to the embodiments described above, but can be practiced with modification and alteration without departing from the scope of the appended claims. The above embodiments may include only a subset of the features, a different order of the features, a different combination of the features, and / or additional features other than those explicitly listed. Therefore, the scope of the embodiments should be determined by reference to the appended claims and the full scope of equivalents to which the claims are entitled.

Claims

1. A device comprising: A substrate comprising a glass layer, the substrate comprising one or more through-glass vias (TGVs) extending through the glass layer, wherein an individual TGV of the one or more TGVs comprises: a TGV sidewall, the TGV sidewall comprising a TGV length equal to the thickness of the substrate; an organic dielectric layer on a sidewall of the TGV; and A conductive layer is on the organic dielectric layer.

2. The device according to claim 1, wherein: The conductive layer includes at least one of copper or a copper alloy.

3. The device according to claim 1, wherein: The organic dielectric layer includes one or more of an epoxy molding compound, a build-up dielectric, or a photoimageable dielectric (PID).

4. The device according to claim 1, wherein: The organic dielectric layer includes a filling material, and the filling material includes one or more of silicate, quartz, mica, titanium dioxide, amorphous silicon dioxide, magnesium carbonate, aluminum nitride, aluminum oxide, boron nitride, magnesium hydroxide, chalk, limestone, feldspar or barium sulfate.

5. The device according to claim 4, wherein: The filling material includes a hollow filling material.

6. The device according to claim 5, wherein: The concentration of the hollow filling material in the organic dielectric layer includes 1 to 85 weight percent.

7. The device according to claim 1, wherein: The organic dielectric layer includes a first organic dielectric layer, and wherein a second organic dielectric layer is on the conductive layer and opposite to the first organic dielectric layer.

8. The device according to claim 1, wherein: The individual TGVs of the one or more TGVs are filled with the conductive layer.

9. The device according to claim 1, wherein: The conductive layer includes a lateral width greater than twice a lateral width of the organic dielectric layer.

10. The device according to claim 1, wherein: A surface conductive layer is on the surface of the substrate and contacts the one or more TGVs.

11. The device according to claim 1, wherein: The substrate includes a glass interposer or a glass core structure having a rectangular shape in a plan view.

12. The apparatus of claim 1, further comprising a die coupled to the substrate.

13. An apparatus comprising: A substrate comprising a glass layer, the substrate comprising one or more through-glass vias (TGVs) extending through the glass layer, wherein an individual TGV of the one or more TGVs comprises: a TGV sidewall, the TGV sidewall comprising a TGV length equal to the thickness of the substrate; a conductive layer adjacent to the TGV sidewall; and An organic dielectric layer is on the conductive layer.

14. The device according to claim 13, wherein: A parylene layer is between the conductive layer and the TGV sidewalls.

15. The device according to claim 13, wherein: The organic dielectric layer comprises a thickness greater than twice a thickness of the conductive layer, and wherein the organic dielectric layer fills the individual TGVs of the one or more TGVs.

16. The device according to claim 13, wherein: The organic dielectric layer includes a filling material, and the filling material includes one or more of silicate, quartz, mica, titanium dioxide, amorphous silicon dioxide, magnesium carbonate, aluminum nitride, aluminum oxide, boron nitride, magnesium hydroxide, chalk, limestone, feldspar or barium sulfate.

17. The apparatus of claim 13, further comprising a die coupled to the substrate.

18. A method comprising: providing a substrate including a glass layer; forming one or more through glass vias (TGVs) in the substrate; forming an organic dielectric layer on TGV sidewalls of individual TGVs of the one or more TGVs; and A conductive layer is formed on the organic dielectric layer.

19. The method of claim 18, further comprising forming an additional organic dielectric layer on the conductive layer.

20. The method according to claim 18, further comprising forming a parylene layer between the organic dielectric layer and the conductive layer, wherein The organic dielectric layer includes a plurality of hollow filling materials.

21. The method according to claim 18, wherein: The glass layer includes one or more of aluminosilicate, borosilicate, aluminoborosilicate, silica or fused silica.

22. The method according to claim 18, wherein: The one or more TGVs extend through the glass layer.

23. The method according to claim 18, wherein: Forming the conductive layer includes forming at least one of copper or a copper alloy.

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