Package substrate, method for manufacturing device package, and method for manufacturing package substrate

Abstract

The present specification relates to a method for manufacturing a package substrate and a package substrate using the same. A package substrate according to the present specification may include a core layer, the core layer may include a glass core and a cavity portion, the glass core may be a glass substrate including a first surface and a second surface facing each other, the cavity portion may be formed by recessing or penetrating a portion of the glass core, and the first surface and the second surface of the glass core are both provided with a first surface and a second surface facing each other. The cavity part is provided with an accommodating space for accommodating electronic devices, a device package can be arranged in the accommodating space of the cavity part, and the device package can comprise a plurality of electronic devices which are arranged; and a molding portion including a molding material and arranged to surround the electronic device, in the device package, a recessed portion may be arranged in the molding portion, and pits are arranged in the recessed portion.

Description

Technical Field

[0001] This document relates to a packaging substrate, a method for manufacturing a device package, and a method for manufacturing a packaging substrate. Background Art

[0002] When manufacturing electronic components, realizing circuits on semiconductor wafers is called the front-end (FE) process, and assembling the wafers into a state that can be used in actual products is called the back-end (BE) process. The back-end process includes the packaging process.

[0003] The four core technologies of the semiconductor industry that have recently enabled the rapid development of electronic products are semiconductor technology, semiconductor packaging technology, manufacturing process technology and software technology.

[0004] Semiconductor technology is developing in various forms, such as line widths of nanometer units below micrometers, more than 10 million cells, high-speed operation, and release of large amounts of heat, but there is still a lack of technical support for relatively complete packaging of the above semiconductors.

[0005] Therefore, the electrical performance of a semiconductor sometimes depends on the packaging technology and the corresponding electrical connections, rather than on the performance of the semiconductor technology itself.

[0006] As the material of the mounting substrate, ceramic or resin is suitable. In the case of a ceramic substrate such as a silicon substrate, it is difficult to mount a high-performance high-frequency semiconductor device due to the high resistance value or high dielectric constant. In the case of a resin substrate, although relatively high-performance high-frequency semiconductor devices can be mounted, there are limitations in reducing the spacing of wiring.

[0007] Recently, silicon or glass can be applied to high-end packaging substrates. By forming a through hole on the silicon or glass substrate and applying a conductive material to the through hole, the wiring length between the device and the motherboard can be shortened, and excellent electrical characteristics can be obtained.

[0008] As related prior arts, there are Korean Patent Publication No. 10-2023-0029115, Korean Patent Publication No. 10-2015-0143309, and the like.

[0009] Prior art literature

[0010] Patent Literature

[0011] Patent document 0001 Korean Patent Publication No. 10-2023-0029115.

[0012] Patent document 0002 Korean Patent Publication No. 10-2015-0143309. Summary of the invention

[0013] Problem that the invention aims to solve

[0014] The present embodiment aims to provide a method for manufacturing a packaging substrate using a glass core, in which a device package (device mold package) having a recessed portion formed on the upper surface is inserted into a cavity, and a packaging substrate using the same.

[0015] The present embodiment aims to provide a method for manufacturing a device package in which a device arrangement distance is maintained using a mold having a protrusion formed on an upper portion of the mold, and a package substrate using the same.

[0016] Means used to solve problems

[0017] In order to achieve the above-mentioned objective, one embodiment provides a packaging substrate, a method for manufacturing a device package, and a method for manufacturing a packaging substrate.

[0018] The packaging substrate according to the present specification includes a core layer, the core layer includes a glass core and a cavity portion, the glass core is a glass substrate including a first surface and a second surface facing each other, the cavity portion is formed by recessing or penetrating a portion of the glass core, and has a accommodating space for accommodating electronic devices, a device package is arranged in the accommodating space of the cavity portion, and the device package includes: i) a plurality of arranged electronic devices; and ii) a molding portion containing a molding material and arranged so that the molding material surrounds the electronic devices, in the device package, a recessed portion is arranged in the molding portion, and pits are arranged in the recessed portion.

[0019] The above-mentioned recess may be arranged between adjacent electronic devices.

[0020] The recessed portion may include a plurality of pits arranged in a dotted line shape when viewed from the first surface toward the second surface.

[0021] The package substrate may further include an insulating layer disposed on the cavity portion.

[0022] The insulating material of the insulating layer may be recessed in the recessed portion.

[0023] The molding material may include liquid crystal polymer (LCP), epoxy molding compound (EMC), Ajinomoto build-up film (ABF) or modified polyimide (MPI).

[0024] The insulating layer may include an insulating mixture, and the insulating mixture may include inorganic particles and a polymer resin.

[0025] A boundary between the molding part and the insulating layer may be located in the cavity part.

[0026] A recessed portion may be arranged at the boundary, wherein the recessed portion has a pit recessed toward the electronic device.

[0027] In order to achieve the above-mentioned purpose, a manufacturing method of a device package according to one embodiment manufactures the above-mentioned device package by including the following steps: a device arrangement step, preparing a mold with an injection port, and arranging multiple electronic devices at predetermined positions of the above-mentioned mold; an injection step, injecting a molding material into the above-mentioned injection port; and a mold forming step, forming a molding part by solidifying the above-mentioned molding material.

[0028] A protrusion is arranged around the injection port of the mold, and a plurality of protrusions are arranged in the protrusion. The device package includes: a plurality of arranged electronic devices; and a molding portion containing a molding material and arranged to surround the plurality of electronic devices. In the device package, a recess is arranged in the molding portion, and pits are arranged in the recess, and positions of the recess and the protrusion correspond to each other.

[0029] In the above-mentioned device arrangement step, the above-mentioned plurality of electronic devices may be arranged on the bonding surface and their positions may be fixed.

[0030] The position where the electronic components are arranged in the mold forming step is substantially the same as the position where the electronic components are arranged in the component arranging step.

[0031] The protrusions may be arranged between adjacent electronic devices.

[0032] The above-mentioned device package may be produced through a transfer molding process using a transfer mold having a protrusion formed on an upper portion of the mold.

[0033] On the other hand, in order to achieve the above-mentioned purpose, a manufacturing method of a packaging substrate according to one embodiment manufactures the above-mentioned packaging substrate by including the following steps: preparing a glass core having a cavity portion and a device package; arranging the above-mentioned device package in the above-mentioned cavity portion; and forming an insulating layer by arranging an insulating material on the above-mentioned glass core or the above-mentioned cavity portion and curing the above-mentioned insulating material.

[0034] In the step of forming the insulating layer, the insulating material flows so that a portion of the insulating material may move to a concave portion of the pit on the cavity device.

[0035] Effects of the Invention

[0036] The method for manufacturing a packaging substrate and the packaging substrate using the same according to the present embodiment can produce a device package while maintaining the interval between electronic devices, thereby preventing short circuits from occurring in the electronic devices.

[0037] In addition, by using a mold having a protrusion formed on an upper portion, the position of the electronic device can be prevented from being changed during the molding process, thereby having an effect of preventing problems such as a short circuit by preventing contact between the electronic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 Schematic diagram for explaining the cross-sectional structure of a package substrate according to the present embodiment.

[0039] Figure 2 FIG. 1 is a schematic diagram illustrating a cross-sectional structure of a package substrate according to another embodiment.

[0040] Figure 3 Parts (a) and (b) of FIG. 1 are schematic diagrams each illustrating a portion of a package substrate according to the present embodiment in cross section.

[0041] Figure 4 The present invention is a cross-sectional flow chart for explaining a process of generating a core distribution layer in a process of manufacturing a package substrate according to the present embodiment.

[0042] Figure 5 The present invention is a cross-sectional flow chart for explaining a process of generating an insulating layer in a process of manufacturing a package substrate according to the present embodiment.

[0043] Figure 6 A cross-sectional flow chart showing a process of generating a device package by a conventional transfer molding process, wherein part (a) shows a process of attaching a mold to a lower portion, part (b) shows a process of arranging devices, and part (c) shows a process of injecting a molding material (F represents flow).

[0044] Figure 7 A cross-sectional flow chart illustrating a process of generating a device package by a transfer molding process according to the present embodiment, wherein part (a) shows a process of attaching a mold to a lower portion, part (b) shows a process of arranging devices, and part (c) shows a process of injecting a molding material (F represents flow).

[0045] Figures 8a to 8c Each of them is a conceptual diagram illustrating in cross section a device package produced by a transfer molding process using a transfer mold having a protrusion formed therein according to the present embodiment.

[0046] Figure 9a and Figure 9b 1 and 10 are conceptual diagrams respectively illustrating a transfer mold having a protrusion formed according to the present embodiment and a portion of a surface of a device package produced by the transfer mold.

[0047] Fig.10a and Fig.10b 1 and 2 are conceptual diagrams respectively showing a transfer mold having a protrusion formed according to the present embodiment and a portion of a surface of a device package produced by the transfer mold.

[0048] Fig.11 The present invention is a cross-sectional flow chart showing a method for manufacturing a packaging substrate according to the present embodiment, wherein part (a) shows a process of preparing a molded packaging body, part (b) shows a process of inserting the molded packaging body into a cavity space, part (c) shows a process of forming an upper insulating layer, part (d) shows a process of forming a lower insulating layer, and part (e) shows a process of curing the upper insulating layer and the lower insulating layer.

[0049] Description of Reference Numerals

[0050] 100: semiconductor device; 10: motherboard; 30: semiconductor device portion; 32: first semiconductor device; 34: second semiconductor device; 36: third semiconductor device; 20: package substrate; 21, 21a: glass core; 22: core layer; 223: core insulating layer; 213: first surface; 214: second surface; 23: core through hole; 24: core distribution layer; 241: core distribution pattern; 26: upper layer; 25: upper distribution layer; 251: upper distribution pattern; 25 2: blind hole; 253: upper insulating layer; 27: upper connection layer; 271: upper connection electrode; 272: upper connection pattern; 28: cavity; 281: internal space; 282: cavity distribution layer; 40: electronic device; 50: connection part; 51: device connection part; 52: board connection part; 60: transfer mold; 61: upper part of mold; 62: lower part of mold; 63: mold cavity; 64: molding part; 70: protrusion; 80: device package; 81: recess DETAILED DESCRIPTION

[0051] The following detailed description is provided to help the reader fully understand the method, device and / or system described herein. However, after understanding the disclosure of the application, various changes, modifications and equivalents of the method, device and / or system described herein will be apparent. For example, the order of operations described herein is merely an example and is not limited to those set forth herein. The order of operations can be changed, as will be apparent after understanding the disclosure of the application, except for the operations that must occur in a specific order. In addition, after understanding the disclosure of the application, the description of known features can be omitted to increase clarity and simplicity. However, the omission of features and their descriptions is not intended to admit their common sense either.

[0052] The features described herein may be embodied in different forms and should not be construed as being limited to the examples described herein. Rather, the examples described herein are provided only to illustrate some of the many possible ways to implement the methods, devices and / or systems described herein, which will be apparent after understanding the disclosure of the present application.

[0053] Although terms such as "first", "second", and "third" may be used herein to describe various components, parts, regions, layers, or sections, these components, parts, regions, layers, or sections should not be limited by these terms. Rather, these terms are only used to distinguish one component, part, region, layer, or section from another component, part, region, layer, or section. Therefore, without departing from the teachings of the examples described herein, the first component, part, region, layer, or section mentioned in the examples may also be referred to as the second component, part, region, layer, or section.

[0054] Throughout the specification, when a device such as a layer, a region or a substrate is described as being "on another device", "connected to another device" or "coupled to another device", it may be directly "on another device", "connected to another device" or "coupled to another device", or one or more other devices may be interposed therebetween. Conversely, when a device is described as being "directly on another device", "directly connected to another device" or "directly coupled to another device", no other device may be interposed therebetween. Similarly, expressions such as "between" and "immediately between" and "adjacent" and "immediately adjacent" may also be interpreted as described above.

[0055] The terms used herein are only used for the purpose of describing specific examples and are not used to limit the present disclosure. As used herein, the singular forms "one", "an" and "the" are intended to also include plural forms, unless the context clearly states otherwise. As used herein, the term "and / or" includes any one of the items listed in the relevant list and any combination of any two or more items. As used herein, the terms "include", "comprise" and "have" specify the existence of stated features, numbers, operations, devices, parts and / or their combinations, but do not exclude the existence or addition of one or more other features, numbers, operations, devices, parts and / or their combinations. The use of the term "may" herein about examples or embodiments (for example, about the content that can be included or implemented in examples or embodiments) means that there is at least one example or embodiment in which such features are included or implemented, and all examples are not limited thereto.

[0056] In the present application, “B is placed on A” means that B is placed in direct contact with A or placed on A with another layer or structure interposed therebetween, and thus should not be construed as limited to B being placed in direct contact with A.

[0057] Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs consistent with and after understanding the present disclosure. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner unless explicitly defined herein.

[0058] In one or more examples, the description of "A and / or B" means "A, B, or A and B."

[0059] In one or more examples, terms such as "first," "second," "A," or "B" are used to distinguish the same terms.

[0060] In one or more examples described above, unless otherwise specified, an expression in the singular is interpreted as including the meaning of the singular or plural as interpreted in the context.

[0061] Figure 1 2 is a schematic diagram for explaining a cross-sectional structure of a package substrate according to the present embodiment. Figure 2 2 is a schematic diagram illustrating a cross-sectional structure of a package substrate according to another embodiment. Figure 3 Parts (a) and (b) of FIG. 1 are schematic diagrams each illustrating a portion of a package substrate according to the present embodiment in cross section.

[0062] In order to achieve the above-mentioned purpose, the semiconductor device 100 according to the present embodiment includes: a semiconductor device unit 30, in which one or more semiconductor devices 32, 34, 36 are located; a packaging substrate 20, which is electrically connected to the semiconductor device; and a motherboard 10, which is electrically connected to the packaging substrate 20, transmits external electrical signals to the semiconductor devices 32, 34, 36 and connects the above-mentioned semiconductor devices and the external electrical signals.

[0063] The package substrate 20 according to an embodiment includes: a core layer 22 ; an upper layer 26 located on one surface of the core layer 22 ; and a cavity portion 28 in which an electronic device 40 may be located.

[0064] The semiconductor device section 30 is a device mounted on a semiconductor device, and is mounted on the package substrate 20 via connection electrodes, etc. Specifically, as the semiconductor device section 30, for example, a computing device such as a CPU, a GPU (first device: 32, a second device: 34), a storage device such as a memory chip (third device: 36), etc. can be applied, but any semiconductor device mounted on a semiconductor device can be applied without limitation.

[0065] The motherboard 10 may be a motherboard such as a printed circuit board or a printed wiring board.

[0066] The package substrate 20 may selectively further include a lower layer (not shown) located below the core layer.

[0067] The core layer 22 may include: a glass core 21, including a first region 221 and a second region 222, wherein the first region 221 has a first thickness 211, and the second region 222 is adjacent to the first region 221 and has a second thickness 212 thinner than the first thickness; a plurality of core through holes 23, penetrating the glass core 21 in the thickness direction; and a core distribution layer 24, located on the surface of the glass core 21 or the core through holes 23, and electrically connecting the first surface 213 of the glass core 21 and the second surface 214 facing the first surface through the core through holes 23.

[0068] The second region 222 of the core layer 22 may function as a cavity structure.

[0069] In the same region, the glass core 21 has a first surface 213 and a second surface 214 facing each other. The two surfaces are substantially parallel to each other, so that the glass core 21 has a certain thickness as a whole.

[0070] The inner space 281 formed by the thickness difference between the first region 221 and the second region 222 serves to accommodate a part or all of the electronic device 40 .

[0071] The glass core 21 may include a core through hole 23 penetrating the first surface 213 and the second surface 214. The core through holes 23 may be formed in both the first region 221 and the first and second regions 222, and may be formed at intended intervals and patterns.

[0072] As a packaging substrate for semiconductor devices, a stacked form of silicon substrate and organic substrate has been used in the past. Due to the characteristics of semiconductors, silicon substrates may produce parasitic devices when used in high-speed circuits, and have the disadvantage of relatively large power loss. In addition, organic substrates need to be large in area in order to form more complex distribution patterns, but this does not conform to the trend of manufacturing ultra-miniaturized electronic devices. In order to form a complex distribution pattern within a predetermined size, the pattern needs to be miniaturized, but due to the characteristics of materials such as polymers suitable for organic substrates, there are actually limitations to pattern miniaturization.

[0073] In this embodiment, as a method for solving the above-mentioned problem, the glass core 21 is used as a support body of the core layer 22. In addition, together with the glass core 21, the core through hole 23 formed through the glass core 21 is also applied, thereby providing a package substrate 20 with a shorter current length, more miniaturization, faster response, and less loss characteristics.

[0074] The glass core 21 is preferably a glass substrate suitable for semiconductors, for example, a borosilicate glass substrate, an alkali-free glass substrate, etc., but the present invention is not limited thereto.

[0075] The core through hole 23 penetrates the glass core 21. The core through hole 23 may be formed by removing a predetermined region of the glass core 21, and more specifically, may be formed by etching a plate-shaped glass using a physical and / or chemical method.

[0076] Specifically, when forming the core through hole 23, a method of forming a defect (stain) on the surface of the glass substrate by laser or the like and then performing chemical etching or laser etching may be used, but the present invention is not limited thereto.

[0077] Based on the unit area (1 cm×1 cm) of the glass core 21, 100 to 3000 core through holes 23 may be provided, or 100 to 2500 core through holes 23 may be provided, or 225 to 1024 core through holes 23 may be provided. When the above spacing conditions are met, it is more conducive to forming a conductive layer, etc., and the performance of the package substrate may be improved.

[0078] The core distribution layer 24 includes a core distribution pattern 241 and a core insulation layer 223. The core distribution pattern 241 is a conductive layer that electrically connects the first surface and the second surface of the glass core through a through hole, and the core insulation layer 223 surrounds the core distribution pattern. The core layer 22 is formed with a conductive layer through the core through hole to serve as an electrical path across the glass core 21, thereby connecting the upper and lower parts of the glass core with a relatively short distance, and can have faster electrical signal transmission and low loss characteristics. For example, the conductive layer can be a copper plating layer, but the present invention is not limited to this.

[0079] The cavity 28 is generally in the shape of a circle, a triangle, a quadrilateral, a hexagon, an octagon, a cross, etc., and its shape is not limited.

[0080] The shape of the electronic device 40 may be cylindrical, rectangular or polygonal.

[0081] The cavity portion 28 may include a cavity distribution pattern as a conductive layer electrically connecting the electronic device 40 and the core distribution layer 24 and an insulating layer surrounding the cavity distribution pattern.

[0082] On the other hand, the cavity portion according to another embodiment may be implemented in the form of penetrating the first surface 213 and the second surface 214 of the glass core 21. In this case, the cavity portion may be formed according to the same process as the core through hole 23, and the area and shape of the penetrating glass core 21 may be different from those of the core through hole 23.

[0083] In this embodiment, the insulating layer may be formed after the electronic device 40 is arranged in the cavity portion. That is, the insulating layer may also be formed in the cavity portion through the process of forming the core insulating layer 223 described above.

[0084] The core allocation pattern 241 may be formed as a pattern capable of being electrically connected to the above-mentioned electronic device 40 .

[0085] The electronic device 40 may include an active device such as a transistor or a power transmission device, ie, a passive device, such as a multi-layer ceramic capacitor (MLCC).

[0086] When a device such as a transistor that converts an electrical signal between a motherboard and a semiconductor device into an appropriate level is used as the electronic device 40, the transistor is used in the path of the packaging substrate 20, thereby providing a semiconductor device 100 with higher efficiency and speed.

[0087] In addition, power transmission devices such as multilayer ceramic capacitors (MLCCs) play an important role in the performance of semiconductor devices. Generally, more than 200 power transmission devices as passive devices are applied to semiconductor devices, and their performance is also affected by the characteristics of the conductive layer around the device when transmitting power. In one embodiment, non-circular core vias can be applied to places where low-resistance conductive layers are required, such as the above-mentioned power transmission devices, instead of circular core vias.

[0088] On the other hand, the electronic device 40 may be in the form of a passive device such as a capacitor inserted separately, or may be formed in the form of being embedded between insulator layers (electronic device insulating layers) so that the electrodes of a device group including a plurality of passive devices are exposed and then inserted into the electronic device. In the latter case, the workability of manufacturing the package substrate can be improved more smoothly, and the insulating layer can be more advantageously fully and reliably arranged in the space between the complex devices.

[0089] The glass core 21 plays an intermediate role in connecting the semiconductor device portion 30 and the motherboard 10 to the upper and lower parts, respectively, and the core through hole 23 serves as a path for transmitting their electrical signals, thereby achieving smooth signal transmission.

[0090] The upper layer 26 is located on the first surface 213 .

[0091] The upper layer 26 includes an upper distribution layer 25 and an upper connection layer 27 located on the upper distribution layer 25 . The uppermost layer 26 may be protected by a cover layer 260 having an opening for directly contacting the connection electrode of the semiconductor device.

[0092] The upper distribution layer 25 includes: an upper insulating layer 253, which is located on the first surface; and an upper distribution pattern 251, which is a conductive layer having a predetermined pattern and at least a portion of which is electrically connected to the core distribution layer 24, and the upper distribution pattern 251 is embedded in the upper insulating layer 253. The upper distribution pattern 251 can be connected to the upper or lower conductive layer through a blind hole 252.

[0093] As the upper insulating layer 253 , any material as long as it is suitable for use as an insulating layer in a semiconductor device or a package substrate can be used. For example, epoxy resin including a filler can be used, but the present invention is not limited thereto.

[0094] The insulator layer may be formed by forming a coating and curing it, or may be formed by laminating an insulator film formed in an uncured or semi-cured state on the core layer 22 and curing it. At this time, if a reduced pressure lamination method or the like is adopted, the insulator is embedded in the space inside the core through hole 23, so that the process can be performed efficiently.

[0095] According to one embodiment, even if multiple insulating layers are stacked for application, it may be difficult to substantially distinguish between the insulating layers, and the multiple insulating layers are collectively referred to as upper insulating layers. In addition, the core insulating layer 223 and the upper insulating layer 253 may be made of the same insulating material, in which case, their boundaries may be substantially indistinguishable. Alternatively, according to another embodiment, the boundaries of the insulating layers may be generated by setting the curing pressure and temperature of the multiple insulating layers differently.

[0096] The upper distribution pattern 251 refers to a conductive layer located in the upper insulating layer 253 in a predetermined shape, and can be formed, for example, by a build-up layer method. Specifically, after forming an insulating layer, unnecessary portions of the insulating layer are removed, and then a conductive layer is formed by a method such as copper plating, and then unnecessary portions of the conductive layer are selectively removed, and then an insulating layer is formed again on the conductive layer, and then unnecessary portions are removed again, and then a conductive layer is formed by plating, and the above method is repeated, so that an upper distribution pattern 251 having a conductive layer formed in a desired pattern in a vertical or horizontal direction can be formed.

[0097] The upper distribution pattern 251 is located between the core layer 22 and the semiconductor device portion 30, and is therefore formed to include a fine pattern in at least a portion thereof, so as to smoothly transmit electrical signals with the semiconductor device portion 30 and fully accommodate the required complex pattern. At this time, the fine pattern refers to a pattern with a width and a spacing less than 4 μm, or a pattern with a width and a spacing less than 3.5 μm, or a pattern with a width and a spacing less than 3 μm, or a pattern with a width and a spacing less than 2.5 μm, or a pattern with a width and a spacing of 1 μm to 2.3 μm (hereinafter, the description of the fine pattern is the same).

[0098] The upper connection layer 27 includes: an upper connection pattern 272 , at least a portion of which is electrically connected to the upper distribution pattern 251 and is located on the upper insulating layer 253 ; and an upper connection electrode 271 , which electrically connects the semiconductor device portion 30 and the upper connection pattern 272 .

[0099] The upper connection pattern 272 may be located on one side of the upper insulating layer 253, or may be embedded in a manner that at least a portion thereof is exposed on the upper insulating layer. For example, in the case where the upper connection pattern is located on one side of the upper insulating layer, the upper insulating layer may be formed by plating or the like, and in the case where the upper connection pattern is embedded in a manner that a portion thereof is exposed on the upper insulating layer, after forming a copper plating layer or the like, a portion of the insulating layer or the conductive layer may be removed by surface polishing, surface etching or the like.

[0100] Similar to the upper distribution pattern 251 described above, at least a portion of the upper connection pattern 272 may include a fine pattern. The upper connection pattern 272 including the fine pattern as described above electrically connects more devices even in a narrow area, thereby making the electrical signal connection between devices or with the outside smoother and enabling a more integrated package.

[0101] The upper surface connection electrode 271 may be directly connected to the semiconductor device portion 30 through a terminal or the like, or may be connected via a device connection portion 51 such as a solder ball or the like.

[0102] The cavity portion 28 includes a cavity distribution layer 282 located above and / or below the second region 222 and electrically connected to the core distribution pattern 241 , and an inner space 281 in which the electronic device 40 is positioned.

[0103] Specifically, the thickness of the glass core 21 in the second region 222 is thinner than that in the first region 221, and the electronic device 40 can be located in the internal space 281 formed due to the difference in thickness. In addition, the core through hole 23 and the core distribution layer 24 formed in the glass core 21 play a role as an electrical connection structure connecting the electronic device 40 and external devices.

[0104] In addition, as described above, a cavity portion may be formed in the form of penetrating the first region 221 instead of the second region 222 , ie, penetrating the first surface 213 and the second surface 214 of the glass core 21 , and the electronic device 40 may be arranged in the cavity portion.

[0105] The package substrate 20 is also connected to the motherboard 10. The terminals of the motherboard 10 can be directly connected to the core distribution pattern 241 located on at least a portion of the second surface 214 of the core layer 22, and the motherboard 10 can be electrically connected via a board connection portion 52 such as a solder ball. In addition, the core distribution pattern 241 connected to the motherboard 10 can be connected to the motherboard 10 via a lower layer (not shown in the figure) located at the lower part of the core layer 22.

[0106] The connection part 50 refers to a medium connecting the package substrate 20, the motherboard 10 and / or the semiconductor device part 30, and for example, a connection part such as solder balls of the same or different sizes can be applied. The size of the solder ball arranged between the package substrate 20 and the motherboard 10 can be equal to or larger than the size of the solder ball arranged between the package substrate 20 and the semiconductor device part 30.

[0107] According to an example, the package substrate 20 between the semiconductor device portion 30 and the motherboard 10 may not substantially use any additional substrate other than the glass core 21 .

[0108] In the past, the interposer and the organic substrate were stacked together and applied to the connection portion between the device and the motherboard. It is understood that this multi-level structure is adopted for at least two reasons: one is that there are scale issues when directly connecting the fine pattern of the device to the motherboard, and the other is that during the bonding process or the driving process of the semiconductor device, the difference in thermal expansion coefficient may cause wiring damage.

[0109] In this embodiment, the above problems are solved by using a glass core having a thermal expansion coefficient similar to that of a semiconductor device and forming a fine pattern having a fine scale sufficient for mounting a device on the first surface of the glass core and its upper layer.

[0110] A method of manufacturing a package substrate according to an embodiment of the present invention will be described below.

[0111] Figure 4 and Figure 5 A cross-sectional flow chart illustrating a process of manufacturing a package substrate according to the present embodiment.

[0112] First, if Figure 4 As shown in part (a), a glass core 21a having a flat first surface and a flat second surface is prepared, and a defect 21b (groove) is formed at a predetermined position on the glass surface in order to form a core through hole. The above-mentioned glass can be a glass core suitable for a substrate of an electronic device, for example, an alkali-free glass core, etc. can be used, but it is not limited to this. As a commercial product, products manufactured by manufacturers such as Corning, Schott, and AGC can be used. The above-mentioned defect (groove) can be formed by mechanical etching, laser irradiation, etc.

[0113] like Figure 4 As shown in part (b) of FIG. 1 , an etching step is performed to form a core through hole 23 in the glass core 21a having the defect 21b (groove) formed therein by a physical or chemical etching process. In the etching process, the surface of the glass core 21a may be etched while forming the core through hole in the defective portion of the glass core. In order to prevent such etching of the glass surface, a mask film or the like may be applied, but in consideration of the trouble of the process of applying and removing the mask film, etc., the glass core itself with the defect may be etched, in which case the thickness of the glass core having the core through hole may be slightly thinner than the thickness of the original glass core.

[0114] Then, if Figure 4 As shown in parts (c) and (d) of FIG. 2 , the core layer preparation step may be performed by forming a conductive layer 21d on the glass core. Representatively, the conductive layer may be a metal layer including copper metal, but the present invention is not limited thereto.

[0115] The surface of the glass (including the surface of the glass core and the surface of the core through hole) and the surface of the copper metal have different properties, so the adhesion is poor. In this embodiment, the adhesion between the glass surface and the metal is improved by two methods, a dry method and a wet method.

[0116] The dry method is a method for applying sputtering, that is, a method for forming a seed layer 21c on the glass surface and the inner diameter of the core through hole by metal sputtering. When forming the above-mentioned seed layer, a dissimilar metal such as titanium, chromium, nickel, etc. can be sputtered together with copper, etc. In this case, it is believed that the adhesion between glass and metal is improved by the surface morphology of the glass and the anchoring effect of the interaction of metal particles.

[0117] Wet method is the method for carrying out primer treatment, is the method for forming primer layer 21c by pre-treating with the compound substance with the functional group such as amine etc. According to the required adhesion degree, after pre-treating with silane coupling agent, primer treatment can be carried out with the compound or particle with amine functional group.As mentioned above, the support substrate of present embodiment needs to have the high performance of the degree that is enough to form fine pattern, even after primer treatment, also need to keep this state.Therefore, when this primer comprises nanoparticle, preferably suitable average diameter is the nanoparticle below 150nm, for example, the particle with amine group is preferably used as nanoparticle.For example, above-mentioned primer layer can be formed by being suitable for the adhesion modifier made by CZ series etc. of MEC company.

[0118] In the seed layer / primer layer 21c, the conductive layer can selectively form a metal layer with or without removing the portion where the conductive layer is not required to be formed. In addition, the seed layer / primer layer 21c selectively processes the portion where the conductive layer is required to be formed or the portion where the conductive layer is not required to be formed into an activated state or an inactivated state for metal plating to carry out subsequent processes. For example, the activation or inactivation treatment can use a light irradiation treatment or chemical treatment with a laser having a predetermined wavelength. When forming the metal layer, a copper plating method suitable for manufacturing semiconductor devices can be used, but the present invention is not limited thereto.

[0119] like Figure 4 As shown in part (e), when a portion of the core distribution layer is not needed, it can be removed, or metal plating can be performed after partially removing or inactivating the seed layer to form a conductive layer in a predetermined pattern, thereby forming an etching layer 21e of the core distribution layer.

[0120] Figure 5 A preparation step of forming an insulating layer and an upper distribution pattern according to an embodiment is described.

[0121] like Figure 5As shown in part (a), after forming the core distribution layer as the above-mentioned conductive layer, the core through hole can be subjected to an insulating layer forming step of filling the empty space with an insulating layer. At this time, the insulating layer applied can be an insulating layer prepared in the form of a film, for example, it can be applied by a method of decompressing and laminating an insulating layer in the form of a film, etc. When decompressing and laminating in this way, the insulating layer is fully embedded in the empty space inside the above-mentioned core through hole to form a core insulating layer without voids.

[0122] Figure 5 Parts (b) to (e) of FIG. 1 illustrate the upper layer preparation steps.

[0123] The upper layer preparation step is a step of forming an upper distribution layer including an upper insulating layer and an upper distribution pattern on the core layer. The upper insulating layer can be formed by coating a resin composition for forming the insulating layer 23a or by stacking insulating films. Simply, it is preferred to stack insulating films. The stacking of insulating films can be performed by laminating insulating films and curing. At this time, if a reduced pressure lamination method is adopted, the insulating resin can be fully recessed into the layer where the conductive layer is not formed inside the core through hole, etc. At least a portion of the above-mentioned upper insulating layer is also in direct contact with the glass substrate, so a layer with sufficient adhesion is suitable. Specifically, the above-mentioned glass core and the above-mentioned upper insulating layer preferably have a characteristic that the adhesion test value according to ASTM D3359 meets 4B or above.

[0124] The upper distribution pattern can be formed by repeatedly forming the above-mentioned insulating layer 23a, forming the conductive layer 23c in a predetermined pattern and etching unnecessary parts to form an etching layer 23d of the conductive layer. In the case of a conductive layer formed adjacent to the insulating layer, it can be formed by performing a plating process after forming a blind hole 23b in the insulating layer. The blind hole can be formed by a dry etching method such as laser etching and plasma etching, a wet etching method using a mask layer and an etching solution, etc.

[0125] Thereafter, although not shown in the drawings, an upper connection layer and a cover layer may be formed.

[0126] The upper connection pattern and the upper connection electrode can also be formed by a process similar to the process of forming the upper distribution layer. Specifically, it can be formed by forming an etching layer of the insulating layer on the insulating layer 23e, and then forming a conductive layer thereon, and then forming an etching layer of the conductive layer, but it can also be formed by only selectively forming the conductive layer without using an etching method. An opening portion (not shown in the figure) is formed at a position of the covering layer corresponding to the upper connection electrode, so that the upper connection electrode can be exposed and directly connected to the device connection portion or the terminal of the device.

[0127] Once the upper layer is produced, the lower layer process can be carried out by forming the lower connecting layer and the covering layer. The lower distribution layer and / or the lower connecting layer can be formed in a similar manner to the upper connecting layer and the covering layer formation steps described above, and optionally, a covering layer (not shown in the figure) can also be formed.

[0128] On the other hand, as described above, the core layer may include a glass core and a cavity portion, wherein the glass core is a glass substrate having a first surface and a second surface facing each other, and the cavity portion may be formed by recessing or penetrating a portion of the glass core and having a storage space for accommodating electronic devices.

[0129] Electronic devices can be arranged in the accommodating space of the above-mentioned cavity portion. In addition, in the case of embedding multiple electronic devices, especially when multiple electronic devices are arranged in adjacent positions for internal installation, in order to prevent short circuits, it is necessary to maintain a spacing between the devices. As a result, the empty space of the cavity portion that must be filled with the insulating layer in the form of a thin film will increase, and it may become difficult to maintain the flatness of the upper surface of the insulating layer in the entire substrate area. The above-mentioned insulating layer may include inorganic particles and polymer resins such as Ajinomoto Build-up Film (ABF).

[0130] Thus, a device package (element package, element molding package) in which multiple electronic devices are embedded can be manufactured and the device package is arranged in the receiving space of the cavity to manufacture a device built-in substrate. Here, a device molded package manufactured by molding a device is referred to as a device package.

[0131] Here, the device package may be manufactured through a transfer molding process using a transfer mold.

[0132] Figure 6 FIG. 1 is a cross-sectional flow chart illustrating a process of producing a device package using a conventional transfer molding process.

[0133] For example, according to the existing transfer molding process, a plurality of electronic devices may be arranged in a mold cavity of a transfer mold, and then a molding material may be poured into the mold cavity and cured, thereby generating a device package in which the plurality of electronic devices are embedded.

[0134] For example, refer to Figure 6 In the part (a), the mold lower part 62 may be disposed on the bottom surface of the transfer mold 60 formed with the mold cavity 63. PI tape (polyimide tape) or the like may be applicable to the above-mentioned mold lower part 62, but is not limited thereto.

[0135] Secondly, refer to Figure 6In part (b), a plurality of electronic devices 40 may be arranged in the mold cavity 63 of the transfer mold 60, such as Figure 6 As shown in part (c) of FIG. 1 , the upper surface of the transfer mold 60 is covered with a mold upper portion 61 , and a molding material 64 is poured through a gate of the mold upper portion 61 and cured, thereby producing a device package.

[0136] The above-mentioned device package may include a plurality of electronic devices and a molding part.

[0137] The plurality of electronic devices may be arranged in a predetermined form.

[0138] The molding part may be arranged / cured such that the molding material surrounds the plurality of electronic devices in a manner that the arrangement of the plurality of electronic devices is maintained.

[0139] The molding material may be a polymer resin, a mixed material of a polymer resin and a filler (inorganic particles, organic particles, organic-inorganic composite particles, etc.), or the like.

[0140] For example, the polymer resin may be an acrylic resin, an epoxy resin or a modified resin thereof, and may be a material applicable to electronic devices for the purpose of molding, etc. For example, a liquid crystal polymer (LCP) may be used.

[0141] For example, the mixed material may be a mixture of acrylic resin and filler, a mixture of acrylic resin and epoxy resin and a mixture of filler, and a mixture of epoxy resin and filler. The filler may be inorganic particles, for example, silica particles. As commercial products, Ajinomoto built-in film (ABF), epoxy molding compound (EMC), and modified polyimide (MPI) may be used, but the present invention is not limited thereto.

[0142] Specifically, the molding material may include epoxy molding compound (EMC), liquid crystal polymer (LCP) and / or Ajinomoto build-up film (ABF).

[0143] In the existing transfer molding process for producing the above-mentioned device packages, during the injection of the molding material, the lower part of the mold (e.g., PI tape) may not be able to adequately fix the position of the individual devices (e.g., due to insufficient adhesion or the need for rapid injection to improve process efficiency, etc.). In this case, the problem of the device deviating from its original position may occur.

[0144] Since devices deviate from their original positions and contacts between devices occur, which may cause problems such as short circuits, this specification proposes some embodiments that can prevent device movement during the process of generating device packages.

[0145] As an example, an embodiment can be proposed in which a device package in which a plurality of electronic devices are embedded is produced by performing a transfer molding process using a transfer mold having a protrusion formed on an upper portion of the mold.

[0146] Figure 7 A cross-sectional flow chart illustrating a process of producing a device package through a transfer molding process according to the present embodiment.

[0147] A method of manufacturing a device package according to an embodiment of the present specification is as follows.

[0148] For example, a device package is manufactured by a method including a device arrangement step of preparing a mold having an injection port and arranging a plurality of electronic devices at predetermined positions in the mold, an injection step of injecting a molding material into the injection port, and a mold forming step of curing the molding material to form a molding portion.

[0149] Here, a protrusion is arranged around the injection port of the mold, a plurality of protrusions are arranged in the protrusion, and the position of the recessed portion in which the pits are arranged in the device package and the position of the protrusion may correspond to each other.

[0150] Specifically, as one embodiment, refer to Figure 7 In the (a) portion, the mold lower portion 62 may be attached to the bottom surface of the transfer mold 60 formed with the mold cavity 63. A polyimide tape (PI tape) may be disposed on a portion or the entirety of the mold lower portion 62 described above.

[0151] Secondly, refer to Figure 7 In part (b), a plurality of electronic devices may be arranged in the mold cavity 63 of the transfer mold 60, such as Figure 7 As shown in part (c) of FIG. 1 , the upper surface of the transfer mold 60 is covered with a mold upper portion 61, and a molding material is poured through a gate of the mold upper portion 61 and solidified to form a molded portion, thereby producing a device package. The gate is an inlet for injecting a molding material or the like.

[0152] For example, the mold upper portion 61 may be formed with a protrusion 70 in which protrusions are arranged inward.

[0153] Due to the protrusion 70 formed on the above-mentioned mold upper part 61, when pouring the molding material, the force applied to the device by pouring the molding material can be reduced, and the phenomenon of the device being separated from its original position can be substantially prevented.

[0154] For example, the protrusions formed on the mold upper portion 61 may be located between the electronic devices when viewed from a cross section of the transfer mold 60. That is, the protrusions formed on the mold upper portion 61 may be arranged between adjacent electronic devices.

[0155] Since the specific description about the above molding material overlaps with the above description, the detailed description thereof will be omitted.

[0156] On the other hand, Figure 7 The positions of the protrusions (projections) arranged on the mold shown are one example and are not limited thereto.

[0157] For example, the mold may be provided with protrusions around the injection port.

[0158] like Figure 7 As shown, a protrusion 70 may be formed on the mold upper portion 61. Alternatively, for example, a protrusion 70 may be formed on the mold lower portion 62. Alternatively, for example, a protrusion 70 may be formed on the mold upper portion 61 and the mold lower portion 62. The protrusion may help to keep the position where the electronic device is arranged in the device arrangement step and the position where the electronic device is arranged in the mold forming step substantially the same.

[0159] Figures 8a to 8c Each of them is a conceptual diagram illustrating in cross section a device package produced by a transfer molding process using a transfer mold having a protrusion formed therein according to the present embodiment.

[0160] For example, refer to Figures 8a to 8c The device package 80 includes a plurality of arranged electronic devices 40 and a molding portion 64 including a molding material and arranged such that the molding material surrounds the electronic devices.

[0161] Exemplarily, as described above, the molding material surrounding the plurality of electronic devices may be a polymer resin, a mixed material of a polymer resin and a filler (inorganic particles, organic particles, organic-inorganic composite particles, etc.), or the like.

[0162] Furthermore, in the device package, a recessed portion is disposed in a portion of the molding material of the molding portion, and dimples are arranged in the recessed portion. Positions of the recessed portion and the protruding portion may correspond to each other.

[0163] For example, refer to Figure 8a A recessed portion in which pits are arranged may be disposed on an upper surface of the molding portion of the device package 80 .

[0164] Or, for example, refer to Figure 8b A recessed portion in which dimples are arranged may be disposed on a bottom surface of the molding portion of the device package 80 .

[0165] Or, for example, refer to Figure 8c The recessed portions in which the dimples are arranged may be disposed on the upper surface and the bottom surface of the molding portion of the device package 80 , respectively.

[0166] For example, due to the protrusion 70 formed on the mold upper portion 61 , the recessed portion 81 may be formed on the upper surface of the molding portion of the device package 80 .

[0167] Alternatively, for example, due to the protrusion 70 formed on the mold lower portion 62 , the recessed portion 81 may be formed on the bottom surface of the molding portion of the device package 80 .

[0168] Alternatively, for example, due to the protrusions 70 formed on the mold upper portion 61 and the mold lower portion 62 , the recessed portion 81 may be formed on the upper and bottom surfaces of the molding portion of the device package 80 .

[0169] The recess may be disposed between adjacent electronic devices 40 of the device package 80. For example, the recess may be disposed between adjacent first and second electronic devices of the device package 80.

[0170] The recessed portion 81 may have various shapes according to the shape of the protruding portion 70. For example, the shape of the cavity of the glass core may be various shapes such as a cross, a T-shape, or a rectangle, and the shape of the cavity of the transfer mold 60 may also be changed similarly. Considering the shape of the cavity, the overall shape of the recessed portion 81 or the protruding portion 70 may be various shapes.

[0171] In addition, the shape of the protrusion 70 formed on the mold may be various shapes. For example, the shape of the protrusion 70 formed on the mold may have an intermittent structure so as not to hinder the flow of the molding material when the molding material is injected.

[0172] Figure 9a to Figure 9b A conceptual diagram for explaining a transfer mold having a protrusion formed according to the present embodiment and a portion of the surface of a device package produced by the transfer mold.

[0173] For example, a mold having an injection port may be provided, and protrusions may be arranged around the injection port (gate) of the mold. For example, a protrusion arranged with protrusions may be arranged on the mold upper portion of the mold. Or, for example, the protrusion may be arranged on the mold lower portion of the mold. Or, for example, the protrusion may be arranged on the mold upper portion and the mold lower portion of the mold. The position of the protrusion arranged on the mold and the arrangement of the protrusions are an example and are not limited thereto.

[0174] For example, refer to Figure 9aThe protrusion 70 may be arranged on the mold upper part 61 and / or the mold lower part 62. For example, the protrusion formed on the mold upper part 61 and / or the mold lower part 62 may be in the shape of a triangular prism with a triangular cross section. The protrusion may be formed so that one square surface of the triangular prism is in contact with the mold upper part 61 and / or the mold lower part 62.

[0175] The protrusions arranged on the mold upper portion 61 and / or the mold lower portion 62 may be arranged between adjacent electronic devices of the device package 80. For example, the protrusions arranged on the mold upper portion 61 may be arranged between adjacent first and second electronic devices of the device package 80. The embodiments shown in the drawings are merely exemplary, and those skilled in the art may make various variations and modifications using the basic concepts of the present embodiment.

[0176] in addition, Figure 9b By way of example, the Figure 9a The protrusion 70 is shown as a portion of the surface of a device package 80 produced by the transfer mold 60 .

[0177] For example, refer to Figure 9a A recessed portion 81 in which pits are arranged may be formed on an upper surface and / or a bottom surface of the molding portion of the device package 80 .

[0178] For example, refer to Figure 9b Due to the protrusion 70 arranged with protrusions in a part of the mold, a recessed part 81 arranged with pits may be formed in a part of the molding material of the molding part of the device package 80. The positions of the recessed part and the protrusion may correspond to each other. Also, the positions of the pit and the protrusion may correspond to each other.

[0179] For example, the aspect ratio of the pit may be the aspect ratio of the opening of the pit. When the pit is viewed from above, the aspect ratio may be the ratio of the major axis to the minor axis of the pit entrance (opening).

[0180] For example, when the entrance of the pit is rectangular, the aspect ratio may be the ratio of the horizontal to the vertical. For example, when the entrance of the pit is elliptical, the aspect ratio may be the ratio of the major axis to the minor axis. For example, when the entrance of the pit is triangular, the aspect ratio may be the ratio of the base to the height.

[0181] The aspect ratio of the above-mentioned pits may be 1 to 12, or may be 1.5 to 8.

[0182] In the protrusion 70 formed in the above-mentioned mold proposed in the present specification, a plurality of small protrusions may be arranged in a dotted line shape in order to substantially suppress positional movement of the device and maximize the flow of the molding material.

[0183] The above-mentioned dotted line shape refers to the arrangement of multiple protrusions at intervals in the space of the installation cavity. In this case, the protrusion 70 can be formed by arranging adjacent individual protrusions at intervals. The above-mentioned intervals can be constant or irregular. That is, the size of the protrusion and / or the arrangement between the protrusions can be regular or irregular. As the above-mentioned dotted line shape, all or at least a part of the above-mentioned protrusion can be arranged between the above-mentioned electronic devices in the space where the electronic devices are arranged.

[0184] Figure 10a to Figure 10b A conceptual diagram for explaining a transfer mold having a protrusion formed according to the present embodiment and a portion of the surface of a device package produced by the transfer mold.

[0185] Reference Fig.10a , the protrusion 70 may be arranged on the mold upper portion 61 and / or the mold lower portion 62 .

[0186] For example, protrusions spaced apart from each other at predetermined intervals may be arranged on the mold upper portion 61 and / or the mold lower portion 62. A certain number of protrusions arranged on the mold upper portion 61 and / or the mold lower portion 62 may be arranged between adjacent electronic devices of the device package 80.

[0187] For example, the protrusion may include protrusions arranged in a dotted line shape. Since the specific description about the dotted line shape is repeated with the above description, the detailed description thereof will be omitted.

[0188] For example, a certain number of protrusions 70 arranged on the mold upper portion 61 and / or the mold lower portion 62 may be arranged between adjacent first and second electronic devices of the device package 80. The embodiments shown in the drawings are merely exemplary, and those skilled in the art may make various variations and modifications using the basic concepts of the present embodiment.

[0189] Fig.10b By way of example, the Fig.10a The protrusion 70 is shown as a portion of the surface of a device package 80 produced by the transfer mold 60 .

[0190] For example, a recessed portion 81 in which pits are arranged may be formed on the upper surface and / or the bottom surface of the molding portion of the device package 80. Fig.10a Due to the protrusion 70 formed in a part of the mold, a recessed portion 81 with pits arranged therein may be formed in a part of the molded portion of the device package 80. For example, the positions of the recessed portion and the protrusion may correspond to each other. In addition, the positions of the protrusion and the pit may correspond to each other.

[0191] Reference Fig.10bWhen the recessed portion 81 is observed from a first surface (eg, an upper surface of the device package) to a second surface (eg, a bottom surface of the device package), a plurality of recesses may be arranged in a dotted line form.

[0192] The above-mentioned dotted line shape refers to a plurality of pits arranged at intervals in the space of the installation cavity. In this case, the recessed portion 81 may be composed of individual pits arranged at intervals and adjacent to each other. The above-mentioned intervals may be constant or irregular. That is, the size of the pits and / or the arrangement between the pits may be regular or irregular. In the above-mentioned dotted line shape, all or at least a portion of the above-mentioned recessed portion or the above-mentioned pits may be between the above-mentioned electronic devices in the space where the electronic devices are arranged.

[0193] On the other hand, the protrusion formed on the upper part of the mold and the recessed part formed on the molding part of the device package proposed in this specification are not limited to the above embodiments. For example, considering the shape of the cavity part where the device package is arranged, various shapes of protrusions and recessed parts can be applied.

[0194] In addition, this specification proposes a method for manufacturing a package substrate according to this embodiment.

[0195] According to an embodiment of the present specification, a method for manufacturing a packaging substrate may include the following steps: preparing a glass core having a cavity portion and a device package; arranging the device package in the cavity portion; and forming an insulating layer by arranging an insulating material on the glass core or the cavity portion and curing the insulating material.

[0196] Fig.11 A cross-sectional flow chart illustrating a method for manufacturing a package substrate according to the present embodiment.

[0197] Reference Fig.11 In part (a), a glass core having a cavity portion and a device package 80 may be prepared.

[0198] For example, the encapsulation substrate may include a core layer, the core layer including a glass core and a cavity portion, the glass core having a first surface and a second surface facing each other, and the cavity portion penetrating the glass core. A glass core having a first surface and a second surface facing each other may be provided, and the cavity portion penetrating the glass core may be arranged at the glass core.

[0199] In addition, for example, the device package 80 may be produced by a transfer molding process using a transfer mold 60 formed with the protrusion 70. For example, a mold having an injection port may be provided, and a plurality of protrusions may be arranged around the injection port of the mold.

[0200] For example, a protrusion may be arranged on the mold upper part 61 of the mold. Alternatively, for example, a protrusion may be formed on the mold lower part 62 of the mold. Alternatively, for example, a protrusion may be arranged on the mold upper part 61 and the mold lower part 62 of the mold.

[0201] The shape of the protrusion or the arrangement of the protrusions is the same as described above.

[0202] Next, the electronic device may be arranged at a predetermined position of the mold, and the molding material may be injected through the injection port.

[0203] For example, a plurality of electronic devices may be arranged in a mold cavity 63 of a transfer mold 60 in which the upper mold 61 and / or the lower mold 62 are formed with a protrusion 70, and a molded portion of a device package 80 may be generated by pouring a molding material into the mold cavity 63 and curing it.

[0204] The device package 80 may include: a plurality of arranged electronic devices; and a molding part including a molding material and arranged to surround the electronic devices.

[0205] Since the description about the device package overlaps with the above description, its detailed description will be omitted.

[0206] In addition, projections of various shapes can be formed on the above-mentioned mold.

[0207] For example, the protrusions arranged on the mold upper part 61 and / or the mold lower part 62 may be in the shape of a triangular prism having a triangular cross section. The protrusions may be arranged so that one square surface of the triangular prism is in contact with the mold upper part 61 and / or the mold lower part 62. Alternatively, for example, protrusions spaced apart at predetermined intervals may be arranged on the mold upper part 61 and / or the mold lower part 62. The protrusions may be arranged between the adjacent first electronic device and the second electronic device of the device package 80.

[0208] In addition, for example, a recessed portion is arranged in the molding portion of the device package 80, and pits are arranged in the recessed portion. For example, pits of various shapes may be arranged on the upper surface and / or the bottom surface of the molding portion.

[0209] For example, the above-mentioned pits can be formed so that a square surface of the triangular prism is connected to the above-mentioned mold upper part 61 and / or the above-mentioned mold lower part 62. Or, for example, when viewed from the above-mentioned first surface to the above-mentioned second surface, a plurality of the above-mentioned pits can be arranged in a dotted line shape. In this case, for example, pits spaced apart at predetermined intervals can be arranged in the above-mentioned mold upper part 61 and / or the above-mentioned mold lower part 62. The above-mentioned pits can be arranged between the adjacent first electronic device and the second electronic device of the above-mentioned device package 80.

[0210] Next, for example, refer to Fig.11 In part (b), the device package 80 may be arranged in the cavity portion 28 .

[0211] For example, the glass core 21 may be attached to an adhesive film such as a polyimide tape (PI tape), and the device package 80 may be disposed in the cavity 28. The electronic device 40 of the device package 80 may include an active device such as a transistor or a power transmission device such as a capacitor, i.e., a passive device.

[0212] Next, an insulating layer may be laminated on the glass core. The insulating layer may be formed by placing an insulating material on the glass core or the cavity and solidifying it.

[0213] For example, Fig.11 As shown in part (c) of FIG. 2 , a process of laminating an upper insulating layer on the first surface of the glass core 21 (Lamination on top) may be performed.

[0214] The adhesive film may be removed in a subsequent process as needed. For example, the adhesive film may be an adhesive film whose adhesive force may be reduced due to ultraviolet irradiation or the like.

[0215] The adhesive force of the adhesive film can be reduced by irradiating ultraviolet rays directly or through the glass core, and the adhesive film can be easily removed from the glass core.

[0216] Secondly, if Fig.11 As shown in part (d) of FIG. 2 , a process of laminating a lower insulating layer on the second surface of the glass core 21 (Lamination on bottom) may be performed.

[0217] Afterwards, refer to Fig.11 The upper insulating layer and the lower insulating layer may be pre-cured in the portion (e). The upper insulating layer may be recessed into the recessed portion 81 of the device package 80 and / or the inner space of the cavity portion 28 .

[0218] The insulating material may be a polymer resin, a mixed material of a polymer resin and a filler (inorganic particles, organic particles, organic-inorganic composite particles, etc.), or the like.

[0219] For example, the polymer resin may be an acrylic resin, an epoxy resin or a modified resin thereof, and may be a material applicable to electronic devices for the purpose of molding, etc. For example, a liquid crystal polymer (LCP) may be used.

[0220] For example, the mixed material may be a mixture of acrylic resin and filler, a mixture of acrylic resin and epoxy resin and a mixture of filler, and a mixture of epoxy resin and filler. The filler may be inorganic particles, for example, silica particles. As commercial products, Ajinomoto built-in film (ABF), epoxy molding compound (EMC), and modified polyimide (MPI) may be used, but the present invention is not limited thereto.

[0221] Specifically, the insulating material suitable for the insulating layer may include an insulating mixture, which may include inorganic particles and a polymer resin.

[0222] The insulating material may include epoxy molding compound (EMC) and / or Ajinomoto build film (ABF).

[0223] The insulating material may flow so that a portion thereof moves into the recessed portion (pit) on the cavity device.

[0224] In the cross section of the package substrate, the insulating layer and the cavity device can be distinguished. That is, the boundary between the insulating layer and the device package can be observed. The boundary is observed in the cavity portion.

[0225] In one embodiment, the insulating layer and the device package are stacked up and down, and the molding material of the device package and the insulating material of the insulating layer may be substantially the same. In this case, the boundary between the insulating layer and the device package of the cavity device may be difficult to distinguish. That is, it may be substantially difficult to observe the shape of the recess or pit.

[0226] In another embodiment, the insulating layer and the cavity device may be stacked up and down, and the molded portion and the insulating material of the applicable device package may be distinguished from each other. In this case, in the cross section of the cavity, the boundary between the molded portion and the insulating layer may be distinguished, and a recessed portion (or pit) may be observed at the boundary.

[0227] As for the distinction between the molded portion and the insulating layer, even if the materials are substantially the same, a boundary between the molded portion and the insulating layer may be generated by setting different curing pressures and temperatures.

[0228] The above-mentioned boundary can be distinguished by using different materials. In this case, the boundary of the cavity portion and the recessed portion (or pit) can be more easily distinguished in the cross section of the cavity portion.

[0229] In the cross section, as the above-mentioned boundary, the boundary of the color difference can be observed in the form of a line.

[0230] In the cross section, as the above-mentioned boundary, a color changing band with a relatively constant thickness (for example, a color change like a gradient) can be observed. Exemplarily, the above-mentioned constant interval may be 2 μm to 30 μm, or may be 3 μm to 10 μm.

[0231] In the cross section, the above boundary can be distinguished by including fillers of different sizes based on the above boundary. Thus, the stress of the glass substrate caused by the difference in thermal expansion coefficient of the insulating material can be more easily controlled and adjusted.

[0232] At this time, fillers of different sizes refer to fillers having different d50 values ​​measured by a particle size analysis method.

[0233] The molding part and the insulating layer may be made of materials having the same or different coefficients of thermal expansion (CTE). Preferably, a material having a smaller difference in CTE between the molding part and the insulating layer may be used.

[0234] The difference in thermal expansion coefficient between the molded part and the insulating layer may be 2 ppm / °C or less, 1.5 ppm / °C or less, 1 ppm / °C or less, or 0.5 ppm / °C or less. The difference in thermal expansion coefficient may be 0 ppm / °C or more, 0.1 ppm / °C or more, or 0.2 ppm / °C or more.

[0235] The thermal expansion coefficient of the molded part may be 8 ppm / °C or more, 10 ppm / °C or more, 12 ppm / °C or more, or 14 ppm / °C or more. The thermal expansion coefficient may be 20 ppm / °C or less, 18 ppm / °C or less, or 17 ppm / °C or less.

[0236] The thermal expansion coefficient of the insulating layer may be 8 ppm / °C or more, 10 ppm / °C or more, or 12 ppm / °C or less. The thermal expansion coefficient may be 20 ppm / °C or less, 18 ppm / °C or less, 16 ppm / °C or less, or 14 ppm / °C or less.

[0237] The molding part and the insulating layer may be made of materials with different dielectric constants. Preferably, the material of the insulating layer may be selected and applied so that the dielectric constant of the molding part is lower than the dielectric constant of the insulating layer.

[0238] The molded portion and the insulating layer may be made of materials having a difference in relative dielectric constant Dk at a high frequency of 5.8 GHz. Exemplarily, the difference between the Dk of the molded portion and the Dk of the insulating layer may be greater than 0.1. The difference in Dk may be greater than 0.1, greater than 0.13, greater than 0.16, or greater than 0.2. The difference in Dk may be less than 1, less than 0.8, less than 0.6, less than 0.5, less than 0.4, less than 0.3, or less than 0.25.

[0239] The Dk of the molded portion may be 2.3 or more, 2.5 or more, 2.7 or more, or 2.9 or more. The Dk may be 3.4 or less, 3.2 or less, or 3.1 or less.

[0240] The Dk of the insulating layer may be greater than or equal to 3.0, greater than or equal to 3.1, or greater than or equal to 3.2. The Dk may be less than or equal to 3.6, less than or equal to 3.5, or less than or equal to 3.4.

[0241] The molded part and the insulating layer may be made of materials having different dielectric loss factors Df. Preferably, a material in which the difference between the Df of the molded part and the Df of the insulating layer is 0.0001 or more may be used. The difference in Df may be 0.0001 or more, 0.0005 or more, or 0.001 or more. The difference in Df may be 0.02 or less.

[0242] The Df of the molded portion may be 0.004 or less, 0.0038 or less, or 0.0036 or less. The Df may be 0.001 or more, 0.0015 or more, 0.0018 or more, or 0.002 or more.

[0243] The Df of the insulating layer may be 0.005 or less, 0.0048 or less, or 0.0046 or less. The Df may be 0.003 or more, 0.0032 or more, or 0.0034 or more.

[0244] For example, ABF may be applied to the insulating layer, and LCP may be applied to the molding part. For example, EMC may be applied to the insulating layer, and LCP may be applied to the molding part. For example, ABP having different dielectric constants may be applied to the insulating layer and the molding part.

[0245] The method for manufacturing a package substrate and the package substrate using the same according to the above-described embodiments can prevent a phenomenon in which a plurality of devices are deviated from their arranged positions when being embedded by inserting a device package produced using a mold having a protruding portion into a cavity portion.

[0246] Thus, the arrangement position of the devices can be maintained by the device package having the recessed portion disposed in a portion of the molded portion, and contact between the devices can be prevented, thereby achieving the effect of avoiding problems such as short circuits.

[0247] Above, this specification is described with reference to the embodiments illustrated in the accompanying drawings, but this is only an example. As long as a person skilled in the art will understand, various modifications and equivalent other embodiments can be derived from this. In other words, the scope of this specification is not limited to the above-mentioned embodiments, but various changes or modifications of the basic concepts of this embodiment defined in the attached additional description by a person skilled in the art belong to the scope of this embodiment. Therefore, the true technical protection scope of this specification should be determined according to the technical ideas of the attached claims.

Claims

1. A packaging substrate, characterized in that: comprising a core layer, wherein the core layer comprises a glass core and a cavity portion, The glass core is a glass substrate including a first surface and a second surface facing each other. The cavity is formed by recessing or penetrating a portion of the glass core and has a storage space for storing electronic components. A device package is arranged in the accommodation space of the cavity portion. The device package comprises: i) a plurality of arranged electronic devices; and ii) a molding portion containing a molding material and arranged such that the molding material surrounds the electronic devices. In the device package, a recessed portion is disposed in a portion of the molded portion, and dimples are arranged in the recessed portion.

2. The packaging substrate according to claim 1, characterized in that: The above-mentioned pits are arranged between adjacent electronic devices.

3. The packaging substrate according to claim 1, characterized in that: The recessed portion includes a plurality of pits arranged in a dotted line shape when viewed from the first surface toward the second surface.

4. The packaging substrate according to claim 1, characterized in that: The package substrate further includes an insulating layer arranged on the cavity portion. The insulating material of the insulating layer is recessed in the recessed portion.

5. The packaging substrate according to claim 1, characterized in that: The molding material includes liquid crystal polymer (LCP), epoxy molding compound (EMC), Ajinomoto build-up film (ABF) or modified polyimide (MPI).

6. The packaging substrate according to claim 4, characterized in that: The above-mentioned insulating layer comprises an insulating mixture, The above-mentioned insulating mixture includes inorganic particles and polymer resin.

7. The packaging substrate according to claim 4, characterized in that: The boundary between the molding part and the insulating layer is located in the cavity part. A recessed portion is arranged at the boundary, and the recessed portion has a pit recessed toward the electronic device.

8. A method for manufacturing a device package, characterized in that: include: A device placement step, preparing a mold with an injection port, and placing a plurality of electronic devices at predetermined positions of the mold; An injection step of injecting the molding material into the injection port; and a mold forming step of forming a molded portion by solidifying the molding material; A protrusion is arranged around the injection port of the mold, and a plurality of protrusions are arranged in the protrusion. The device package includes: i) a plurality of arranged electronic devices; and ii) a molding portion containing a molding material and arranged to surround the plurality of electronic devices, wherein a recessed portion is arranged in a portion of the molding portion, and pits are arranged in the recessed portion. The positions of the recessed portion and the protruding portion correspond to each other.

9. The method for manufacturing a device package according to claim 8, wherein: In the device placement step, the plurality of electronic devices are placed on the bonding surface and their positions are fixed. The position where the electronic components are arranged in the mold forming step is substantially the same as the position where the electronic components are arranged in the component arranging step.

10. The method for manufacturing a device package according to claim 8, wherein: The protrusions are arranged between adjacent electronic devices.

11. The method for manufacturing a device package according to claim 8, wherein: The device package is produced through a transfer molding process using a transfer mold having a protrusion formed on an upper portion of the mold.

12. A method for manufacturing a packaging substrate, which is a method for manufacturing the packaging substrate according to claim 1, characterized in that: The steps include: preparing a glass core having a cavity portion and a device package; placing the device package in the cavity; and The insulating layer is formed by disposing an insulating material on the glass core or the cavity portion and solidifying the insulating material.

13. The method for manufacturing a packaging substrate according to claim 12, wherein: In the step of forming the insulating layer, the insulating material flows so that a portion of the insulating material moves to a concave portion of the recess on the device package.

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