Self-aligned assisted assembly of multi-stage die composites

Abstract

The present disclosure relates to self-aligned assisted assembly of multi-stage die composites. Hybrid bonded multi-level die stacks, related devices, systems, and methods of manufacture are disclosed. A first level integrated circuit (IC) die and a base substrate each include a hybrid bonding region surrounded by a hydrophobic structure. The hybrid bonding regions are placed together with droplets therebetween, and capillary forces self-align the IC die. The hybrid bond is formed by evaporating the droplets and then annealing. The hybrid bonding region of the second level IC die is similarly bonded to the hybrid bonding region on the backside of the first level IC die. This is repeated for any number of subsequent levels of IC dies. An IC structure including the bonded IC die and portions of the base substrate is singulated and assembled.

Description

Background Art

[0001] The integrated circuit industry is constantly striving to produce faster, smaller and more efficient integrated circuit devices, packages and systems for various electronic products. Current die stacks can be formed using solder to solder bump attachment technology. For example, on two separate die, solder bumps can be deposited on copper pillars. Solder bumps can then be made to contact the die to be bonded, and bottom fill material can be formed between the solder bonding and the copper pillars. Such a process disadvantageously requires a large distance between the bonded die, and limits the ability to be reduced to a lower spacing.

[0002] Alternatively, a hybrid bond can be formed between corresponding metal bonding pads on two dies, where the metal bonding pads are interspersed between dielectric materials (e.g., oxides). Prior to bonding, the surface of each die can be controlled to facilitate bonding by providing a recess of the metal bonding pad relative to the dielectric material, making the dielectric material flat and relatively smooth, and the like. The dies with mirrored bonding pads are then placed together so that the corresponding metal bonding pads and corresponding dielectric material surfaces of the two dies are in contact with each other. At room temperature, the dielectric materials are sufficiently adhered to each other (due to van der Waals forces) to maintain bonding. A high temperature anneal is then performed to bond the corresponding metal bonding pads and improve the dielectric material bonding. Such a process reduces the distance between the bonded dies, reduces the spacing between the metal bonds, and provides other advantages. For example, solder bump technology can be limited to a spacing of about 30 μm, while hybrid bonding can achieve a spacing of less than 10 μm or even less than 1 μm.

[0003] However, difficulties in forming 3D die stacks using hybrid bonding techniques still exist. In view of these and other considerations, improvements of the present invention are needed. As the desire to provide improved integrated circuit devices, packages, and systems becomes more prevalent, such improvements may become critical. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The materials described herein are shown in the accompanying drawings by way of example and not by way of limitation. For simplicity and clarity of illustration, the elements shown in the drawings are not necessarily drawn to scale. For example, for clarity, the size of some elements may be exaggerated relative to other elements.

[0005] Further, where considered appropriate, reference numerals have been repeated among the drawings to indicate corresponding or analogous elements. In the drawings:

[0006] Figure 1 A flow chart illustrating an example process for fabricating an IC structure including a multi-level 3D die stack having multiple levels bonded by hybrid bonding regions within a containment feature is provided;

[0007] Figure 2 , Figure 3 , Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E is an illustration of a cross-sectional side view of an integrated circuit (IC) structure prepared for self-aligned bonding;

[0008] Figure 4F Shows Figure 4E A top view of an IC structure showing a bonding area defined by a hydrophobic pattern;

[0009] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13A , Fig. 13B , Fig.14 , Fig.15 and Fig.16 is an illustration of a cross-sectional side view of an IC structure during self-aligned bonding and hybrid bonding;

[0010] Fig.17 is similar to the packaging and deployment of heat removal solutions Fig.12 An illustration of a cross-sectional side view of a component structure of an IC structure;

[0011] Fig.18 An exemplary system for deploying a multi-level 3D die stack having multiple levels bonded via hybrid bonding regions within confined features is shown; and

[0012] Fig.19 is a functional block diagram of an electronic computing device, all arranged in accordance with at least some embodiments of the present disclosure. DETAILED DESCRIPTION

[0013] One or more embodiments or implementations are now described with reference to the accompanying drawings. Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. It should be appreciated by those skilled in the relevant art that other configurations and arrangements may be employed without departing from the spirit and scope of this specification. It will be apparent to those skilled in the relevant art that the techniques and / or arrangements described herein may also be employed in various other systems and applications in addition to the systems and applications described herein.

[0014] In the following specific embodiments, reference is made to the accompanying drawings that form a part of the specific embodiments, wherein the same reference numerals may always represent the same parts to represent corresponding or similar elements. It should be understood that, for the sake of simplicity and / or clarity of explanation, the elements shown in the figures are not necessarily drawn to scale. For example, for the sake of clarity, the sizes of some elements may be exaggerated relative to other elements. In addition, it should be understood that other embodiments may be utilized without departing from the scope of the claimed subject matter, and structural and / or logical changes may be made. It should also be noted that directions and references (e.g., up, down, top, bottom, above, below, etc.) may be used to facilitate discussion of the drawings and embodiments, and these directions and references are not intended to limit the application of the claimed subject matter. Therefore, the following specific embodiments should not be considered to have a limiting meaning, and the scope of the claimed subject matter is defined by the appended claims and their equivalents.

[0015] In the following description, many details are set forth. However, it will be apparent to those skilled in the art that the present invention can be practiced without these specific details. In some cases, known methods and apparatus are shown in block diagram form rather than in detail to avoid making the present invention difficult to understand. References to "embodiment" or "one embodiment" throughout this specification are included in at least one embodiment of the present invention in conjunction with the specific features, structures, functions or characteristics described in the embodiment. Therefore, the phrases "in an embodiment" or "in an embodiment" that appear throughout this specification do not necessarily refer to the same embodiment of the present invention. In addition, specific features, structures, functions or characteristics can be combined in any suitable manner in one or more embodiments. For example, the first embodiment can be combined with the second embodiment at any place where the specific features, structures, functions or characteristics associated with the two embodiments are not mutually exclusive.

[0016] As used in the description of the present invention and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0017] The terms "coupled" and "connected" and their derivatives may be used in this article to describe the structural relationship between components. It should be understood that these terms are not intended to be synonymous with each other. On the contrary, in a particular embodiment, "connected" may be used to represent that two or more elements are in direct physical or electrical contact with each other. "Coupled" may be used to represent that two or more elements are in direct or indirect (with other intermediate elements between them) physical or electrical contact with each other, and / or that two or more elements cooperate or interact with each other (e.g., as in a cause-and-effect relationship).

[0018] As used herein, the terms "above", "below", "between", "on", etc. refer to the relative position of a material layer or component relative to other layers or components. For example, a layer disposed above or below another layer may be in direct contact with the other layer, or may have one or more intermediate layers. In addition, a layer disposed between two layers may be in direct contact with the two layers, or may have one or more intermediate layers. In contrast, a first layer "on" a second layer is in direct contact with the second layer. Similarly, unless otherwise expressly stated, a feature disposed between two features may be in direct contact with an adjacent feature, or may have one or more intermediate features. The term "adjacent" indicates that these features are in direct contact. In addition, the terms "substantially", "close", "approximately", "nearly", and "approximately" generally refer to within + / -10% of a target value. The term layer used herein may include a single material or multiple materials. As used throughout this specification and claims, a list of items connected by the terms "at least one of" or "one or more of" may represent any combination of the listed terms. For example, the phrase “at least one of A, B, or C” may mean A; B; C; A and B; A and C; B and C; or A, B, and C.

[0019] Integrated circuit structures, 3D die stack structures, devices, apparatus, systems and methods are described herein that involve multi-level 3D die stacks interconnected by confined hybrid bonding regions within confined features.

[0020] As described above, hybrid bonding technology provides advantages in the assembly of 3D die stacks. As used herein, the term multi-stage 3D die stacks represents a stack of devices or structures with at least partially vertically aligned layers, so that each layer or level of the 3D die stack can each use one or more IC dies. The layer or level of the term 3D die stack represents the horizontal portion of the 3D die stack, and the 3D die stack only includes a device (onedepth of device) of a depth in the horizontal portion (for example, each layer or level can have any number of IC dies in the horizontal plane). The term multi-stage 3D die stack represents a die stack with multiple levels (for example, two or more levels) on the base substrate. The term IC die includes any monolithic integrated device that provides electrical, computing, storage or similar functions. IC die includes core grains (chiplet), core grain die, memory die, processor die, wiring die, etc. In this article, the term core grain and IC die are used interchangeably. The IC die may be passive, such that it includes only electrical wiring, or it may be active, such that it includes electrical devices such as transistors, capacitors, etc. The terms base substrate, base wafer, or base die refer to a substrate having active or passive electrical features. In contrast, the terms structural substrate, structural wafer, or structural die refer to a substrate without any active or passive electrical features. For example, the structural substrate may be a single piece of material, such as silicon, or may be other base materials that provide structural support and heat removal.

[0021] In the case of hybrid bonding of IC dies, faster throughput can be achieved during die-to-wafer hybrid bonding (D2WHB) using self-alignment assisted assembly (SA3). In the SA3 process flow, droplets are dispensed on the bonding area on the top core die or base wafer to be bonded. The core die is then picked up and placed on the base wafer using a bonder with coarse alignment (e.g., ~25-50um) so that the droplets are sandwiched in the bonding area between the core and the base wafer. Due to the restriction features (e.g., SA3 features) designed into the core die and the base wafer (the restriction features restrict the droplets to the bonding area with high precision), capillary forces cause the core to self-align to its desired bonding position on the wafer with high positional accuracy (e.g., <200nm). Such restriction features can be characterized as alignment features, SA3 features, etc. The liquid is then evaporated, thereby bonding the core particle to the base wafer at room temperature due to attractive surface forces (e.g., van der Waals forces) between the core particle and the dielectric regions on the base wafer. An annealing step is then performed to form and / or strengthen bonds between metal pads (e.g., copper pads) dispersed between the dielectric regions, thereby forming electrical interconnections between the core particle and the base wafer. The annealing step can also strengthen the bonds between the dielectric regions.

[0022] Some current product architectures require that dies be stacked in two or more layers to form a multi-level die complex. It is advantageous to stack hybrid bonded dies in a multi-level die complex, where the hybrid bonding interconnects between multiple layers of the multi-level 3D stack. It is noteworthy that as the number of levels and therefore the number of die transfers increases, assembly speed becomes even more important in such a multi-level 3D stack. Current die-to-wafer hybrid bonding using precision pick and place cannot meet the throughput required when forming a multi-level 3D stack. The techniques and structures discussed herein address these challenges by implementing restriction features (e.g., SA3 features) at multiple levels (e.g., at each level of the multi-level die complex) when assembling a multi-level die complex using die-to-wafer bonding. The restriction features (e.g., SA3 features) enable fast throughput assembly of multi-level die complexes using die-to-wafer hybrid bonding, as further discussed herein. In some embodiments, the first level core dies (e.g., those directly above the base substrate) have through vias (e.g., through silicon vias, TSVs) for back side connections so that the first level core dies can be placed face up or face down on the base substrate (the "face" side or surface is defined as having the active layer). After the dielectric fill of the first level core dies, a hybrid bonding layer with confining features (e.g., SA3 features) is fabricated for bonding the second level core dies to any combination of the first level core dies with back side through vias or front side interconnects. The second level core dies are then bonded using confining features (e.g., SA3 features) as discussed. This sequence of hybrid bonding using droplets within confining features, forming a hybrid bonding layer over the bonded cores, confining the hybrid bonding area within confining features, hybrid bonding using droplets within confining features, etc. can be continued for any number of levels.

[0023] Figure 1 A flow chart is provided showing an example process 100 for manufacturing an IC structure including a multi-level 3D die stack having multiple levels bonded by hybrid bonding regions within confinement features arranged according to at least some embodiments of the present disclosure. For example, process 100 may be implemented to manufacture IC structures 1200, 1500, 1600, or an assembly structure (including manufacturing IC structures 1200, 1500, 1600), such as assembly structure 1700, or any other structure discussed herein. In the illustrated embodiment, process 100 includes one or more operations as shown in operations 101-112. However, embodiments herein may include additional operations, omit certain operations, or perform operations out of the order provided. Figure 2 , Figure 3 , Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E and Figure 5-17 The structure and components used in practicing the method of process 100 are shown.

[0024] Figure 2 , Figure 3 , Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E is an illustration of a cross-sectional side view of an integrated circuit (IC) structure prepared for self-aligned bonding, arranged in accordance with at least some embodiments of the present disclosure. Figure 4F Shown are arranged according to at least some embodiments of the present disclosure Figure 4E Top view of the IC structure showing the bonding area defined by the hydrophobic pattern. Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13A , Fig. 13B , Fig.14 , Fig.15 and Fig.16 is an illustration of a cross-sectional side view of an IC structure during self-aligned bonding and hybrid bonding, arranged in accordance with at least some embodiments of the present disclosure. Fig.17 is similar to after packaging and deploying a heat removal solution arranged in accordance with at least some embodiments of the present disclosure Fig.12 Illustration of a cross-sectional side view of a component structure of an IC structure.

[0025] Process 100 begins at operation 101, where bonding areas surrounded by hydrophobic confinement features are prepared on a base wafer and on an IC die or core. In process 100, the IC die or core are attached to a base wafer or substrate so that they can be directly attached to the base wafer or substrate or to a layer or level of a previously assembled IC die or core. This attachment technique places the IC die or core onto the base substrate quickly and in a coarse alignment, and then uses droplets between the bonding areas of the placed IC die or core and the corresponding bonding areas of the base substrate to provide fine alignment using capillary forces. This self-aligned bonding technique allows high throughput because high-precision, high-duration pick-and-place alignment is not required.

[0026] Figure 22 is an illustration of a cross-sectional side view of an IC structure 200 prepared for self-aligned bonding. As shown, the IC structure 200 includes a substrate 201 and a hybrid bonding layer 202 formed on the substrate 201. The substrate 201 can be a base wafer (as discussed further below) or a structural wafer or panel, etc., on which the IC die or core particles are prepared for hybrid bonding. For example, the substrate 201 can be a monolithic material, a crystalline material or a composite material, a structural material, or the substrate 201 can be a base substrate including an interconnect layer, an optional device layer, and wiring passing through the substrate 201 to connect to an external package or board.

[0027] The hybrid bonding layer 202 includes a metal bonding pad 203 interspersed in an inorganic dielectric material 204. The inorganic dielectric material 204 can be any suitable material for forming a bond between the hybrid bonding layer 202 and another hybrid bonding layer. As used herein, the term inorganic material means a material that does not use carbon as a basic component or a material that does not have a carbon-hydrogen bond. In some embodiments, the inorganic dielectric material 204 is silicon oxide. In some embodiments, the inorganic dielectric material 204 is silicon nitride, silicon oxynitride, silicon carbonitride or silicon carbide. In some embodiments, the outward-facing surface of the hybrid bonding layer 202 can be flattened to a smooth finish for subsequent bonding. The metal bonding pad 203 can be any suitable material for forming a bond between the hybrid bonding layer 202 and another hybrid bonding layer and a suitable conductor for the current application. In some embodiments, the metal bonding pad 203 is copper, but other metals can be used. In some embodiments, the bulk inorganic dielectric material is formed on the substrate 201 and is flattened. Metal bond pad 203 is then formed using any suitable technique or techniques, such as single or dual damascene techniques.

[0028] Figure 3 An IC structure 300 similar to IC structure 200 is shown after forming a hydrophilic structure 301 for self-aligned bonding. As discussed, the hydrophilic structure 301 includes metal bonding pads 203 dispersed in an inorganic dielectric material 204, which may be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or silicon carbide. Such materials are hydrophilic so that liquids (e.g., water) will spread out on the hydrophilic structure 301 because the liquid minimizes its surface energy. Thus, the patterned hydrophilic structure 301 defines a hybrid bonding area 303, which will bond to a corresponding hybrid bonding area to build a multi-level 3D die stack, as discussed further below.

[0029] The hydrophilic structures 301 and the openings or trenches 302 can be formed from the hybrid bonding layer 202 using any suitable technique or techniques, such as patterning a resist layer on or over the hybrid bonding layer 202, etching exposed portions of the hybrid bonding layer 202 (e.g., by dry etching), and removing the resist layer. In some embodiments, the pattern of the hydrophilic structures 301, as defined by the hybrid bonding regions 303, matches the desired layout of the die or IC die on the substrate 201.

[0030] Figure 4A An IC structure 400 similar to IC structure 300 is shown after forming a hydrophobic structure 401 adjacent to the hydrophilic structure 301. The hydrophobic structure 401 may be formed on the sidewalls 305 of the hydrophilic structure 301 using any suitable technique or techniques. In some embodiments, a conformal hydrophobic material layer is formed on the exposed surfaces of the hydrophilic structure 301 and the substrate 201 using, for example, spin coating or conformal vapor deposition. The conformal hydrophobic material layer is then removed from the lateral or horizontal surfaces via an anisotropic etch, such as a dry etch, while the conformal hydrophobic material layer remains on the sidewalls 305.

[0031] The hydrophobic structure 401, which may be characterized as a hydrophobic spacer, a hydrophobic material, etc., may include any suitable hydrophobic material (e.g., a material that causes a liquid water droplet to have a contact angle greater than 90°). In some embodiments, the hydrophobic structure 401 is a chemical coating or hydrophobic material that produces a hydrophobic boundary with a large contact angle (e.g., >90°) around the hybrid bonding region 303. In some embodiments, the hydrophobic material of the hydrophobic structure 401 is or includes a self-assembled monolayer (SAM) material, such as an alkyl or fluoroalkyl silane (e.g., ODS, FDTS), a thiol (e.g., hexadecanethiol), a phosphonic acid (e.g., octadecyl or perfluorooctanephosphonic acid), or an alkanoic acid (e.g., heptadecanoic acid). However, non-SAM-based materials or films may be used. In some embodiments, the hydrophobic material of the hydrophobic structure 401 is or includes a thin polymer film, such as siloxane (e.g., PDMS and derivatives, HMDSO), silazane (HMDS), polyolefin (e.g., PP), or fluorinated polymer (e.g., PTFE, PFPE, PFDA, C4F8 plasma polymerized film, etc.). Other hydrophobic materials may be used.

[0032] As discussed, the hydrophobic structure 401 confines the liquid within the hybrid bonding region 303, while the hydrophilic structure 301 allows the liquid to spread in the hybrid bonding region 303. For example, the hydrophilic structure 301 can be an inorganic material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or silicon carbide. Such a material is hydrophilic, so that the liquid (e.g., water) will spread on the hydrophilic structure 301 because the liquid minimizes its surface energy. In contrast, a hydrophobic structure (such as the hydrophobic structure 401) will confine the liquid. A hydrophilic material or surface causes a droplet to have a contact angle of less than 90° (e.g., water on silicon oxide has a contact angle of ~10-20°), while a hydrophobic structure causes a droplet to have a contact angle greater than 90°. As used herein, the term hydrophobic structure includes both: a topological change to the material (e.g., a change to another hydrophilic structure) and a hydrophobic material applied to the hydrophilic structure.

[0033] exist Figure 4A In the embodiment of the present invention, the hybrid bonding region 303 is within the hydrophobic structure 401 and the groove 302. It is worth noting that the groove 302 is also a hydrophobic structure. Figure 4C Further discussion. Figure 4A Embodiments of the invention provide the advantages of a variety of different hydrophobic structures (eg, both material-based hydrophobic structures and structure-based hydrophobic structures) at the expense of increased manufacturing complexity. Figure 4B-4E Alternative hydrophilic and hydrophobic structures for confining liquid within the hybrid bonding region 303 are shown.

[0034] Figure 4B An IC structure 410 similar to IC structure 200 is shown after forming a hydrophobic structure 402 to define a hybrid bonding region 303 as part of the hybrid bonding layer 202 (which is also labeled as a hydrophilic structure 404). The hydrophobic structure 402 can be formed using any suitable technique or techniques, such as forming a conformal hydrophobic material layer on the hybrid bonding layer 202, then patterning the conformal hydrophobic material layer by patterning a resist layer on or over the hydrophobic material layer, etching exposed portions of the hydrophobic material layer, and removing the resist layer. For example, the pattern of the hydrophobic structure 402 defines the hybrid bonding region 303.

[0035] The hydrophobic structure 402 may include any of the hydrophobic materials discussed with respect to the hydrophobic structure 401. For example, the hydrophobic structure 402 may be or include a self-assembled monolayer material such as an alkyl or fluoroalkyl silane, a thiol, a phosphonic acid, or an alkanoic acid, or the hydrophobic structure 402 may be or include a polymer film such as a siloxane, a silazane, a polyolefin, or a fluorinated polymer. Other hydrophobic materials may be used. As discussed, the hydrophobic structure 402 confines the liquid within the hybrid bonding region 303, while the hydrophilic structure 404 allows the liquid to spread out within the hybrid bonding region 303. Figure 4B In the embodiment of FIG. 4 , the hybrid bonding region 303 is within the hydrophobic structure 402 and on a specific region or area of ​​the hydrophilic structure 404. Such a structure provides the advantage that the hydrophobic structure 402 is relatively easy to manufacture based on the material.

[0036] Figure 4C IC structure 420 is shown similar to IC structure 300, where trench 302 acts as a hydrophobic structure. As discussed, hydrophilic structure 301 causes liquid (e.g., water) to spread out on hydrophilic structure 301 because the liquid minimizes its surface energy. In contrast, trench 302, which can be characterized as hydrophobic structure 422, will confine the liquid. Figure 4C In the case of , the hydrophobic structure is a groove 302 in the hybrid bonding layer 202, such that the sidewalls 305 and the corners 403 are defined by the groove 302. Due to the groove 302, when the droplet spreads out, it interacts with the corners 403, which changes the surface energy characteristics of the droplet, thereby changing the effective contact angle to greater than 90°. Figure 4C As shown, in some embodiments, the trench 302 extends to the top surface of the substrate 201. Alternatively, the bottom of the trench 302 may include a portion of the hybrid bonding layer 202. For example, the trench 302 may be deployed to any depth that provides a corner 403.

[0037] Figure 4DAn IC structure 430 similar to the IC structure 200 is shown after forming a hydrophobic structure 405 including a roughened surface 406 for self-aligned bonding. The hydrophobic structure 405 can be formed using any suitable technique or techniques, such as a surface texturing technique including laser surface roughening. The roughened surface 406 can have any suitable surface roughness relative to the surface of the hydrophilic structure 404 in the hybrid bonding area 303. In some embodiments, the surface roughness of the roughened surface 406 (i.e., measured as the deviation from its ideal form in the direction of the normal vector of the actual surface) is not less than twice the surface roughness of the surface of the hydrophilic structure 404 in the hybrid bonding area 303. For example, the ratio of roughness can be defined as the surface roughness of the roughened surface 406 divided by the surface roughness of the surface of the hydrophilic structure 404 in the hybrid bonding area 303. In some embodiments, the ratio is not less than 2. In some embodiments, the ratio is not less than 5, 10, or 20. In some embodiments, the ratio is not less than 100. Other surface roughness ratios can be used.

[0038] As discussed, the hydrophobic structure 405 confines the liquid within the hybrid bonding region 303, while the modified layer 414 allows the liquid to spread out within the hybrid bonding region 303. Figure 4D In the embodiment of FIG. 4 , the hybrid bonding region 303 of the modified layer 414 is confined between the roughened surfaces 406 .

[0039] Figure 4E An IC structure 440 similar to IC structure 430 is shown after forming a hydrophobic structure 412 to provide confinement within hybrid bonding region 303. Hydrophobic structure 412 can be formed using any suitable technique or techniques, such as forming a conformal hydrophobic material layer on modified layer 414, then patterning the conformal hydrophobic material layer by patterning a resist layer on or over the hydrophobic material layer, etching exposed portions of the hydrophobic material layer, and removing the resist layer. Hydrophobic structure 412 can include any hydrophobic material discussed herein, such as a self-assembled monolayer material including an alkyl or fluoroalkyl silane, a thiol, a phosphonic acid, or an alkanoic acid, or a polymer film including a siloxane, a silazane, a polyolefin, or a fluorinated polymer. Other hydrophobic materials can be used. According to some embodiments of the present disclosure, structure 412 may include a material layer having an atomic composition of at least 10% carbon, a material layer having an atomic composition of at least 10% fluorine, a material layer having an atomic composition of at least 10% phosphorus, a material layer having an atomic composition of at least 10% sulfur, and / or a material layer having an atomic composition of at least 10% silicon.

[0040] The hydrophobic structure 412 together with the roughened surface 406 further helps to confine the liquid within the hybrid bonding area 303 while allowing the liquid to spread out. Figure 4E As shown, any of the previously discussed hydrophobic structures define a stop-in region or hydrophobic pattern 415 that completely or nearly completely surrounds each of the hybrid bonding regions 303 with the hydrophobic structure.

[0041] Figure 4F A top view of an IC structure 440 is shown, showing the hybrid bonding area 303 defined by the hydrophobic pattern 415. Figure 4F In the example of , the hydrophobic structure 412 and the hydrophobic structure 405 provide confinement within the hybrid bonding area 303 (only the hydrophobic structure 412 is visible in the top view). However, any of the hydrophobic structures 401, 402, 422, 405 can provide the same hydrophobic pattern 415. As shown, the hybrid bonding area 303 can have the same or different sizes, and the hybrid bonding area 303 defines a core particle or IC die layout on the substrate 201, which is located below the hydrophobic pattern 415 and the hybrid bonding area 303. In some embodiments, the IC die or core particle is first coarsely aligned with each hybrid bonding area 303. This coarse alignment can be performed by a pick and place device and can be within, for example, 25-50 μm. Then, a droplet (e.g., a water droplet) between each hybrid bonding area 303 and the corresponding IC die or core particle provides fine alignment of the IC die or core particle within each hybrid bonding area 303 (in a self-aligned manner) via capillary forces. Such fine alignment may be in the range of, for example, 200 nm or less.Alternatively, die may be cut from the substrate 201 based on the hydrophobic pattern 415 to provide IC dies or die for bonding to a base substrate.

[0042] Return to Figure 1 , process 100 continues at operation 102, where a first-level IC die or core particle is self-assembled onto a base wafer using droplets between bonding areas and within the hydrophobic confinement features prepared at operation 101. In some embodiments, the droplets are applied to the hydrophilic bonding areas on the base substrate. In some embodiments, the droplets are applied to the hydrophilic bonding areas of the IC die or core particle. In either case, the hydrophilic bonding areas of the IC die are placed on or over the hydrophilic bonding areas of the base substrate (using coarse alignment), and the interaction of the droplets, the hydrophilic bonding areas, and the hydrophobic confinement features causes the IC die to self-align with high precision.

[0043] Figure 5is an illustration of a cross-sectional side view of an IC structure 500 during self-aligned bonding. As shown, the IC structure 500 includes a hydrophilic structure 301 on or above a base substrate 501 and a hydrophobic structure 401 adjacent to the hydrophilic structure 301 and also on or above the base substrate 501. Although the description is directed to the hydrophilic structure 301 and the hydrophobic structure 401, any of the hydrophilic structures 301 and the hydrophobic structures discussed herein may be deployed on Figure 5-17 The hydrophobic structure 401 and the adjacent hydrophilic structure 301 may be formed on the substrate 501 using any suitable technique or techniques discussed above.

[0044] As shown, the base substrate 501 includes an active layer 502. The active layer 502 (or active surface) includes a device layer and / or an interconnect layer. For example, the device layer may include transistors, capacitors, or other IC devices. The interconnect layer may be above the device layer and may include a metallization level that interconnects the devices of the device layer and provides wiring to external devices. In some embodiments, the base substrate 501 includes active devices in the active layer 502 and wiring from the active layer 502 to the back surface 511 of the base substrate 501. In some embodiments, the base substrate 501 includes wiring from the active layer 502 to the back surface 511, and there are no active devices. The base substrate 501 may include any suitable material or materials, such as semiconductor materials, such as single crystal silicon (Si), germanium (Ge), silicon germanium (SiGe), III-V materials (e.g., gallium arsenide (GaAs)), silicon carbide (SiC), sapphire (Al2O3) or any combination thereof. As discussed, the base substrate, base wafer, or base die represents a substrate with active or passive electrical features. In some embodiments, a multi-level stack of IC dies is formed on top of a base substrate 501 using die-to-wafer bonding, and 3D die complexes are segmented from the base substrate 501 such that each 3D die complex includes a portion of the base substrate 501 and associated attached core particles on top of the segmented portion of the base substrate 501.

[0045] In addition, each of the IC die 521 includes a substrate 523, an active layer 522, and a through-hole 524 extending between the active layer 522 and the back surface 507 of each IC die 521. Similar to the active layer 502, the active layer 522 (or active surface) includes a device layer and / or an interconnect layer. For example, the device layer may include transistors, capacitors, or other IC devices. The interconnect layer may be above the device layer and may include a metallization level that interconnects the devices of the device layer and provides wiring to external devices. The substrate 523 may include any suitable material or materials, such as semiconductor materials, such as single crystal silicon (Si), germanium (Ge), silicon germanium (SiGe), III-V materials (e.g., gallium arsenide (GaAs)), silicon carbide (SiC), sapphire (Al2O3), or any combination thereof. The back surface 507 is opposite to the active layer 522 and may be characterized as a non-active surface.

[0046] On or above each IC die 521, as described above, a hydrophilic structure 517 (similar to hydrophilic structure 301) and a hydrophobic structure 515 (similar to hydrophobic structure 401) are formed to define a hybrid bonding region 527. For example, the hydrophilic structure 517 includes a metal bonding pad 514 and an inorganic dielectric material 513, which can have any of the properties discussed for the metal bonding pad 203 and the inorganic dielectric material 204. Similarly, the hydrophobic structure 515 can have any of the properties discussed for the hydrophobic structure 401, and although the hydrophobic structure 515 is shown as being similar to the hydrophobic structure 401, any hydrophobic structure discussed herein can be deployed. For example, the hydrophilic structure 517 and the hydrophobic structure 515 can be formed on a wafer including one or more IC dies 521 using the above-described techniques, and the IC dies 521 can be singulated (e.g., cut) from the wafer for pick-up and placement onto the hybrid bonding region 303. It is worth noting that the hydrophilic structure 517 and the hydrophobic structure 515 can be formed to form Figure 2 , Figure 3 and Figures 4A-4F The structures discussed are, but not limited to, these.

[0047] The combination of hydrophilic structure / hydrophobic structure on base substrate 501 and the combination of hydrophilic structure / hydrophobic structure on IC die 521 can be the same (as shown), or they can be different. Figure 4B The hydrophilic structure / hydrophobic structure shown may not be combined with other hydrophilic structures / hydrophobic structures (i.e., except Figure 4B Any hydrophilic structure / hydrophobic structure other than those of Figure 4BThe hybrid bonding area 303 , 527 surrounded by the hydrophobic structure will not come into contact if used on both the base substrate 501 and any IC die 521 .

[0048] As shown, a droplet 506 is placed on the hybrid bonding area 303 of the hydrophilic structure 301 (or on the bonding area 527 of the hydrophilic structure 517). The droplet 506 can be any suitable liquid, such as any suitable volume of water. The hybrid bonding area 303 and the hybrid bonding area 527 are brought together using, for example, pick and place of IC die 521. As shown, the droplet 506 spreads out on the hybrid bonding area 303 (or hybrid bonding area 527) and is confined by the hydrophobic structure 401 (or hydrophobic structure 515). The IC die 521 is advantageously and quickly coarsely aligned to the hybrid bonding area 303 and the droplet 506 (confined by the self-alignment assist features discussed herein) by pick and place 582, and each IC die 521 is quickly finely aligned to the corresponding bonding area 303.

[0049] IC die 521 may be fabricated and attached such that they are in a face-down configuration 531 or a face-up configuration 532. In the face-down configuration 531, active layer 502 and active layer 522 are adjacent to each other and are directly connected via hybrid bonding therebetween, as discussed further below. Advantageously, through vias 524 (which may be characterized as through-substrate vias or through-silicon vias, TSVs) have backside connections on or above backside surface 507 such that wiring from hybrid bonding and active layer 522 is provided to additional IC die in the stack (e.g., extending in the z dimension). In the face-up configuration 532, active layer 522 is opposite active layer 502 relative to substrate 523. In this case, through vias 524 also have backside connections on or above backside surface 507 such that wiring from hybrid bonding may be provided to active layer 522 and then to additional IC die in the stack (e.g., extending in the z dimension).

[0050] Return to Figure 1 , process 100 continues at operation 103, where the IC die or core is bonded to the base substrate or wafer by evaporating the droplet and annealing. For example, the droplet applied at operation 102 evaporates relatively quickly after alignment, and the inorganic material holds the IC die or core in place due to, for example, van der Waals forces. A subsequent annealing operation may be performed to bond the IC die or core to the bonding area of ​​the structural wafer by melting the metal bond pad and the inorganic material therebetween.

[0051] Figure 66 is an illustration of a cross-sectional side view of an IC structure 600 similar to IC structure 500 after droplet 506 evaporates and after bonding is performed to form a composite metal structure 601 and a composite dielectric portion 602 between each IC die 521 and base substrate 501. In addition, hydrophobic structures 401, 515 can be bonded to form a composite hydrophobic structure 603. In other cases, no bonding occurs between hydrophobic structures 401, 515. In some embodiments, hydrophobic structures 401, 515 can be partially or completely decomposed and volatilized during hybrid bonding annealing. As shown, IC structure 600 includes a base substrate 501, which is coupled to an active layer 522 or a back surface 507 of each IC die 521, depending on whether each IC die is in a face-down configuration 531 or a face-up configuration 532 during bonding.

[0052] As shown, the hybrid bonding discussed forms a composite metal structure 601 and a composite dielectric portion 602 on a bonding plane 643. Thus, hybrid bonds 621 between the IC die 521 and the base substrate 501 are formed. Each hybrid bond 621 includes a composite metal structure 601 and a composite dielectric portion 602. The composite dielectric portion 602 can be characterized as an inorganic material, an inorganic bonding layer, an inorganic bonding material, etc. As shown, each hybrid bond 621 is surrounded by a composite hydrophobic structure 603 or by a related hydrophobic structure deployed in forming the hybrid bond 621.

[0053] As shown in inset 612, in some embodiments, adjacent metal pads are annealed to form a composite metal structure 613 (one of composite metal structures 601) such that metal structure 613 has substantially aligned sidewalls 623. However, in other embodiments, adjacent metal pads 203, 514 have a misalignment 614 during annealing and composite metal structure 633 is formed such that metal structure 633 has substantially misaligned sidewalls, and thus metal structure 633 includes juts 624 and overhangs 625. For example, the sidewalls of metal structure 633 may have substantially vertical sidewall portions and substantially horizontal sidewall portions (e.g., at juts 624 and overhangs 625).

[0054] Similarly, as shown in inset 622, in some embodiments, adjacent hydrophobic structures 401, 515 form a composite hydrophobic structure 663 (e.g., any one of the composite hydrophobic structures 603) having substantially aligned sidewalls 673. However, in other embodiments, adjacent hydrophobic structures 401, 515 have a misalignment 664 during annealing and form a composite hydrophobic structure 683 (e.g., any one of the hydrophobic structures 603) having substantially misaligned sidewalls 674, and thus the hydrophobic structure 683 includes a protrusion or overhang 675. For example, the sidewalls of the hydrophobic structure 683 can have substantially vertical sidewall portions and substantially horizontal sidewall portions. In some embodiments, the composite hydrophobic structure 603 extends from the surface of the active layer 502 to the active layer 522 or the back surface 507 of the IC die 521.

[0055] As discussed, each hybrid bond 621 is surrounded (completely or mostly, i.e., >90%) by a hydrophobic structure 603. Figure 6 In the case of , the hydrophobic structure 603 is formed by the hydrophobic structures 401, 515, although the materials of the hydrophobic structures 401, 515 may not be combined or melted. Figure 6 As shown, the hydrophobic structure 603 extends around the perimeter P1 of the hybrid bond 621 (see Figure 4F ). As used herein, the term perimeter is used in its ordinary sense to refer to the outer boundary of the hydrophobic structure 603 in the xy plane. For perimeters that are not intercepted in the same plane, such perimeters are projected into the same plane to determine their size. In addition, the outer perimeter P2 of the hydrophobic structure 603 is completely within the outer perimeter P3 of the IC die 521. It should be noted that a single continuous hydrophobic structure 603 can surround the hybrid bond 621, or multiple discontinuous hydrophobic structures 603 can surround the hybrid bond 621.

[0056] Return to Figure 1 , process 100 continues at operation 104, where a gap-fill dielectric is formed between the first-level IC dies and planarized to provide a top surface for second-level IC die or die attachment in a multi-level 3D die stack. In some embodiments, the gap-fill dielectric is an inorganic dielectric material, such as silicon nitride, silicon oxynitride, silicon carbonitride, or silicon carbide. The gap-fill dielectric can be formed using any suitable technique or techniques, such as a deposition technique, and then planarized.

[0057] Figure 7701 is an illustration of a cross-sectional side view of an IC structure 700 similar to IC structure 600 after forming an inorganic dielectric 701 and a substantially flat surface 702. As shown, the inorganic dielectric 701 can be deposited as a fill material using any suitable technique or techniques (e.g., vapor deposition techniques). The fill material is then planarized using a chemical mechanical polishing technique to form a flat surface 702. The inorganic dielectric 701 can be any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbide, or a combination thereof (e.g., a layer of one of these materials covered by a second layer of another of these materials). Although inorganic dielectric materials may be advantageous, organic dielectrics may be used. As discussed below, the flat surface 702 provides a surface for IC dies or core particles of subsequent levels in a multi-level 3D die stack.

[0058] Return to Figure 1 , process 100 continues at operation 105, where a hybrid bonding region surrounded by a hydrophobic confinement feature is formed to prepare for a subsequent level of IC die or core in a multi-level 3D die stack. The hybrid bonding region and the hydrophobic confinement feature may be formed using any suitable technique or techniques, such as those described for operations 101 and Figure 2 , Figure 3 and Figures 4A-4F Those techniques discussed. In some embodiments, a bulk inorganic dielectric material is formed over a first-level IC die or core particle, and the inorganic dielectric material is then planarized. Metal bonding pads dispersed in the inorganic dielectric material may then be formed using any suitable technique or techniques (e.g., single or dual inlay techniques). Then, as discussed above, hydrophobic confinement features may be formed around the hybrid bonding region. Such a hybrid bonding region surrounded by hydrophobic confinement features is formed both over the base substrate (e.g., over an already attached first-level IC die or core particle) and over an IC die or core particle to be bonded thereto (e.g., over a second-level IC die or core particle to be attached).

[0059] Figure 8 An IC structure 800 similar to IC structure 700 is shown after forming a hydrophilic structure 801 surrounded by hydrophobic structures 805, each of which is used for self-aligned bonding to base substrate 501. Hydrophilic structure 801 can have any of the properties discussed for hydrophilic structure 301, and hydrophilic structure 801 includes metal bonding pads 803 interspersed in an inorganic dielectric material 804, which can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or silicon carbide. Hydrophobic structure 805 can have any of the properties discussed above, and hydrophobic structure 805 defines a hybrid bonding region 802.

[0060] Return to Figure 1 , process 100 continues at operation 106, where the second level IC die or core particles are self-assembled onto the base wafer using droplets between bonding regions and within the hydrophobic confinement features prepared at operation 103. The water droplets may be applied to the hydrophilic bonding regions of the base substrate or the attached IC die or core particles. As discussed, after coarse alignment, the interaction of the droplets, the hydrophilic bonding regions, and the hydrophobic confinement features allows the second level IC die to self-align with high precision.

[0061] Fig. 9 9 is an illustration of a cross-sectional side view of an IC structure 900 similar to IC structure 800 during self-aligned bonding. As discussed, IC structure 900 includes a hydrophilic structure 801 on a base substrate 501 and a hydrophobic structure 801 adjacent to and surrounding the hydrophilic structure 801. In addition, IC structure 900 includes a plurality of second-level IC dies 921, each of which includes a substrate 923, an active layer 922, and a through via 924 extending between the active layer 922 and its back surface 907. The active layer 922 can have any of the characteristics discussed for the active layer 522, and the substrate 923 can have any of the characteristics discussed for the substrate 523.

[0062] On or above each IC die 921, a hydrophilic structure 917 and a hydrophobic structure 915 are formed to define a hybrid bonding region 927. The hydrophilic structure 917 includes metal bonding pads 914 dispersed in an inorganic dielectric material 913, which may have any of the properties discussed for other hybrid bonding regions herein. Any suitable combination of hydrophilic structures / hydrophobic structures may be deployed in the IC structure 900. As shown, a droplet 906 is placed on the hybrid bonding region 802 of the hydrophilic structure 801 (or on the bonding region 927 of the hydrophilic structure 917), and the hybrid bonding region 802 and the hybrid bonding region 927 are placed together using, for example, pick and place 982 of the IC die 921. The droplet 906 spreads out on the hybrid bonding regions 802, 927 and is confined by the hydrophobic structures 805, 915. As discussed, the IC dies 921 are quickly coarse-aligned, and the droplets 906 are quickly fine-aligned to each IC die 921 .

[0063] The IC die 921 can be manufactured and attached so that they are in a face-down configuration 932 or a face-up configuration 931. In the face-down configuration 932, the active layer 522 and the active layer 922 can be adjacent to each other and can be directly connected by hybrid bonding between them. Alternatively, in the face-down configuration 932, the active layer 922 can be adjacent to the back side 507 of the IC die 521. Through vias 924 (e.g., through substrate vias or through silicon vias, TSVs) can have back-side connections on or above the back surface 907 so that wiring from the active layer 922 can be provided as needed. In the face-up configuration 931, the active layer 922 is opposite to the base substrate 501 relative to the substrate 923, and the active layer 522 can be adjacent to the IC die 921 or opposite to the IC die 921 relative to the substrate 523. That is, in the case of a multi-level IC stack, the first layer can be face-up or face-down, and the second layer can also be face-up or face-down, which provides four potential stacking configurations: L1 face-down / L2 face-down, L1 face-down / L2 face-up, L1 face-up / L2 face-down, or L1 face-up / L2 face-up. This arrangement increases with the number of levels of the multi-level IC stack.

[0064] Return to Figure 1 , process 100 continues at operation 107 where the IC die or core is bonded to the base substrate or wafer by evaporating the droplets and an optional annealing process. As discussed, the droplets applied at operation 106 can evaporate quickly and the inorganic material can hold the IC die or core in place. A subsequent anneal can then bond the IC die or core to the bonding area of ​​the structural wafer by melting the metal bond pads and the inorganic material therebetween.

[0065] Fig.101 is an illustration of a cross-sectional side view of IC structure 1000 similar to IC structure 900 after droplet 906 evaporates and after bonding is performed to form composite metal structures 1001 and composite dielectric portions 1002 between each IC die 921 and IC die 521. In addition, hydrophobic structures 805, 915 can be bonded to form composite hydrophobic structures 1003. However, in some cases, there is no obvious bonding between hydrophobic structures 805, 915. The hybrid bonding discussed forms composite metal structures 1001 and composite dielectric portions 1002 on bonding plane 1043. Thus, hybrid bonds 1021 between IC die 921 and IC die 521 are formed. Each hybrid bond 1021 includes composite metal structures 1001 interspersed in composite dielectric portions 1002, and each hybrid bond 1021 is surrounded by composite hydrophobic structures 1003 or by associated hydrophobic structures deployed when forming hybrid bonds 1021. Each of the composite metal structure 1001 and the composite hydrophobic structure 1003 may have a Figure 6 ) for any features discussed.

[0066] As discussed, each hybrid bond 1021 is (completely or mostly) surrounded by a hydrophobic structure 1003. For example, the hydrophobic structure 1003 may extend around the perimeter of the hybrid bond 1021, and the outer perimeter of the hydrophobic structure 1003 may be completely within the outer perimeter of the IC die 921 (see Figure 6 ). The hydrophobic structure 1003 may extend around the perimeter P1 of the hybrid bond 1021, and the outer perimeter P2 of the hydrophobic structure 1003 may be completely within the outer perimeter P3 of the IC die 921. It should be noted that a single continuous hydrophobic structure 1003 may surround the hybrid bond 1021, or a plurality of discontinuous hydrophobic structures 1003 may surround the hybrid bond 1021.

[0067] Return to Figure 1 As shown for process loop 112, the gap filling, hybrid bonding area preparation, self-assembly and die bonding discussed can be cycled any number of times to form a multi-level 3D die stack with any number of IC die or die levels on top of the base substrate wafer, such as a three-level 3D die stack, a four-level 3D die stack or more levels of 3D die stack.

[0068] Fig.11is an illustration of a cross-sectional side view of an IC structure 1100 similar to IC structure 1000 after forming an inorganic dielectric 1101 and a substantially planar surface 1102. For example, the inorganic dielectric 1101 can be deposited as a fill material using vapor deposition, and the fill can be planarized to form the planar surface 1102. The inorganic dielectric 1101 can be any suitable dielectric material discussed for the inorganic dielectric 701. The planar surface 1102 provides a surface for subsequent levels of IC dies or cores in a multi-level 3D die stack, as shown for an extended process option 1103, in which any number of additional levels of IC dies can be deployed.

[0069] Return to Figure 1 Once process loop 112 (if used) is completed, process 100 continues at operation 108 where a final gapfill dielectric is formed between the final level IC die and the gapfill dielectric is planarized to provide a top surface for mounting a support substrate. In some embodiments, the gapfill dielectric is an inorganic dielectric material such as silicon nitride, silicon oxynitride, silicon carbonitride, or silicon carbide. The gapfill dielectric may be formed using any suitable technique or techniques, such as a deposition technique followed by planarization. Reference Fig.11 , inorganic dielectric 1101 may be the final gap-fill dielectric, and surface 1102 may provide a surface for mounting a support substrate. Although two levels of IC die are shown, IC structure 1100 may include any number of IC die levels in a 3D die stack.

[0070] Return to Figure 1 , process 100 continues at operation 109, where the multi-level die stack can be attached to a structural substrate, such as a structural wafer. In some embodiments, the multi-level die stack is bonded to the structural substrate with wafer-to-wafer bonding using an adhesive, tape, dielectric bonding, etc. The structural substrate can be a structural wafer or panel, etc. without any active or passive electrical features. For example, the structural substrate can be a monolithic material, a crystalline material, or a composite material. In some embodiments, the structural substrate is single crystal silicon, such as a silicon wafer. In some embodiments, the structural substrate is or includes germanium, silicon germanium, silicon carbide, or sapphire.

[0071] Fig.121 is an illustration of a cross-sectional side view of an IC structure 1200 similar to IC structure 1100 after IC structure 1100 is bonded to a structural substrate 1201. Structural substrate 1201 may be bonded to IC structure 1100 using an adhesive, tape, or the like (not shown). Structural substrate 1201 may be a structural wafer or panel, and there may be no active or passive electrical features. In some embodiments, structural substrate 1201 is or includes single crystal silicon, germanium, silicon germanium, silicon carbide, or sapphire. In some embodiments, structural substrate 1201 provides structural support during further processing (e.g., cutting, packaging, assembly, etc.). For example, base substrate 501 may be thinned when IC structure 1100 is mounted to structural substrate 1201. After such processing and during deployment in an electronic device, structural substrate 1201 may provide a thermal conduction path while continuing to provide structural support.

[0072] As discussed, a 3D die complex or multi-level stack of IC dies may include any number of die levels. In some embodiments, a die is attached where the die has pre-formed hybrid bonding areas and restriction features on only one side of the die (see Figure 5 and Fig. 9 After attachment using hybrid bonding areas and confinement features, a fill dielectric is deposited and planarized (see Figure 7 and Fig.11 ). Then, the hybrid bonding area is made so that the attached die is in place (see Figure 8 ), and then attach the next level IC die. In other embodiments, the attached IC die may have pre-formed hybrid bonding areas and limiting features on both sides of the die.

[0073] Fig.13A is similar to IC structure 600 (see Figure 6 ) is an illustration of a cross-sectional side view of an IC structure 1300 in which an IC die 521 has a preformed hydrophilic structure 801 surrounded by a preformed hydrophobic structure 805. For example, the IC die 521 can have a hydrophilic structure 517 and a hydrophobic structure 515 formed on a first side thereof, as shown in FIG. Figure 2 , Figure 3 and Figures 4A-4F As discussed above, and the hydrophilic structure 801 and the hydrophobic structure 805 formed on the second side thereof using the same or similar techniques. During hybrid bonding, the first side is attached to the base substrate 501 (see Figure 5 and Figure 6 ), while the second side has exposed hydrophilic structure 801 and hydrophobic structure 805 for further bonding.

[0074] Fig. 13Bis an illustration of a cross-sectional side view of an IC structure 1350 similar to IC structure 1300 after bonding of additional two layers of IC dies 1321, 1331. As shown, IC die 1321 has pre-formed hydrophilic structures and hydrophobic structures on both sides thereof, such that hybrid bonded IC die 1321 forms a composite metal structure 1301, a composite dielectric portion 1302, and in some embodiments, a composite hydrophobic structure 1303, as discussed herein. In some embodiments, composite metal structure 1301 and composite dielectric portion 1302 are part of hybrid bonding 1304. For example, composite metal structure 1301, composite dielectric portion 1302, and optional composite hydrophobic structure 1303 can have any of the properties discussed for composite metal structure 1001, composite dielectric portion 1002, and in some embodiments, composite hydrophobic structure 1003.

[0075] Furthermore, in the example shown, IC die 1331 has pre-formed hydrophilic and hydrophobic structures on only one side thereof (e.g., the bonding side) such that hybrid bonded IC die 1331 forms composite metal structure 1311, composite dielectric portion 1312, and in some embodiments, composite hydrophobic structure 1313. In some embodiments, composite metal structure 1311 and composite dielectric portion 1312 are part of hybrid bonding 1314. Composite metal structure 1311, composite dielectric portion 1312, and optional composite hydrophobic structure 1313 may also have any of the properties discussed with respect to composite metal structure 1001, composite dielectric portion 1002, and in some embodiments, composite hydrophobic structure 1003. It should be noted that the hybrid bonded IC die 1331 forms composite metal structure 1311, composite dielectric portion 1312, and in some embodiments, composite hydrophobic structure 1003. Fig.13A and Fig. 13B The manufacturing steps discussed eliminate the need for dielectric fill, planarization, and hybrid bonding area / limit feature fabrication after each die attach. For example, dielectric fill and planarization can be performed in a single pass after all IC dies are attached.

[0076] Fig.14 is an illustration of a cross-sectional side view of an IC structure 1400 similar to IC structure 1350 after forming an inorganic dielectric 1401 and a substantially planar surface 1402. For example, the inorganic dielectric 1401 can be deposited as a fill material using vapor deposition, and the fill can be planarized to form the planar surface 1402. The inorganic dielectric 1401 can be any suitable dielectric material discussed for the inorganic dielectric 701. For example, the planar surface 1402 provides a surface for attaching a support substrate.

[0077] Fig.15is an illustration of a cross-sectional side view of an IC structure 1500 similar to IC structure 1400 after IC structure 1400 is bonded to a structural substrate 1201. Structural substrate 1201 may be bonded to IC structure 1400 using an adhesive, tape, or the like (not shown), and structural substrate 1201 may be a structural wafer or panel and may be devoid of any active or passive electrical features as discussed above.

[0078] In the case of IC structure 1200 and IC structure 1500, IC die 921, IC die 1321 and IC die 1331 are self-aligned and bonded to the lower core grain or IC die of the same size in the previous level. However, the multi-level self-alignment technology can be extended to align and bond the core grain or IC die on the higher level that is different in size from the core grain or IC die on the lower level. The higher-level IC die can be completely within the occupied area of ​​the lower-level IC die, or at each level, the higher-level IC die can have an offset edge relative to the lower-level IC die. This overlap requires that the limiting features on some levels are not at the edge of the IC die or not between the IC dies. In addition, the IC die on one level can be aligned and bonded to the through-vias in the multiple IC dies and / or dielectric fillers on another level in any combination.

[0079] Fig.16 1 is an illustration of a cross-sectional side view of an IC structure 1600 having second level IC dies 1620, 1621 that do not match the size of the underlying IC die 521. As shown, the IC die 1621 may be within the outer perimeter P3 of one of the IC dies 521. Additionally, the corresponding hybrid bond 1021 (including the composite metal structure 1001 and the composite dielectric portion 1002) and the hydrophobic structure 1003 are also within the outer perimeter P3 of one of the IC dies 521.

[0080] In contrast, the outer edge of IC die 1620 extends beyond the outer perimeter of another of the underlying IC dies 521. As shown, hybrid bond 1622 corresponding to IC die 1620 includes composite metal structure 1601 within perimeter P3 of one of IC die 521 and composite metal structure 1611 outside any perimeter P3 of any IC die 521. Similarly, composite dielectric portion 1602 includes a portion (or sub-portion) within perimeter P3 of one of IC die 521 and a portion (or sub-portion) outside any perimeter P3 of any IC die 521. That is, hybrid bond 1622 extends beyond the exterior of a single underlying IC die 521. Also as shown, hydrophobic structure 1603 surrounding hybrid bond 1622 may be partially within perimeter P3 of underlying IC die 521 and / or outside any perimeter of underlying IC die 521.

[0081] Notably, IC structure 1600 includes through vias 1623 (which may be characterized as vias or through-component vias) that extend from active layer 502, through inorganic dielectric 701, and contact one or more of composite metal structures 1611. In some embodiments, as shown, through via 1623 extends through inorganic dielectric 701 and adjacent IC die 521 to bypass a single-level or single-layer IC die 521. In other embodiments, through via 1623 may bypass two or more levels or layers of IC dies. Through via 1623 may be formed using any suitable technique or techniques, such as patterning and etching techniques to form holes or openings and metal filling and planarization techniques to form through via 1623. Through via 1623 may be any suitable conductive material, such as a metal, including copper. As described with respect to Fig.16 As shown, the techniques discussed herein provide a flexible, high-throughput assembly technique to form an IC structure 1600 having a range of architectures.

[0082] Return to Figure 1 , process 100 continues at operation 110, where the integrated circuit structure is singulated (or cut) from the wafer-to-wafer bonded stack. For example, IC structure 1200, IC structure 1500, or any other IC structure discussed herein can be singulated from the wafer using known cutting techniques. Process 100 continues at operation 111, where the resulting device (e.g., IC structure) can be packaged, assembled, and implemented in any suitable form factor device, such as a laptop, netbook, notebook, ultrabook, smart phone, tablet computer, personal digital assistant, ultra mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, digital video recorder, etc.

[0083] Fig.17 An example microelectronic device assembly 1700 including a multi-level 3D die stack having multiple levels bonded by hybrid bonding regions within confined features is shown in accordance with some embodiments. As shown, the IC structure 1200 can be incorporated into the microelectronic device assembly 1700. Although the embodiment of the present invention is directed to FIG. Figure 4A1700 is described above, but the IC structure 1200 and, thus, the microelectronic device assembly 1700 may include any hydrophobic structure discussed herein. In addition, the microelectronic device assembly 1700 may deploy any IC structure discussed herein, such as the IC structure 1500 or the IC structure 1600. The microelectronic device assembly 1700 may include any number of IC structures 1200 mounted to a substrate 1711 via an interconnect 1709, the interconnect 1709 being optionally embedded in a molding material or an underfill material 1712. The substrate 1711 may be a packaging substrate, an interposer, or a board (such as a motherboard). Any number of IC structures 1200 having the same or different hydrophobic structures may be attached to the substrate 1711.

[0084] The microelectronic device assembly 1700 also includes a power supply 1756 coupled to one or more of the substrate 1711 (i.e., board, package substrate, or interposer), the IC die 521, 921, and / or other components of the microelectronic device assembly 1700. The power supply 1756 may include a battery, a voltage converter, a power supply circuit, etc. The microelectronic device assembly 1700 also includes a thermal interface material (TIM) 1701 disposed on a top surface of the structural substrate 1201. The TIM 1701 may include any suitable thermal interface material and may be characterized as TIM 1. An integrated heat sink 1702 having a surface on the TIM 1701 extends over the IC structure 1200 and is mounted to the substrate 1711. The microelectronic device assembly 1700 also includes a TIM 1703 disposed on a top surface of the integrated heat sink 1702. The TIM 1703 may include any suitable thermal interface material and may be characterized as TIM 2. The TIM 1701 and the TIM 1703 may be the same material, or they may be different. Heat sink 1704 (e.g., an exemplary heat sink device or thermal solution) is on TIM 1703 and dissipates heat. Microelectronic device assembly 1700 can be used in desktop and server form factors. In other cases, thermal solutions such as heat pipes or heat sinks can be mounted directly on TIM 1701. Such an assembly can be used in smaller form factor devices. Other heat sink devices can be used.

[0085] Fig.18An exemplary system 1800 for deploying a multi-level 3D die stack according to some embodiments is shown, the multi-level 3D die stack having multiple levels bonded by hybrid bonding areas within a restricted feature. For example, the system can be a mobile computing platform 1805 and / or a data server machine 1806. Any one can employ a component assembly including an IC structure as described herein. The server machine 1806 can be any commercial server, for example, including any number of high-performance computing platforms arranged in a rack and networked together for electronic data processing, which in an exemplary embodiment includes an integrated circuit (IC) die assembly 1850, the IC die assembly 1850 having a multi-level 3D die stack having multiple levels bonded by hybrid bonding areas within a restricted feature as described elsewhere herein. The mobile computing platform 1805 can be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, etc. For example, the mobile computing platform 1805 may be any of a tablet computer, a smart phone, a laptop computer, etc., and may include a display screen (e.g., a capacitive, inductive, resistive, or optical touch screen), a chip-level or package-level integrated system 1810, and a battery 1815. Although described with respect to the mobile computing platform 1805, in other examples, the chip-level or package-level integrated system 1810 and the battery 1815 may be implemented in a desktop computing platform, an automotive computing platform, an Internet of Things platform, etc. As discussed below, in some examples, the disclosed system may include a subsystem 1860, such as a system on a chip (SOC) or an integrated system of multiple ICs, which is described with respect to the mobile computing platform 1805.

[0086] Whether disposed within the integrated system 1810 shown in the expanded view 1820 or disposed as a stand-alone packaged device within the data server machine 1806, the subsystem 1860 may include a memory circuit and / or a processor circuit 1850 (e.g., a RAM, a microprocessor, a multi-core microprocessor, a graphics processor, etc.), a power management integrated circuit (PMIC) 1830, a controller 1835, and a radio frequency integrated circuit (RFIC) 1825 (e.g., including a broadband RF transmitter and / or receiver (TX / RX)). As shown, an IC die (such as a memory circuit and / or a processor circuit 1850) may be packaged, assembled, and implemented such that the package has one or more levels of a 3D die stack having multiple levels bonded by hybrid bonding regions within a confining feature as described herein. In some embodiments, the RFIC 1825 includes a digital baseband and an analog front end module, which also includes a power amplifier on a transmit path and a low noise amplifier on a receive path. Functionally, PMIC 1830 may perform battery power regulation, DC to DC conversion, etc., and thus has an input coupled to battery 1815 and an output that provides current supply to other functional modules. Fig.18 As further shown in the figure, in an exemplary embodiment, the RFIC 1825 has an output coupled to an antenna (not shown) to implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols named 3G, 4G, 5G and above. The memory circuit and / or processor circuit 1850 can provide memory functions, high-level control, data processing, etc. for the subsystem 1860. In alternative embodiments, each of the SoC modules can be integrated into a separate IC coupled to a package substrate, interposer or board.

[0087] Fig.19is a functional block diagram of an electronic computing device 1900 according to some embodiments. For example, the device 1900 may employ a multi-level 3D die stack having multiple levels bonded by hybrid bonding regions within the limiting features according to any embodiment described elsewhere herein via any suitable component therein. The device 1900 also includes a motherboard or packaging substrate 1902 housing multiple components such as, but not limited to, a processor 1901 (e.g., an application processor). The processor 1901 may be physically and / or electrically coupled to the packaging substrate 1902. In some examples, the processor 1901 is within a packaged IC assembly that includes a multi-level 3D die stack having multiple levels bonded by hybrid bonding regions within the limiting features as described elsewhere herein. In general, the term "processor" or "microprocessor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that may be further stored in registers and / or memory.

[0088] In various examples, one or more communication chips 1904, 1905 may also be physically and / or electrically coupled to the packaging substrate 1902. In further embodiments, the communication chips 1904, 1905 may be part of the processor 1901. Depending on its application, the computing device 1900 may include other components that may or may not be physically and electrically coupled to the packaging substrate 1902. These other components include, but are not limited to, volatile memory (e.g., DRAM 1907, 1908), non-volatile memory (e.g., ROM 1910), flash memory (e.g., NAND or NOR), magnetic memory (MRAM), a graphics processor 1912, a digital signal processor, a cryptographic processor, a chipset 1906, an antenna 1916, a touch screen display 1917, a touch screen controller 1911, a battery 1918, a power supply 1919, an audio codec, a video codec, a power amplifier 1909, a global positioning system (GPS) device 1913, a compass 1914, an accelerometer, a gyroscope, a speaker 1915, a camera 1903, and a mass storage device (e.g., a hard disk drive, a solid-state drive (SSD), a compact disk (CD), a digital versatile disk (DVD)), etc.

[0089] The communication chips 1904, 1905 can implement wireless communication for transmitting data to and from the computing device 1900. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, technologies, communication channels, etc. that can transmit data by using modulated electromagnetic radiation passing through a non-solid medium. The term does not imply that the associated device does not contain any wires, although in some embodiments they may not contain any wires. The communication chips 1904, 1905 can implement any of a variety of wireless standards or protocols, including but not limited to those described in other parts of this document. As discussed, the computing device 1900 may include multiple communication chips 1904, 1905. For example, a first communication chip can be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and a second communication chip can be dedicated to longer-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0090] Although certain features set forth herein have been described with reference to various embodiments, this description is not intended to be interpreted in a limiting sense. Therefore, various modifications of the embodiments described herein and other embodiments that are obvious to those skilled in the art to which the present disclosure belongs are deemed to fall within the spirit and scope of the present disclosure.

[0091] It will be appreciated that the invention is not limited to the embodiments thus described but may be practiced with modification and alteration without departing from the scope of the appended claims.For example, the embodiments described above may include specific feature combinations as further provided below.

[0092] The following relates to exemplary embodiments.

[0093] In one or more first embodiments, a device includes: a first substrate, the first substrate including a first interconnect layer; a first integrated circuit (IC) die, the first integrated circuit (IC) die including a second interconnect layer and a back surface opposite to the second interconnect layer, wherein the second interconnect layer or the back surface of the first IC die is coupled to the first interconnect layer of the first substrate via a first composite metal structure therebetween, and wherein the first composite metal structure is surrounded by one or more first hydrophobic structures; and a second IC die, the second IC die is coupled to the other of the second interconnect layer or the back surface of the first IC die via a second composite metal structure therebetween, wherein the second composite metal structure is surrounded by one or more second hydrophobic structures.

[0094] In one or more second embodiments further directed to the first embodiment, the first composite metal structure is dispersed in a first inorganic dielectric material, and the second composite metal structure is dispersed in a second inorganic dielectric material.

[0095] In one or more third embodiments further to the first or second embodiment, an outer perimeter of the second inorganic dielectric material is surrounded by the one or more second hydrophobic structures, and wherein an outer perimeter of the second hydrophobic structures is completely within an outer perimeter of the second IC die.

[0096] In one or more fourth embodiments further directed to the first to third embodiments, the device also includes a third IC die, the third IC die including a third interconnect layer and a back surface opposite to the third interconnect layer, wherein the third interconnect layer of the third IC die is coupled to the first interconnect layer of the first substrate via a third composite metal structure therebetween, wherein the third composite metal structure is surrounded by one or more third hydrophobic structures, and wherein the back surface of the first IC die is coupled to the first interconnect layer of the first substrate via the first composite metal structure.

[0097] In one or more fifth embodiments further directed to the first to fourth embodiments, the device further comprises a third IC die coupled to the second IC die via a third composite metal structure therebetween, wherein the third composite metal structure is surrounded by one or more third hydrophobic structures.

[0098] In one or more sixth embodiments further directed to the first to fifth embodiments, the device also includes: a dielectric material, which is laterally adjacent to the first IC tube core; and a via, which contacts the first interconnect layer of the first substrate and contacts a third composite metal structure, which is laterally adjacent to the second composite metal structure and outside the perimeter of the first IC.

[0099] In one or more seventh embodiments further directed to the first to sixth embodiments, the device also includes a third IC die, the third IC die is coupled to the first interconnect layer of the first substrate via a third composite metal structure therebetween, wherein the third composite metal structure is surrounded by one or more third hydrophobic structures, wherein the second IC die is coupled to the third IC die via a fourth composite metal structure therebetween, and wherein the fourth composite metal structure is surrounded by one or more second hydrophobic structures.

[0100] In one or more eighth embodiments further directed to the first to seventh embodiments, the apparatus further includes a second substrate over the second IC die, wherein the second substrate includes a monolithic material.

[0101] In one or more ninth embodiments further directed to the first to eighth embodiments, the first hydrophobic structure or the second hydrophobic structure comprises a hydrophobic material, and the hydrophobic material comprises one of a self-assembled monolayer material or a polymer film.

[0102] In one or more tenth embodiments further directed to the first to ninth embodiments, the first hydrophobic structure or the second hydrophobic structure comprises a roughened surface of an inorganic layer or grooves in an inorganic layer.

[0103] In an eleventh embodiment further directed to one or more of the first to tenth embodiments, the apparatus further includes a power source coupled to the first substrate, the first IC die, or the second IC die.

[0104] In one or more twelfth embodiments, a device includes: a first substrate, the first substrate including a first interconnect layer; a first integrated circuit (IC) die, the first IC die including a second interconnect layer and a back surface opposite to the second interconnect layer, wherein the second interconnect layer or the back surface of the first IC die is coupled to the first interconnect layer of the first substrate via a first composite metal structure therebetween, wherein the first composite metal structure is surrounded by one or more first structures, and wherein the one or more first structures include a first material layer having an atomic composition of at least ten percent carbon or at least ten percent fluorine; a second IC die, the second IC die is coupled to the second interconnect layer or the other of the back surface of the first IC die via a second composite metal structure therebetween, wherein the second composite metal structure is surrounded by one or more second structures, and wherein the one or more second structures include a second material layer having an atomic composition of at least ten percent carbon or at least ten percent fluorine.

[0105] In one or more thirteenth embodiments further directed to the twelfth embodiment, the device also includes a third IC die, the third IC die including a third interconnect layer and a back surface opposite to the third interconnect layer, wherein the third interconnect layer of the third IC die is coupled to the first interconnect layer of the first substrate via a third composite metal structure therebetween, wherein the third composite metal structure is surrounded by one or more third structures, wherein the one or more third structures include a third material layer having an atomic composition of at least ten percent carbon or at least ten percent fluorine, and wherein the back surface of the first IC die is coupled to the first interconnect layer of the first substrate via the first composite metal structure.

[0106] In one or more fourteenth embodiments further directed to the twelfth or thirteenth embodiments, the device also includes a third IC die, which is coupled to the second IC die via a third composite metal structure therebetween, wherein the third composite metal structure is surrounded by one or more third structures, and the one or more third structures include a third material layer having an atomic composition of at least ten percent carbon or at least ten percent fluorine.

[0107] In further one or more of the twelfth to fourteenth embodiments, the device also includes: a dielectric material, which is laterally adjacent to the first IC tube core; and a via, which contacts the first interconnect layer of the first substrate and contacts a third composite metal structure, which is laterally adjacent to the second composite metal structure and outside the perimeter of the first IC tube core.

[0108] In one or more sixteenth embodiments further directed to the twelfth to fifteenth embodiments, further directed to the first to tenth embodiments, the apparatus further includes a power source coupled to the first substrate, the first IC die, or the second IC die.

[0109] In one or more seventeenth embodiments, a method includes: evaporating a first droplet between a first bonding area of ​​a base substrate and a second bonding area of ​​a first integrated circuit (IC) die to bond the first bonding area and the second bonding area, the first bonding area being surrounded by a first hydrophobic structure, and the second bonding area being surrounded by a second hydrophobic structure; forming a third bonding area above the first IC die; forming a third hydrophobic structure surrounding the third bonding area; and evaporating a second droplet between the third bonding area and a fourth bonding area of ​​a second IC die to bond the third bonding area and the fourth bonding area, the fourth bonding area being surrounded by a fourth hydrophobic structure.

[0110] In one or more eighteenth embodiments further directed to the seventeenth embodiment, forming the third bonding region includes forming an inorganic dielectric material over the bonded first IC die, and forming a first metal pad within the inorganic dielectric material.

[0111] In one or more nineteenth embodiments further directed to the seventeenth or eighteenth embodiments, the bonding between the first bonding area and the second bonding area and the bonding between the third area and the fourth area include die-to-wafer bonding of the first IC die and the second IC die, and the method also includes cutting a multi-level IC structure from a base substrate.

[0112] In one or more twentieth embodiments further relating to the seventeenth to nineteenth embodiments, the first hydrophobic structure comprises a hydrophobic material comprising a self-assembled monolayer material or a polymer film, or the first hydrophobic structure comprises a roughened surface of an inorganic layer or grooves in an inorganic layer.

[0113] It should be appreciated that the present invention is not limited to the embodiments described above, but can be practiced in a modified and altered manner without departing from the scope of the appended claims. For example, the above-described embodiments may include a specific combination of features. However, the above-described embodiments are not limited in this regard, and in various embodiments, the above-described embodiments may include only a subset of these features, a different order of these features, a different combination of these features, and / or additional features other than those features explicitly listed. Therefore, the scope of the present invention should be determined with reference to the appended claims and the full scope of equivalents granted by these claims.

Claims

1. A device comprising: a first substrate, the first substrate comprising a first interconnect layer; a first integrated circuit (IC) die, the first integrated circuit (IC) die comprising a second interconnect layer and a back surface opposite the second interconnect layer, wherein the second interconnect layer or the back surface of the first IC die is coupled to the first interconnect layer of the first substrate via a first composite metal structure therebetween, and wherein the first composite metal structure is surrounded by one or more first hydrophobic structures; and A second IC die is coupled to the other of the second interconnect layer or the back surface of the first IC die via a second composite metal structure therebetween, wherein the second composite metal structure is surrounded by one or more second hydrophobic structures.

2. The device according to claim 1, wherein: The first composite metal structure is dispersed in a first inorganic dielectric material, and the second composite metal structure is dispersed in a second inorganic dielectric material.

3. The device according to claim 2, wherein: An outer perimeter of the second inorganic dielectric material is surrounded by the one or more second hydrophobic structures, and wherein an outer perimeter of the second hydrophobic structures is completely within an outer perimeter of the second IC die.

4. The device according to any one of claims 1 to 3, further comprising: A third IC die, the third IC die comprising a third interconnect layer and a back surface opposite to the third interconnect layer, wherein the third interconnect layer of the third IC die is coupled to the first interconnect layer of the first substrate via a third composite metal structure therebetween, wherein the third composite metal structure is surrounded by one or more third hydrophobic structures, and wherein the back surface of the first IC die is coupled to the first interconnect layer of the first substrate via the first composite metal structure.

5. The device according to any one of claims 1 to 3, further comprising: A third IC die is coupled to the second IC die via a third composite metal structure therebetween, wherein the third composite metal structure is surrounded by one or more third hydrophobic structures.

6. The device according to any one of claims 1 to 3, further comprising: a dielectric material laterally adjacent to the first IC die; as well as A via contacts the first interconnect layer of the first substrate and contacts a third composite metal structure laterally adjacent to the second composite metal structure and outside a perimeter of the first IC.

7. The device according to any one of claims 1 to 3, further comprising: a third IC die, wherein the third IC die is coupled to the first interconnect layer of the first substrate via a third composite metal structure therebetween, wherein the third composite metal structure is surrounded by one or more third hydrophobic structures, wherein the second IC die is coupled to the third IC die via a fourth composite metal structure therebetween, and wherein the fourth composite metal structure is surrounded by one or more second hydrophobic structures.

8. The device according to any one of claims 1 to 3, further comprising: A second substrate is over the second IC die, wherein the second substrate comprises a monolithic material.

9. The device according to any one of claims 1 to 3, wherein: The first hydrophobic structure or the second hydrophobic structure includes a hydrophobic material, and the hydrophobic material includes one of a self-assembled monolayer material and a polymer film.

10. The device according to any one of claims 1 to 3, wherein: The first hydrophobic structure or the second hydrophobic structure includes a roughened surface of an inorganic layer or grooves in the inorganic layer.

11. The apparatus of any one of claims 1 to 3, further comprising a power source coupled to the first substrate, the first IC die, or the second IC die.

12. An apparatus comprising: a first substrate, the first substrate comprising a first interconnect layer; a first integrated circuit (IC) die, the first integrated circuit (IC) die comprising a second interconnect layer and a back surface opposite the second interconnect layer, wherein the second interconnect layer or the back surface of the first IC die is coupled to the first interconnect layer of the first substrate via a first composite metal structure therebetween, wherein the first composite metal structure is surrounded by one or more first structures, and wherein the one or more first structures comprise a first material layer having an atomic composition of at least ten percent carbon or at least ten percent fluorine; and a second IC die coupled to the other of the second interconnect layer or the back surface of the first IC die via a second composite metal structure therebetween, wherein the second composite metal structure is surrounded by one or more second structures, wherein the one or more second structures include a second material layer having an atomic composition of at least ten percent carbon or at least ten percent fluorine.

13. The apparatus according to claim 12, further comprising: A third IC die, the third IC die comprising a third interconnect layer and a back surface opposite to the third interconnect layer, wherein the third interconnect layer of the third IC die is coupled to the first interconnect layer of the first substrate via a third composite metal structure therebetween, wherein the third composite metal structure is surrounded by one or more third structures, wherein the one or more third structures comprise a third material layer having an atomic composition of at least ten percent carbon or at least ten percent fluorine, and wherein the back surface of the first IC die is coupled to the first interconnect layer of the first substrate via the first composite metal structure.

14. The apparatus according to claim 12, further comprising: A third IC die, the third IC die is coupled to the second IC die via a third composite metal structure therebetween, wherein the third composite metal structure is surrounded by one or more third structures, and the one or more third structures include a third material layer having an atomic composition of at least ten percent carbon or at least ten percent fluorine.

15. The apparatus according to claim 12, further comprising: A third IC die, the third IC die is coupled to the first interconnect layer of the first substrate via a third composite metal structure therebetween, wherein the third composite metal structure is surrounded by one or more third structures, wherein the one or more third structures include a third material layer having an atomic composition of at least ten percent carbon or at least ten percent fluorine, wherein the second IC die is coupled to the third IC die via a fourth composite metal structure therebetween, wherein the fourth composite metal structure is surrounded by one or more fourth structures, and wherein the one or more fourth structures include a fourth material layer having an atomic composition of at least ten percent carbon or at least ten percent fluorine.

16. The device according to any one of claims 12 to 15, further comprising: a dielectric material laterally adjacent to the first IC die; as well as A via contacts the first interconnect layer of the first substrate and contacts a third composite metal structure laterally adjacent to the second composite metal structure and outside a perimeter of the first IC die.

17. The device according to any one of claims 12 to 15, further comprising: A second substrate is over the second IC die, wherein the second substrate comprises a monolithic material.

18. The apparatus of any one of claims 12 to 15, further comprising a power source coupled to the first substrate, the first IC die, or the second IC die.

19. A method comprising: evaporating a first droplet between a first bonding region of a base substrate and a second bonding region of a first integrated circuit (IC) die to bond the first bonding region and the second bonding region, the first bonding region being surrounded by a first hydrophobic structure and the second bonding region being surrounded by a second hydrophobic structure; forming a third bonding area over the first IC die; forming a third hydrophobic structure surrounding the third bonding region; and A second liquid droplet is evaporated between the third bonding region and a fourth bonding region of a second IC die to bond the third bonding region to the fourth bonding region, the fourth bonding region being surrounded by a fourth hydrophobic structure.

20. The method according to claim 19, wherein: Forming the third bonding region includes forming an inorganic dielectric material over the bonded first IC die and forming a first metal pad within the inorganic dielectric material.

21. The method according to claim 19, wherein: The bonding between the first bonding region and the second bonding region and the bonding between the third bonding region and the fourth bonding region include die-to-wafer bonding of the first IC die and the second IC die, and the method further includes cutting a multi-level IC structure from the base substrate.

22. The method according to any one of claims 19 to 21, wherein: The first hydrophobic structure includes a hydrophobic material, and the hydrophobic material includes one of a self-assembled monolayer material or a polymer film.

23. The method according to any one of claims 19 to 21, wherein: The first hydrophobic structure includes a roughened surface of an inorganic layer or grooves in the inorganic layer.

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