A board level package structure and package system
By employing a large-area square panel and conductive pillars in the board-level packaging structure, combined with bridging chips and modular structures, high-density interconnection and vertical power supply are achieved, solving the performance limitations of SoW systems and improving chip capacity and system performance.
Patent Information
- Application Number
- CN202411896161.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-20
- Publication Date
- 2025-12-12
- Estimated Expiration
- 2044-12-20
AI Technical Summary
The overall performance of a single SoW system is limited by wafer size, and existing technologies cannot effectively improve chip capacity and system performance.
It adopts a large square panel with multiple conductive pillars and grooves that run through its thickness. Combined with bridging chips, chip computing modules, power management modules and connection modules, it achieves high-density interconnection and vertical power supply, reducing the package height.
It significantly improves chip capacity, area utilization, and I/O density, solves the problem of limited performance of a single SoW system, and achieves high computing power integration and system performance improvement.
Smart Images
Figure CN119725318B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The embodiment of the present disclosure belongs to the technical field of semiconductor packaging, and particularly relates to a board-level packaging structure and a packaging system. BACKGROUND
[0002] SoW (System on wafer) is to integrate a certain number of computing chips onto a whole wafer as a whole to form a HPC (High Performance Computing) chip system.
[0003] SoW is to reconfigure computing chips into a wafer by using FO technology with a glass carrier as a carrier, to complete interconnection between chips through plastic packaging and re-wiring, to peel off the carrier, and to form the whole SoW system by interconnecting power devices with computing chips in a flip-chip manner on the reconfigured wafer.
[0004] Due to the limitation of wafer size, the overall performance of a single SoW system is limited.
[0005] In view of the above problems, it is necessary to provide a board-level packaging structure and a packaging system which are reasonable in design and effective in solving the above problems. SUMMARY
[0006] The embodiment of the present disclosure aims to at least solve one of the technical problems existing in the prior art, and provides a board-level packaging structure and a packaging system.
[0007] The embodiment of the present disclosure provides a board-level packaging structure, comprising:
[0008] a square panel, a first surface of the square panel being provided with a plurality of recesses, and the square panel being provided with a plurality of conductive columns penetrating through the thickness thereof;
[0009] a plurality of bridge chips, a non-functional surface of the bridge chip being arranged in the corresponding recess;
[0010] a chip operation module and a first connection module, arranged on the first surface of the square panel and electrically connected with the bridge chip and the conductive column respectively;
[0011] a power management module and a second connection module, arranged on the second surface of the square panel and electrically connected with the conductive column.
[0012] Optionally, the chip operation module comprises a first re-wiring layer and a chip operation layer.
[0013] The first re-wiring layer is arranged on the first surface of the square panel and the functional surface of the bridge chip, and is electrically connected with the bridge chip and the conductive column respectively.
[0014] The chip operation layer is arranged on the first redistribution layer and is electrically connected with the first redistribution layer.
[0015] Optionally, the bridge chip has a gap with the sidewall of the groove; the first redistribution layer comprises a first dielectric layer and a first metal layer; wherein,
[0016] The first dielectric layer is arranged on the gap, the first surface of the square panel and the functional surface of the bridge chip.
[0017] The first dielectric layer arranged on the first surface of the square panel and the functional surface of the bridge chip is provided with an opening, and the first metal layer electrically connected with the bridge chip and the conductive column is arranged in the opening.
[0018] Optionally, the chip operation layer comprises a plurality of computing chips, or the chip operation layer comprises a plurality of computing chips and a plurality of storage chips.
[0019] Optionally, the first connection module comprises a plurality of first connectors arranged on the first redistribution layer and a first cable arranged on the first connector.
[0020] Optionally, the first connection module further comprises a plurality of photoelectric conversion chips arranged on the first redistribution layer and an optical fiber arranged on the photoelectric conversion chip.
[0021] Optionally, the power management module comprises a second redistribution layer and a power management chip;
[0022] The second redistribution layer is arranged on the second surface of the square panel and is electrically connected with the conductive column;
[0023] The power management chip and the second connection module are arranged on the second redistribution layer and are electrically connected with the second redistribution layer.
[0024] Optionally, the second connection module comprises a plurality of second connectors arranged on the second redistribution layer and a second cable arranged on the second connector.
[0025] Optionally, the square panel adopts a glass panel.
[0026] Another aspect of the embodiment of the present disclosure provides a board-level packaging system comprising at least one board-level packaging structure described above; wherein,
[0027] When the board-level packaging system comprises a plurality of board-level packaging structures, the plurality of board-level packaging structures are electrically connected through the first connection module and the second connection module respectively.
[0028] The board-level packaging structure and the packaging system of the embodiment of the present disclosure, the board-level packaging structure adopts a large-area square panel, significantly improves the chip capacity, area utilization rate and I / O density, significantly improves the system performance, thereby solving the problem of limited performance of a single SoW system, and realizing high-computing power integration; the chip computing module realizes high-density interconnection with the aid of multiple bridge chips, and no longer needs to rely on constructing a fine line structure in the RDL; the square panel is provided with multiple conductive columns penetrating through the thickness thereof, the first surface of the square panel is provided with the chip computing module and the first connecting module, the second surface of the square panel is provided with the power management module and the second connecting module, the back surface of the square panel is vertically powered through the conductive columns, and the transmission path is effectively shortened; the first surface of the square panel is provided with multiple grooves, and the multiple bridge chips are arranged in the grooves of the square panel corresponding thereto, and the packaging height of the entire packaging structure is reduced. BRIEF DESCRIPTION OF DRAWINGS
[0029] Figure 1 A cross-sectional view of a board-level packaging structure according to an embodiment of the present disclosure;
[0030] Figure 2 A cross-sectional view of a board-level packaging structure according to another embodiment of the present disclosure;
[0031] Figure 3 A plan view of a board-level packaging structure according to another embodiment of the present disclosure;
[0032] Figure 4 A structural schematic diagram of a board-level packaging system according to another embodiment of the present disclosure. DETAILED DESCRIPTION
[0033] In order for those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the embodiments of the present disclosure are further described in detail below with reference to the drawings and specific embodiments.
[0034] As shown in the drawings, Figures 1 to 3 An aspect of the embodiment of the present disclosure provides a board-level packaging structure 100, which comprises a square panel 22, multiple bridge chips 24, a chip computing module, a first connecting module, a power management module and a second connecting module.
[0035] The first surface of the square panel 22 is provided with multiple grooves, and the square panel 22 is provided with multiple conductive columns 46 penetrating through the thickness thereof.
[0036] The non-functional surface of the multiple bridge chips 24 is arranged in the groove corresponding thereto. That is, the non-functional surface of the bridge chip 24 is arranged on the bottom wall of the groove corresponding thereto.
[0037] The chip operation module and the first connection module are arranged on the first surface of the square panel 22 and are electrically connected with the bridge chip 24 and the conductive column 46 respectively. The first connection module is used for electrical connection between the plurality of package-on-package structures 100.
[0038] Specifically, the chip operation module and the first connection module are arranged on the top surface of the square panel 22, and in this embodiment, the chip operation module is arranged in the central region of the first surface of the square panel 22, and the first connection module is arranged in the edge region of the second surface of the square panel 22.
[0039] The power management module and the second connection module are arranged on the second surface of the square panel 22 and are electrically connected with the conductive column 46. The second connection module is used for electrical connection between the plurality of package-on-package structures 100.
[0040] Specifically, the power management module and the second connection module are arranged on the bottom surface of the square panel 22, and in this embodiment, the power management module and the second connection module can be arranged at intervals. Of course, the power management module can be arranged in the central region of the second surface of the square panel 22, and the second connection module can be arranged in the edge region of the second surface of the square panel 22. The distribution positions of the power management module and the second connection module are not limited in this embodiment.
[0041] The package-on-package structure of the embodiment of the present disclosure adopts a large-area square panel, which significantly improves the chip capacity, area utilization rate and I / O density, significantly improves the system performance, thereby solving the problem of limited performance of a single SoW system and realizing high-computing power integration. The chip operation module realizes high-density interconnection with the aid of a plurality of bridge chips, and no longer needs to rely on constructing a fine line structure in the RDL. The square panel is provided with a plurality of conductive columns penetrating through the thickness thereof, the first surface of the square panel is provided with the chip operation module and the first connection module, the second surface of the square panel is provided with the power management module and the second connection module, the back surface of the square panel is vertically powered through the conductive columns, and the transmission path is effectively shortened. The first surface of the square panel is provided with a plurality of grooves, and the plurality of bridge chips are arranged in the grooves of the square panel corresponding thereto, thereby reducing the packaging height of the entire package structure.
[0042] As shown in the examples of FIGS. 1 and 2, Figure 1 and Figure 2 The chip operation module includes a first re-wiring layer and a chip operation layer 32.
[0043] The first re-wiring layer is arranged on the first surface of the square panel 22 and the functional surface of the bridge chip 24 and is electrically connected with the bridge chip 24 and the conductive column 46 respectively.
[0044] The chip operation layer 32 is arranged on the first re-wiring layer and is electrically connected with the first re-wiring layer.
[0045] It should be noted that in the embodiment, the chip operation layer 32 can only include a plurality of computing chips, or the chip operation layer 32 can include a plurality of computing chips and a plurality of storage chips. Of course, the chip operation layer 32 can also adopt other types of chips. The chips in the chip operation layer 32 are electrically interconnected through the first redistribution layer and the bridge chip 24. According to the area of the square panel 22, the chip operation layer 32 is distributed in a matrix, which can significantly improve the chip capacity, area utilization and I / O density of the entire packaging structure.
[0046] It should be noted that the type and number of chip operation layer 32 are not specifically limited and can be selected as needed.
[0047] As shown in Figure 1 and Figure 2 , the bridge chip 24 has a gap between the side wall of the groove; the first redistribution layer includes a first dielectric layer 28 and a first metal layer 30. The first dielectric layer 28 is arranged in the gap, the first surface of the square panel 22 and the functional surface of the bridge chip 24.
[0048] That is, the dielectric material fills the gap between the bridge chip 24 and the side wall of the groove, and is arranged on the bumps of the first surface of the square panel 22 and the functional surface of the bridge chip 24.
[0049] The first dielectric layer 28 arranged on the first surface of the square panel 22 and the functional surface of the bridge chip 24 is provided with an opening, and the first metal layer 30 electrically connected with the bridge chip 24 and the conductive column 46 is arranged in the opening. In the embodiment, the first dielectric layer 28 can be a PI layer, and the first metal layer 30 can be a copper layer.
[0050] In the embodiment, by arranging the first redistribution layer, high-density interconnection of the chip operation layer can be realized.
[0051] As shown in Figure 1 , in an embodiment, the first connection module includes a plurality of first connectors 34 arranged on the first redistribution layer and a first cable 36 arranged on the first connector 34.
[0052] Specifically, as shown in Figure 1 and Figure 3 , a plurality of first connectors 34 are arranged on the first metal layer 30 of the edge area of the square panel 22, and a first cable 36 is arranged on each first connector 34.
[0053] It should be noted that the number of first connectors 34 is not specifically limited in the embodiment and can be selected as needed.
[0054] As shown inFigure 2 As shown in another embodiment, the first connection module further comprises a plurality of photoelectric conversion chips 38 disposed on the first redistribution layer and optical fibers 40 disposed on the photoelectric conversion chips 38.
[0055] Specifically, as shown in Figure 2 and Figure 3 the plurality of photoelectric conversion chips 38 are disposed on the first metal layer 30 of the edge region of the square panel 22, and each photoelectric conversion chip 38 is provided with an optical fiber 40.
[0056] It should be noted that the number of photoelectric conversion chips 38 is not specifically limited and can be selected as needed.
[0057] It should be further noted that the specific type of the first connection module is not specifically limited and can be selected as needed.
[0058] For example, as shown in Figure 1 and Figure 2 the power management module comprises a second redistribution layer and a power management chip 56. The second redistribution layer is disposed on the second surface of the square panel 22 and is electrically connected with the conductive column 46. The power management chip 56 and the second connection module are disposed on the second redistribution layer and are both electrically connected with the second redistribution layer. Among them, the power management chip 56 is used to power the board-level packaging structure, and the second connection module is used for electrical connection between a plurality of board-level packaging structures.
[0059] In this embodiment, the high-density interconnection of the power management chip can be realized through the second redistribution layer, and the back vertical power supply of the square panel can be realized through the conductive column and the plurality of power management chips disposed on the second surface of the square panel, effectively shortening the transmission path.
[0060] For example, as shown in Figure 1 and Figure 2 the second redistribution layer comprises a second dielectric layer 52 and a second metal layer 53. The second dielectric layer 52 is disposed on the second surface of the square panel 22 and the surface of the conductive column 46 facing the power management chip 56. Among them, the second dielectric layer 52 is provided with a plurality of second openings, and the second metal layer 54 is disposed in the second openings. In this embodiment, the second dielectric layer 52 can be a PI layer, and the second metal layer 54 can be a copper layer.
[0061] For example, as shown in Figure 1 and Figure 2 the second connection module comprises a plurality of second connectors 34' disposed on the second redistribution layer and second cables 36' disposed on the second connectors 34'.
[0062] It should be noted that, as shown in Figure 1 and Figure 2As shown, in this embodiment, multiple second connectors 34' can be distributed at intervals with the power management chip 56. Alternatively, the multiple second connectors 34' can be located on the edge region of the second surface of the square panel 22. This embodiment does not specifically limit the number and distribution of the second connectors 34', and can select them according to actual needs.
[0063] For example, in this embodiment, the square panel 22 may be a glass panel.
[0064] In existing technologies, the carrier board is peeled off during the packaging process, and the final package structure does not contain the carrier board. However, the board-level packaging structure of this disclosure retains the square glass panel. The rigidity of the glass panel effectively controls the warpage of the board-level packaging structure, solving the problem of large-area EMC and chip CTE mismatch in existing technologies, and improving the reliability of the board-level packaging structure. Furthermore, multiple conductive pillars are provided on the retained square panel to achieve vertical interconnection of the packaging structure, effectively shortening the transmission path.
[0065] like Figure 4 As shown, another aspect of this disclosure provides a board-level packaging system A, including at least one board-level packaging structure 100 as described above. The specific structural features of the board-level packaging structure 100 have been described in detail above and will not be repeated here.
[0066] In the case where the board-level packaging system A includes multiple board-level packaging structures 100, the multiple board-level packaging structures 100 are electrically connected to each other through a first connection module and a second connection module, respectively.
[0067] like Figure 1 and Figure 3 As shown, in one embodiment, multiple board-level package structures 100 are electrically connected to each other via a first cable 36 and a second cable 36', respectively, to form... Figure 4 The board-level packaging system A shown is shown.
[0068] like Figure 2 and Figure 3 As shown, in another embodiment, multiple board-level package structures 100 are electrically connected to each other via optical fiber 40 and second cable 36', respectively, to form Figure 4 The board-level packaging system A is shown.
[0069] It should be noted that in this embodiment, the electrical connection method between multiple board-level package structures 100 is not specifically limited, and can be selected according to actual needs.
[0070] It should be further noted that there are no specific requirements for the number of board-level packaging structures 100 in board-level packaging system A, and the number can be selected according to the size of the board-level packaging structure.
[0071] The board-level packaging system of the embodiments of the present disclosure comprises at least one board-level packaging structure as described above, the board-level packaging structure adopts a large-area square panel, significantly improves the chip capacity, area utilization and I / O density, significantly improves the system performance, thereby solving the problem of limited performance of a single SoW system, and realizing high computing power integration; the chip computing module realizes high-density interconnection with the aid of multiple bridge chips, and no longer needs to rely on constructing a fine line structure in the RDL; the square panel is provided with multiple conductive columns penetrating through the thickness thereof, the first surface of the square panel is provided with the chip computing module and the first connecting module, the second surface of the square panel is provided with the power management module and the second connecting module, the back surface of the square panel is vertically powered through the conductive columns, and the transmission path is effectively shortened; the first surface of the square panel is provided with multiple grooves, and the multiple bridge chips are arranged in the grooves of the square panel corresponding thereto, thereby reducing the packaging height of the entire packaging structure.
[0072] It can be understood that the above embodiments are only exemplary embodiments adopted for illustrating the principles of the embodiments of the present disclosure, and the embodiments of the present disclosure are not limited thereto. Various modifications and improvements can be made by those of ordinary skill in the art without departing from the spirit and essence of the embodiments of the present disclosure, and these modifications and improvements are also considered within the protection scope of the embodiments of the present disclosure.
Claims
1. A board-level packaging structure, characterized in that, include: A square panel, wherein a first surface of the square panel is provided with a plurality of grooves, and the square panel is provided with a plurality of conductive pillars penetrating its thickness; Multiple bridging chips, wherein the non-functional surface of the bridging chip is disposed in the corresponding groove; The chip computing module and the first connection module are disposed on the first surface of the square panel and are electrically connected to the bridging chip and the conductive pillar, respectively. A power management module and a second connection module are disposed on the second surface of the square panel and electrically connected to the conductive posts; wherein... The chip computing module includes a first rewiring layer and a chip computing layer; the first rewiring layer is disposed on the first surface of the square panel and the functional surface of the bridging chip, and is electrically connected to the bridging chip and the conductive pillar respectively; the chip computing layer is disposed on the first rewiring layer and is electrically connected to the first rewiring layer; the chip computing layer includes multiple computing chips, or includes multiple computing chips and multiple memory chips; The first connection module includes a plurality of first connectors disposed on the first rewiring layer and a first cable disposed on the first connectors; and / or, the first connection module further includes a plurality of optoelectronic conversion chips disposed on the first rewiring layer and an optical fiber disposed on the optoelectronic conversion chips; The power management module includes a second wiring layer and a power management chip; the second wiring layer is disposed on the second surface of the square panel and is electrically connected to the conductive pillars; the power management chip and the second connection module are disposed on the second wiring layer and are both electrically connected to the second wiring layer. The second connection module includes a plurality of second connectors disposed on the second rewiring layer and a second cable disposed on the second connectors; wherein the second connectors are spaced apart from the power management chip.
2. The package-on-board structure of claim 1, wherein, There is a gap between the bridging chip and the sidewall of the groove; the first redistribution layer includes a first dielectric layer and a first metal layer; wherein, The first dielectric layer is disposed on the gap, the first surface of the square panel, and the functional surface of the bridging chip; An opening is provided in the first dielectric layer located on the first surface of the square panel and the functional surface of the bridging chip, and a first metal layer electrically connected to the bridging chip and the conductive pillar is disposed in the opening.
3. The package-on-board structure of claim 2, wherein, A plurality of the first connectors and a plurality of the photoelectric conversion chips are disposed on the first metal layer in the edge region of the square panel.
4. The package-on-board structure according to any one of claims 1 to 3, wherein, The square panel is made of glass.
5. The package-on-board structure according to any one of claims 1 to 3, wherein The second redistribution layer includes a second dielectric layer and a second metal layer; The second dielectric layer is disposed on the second surface of the square panel and the surface of the conductive pillars facing the power management chip; The second dielectric layer is provided with a plurality of second openings, and the second metal layer is disposed within the second openings.
6. A system for a board level package, comprising: Includes at least one board-level packaging structure as described in any one of claims 1 to 5; wherein, When the board-level packaging system includes multiple board-level packaging structures, the multiple board-level packaging structures are electrically connected to each other through the first connection module and the second connection module, respectively.
7. The board-level package system of claim 6, wherein, The first cable and the second cable are respectively used for electrical connection between the plurality of board-level packaging structures.
8. The system of claim 6, wherein, The optical fiber and the second cable are respectively used for electrical connection between the plurality of board-level packaging structures.
Citation Information
Patent Citations
Fan-out packaging method and structure
CN116031241A
Stackable optoelectronics chip-to-chip interconnects and method of manufacturing
US20050224946A1