Device variation extraction chip

Abstract

The invention discloses a device variation extraction chip, which comprises m MOS (Metal Oxide Semiconductor) devices and a test key, the test key has 2n contacts, n is an integer greater than 4, and m is an integer greater than n-1 and less than or equal to (n-1) 2; the drain end of the kth (n-1) + i MOS device is in short circuit with the ith contact of the test key, i is a positive integer smaller than or equal to n-1, and k is a natural number smaller than or equal to n-2; the gate end of the k (n-1) + i) th MOS device is in short circuit with the (n-1 + i) th contact of the test key; the source ends of the m MOS devices are short-circuited to the (2n-1) th contact; the body ends of the m MOS devices are all connected to the 2nth contact in a short circuit mode. According to the device variation extraction chip, a photomask and a manufacturing procedure do not need to be added, the chip area can be saved, the test time can be saved, a large amount of data can be obtained, and the accuracy of obtaining the device variation and the device mismatching degree can be improved.

Description

Technical Field

[0001] The invention relates to semiconductor circuit design technology, and in particular to a device variation extraction chip. Background Art

[0002] In the semiconductor manufacturing process, the purpose of each generation of process is to shrink the device size, improve performance, reduce leakage and reduce operating voltage. From the perspective of the chip, it means increasing the number of transistors, increasing speed, reducing power consumption and reducing area.

[0003] When a new process is developed, during the process of device miniaturization, the device width (device width) is reduced, the device length (device length) is reduced, and the overall device size is reduced. In essence, the device variation will be higher and it will be easily affected by the process technology. The device variation (device variation) will become larger and larger, and the device mismatch (device mismatch) will become larger and larger, which will cause device failure (Device failure) and even chip function failure (chip function fail).

[0004] To measure device variation and device mismatch, a large amount of device data needs to be measured to determine and analyze device behavior, and then determine which process technologies are the main influences, which process technologies need to be improved first, or to obtain the essential characteristics of the device. Measuring a large amount of device data requires more resources, layout area, and test time.

[0005] In the traditional way, to obtain device variation, multiple test keys are needed to measure multiple devices. Only when the amount of data is sufficient can the device variation be calculated.

[0006] To measure the electrical characteristics of a single device, four pads are required to connect the device's drain, source, gate, and bulk. Generally speaking, Figure 1 As shown in the figure, a 22-pad test key can only measure five devices. The symbolic connection of a single device with four pads is as follows: Figure 2 As shown, the layout connection is as follows Figure 3 shown.

[0007] The traditional way to test device mismatch is to use two adjacent and identical devices as a pair. The difference in electrical characteristics of the two devices is called Δ (delta). Many pairs of Δ are required, and multiple Δ operations can be used to obtain device mismatch. Under this condition, a pair of devices needs to use 7 pads to connect the drain 1, source 1, and gate 1 of device 1 with the drain 2, source 2, and gate 2 of device 2. The bulk of a pair of devices shares one pad. Generally speaking, a 22-pad test key can only measure 3 pairs of devices, such as Figure 4 The symbolic connection of a pair of devices with seven pads is shown in Figure 5 As shown, the layout connection is as follows Figure 6 As shown.

[0008] To calculate device mismatch, a large amount of data needs to be measured, which requires more test keys. Summary of the invention

[0009] The technical problem to be solved by the present invention is to provide a device variation extraction chip, which does not require the addition of masks and process steps, can save chip area, can save test time, can obtain a large amount of data, and can improve the accuracy of obtaining device variation (device variation) and device mismatch (device mismatch).

[0010] In order to solve the above technical problems, the present invention provides a device variation extraction chip, which includes m MOS devices and a test key;

[0011] The test key has 2n contacts, n is an integer greater than 4, and m is an integer greater than n-1 and less than or equal to (n-1);

[0012] The drain end of the k(n-1)+i MOS device is short-circuited to the i-th contact of the test key, where i is a positive integer less than or equal to n-1, and k is a natural number less than or equal to n-2;

[0013] The gate terminal of the k(n-1)+i MOS device is short-circuited with the n-1+i th contact of the test key;

[0014] The source terminals of m MOS devices are all short-connected to the 2n-1th contact;

[0015] The body terminals of the m MOS devices are all short-connected to the 2nth contact.

[0016] Preferably, m = (n-1) 2 .

[0017] Preferably, m is 100 and n is 11;

[0018] The drain terminal of the 10k+i MOS device is short-circuited to the i-th contact point (pad) of the test key, where i is a positive integer less than or equal to 10, and k is a natural number less than or equal to 9;

[0019] The gate terminal of the 10k+i MOS device is short-circuited with the 10+i contact of the test key;

[0020] The source terminals of 100 MOS devices are all shorted to the 21st contact;

[0021] The body terminals of 100 MOS devices are shorted to the 22nd contact.

[0022] Preferably, m<(n-1) 2 .

[0023] Preferably, m is 54 and n is 9;

[0024] The drain end of the 8k+i MOS device is short-circuited to the i-th contact of the test key, where i is a positive integer less than or equal to 8, and k is a natural number less than or equal to 7;

[0025] The gate terminal of the 8k+i MOS device is short-circuited with the 8+i contact of the test key;

[0026] The source terminals of the 54 MOS devices are shorted to the 17th contact;

[0027] The body terminals of the 54 MOS devices are shorted to the 18th contact.

[0028] The device variation extraction chip of the present invention is a layout design of an array structure. Based on a test key with 2n pads, the total number of test keys that can be designed is (n-1). 2 The variation extraction architecture of MOS devices can measure (n-1) 2 The electrical characteristics of a MOS device (such as threshold voltage Vt, on-state current Id, etc.) can also be converted to The difference in the electrical characteristics of the device is called Δ (delta). Using a test key with 2n contacts (pads), the chip layout architecture for device variation extraction can be completed. A large amount of MOS device electrical characteristic data can be measured with a smaller chip area, reducing the measurement time. These electrical characteristic data can be used to calculate the standard deviation of the device variation and device mismatch with high accuracy. This can be used to obtain the essential characteristics of the device and observe the stability of the process technology, determine the direction of improvement, improve the device electrical characteristics and improve the process technology, and further analyze the yield to reduce the research and development cycle time of chip products and improve the yield of chip products. The device variation extraction chip does not need to add masks or process steps, can save chip area, can save test time, can obtain a large amount of data, can improve the accuracy of obtaining device variation and device mismatch, and can save chip development costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0030] Figure 1 This is a schematic diagram of a 22-contact test key testing a single device;

[0031] Figure 2 It is a symbolic connection diagram of a single device and four contacts;

[0032] Figure 3 It is a schematic diagram of the layout connection of a single device with four contacts;

[0033] Figure 4 It is a schematic diagram of a 22-contact test key testing a pair of devices;

[0034] Figure 5 It is a symbolic connection diagram of a pair of devices and seven contacts;

[0035] Figure 6 It is a schematic diagram of the layout connection of a pair of devices with seven contacts;

[0036] Figure 7 A schematic diagram of the test key configuration of a device variation extraction chip according to an embodiment of the present invention;

[0037] Figure 8 A schematic diagram of symbolic connections of an embodiment of a device variation extraction chip of the present invention;

[0038] Fig. 9 A schematic diagram of the layout and connection of a device variation extraction chip according to an embodiment of the present invention;

[0039] Fig.10 A partial schematic diagram of the layout and connection of a device variation extraction chip according to an embodiment of the present invention. DETAILED DESCRIPTION

[0040] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] The words "first", "second" and similar terms used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprises" and similar terms mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative position relationships. When the absolute position of the object being described changes, the relative position relationship may also change accordingly.

[0042] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0043] Embodiment 1

[0044] like Figure 7 As shown, a device variation extraction chip includes m MOS devices and a test key;

[0045] like Figure 7 As shown, the test key has 2n pads, n is an integer greater than 4, and m is greater than n-1 and less than or equal to (n-1). 2 integer;

[0046] The drain terminal Drain of the k(n-1)+i MOS device is short-circuited with the i-th contact point (pad) of the test key, where i is a positive integer less than or equal to n-1, and k is a natural number less than or equal to n-2;

[0047] The gate terminal of the k(n-1)+i MOS device is short-connected to the n-1+i pad of the test key; the source terminals of the m MOS devices are all short-connected to the 2n-1 pad;

[0048] The body terminals of the m MOS devices are all short-connected to the 2nth contact point (pad).

[0049] The device variation extraction chip of the first embodiment is a layout design of an array structure. Based on a test key with 2n pads, the total number of test keys that can be designed is (n-1). 2 The variation extraction architecture of MOS devices can measure (n-1) 2 The electrical characteristics of a MOS device (such as threshold voltage Vt, on-state current Id, etc.) can also be converted to The difference in the electrical characteristics of the device is called Δ (delta). Using a test key with 2n contacts (pads), the chip layout architecture can be completed to extract the device variation. A large amount of MOS device electrical characteristic data can be obtained with a smaller chip area, reducing the measurement time. These electrical characteristic data can be used to calculate the high-precision device variation and the standard deviation of the device mismatch. It can be used to obtain the essential characteristics of the device and observe the stability of the process technology, determine the direction of improvement, improve the device electrical characteristics and improve the process technology, and further analyze the yield to reduce the research and development cycle time of chip products and improve the yield of chip products.

[0050] The device variation extraction chip of the first embodiment does not require the addition of a mask or process steps, can save chip area, can save test time, can obtain a large amount of data, can improve the accuracy of obtaining device variation and device mismatch, and can save chip development costs.

[0051] Embodiment 2

[0052] Based on the device variation extraction chip of Example 1, m=(n-1) 2 .

[0053] Embodiment 3

[0054] Based on the device variation extraction chip of Example 1, Figure 7 , Figure 8 , Fig. 9 and Fig.10 As shown, m is 100 and n is 11;

[0055] The drain terminal Drain of the 10k+i MOS device is short-circuited with the i-th contact point (pad) of the test key, where i is a positive integer less than or equal to 10, and k is a natural number less than or equal to 9;

[0056] The gate terminal of the 10k+i MOS device is short-circuited with the 10+i pad of the test key;

[0057] The source terminals of 100 MOS devices are all shorted to the 21st contact (pad);

[0058] The body terminals of 100 MOS devices are shorted to the 22nd pad.

[0059] In the device variation extraction chip of the third embodiment, the drain terminals Drain of MOS devices 1, 11, 21, 31, 41, 51, 61, 71, 81, 91 are shorted to the first contact (pad 1), the drain terminals Drain of MOS devices 2, 12, 22, 32, 42, 52, 62, 72, 82, 92 are shorted to the second contact (pad 2), the drain terminals Drain of MOS devices 3, 13, 23, 33, 43, 53, 63, 73, 83, 93 are shorted to the third contact (pad 3), and so on for the rest, the drain terminals Drain of MOS devices 10, 20, 30, 40, 50, 60, 70, 80, 90, 100 are shorted to the tenth contact (pad 10); the gate terminals of MOS devices 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 are shorted to the 11th contact (pad 11), the gate terminals of MOS devices 11, 12, 13, 14, 15, 16, 17, 18, 19, 20 are shorted to the 12th contact (pad 12), and so on, the gate terminals of MOS devices 91, 92, 93, 94, 95, 96, 97, 98, 99, 100 are shorted to the 20th contact (pad 20). The device variation extraction chip of the third embodiment is based on a test key with 22 contact pads, and the total number of MOS devices designed is 10x10=100. The electrical characteristics of 100 MOS devices can be measured. Taking a single device as a unit, the device variation of 100 devices (Device 01~Device 100) can be measured; if taking a pair as a unit, the electrical characteristic difference Δ (delta) and device mismatch of 50 pairs (pair01~pair 50) can be measured and calculated.

[0060] Embodiment 4

[0061] Based on the device variation extraction chip of Example 1, m<(n-1) 2 .

[0062] Embodiment 5

[0063] Based on the device variation extraction chip of Example 4, m is 54, and n is 9;

[0064] The drain terminal Drain of the 8k+i MOS device is short-circuited with the i th contact point (pad) of the test key, where i is a positive integer less than or equal to 8, and k is a natural number less than or equal to 7;

[0065] The gate terminal of the 8k+i MOS device is short-circuited with the 8+i pad of the test key;

[0066] The source terminals of the 54 MOS devices are all shorted to the 17th contact (pad);

[0067] The body terminals of the 54 MOS devices are shorted to the 18th pad.

[0068] In the device variation extraction chip of Example 5, the drain terminals Drain of MOS devices 1, 9, 17, 25, 33, 41, and 49 are shorted to the first contact (pad 1), the drain terminals Drain of MOS devices 2, 10, 18, 26, 34, 42, and 50 are shorted to the second contact (pad 2), the drain terminals Drain of MOS devices 3, 11, 19, 27, 35, 43, and 51 are shorted to the third contact (pad 3), the drain terminals Drain of MOS devices 4, 12, 20, 28, 36, 44, and 52 are shorted to the fourth contact (pad 4), the drain terminals Drain of MOS devices 5, 13, 21, 29, 37, 45, and 53 are shorted to the fifth contact (pad 5), and the drain terminals Drain of MOS devices 6, 14, 22, 30, 38, 46, and 54 are shorted to the sixth contact (pad 6). 6), the drain terminals Drain of MOS devices 7, 15, 23, 31, 39, and 47 are short-circuited to the seventh contact (pad 7); the drain terminals Drain of MOS devices 8, 16, 24, 32, 40, and 48 are short-circuited to the eighth contact (pad 8).

[0069] The device variation extraction chip of the fifth embodiment is based on a test key with 18 contact pads. The total number of MOS devices designed is a new architecture of 54, which can measure the electrical characteristics of 54 MOS devices. In terms of single units, the device variation of 54 devices (Device 01 to Device 54) can be measured; if in terms of pairs, the electrical characteristic difference Δ (delta) and device mismatch of 27 pairs (pair 01 to pair 50) can be measured and calculated.

[0070] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A device variation extraction chip, characterized in that: It includes m MOS devices and a test key; The test key has 2n contacts, n is an integer greater than 4, and m is an integer greater than n-1 and less than or equal to (n-1); The drain end of the k(n-1)+i MOS device is short-circuited to the i-th contact of the test key, where i is a positive integer less than or equal to n-1, and k is a natural number less than or equal to n-2; The gate terminal of the k(n-1)+i MOS device is short-circuited with the n-1+i th contact of the test key; The source terminals of m MOS devices are all short-connected to the 2n-1th contact; The body terminals of the m MOS devices are all short-connected to the 2nth contact.

2. The device variation extraction chip according to claim 1, characterized in that: m=(n-1) 2 。 3. The device variation extraction chip according to claim 1, characterized in that: m is 100, n is 11; The drain terminal of the 10k+i MOS device is short-circuited to the i-th contact point (pad) of the test key, where i is a positive integer less than or equal to 10, and k is a natural number less than or equal to 9; The gate terminal of the 10k+i MOS device is short-circuited with the 10+i contact of the test key; The source terminals of 100 MOS devices are all shorted to the 21st contact; The body terminals of 100 MOS devices are shorted to the 22nd contact.

4. The device variation extraction chip according to claim 1, characterized in that: m<(n-1) 2 。 5. The device variation extraction chip according to claim 1, characterized in that: m is 54, n is 9; The drain end of the 8k+i MOS device is short-circuited to the i-th contact of the test key, where i is a positive integer less than or equal to 8, and k is a natural number less than or equal to 7; The gate terminal of the 8k+i MOS device is short-circuited with the 8+i contact of the test key; The source terminals of the 54 MOS devices are shorted to the 17th contact; The body terminals of the 54 MOS devices are shorted to the 18th contact.

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