Driving chip, power chip and switching power supply

Abstract

The embodiment of the invention discloses a driving chip, a power chip and a switching power supply, the driving chip comprises a driving circuit and a current generation circuit, and the current generation circuit comprises a sampling circuit, a slope control circuit and a current output circuit. The sampling circuit controls the current output circuit to output rectifier tube sampling current in the rectifier tube conduction stage. The slope control circuit controls the current output circuit to output (k + 1) th main power tube analog current in the main power tube conduction stage in the (k + 1) th control period according to the rectifier tube sampling current output by the current output circuit in the rectifier tube conduction stage in the k th control period and the k th main power tube analog current output by the current output circuit in the main power tube conduction stage in the (k + 1) th control period. According to the arrangement, based on the sampling current of the rectifier tube and the analog current of the main power tube, the drive circuit controls the connection and disconnection of the main power tube and the rectifier tube, and the control accuracy of the main power tube and the rectifier tube is improved.

Description

Technical Field

[0001] The present application relates to the technical field of switching power supplies, and in particular to a driver chip, a power chip and a switching power supply. Background Art

[0002] A switching power supply can also be called a switch mode power supply (SMPS). A switching power supply can convert the input voltage (AC or DC) to output an output voltage that matches the load. In the control scheme of a switching power supply, information about the inductor current is often required as input for loop feedback. As the switching frequency increases, the on-time of the main power tube of the switching power supply becomes shorter and shorter, resulting in inaccurate sampling of the inductor current, which in turn affects the control effect of the switching power supply. Summary of the invention

[0003] The embodiments of the present application provide a driver chip, a power chip and a switching power supply to solve the problem of inaccurate inductor current sampling.

[0004] In the first aspect, an embodiment of the present application provides a driver chip, which includes a driver circuit and a current generating circuit. The driver circuit is used to connect to the main power tube and the rectifier tube, and the driver circuit can control the main power tube and the rectifier tube. In addition, a current generating circuit is set in the driver chip, and the current generating circuit includes: a sampling circuit, a slope control circuit and a current output circuit. The sampling circuit is used to connect to the rectifier tube, and the sampling circuit is connected to the current output circuit, and the slope control circuit is connected to the current output circuit. Among them, the current output circuit can output the rectifier tube sampling current during the rectifier tube conduction stage of each control cycle, and output the main power tube analog current during the main power tube conduction stage of each control cycle. The sampling circuit can control the current output circuit to output the rectifier tube sampling current according to the current flowing through the rectifier tube during the rectifier tube conduction stage of each control cycle. Furthermore, the slope control circuit can control the current output circuit to output the k+1th main power tube analog current in the main power tube conduction stage in the k+1th control cycle according to the rectifier tube sampling current output by the current output circuit in the rectifier tube conduction stage in the kth control cycle and the kth main power tube analog current output by the main power tube conduction stage, wherein k is an integer greater than 0. With this arrangement, the kth main power tube analog current output in the k+1th control cycle and the rectifier tube sampling current can be used as feedback parameters for outputting the k+1th main power tube analog current in the k+1th control cycle, thereby improving the accuracy of outputting the k+1th main power tube analog current in the k+1th control cycle. Furthermore, the required inductor current can be obtained without directly sampling the current flowing through the main power tube, thereby avoiding the problem of inaccurate sampling accuracy caused by sampling the inductor current. In addition, the rectifier tube sampling current and the main power tube analog current are both input into the controller, and the controller synthesizes them to form an inductor current including the rectifier tube sampling current and the main power tube analog current, so that the controller can regulate the pulse width modulation signal according to the synthesized inductor current, and then output the regulated pulse width modulation signal to the drive circuit, so that the drive circuit can control the conduction and disconnection of the main power tube and the rectifier tube according to the regulated pulse width modulation signal, thereby improving the control accuracy of the main power tube and the rectifier tube.

[0005] Furthermore, since the current generating circuit in the present application is connected to the rectifier tube, the inductor current can be synthesized, so there is no need to set up additional pins on the driver chip to connect to the output voltage of the switching power supply. It is suitable for mainstream small-size, low-pin package products, which can reduce costs and expand the scope of application.

[0006] In addition, the current generating circuit in the embodiment of the present application automatically changes the slope of the main power tube analog current in accordance with the change of the inductance value of the power inductor, so that the inductor current output by the current generating circuit can adapt to the change of the inductance value of the power inductor. In addition, the current generating circuit in the present application can also adapt to the change of the duty cycle of the pulse width modulation signal, and the fitting time of the slope of the main power tube analog current tracks the conduction time of the main power tube in real time.

[0007] In some embodiments, the slope control circuit includes: a first sampling circuit, a second sampling circuit and a control circuit, wherein the first sampling circuit is connected to the current output circuit, the second sampling circuit is connected to the current output circuit, and the control circuit is connected to the first sampling circuit, the second sampling circuit and the current output circuit respectively. In specific applications, the first sampling circuit can collect the first sampling voltage corresponding to the current output circuit outputting the kth main power tube analog current during the main power tube conduction phase of the kth control cycle. In addition, the second sampling circuit can collect the second sampling voltage corresponding to the current output circuit outputting the rectifier tube sampling current during the rectifier tube conduction phase of the kth control cycle. Based on this, the control circuit receives the first sampling voltage and the second sampling voltage, and controls the current output circuit to output the k+1th main power tube analog current during the main power tube conduction phase of the k+1th control cycle according to the received first sampling voltage and the second sampling voltage. With this arrangement, the fitting time of the slope of the k+1th main power tube analog current can track the conduction time of the main power tube in real time. In addition, the voltage corresponding to the kth main power tube analog current and the rectifier tube sampling current output in the kth control cycle can be used as a feedback parameter for outputting the k+1th main power tube analog current in the k+1th control cycle, thereby improving the accuracy of outputting the k+1th main power tube analog current in the k+1th control cycle.

[0008] It is understandable that the current generating circuit can work in K consecutive control cycles, each of which includes a main power tube conduction phase and a rectifier tube conduction phase. The main power tube conduction phase in each control cycle occurs before the rectifier tube conduction phase. K is an integer greater than 1. And 1≤k≤K.

[0009] Exemplarily, the control circuit includes: a regulation generation circuit, a first switch and a first controlled current source, wherein the regulation generation circuit is connected to the first sampling circuit, the second sampling circuit and the control end of the first controlled current source, the first end of the first controlled current source is connected to the current output circuit through the first switch, and the second end of the first controlled current source is grounded. In addition, the regulation generation circuit can receive the first sampling voltage and the second sampling voltage, and control the first controlled current source to generate the first current according to the received first sampling voltage and the second sampling voltage. In addition, the first switch can be in the on state during the main power tube conduction stage, so that the first current generated by the first controlled current source can be input into the current output circuit during the main power tube conduction stage, so as to control the current output circuit to output the k+1th main power tube analog current during the main power tube conduction stage. With this arrangement, the fitting time of the slope of the k+1th main power tube analog current can track the conduction time of the main power tube in real time.

[0010] The first controlled current source is set as a voltage controlled current source (Voltage Controlled Current Source, VCCS), and the regulating generation circuit outputs a control voltage to the control end of the first controlled current source, so that the first current generated by the first controlled current source can change according to the change of the control voltage. For example, the first current increases as the control voltage increases. Alternatively, the first controlled current source can also be formed by a current mirror structure, which is not limited here.

[0011] In some examples, the regulation generation circuit includes a first error amplifier (EA), wherein a negative phase input terminal of the first error amplifier is connected to a first sampling circuit, a positive phase input terminal of the first error amplifier is connected to a second sampling circuit, and an output terminal of the first error amplifier is connected to a control terminal of a first controlled current source. In practical applications, the negative phase input terminal of the first error amplifier receives a first sampling voltage output by the first sampling circuit, and the positive phase input terminal of the first error amplifier receives a second sampling voltage output by the second sampling circuit, thereby outputting a control voltage according to the first sampling voltage and the second sampling voltage, so that the first controlled current source generates a first current.

[0012] Furthermore, the regulation generation circuit also includes a second switch, and the second switch is connected between the negative phase input terminal of the first error amplifier and the positive phase input terminal of the first error amplifier. In actual application, the control end of the second switch receives the third pulse control signal, and is turned on when the third pulse control signal is at the second level, so that the negative phase input terminal and the positive phase input terminal of the first error amplifier are turned on. And, when the third pulse control signal is at the first level, it is disconnected, so that the negative phase input terminal and the positive phase input terminal of the first error amplifier are disconnected.

[0013] In some other examples, the regulation generation circuit includes: a comparator, a selector, and a signal generator, wherein the negative phase input terminal of the comparator is connected to the first sampling circuit, the positive phase input terminal of the comparator is connected to the second sampling circuit, the output terminal of the comparator is connected to the first input terminal of the selector, the second input terminal of the selector is used to receive a selection trigger signal, the first output terminal of the selector is connected to the first control terminal of the signal generator, the second output terminal of the selector is connected to the second control terminal of the signal generator, and the output terminal of the signal generator is connected to the control terminal of the first controlled current source. Based on this, the negative phase input terminal of the comparator can receive the first sampling voltage, the positive phase input terminal of the comparator can receive the second sampling voltage, and the comparator enables the output terminal of the comparator to output a selection control signal according to the first sampling voltage and the second sampling voltage. The selector is used to respond to the selection control signal and the selection trigger signal, and the control signal generator outputs the control voltage according to the first reference current or the second reference current. Exemplarily, if the trigger signal is selected to be a first level (e.g., a high level), and if the control signal is selected to be a first level (e.g., a high level), the selector may control the signal generator to output a first reference current to the control end of the first controlled current source, so that the control end of the first controlled current source is charged, so that the control voltage of the control end of the first controlled current source is increased. If the control signal is selected to be a second level (e.g., a low level), the selector may control the signal generator to output a second reference current to the control end of the first controlled current source, so that the control end of the first controlled current source is discharged, so that the control voltage of the control end of the first controlled current source is reduced. Furthermore, if the trigger signal is selected to be a second level (e.g., a low level), the selector does not control the output of the signal generator.

[0014] Exemplarily, the signal generator includes: a third switch, a fourth switch, a first current source, a second current source and a storage capacitor, wherein the first end of the first current source is connected to the first reference signal end, the second end of the first current source is connected to the first end of the third switch, the second end of the third switch is connected to the control end of the first controlled current source, and the control end of the third switch is connected to the first output end of the selector. The first end of the fourth switch is connected to the control end of the first controlled current source, the second end of the fourth switch is connected to the first end of the second current source, and the control end of the fourth switch is connected to the second output end of the selector. The second end of the second current source is connected to the second reference signal end, the first end of the storage capacitor is connected to the control end of the first controlled current source, and the second end of the storage capacitor is connected to the second reference signal end. In addition, the first current source is used to output the first reference current, and the second current source is used to output the second reference current. In a specific application, the selector controls the third switch to be turned on, the first current source outputs the first reference current to the storage capacitor, charges the storage capacitor, and the voltage after the storage capacitor is charged is output to the control end of the first controlled current source as the control voltage. And, the selector controls the fourth switch to be turned on, the second current source outputs the second reference current to the storage capacitor, so that the storage capacitor is discharged, and the voltage of the storage capacitor after discharge is output as the control voltage to the control end of the first controlled current source. In addition, the voltage of the first reference signal end is higher than the voltage of the second reference signal end. For example, the first reference signal end can be the second power supply end, and the second reference signal end can be grounded.

[0015] In a specific implementation, the first sampling circuit can be controlled to collect the analog current of the k+1th main power tube output by the current output circuit during the first period in the main power tube conduction stage, convert the collected current into a first sampling voltage, and directly output the first sampling voltage during the first period. The first period is the time period between the first reference moment and the end moment in the main power tube conduction stage. In actual application, the first pulse control signal is input to the first sampling circuit to control the first sampling circuit. Specifically, when the first pulse control signal is at the first level, the first sampling circuit is controlled to collect the analog current of the k+1th main power tube output by the current output circuit, and convert the collected current into the first sampling voltage and then output it. When the first pulse control signal is at the second level, the first sampling voltage is kept output. The time period in which the first pulse control signal is at the first level is the above-mentioned first period. In addition, the first sampling circuit can also keep the first sampling voltage output during the rectifier tube conduction stage.

[0016] The first reference moment of the first period can be close to the end moment of the main power tube conduction stage, so as to collect the first sampled voltage in the time period that is about to end in the main power tube conduction stage. The first reference moment is a moment between the start moment and the end moment of the main power tube conduction stage, so that part of the time period in the main power tube conduction stage is set as the first period. Alternatively, the first reference moment is the start moment of the main power tube conduction stage, so that the first reference moment is aligned with the start moment of the main power tube conduction stage, so that the entire main power tube conduction stage is set as the first period.

[0017] In the present application, the first sampling circuit includes a first sample and hold circuit (Sample and Hold circuit, S / H), wherein the control end of the first sample and hold circuit is used to receive a first pulse control signal, so that the first sample and hold circuit can work under the control of the first pulse control signal. In addition, the input end of the first sample and hold circuit is connected to the output end of the current output circuit, and the output end of the first sample and hold circuit is connected to the control circuit.

[0018] In the specific implementation, the second sampling circuit is also controlled to collect the rectifier tube sampling current output by the current output circuit during the second period in the rectifier tube conduction stage, convert the collected current into a second sampling voltage, and directly output the second sampling voltage during the second period. The second period is the time period between the start time and the second reference time in the rectifier tube conduction stage. In actual application, the second pulse control signal is input to the second sampling circuit. When the second pulse control signal is at the first level, the second sampling circuit is controlled to collect the rectifier tube sampling current output by the current output circuit, and convert the collected current into the second sampling voltage and then output it. When the second pulse control signal is at the second level, the second sampling voltage is kept output. The time period in which the second pulse control signal is at the first level is used as the above-mentioned second period. In addition, the second sampling circuit can also keep the second sampling voltage output during the main power tube conduction stage.

[0019] The second reference time of the second period can be close to the start time of the rectifier conduction stage, so as to collect the second sampled voltage in the time period just beginning in the rectifier conduction stage. The second reference time is a time between the start time and the end time of the rectifier conduction stage, so that part of the time period in the rectifier conduction stage is set as the second period. In addition, the second sampling circuit needs to be controlled to maintain the second sampled voltage output in the remaining periods except the second period in the rectifier conduction stage.

[0020] In some embodiments, the current output circuit includes a second controlled current source, the control end of the second controlled current source is connected to the sampling circuit and the slope control circuit, the first end of the second controlled current source is connected to the second power supply end, and the second end of the second controlled current source is connected to the controller. Further, the current output circuit also includes a voltage divider resistor, and the second end of the second controlled current source is grounded through the voltage divider resistor. Based on this, the sampling circuit can output a voltage to the control end of the second controlled current source, so that the second controlled current source can respond to the voltage generated by its control end according to the sampling circuit control in the conduction stage of the rectifier tube, and output the rectifier tube sampling current. In addition, the slope control circuit outputs a current to the control end of the second controlled current source, so that in the conduction stage of the main power tube, the voltage of the control end of the second controlled current source is regulated by the current, so that the second controlled current source can respond to the voltage generated by its control end according to the slope control circuit control, and output the k+1th main power tube analog current.

[0021] Wherein, the second controlled current source is also set to VCCS, so that the second controlled current source generates a rectifier tube sampling current according to the voltage input to its control end by the sampling circuit, and adjusts the voltage of its control end according to the current input to its control end by the slope control circuit, so that the second controlled current source generates the k+1th main power tube analog current. Wherein, the k+1th main power tube analog current changes according to the change of the voltage at its control end. For example, when the voltage at the control end of the second controlled current source decreases, the second controlled current source can generate the k+1th main power tube analog current with an increasing current value, and increase the slope of the k+1th main power tube analog current. Alternatively, the second controlled current source can also be formed by a current mirror structure, which is not limited here.

[0022] In some embodiments, the sampling circuit includes: a current detection circuit and a third sampling circuit, wherein the current detection circuit is respectively connected to the control end, the first end and the second end of the rectifier tube, and the third sampling circuit is respectively connected to the control end, the current detection circuit and the current output circuit of the rectifier tube. In specific applications, the current detection circuit can respond to the drive signal of the control end of the rectifier tube, and generate a first control signal according to the current of the first end of the rectifier tube and the current of the second end of the rectifier tube during the conduction phase of the rectifier tube. The third sampling circuit can also respond to the drive signal of the control end of the rectifier tube, and output the first control signal to the current output circuit during the conduction phase of the rectifier tube to control the current output circuit to generate the rectifier tube sampling current. In specific applications, the third sampling circuit can also respond to the drive signal of the control end of the rectifier tube, and keep the first control signal output at the beginning of the conduction phase of the main power tube.

[0023] Exemplarily, the current detection circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor and a second error amplifier (EA), the control end of the first transistor, the control end of the second transistor and the control end of the rectifier are connected to each other, the first end of the first transistor is connected to the first end of the rectifier, and the second end of the first transistor is connected to the negative phase input end of the second error amplifier.

[0024] The first end of the second transistor is connected to the second end of the rectifier tube, and the second end of the second transistor is connected to the non-inverting input end of the second error amplifier. The control end of the third transistor, the control end of the fourth transistor, and the output end of the second error amplifier are connected to each other, the first end of the third transistor is connected to the second end of the first transistor, and the second end of the third transistor is connected to the second power supply end. The first end of the fourth transistor is connected to the second end of the second transistor, and the second end of the fourth transistor is connected to the second power supply end. The output end of the second error amplifier is also connected to the third sampling circuit.

[0025] The third sampling circuit includes a third sample and hold circuit (Sample and Hold circuit, S / H), the control end of the third sample and hold circuit is connected to the control end of the rectifier tube, so that the third sample and hold circuit can be controlled by the driving signal of the control end of the rectifier tube to work. In addition, the input end of the third sample and hold circuit is connected to the output end of the error amplifier in the current detection circuit, and the output end of the third sample and hold circuit is connected to the current output circuit.

[0026] In the second aspect, the embodiment of the present application also provides a power chip, which includes: a power device and a driver chip. Among them, the power device includes a main power tube and a rectifier tube, and the driver chip is connected to the main power tube and the rectifier tube respectively. In addition, the driver chip can output the rectifier tube sampling current and the main power tube analog current, and control the main power tube and the rectifier tube. In addition, the driver chip is a driver chip as in the first aspect or various possible designs of the first aspect. Since the driver chip provided in the embodiment of the present application can solve the problem of inaccurate inductor current sampling, the control effect of the power chip can be improved.

[0027] In the third aspect, the embodiment of the present application also provides a switching power supply, which includes: a controller and a power chip. Wherein, the controller is connected to the power chip, and the controller can receive the rectifier tube sampling current and the main power tube analog current output by the power chip, and output a pulse width modulation signal to the power chip according to the rectifier tube sampling current and the main power tube analog current. The power chip is used to receive the pulse width modulation signal, and according to the pulse width modulation signal, drive the above-mentioned driver chip to control the conduction and disconnection of the main power tube, and control the conduction and disconnection of the rectifier tube. In addition, the power chip is a power chip with a driver chip in various possible designs as in the second aspect. Since the driver chip provided in the embodiment of the present application can solve the problem of inaccurate inductor current sampling, the control effect of the switching power supply can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1a This is a schematic diagram of the structure of a switching power supply in an embodiment of the present application;

[0029] Figure 1b A signal timing diagram in one embodiment of the present application;

[0030] Figure 2 This is a schematic diagram of the structure of a power chip in one embodiment of the present application;

[0031] Figure 3a to Figure 3c They are schematic diagrams of the structure of a power chip in another embodiment of the present application;

[0032] Figure 4 A signal timing diagram in another embodiment of the present application;

[0033] Figure 5 This is a schematic diagram of the structure of a driver chip in one embodiment of the present application;

[0034] Figure 6 A schematic diagram of the specific structure of a driver chip in one embodiment of the present application;

[0035] Figure 7 This is a schematic diagram of the specific structure of a driver chip in another embodiment of the present application;

[0036] Figure 8a A signal timing diagram in another embodiment of the present application;

[0037] Figure 8b A signal timing diagram in another embodiment of the present application;

[0038] Figure 8c A signal timing diagram in another embodiment of the present application;

[0039] Fig. 9 This is a schematic diagram of the specific structure of a driver chip in another embodiment of the present application;

[0040] Fig.10a A signal timing diagram in another embodiment of the present application;

[0041] Fig.10b A signal timing diagram in another embodiment of the present application;

[0042] Fig.10c This is a signal timing diagram in yet another embodiment of the present application.

[0043] Reference numerals:

[0044] 10-switching power supply; 20-power chip; 30-controller; 40-driving chip; 50-power device; 60-driving circuit; 61 / 61a / 61b-first gate driving circuit; 62 / 62a / 62b-second gate driving circuit; 70 / 70a / 70b-current generating circuit; 71-sampling circuit; 711-current detecting circuit; 712-third sampling circuit; QS1-first transistor; QS2-second transistor; QS3-third transistor; QS4-fourth transistor; 7111-second error amplifier; 7121-third sampling and holding circuit; 72-slope control circuit; 721-first sampling circuit; 7211-first sampling and holding circuit; 722-second sampling circuit; 7221-second sampling and holding circuit; 7 23-regulation circuit; 73-current output circuit; 730-regulation generation circuit; 731-first error amplifier; 732-comparator; 733-selector; 734-signal generator; K1-first switch; K2-second switch; K3-third switch; K4-fourth switch; IY1-first current source; IY2-second current source; CS-storage capacitor; 740-first controlled current source; 750-second controlled current source; Q2 / Q2a / Q2b-main power tube; Q1 / Q1a / Q1b-rectifier tube; GH / / GHa / GHb / GL / GLa / GLb-control end; SW / SWa / SWb-first end; PGND / PGNDa / PGNDb-second end; L-power inductor; C-capacitor; RL-load. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings. The specific operating methods in the method embodiments can also be applied to device embodiments or system embodiments. It should be noted that in the description of the present application, "multiple" can be understood as "at least two". In addition, it should be understood that in the description of the present application, words such as "first" and "second" are only used to distinguish the purpose of description, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order.

[0046] It should be noted that in the embodiments of the present application, "connection" refers to electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, A and B are connected, which can be either A and B directly connected, or A and B indirectly connected through one or more other electrical components, for example, A and B are connected, or A and C are directly connected, C and B are directly connected, and A and B are connected through C.

[0047] It should be noted that the same reference numerals in the drawings of this application represent the same or similar structures, and thus their repeated description will be omitted. The words expressing positions and directions described in this application are all explained using the drawings as examples, but they can be changed as needed, and the changes are included in the protection scope of this application. The drawings of this application are only used to illustrate the relative position relationship and do not represent the true proportion.

[0048] In order to facilitate understanding of the technical solution provided by the embodiments of the present application, the application scenario of the solution of the present application is first explained below.

[0049] The driver chip provided in the embodiment of the present application can be widely used in power chips. Moreover, the power chip provided in the embodiment of the present application can also be widely used in switching power supplies. Due to the driver chip provided in the embodiment of the present application, the problem of inaccurate sampling of the inductor current can be solved, thereby improving the control effect of the switching power supply. Furthermore, the switching power supply provided in the embodiment of the present application can be widely used in various electronic devices, such as industrial control equipment, communication equipment (such as servers, base stations), power equipment, instruments and meters, and security monitoring equipment. It is understandable that the switching power supply in the embodiment of the present application is intended to include but is not limited to application in these and any other suitable types of equipment.

[0050] Figure 1a This is a schematic diagram of the structure of a switching power supply in an embodiment of the present application, referring to Figure 1a The switching power supply 10 includes a controller 30 and a power chip 20. The power chip 20 includes a power device 50 and a driver chip 40. The power device 50 includes a main power tube Q2, a rectifier tube Q1, a power inductor L, a capacitor C and other devices. The power device 50 is connected to the load RL. The controller 30 is connected to the driver chip 40. The driver chip 40 is respectively connected to the control terminal GH of the main power tube Q2 and the control terminal GL of the rectifier tube Q1 to control the conduction and disconnection of the main power tube Q2 and the rectifier tube Q1. In addition, Vin represents the bus voltage of the switching power supply 10, and VO represents the output voltage of the switching power supply 10.

[0051] The above-mentioned main power tube and rectifier tube as well as the transistors and switches described below can be one or more of various types of switch devices such as metal oxide semiconductor field effect transistor (MOSFET), bipolar junction transistor (BJT), insulated gate bipolar transistor (IGBT), silicon carbide (SiC) power tube, etc., and the embodiments of the present application will not list them one by one. Each switch device can include a first end, a second end and a control end, wherein the control end is used to control the conduction or disconnection of the switch device. When the switch device is turned on, current can be transmitted between the first end and the second end of the switch device, and when the switch device is disconnected, current cannot be transmitted between the first end and the second end of the switch device. In addition, the controller can be a general central processing unit (CPU), a general processor, a digital signal processing (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. The controller mentioned above may also be a combination that realizes computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0052] In some examples, reference Figure 1a , the main power tube Q2 and the rectifier tube Q1 can be applied to a half-bridge structure. In addition, the driving chip 40 has a driving circuit 60, and the driving circuit 60 is respectively connected to the control end GH of the main power tube Q2 and the control end GL of the rectifier tube Q1. The controller 30 outputs a pulse width modulation (PWM) signal to the power chip 20. The power chip 20 receives PWM signals hin and lin. The PWM signals hin and lin are input into the driving circuit 60. The driving circuit 60 performs relevant processing (such as enhancement processing) on ​​the PWM signal hin to generate a driving signal gh, and performs relevant processing (such as enhancement processing) on ​​the PWM signal lin to generate a driving signal gl. The driving circuit 60 outputs the driving signal gh to the control end GH of the main power tube Q2 to control the conduction and disconnection of the main power tube Q2. And, the driving circuit 60 outputs the driving signal gl to the control end GL of the rectifier tube Q1 to control the conduction and disconnection of the rectifier tube Q1. For example, Figure 1bThis is a signal timing diagram in one embodiment of the present application, refer to Figure 1b In the main power tube conduction stage T1, the drive signal gh is at a high level, controlling the main power tube Q2 to be turned on. The drive signal gl is at a low level, controlling the rectifier tube Q1 to be turned off. In the rectifier tube conduction stage T2, the drive signal gh is at a low level, controlling the main power tube Q2 to be turned off. The drive signal gl is at a high level, controlling the rectifier tube Q1 to be turned on.

[0053] The driving circuit in the embodiment of the present application may include a gate driver to control the on and off of the main power tube and the rectifier tube through the gate driver. Figure 2 This is a schematic diagram of the structure of a power chip in an embodiment of the present application, referring to Figure 2 The driving circuit 60 includes a first gate driving circuit 61 and a second gate driving circuit 62. The controller 30 is connected to the input end of the first gate driving circuit 61 and the input end of the second gate driving circuit 62 respectively. The output end of the first gate driving circuit 61 is connected to the control end GH of the main power tube Q2. The output end of the second gate driving circuit 62 is connected to the control end GL of the rectifier tube Q1. The first power supply end of the first gate driving circuit 61 is connected to the first power supply end BOOT. The second power supply end of the first gate driving circuit 61 is connected to the first end SW of the rectifier tube Q1. The first power supply end of the second gate driving circuit 62 is connected to the second power supply end VCC. The second power supply end of the second gate driving circuit 62 is grounded. In practical applications, the first gate driving circuit 61 receives the PWM signal hin output by the controller 30. The first gate driving circuit 61 performs relevant processing (such as enhancement processing) on ​​the PWM signal hin to generate a driving signal gh. The driving signal gh is output to the control end GH of the main power tube Q2 to control the conduction and disconnection of the main power tube Q2. The second gate drive circuit 62 receives the PWM signal lin output by the controller 30, and performs relevant processing (such as enhancement processing) on ​​the PWM signal lin to generate a drive signal gl, and the drive signal gl is output to the control terminal GL of the rectifier tube Q1 to control the conduction and disconnection of the rectifier tube Q1.

[0054] In some other examples, reference Figure 3a to Figure 3c , Figure 3a to Figure 3cThey are schematic diagrams of the structure of a power chip in another embodiment of the present application. Among them, the main power tubes Q2a, Q2b and the rectifier tubes Q1a, Q1b can also be applied to the full bridge (H bridge) structure. In addition, the drive circuit 60 is respectively connected to the control terminal GHa of the main power tube Q2a, the control terminal GHb of the main power tube Q2b, the control terminal GLa of the rectifier tube Q1a, and the control terminal GLb of the rectifier tube Q1b. The controller 30 outputs a PWM signal to the power chip 20. The power chip 20 receives the PWM signals hina, hinb, lina, and linb. The PWM signals hina~linb are input to the drive circuit 60. The drive circuit 60 performs relevant processing on the PWM signals hina~linb (for example, For example, the enhanced processing generates driving signals gha to glb, the driving signal gha is output to the control terminal GHa of the main power tube Q2a to control the on and off of the main power tube Q2a, the driving signal ghb is output to the control terminal GHb of the main power tube Q2b to control the on and off of the main power tube Q2b, the driving signal gla is output to the control terminal GLa of the rectifier tube Q1a to control the on and off of the rectifier tube Q1a, and the driving signal glb is output to the control terminal GLb of the rectifier tube Q1b to control the on and off of the rectifier tube Q1b. For example, Figure 4 This is a signal timing diagram in another embodiment of the present application, refer to Figure 4 In the T1 stage, the drive signal gha is at a high level, controlling the main power tube Q2a to be turned on. The drive signal gla is at a low level, controlling the rectifier tube Q1a to be turned off. The drive signal ghb is at a low level, controlling the main power tube Q2b to be turned off. The drive signal glb is at a high level, controlling the rectifier tube Q1b to be turned on. In the T2 stage, the drive signal gha is at a low level, controlling the main power tube Q2a to be turned off. The drive signal gla is at a high level, controlling the rectifier tube Q1a to be turned on. The drive signal ghb is at a high level, controlling the main power tube Q2b to be turned on. The drive signal glb is at a low level, controlling the rectifier tube Q1b to be turned on.

[0055] Reference Figure 3a to Figure 3bThe driving circuit 60 includes a first gate driving circuit 61a, a second gate driving circuit 62a, a first gate driving circuit 61b, and a second gate driving circuit 62b. The controller 30 is respectively connected to the input end of the first gate driving circuit 61a and the input end of the second gate driving circuit 62b. The output end of the first gate driving circuit 61a is connected to the control end GHa of the main power tube Q2a, the output end of the second gate driving circuit 62a is connected to the control end GLa of the rectifier tube Q1a, the output end of the first gate driving circuit 61b is connected to the control end GHb of the main power tube Q2b, and the output end of the second gate driving circuit 62b is connected to the control end GLb of the rectifier tube Q1b. The first power supply end of the first gate drive circuit 61a is connected to the first power supply end BOOT, the second power supply end of the first gate drive circuit 61a is connected to the first end SWa of the rectifier tube Q1a, the first power supply end of the second gate drive circuit 62a is connected to the second power supply end VCC, the second power supply end of the second gate drive circuit 62a is grounded, the first power supply end of the first gate drive circuit 61b is connected to the first power supply end BOOT, the second power supply end of the first gate drive circuit 61b is connected to the first end SWb of the rectifier tube Q1b, the first power supply end of the second gate drive circuit 62b is connected to the second power supply end VCC, and the second power supply end of the second gate drive circuit 62b is grounded. In actual application, the first gate drive circuit 61a receives the PWM signal hina output by the controller 30, and the first gate drive circuit 61a performs relevant processing (such as enhancement processing) on ​​the PWM signal hina to generate a drive signal gha, and the drive signal gha is output to the control end GHa of the main power tube Q2a to control the conduction and disconnection of the main power tube Q2a. The second gate drive circuit 62a receives the PWM signal lina output by the controller 30, and the second gate drive circuit 62a performs relevant processing (such as enhancement processing) on ​​the PWM signal lina to generate a drive signal gla, and the drive signal gla is output to the control terminal GLa of the rectifier tube Q1a to control the on and off of the rectifier tube Q1a. The first gate drive circuit 61b receives the PWM signal hinb output by the controller 30, and the first gate drive circuit 61b performs relevant processing (such as enhancement processing) on ​​the PWM signal hinb to generate a drive signal ghb, and the drive signal ghb is output to the control terminal GHb of the main power tube Q2b to control the on and off of the main power tube Q2b. The second gate drive circuit 62b receives the PWM signal linb output by the controller 30, and the second gate drive circuit 62b performs relevant processing (such as enhancement processing) on ​​the PWM signal linb to generate a drive signal glb, and the drive signal glb is output to the control terminal GLb of the rectifier tube Q1b to control the on and off of the rectifier tube Q1b.

[0056] In order to improve the control accuracy of the main power tube and the rectifier tube, in the control scheme of the switching power supply, the information of the inductor current can be used as the input of the loop feedback, so that the drive circuit can receive and control the on and off of the main power tube and the rectifier tube according to the PWM signal regulated by the inductor current. However, as the switching frequency increases, the on time of the main power tube becomes shorter and shorter, resulting in inaccurate accuracy of directly sampling the inductor current, which in turn affects the control effect. For this reason, refer to Figures 2 to 3c , the present application sets a current generating circuit (eg Figure 2 70 of them Figure 3a 70a in Figure 3b 70b, Figure 3c 70a and 70b), the required inductor current is synthesized by the current generating circuit, so that the required inductor current can be obtained without directly sampling the current flowing through the main power tube, thereby avoiding the problem of inaccurate sampling accuracy caused by sampling the inductor current.

[0057] It is worth mentioning that the main power tube and the rectifier tube corresponding to the current generating circuit are connected to each other and then connected to the same end of the power inductor L. And, referring to Figure 2 , the main power tube and the rectifier tube corresponding to the current generating circuit 70 can be applied to the half-bridge structure. Figure 3a to Figure 3c , the main power tube and rectifier tube corresponding to the current generating circuit can also be applied to the full-bridge structure. And, refer to Figure 3a , a current generating circuit 70a can be set corresponding to the main power tube Q2a and the rectifier tube Q1a. Figure 3b , it is also possible to set a current generating circuit 70b corresponding to the main power tube Q2b and the rectifier tube Q1b. Figure 3c , not only can a current generating circuit 70a be set corresponding to the main power tube Q2a and the rectifier tube Q1a, but also a current generating circuit 70b can be set corresponding to the main power tube Q2b and the rectifier tube Q1b. The following is a detailed description of the main power tube and the rectifier tube corresponding to the current generating circuit 70 applied to the half-bridge structure as an example. For the working process of the main power tube and the rectifier tube corresponding to the current generating circuit provided in the embodiment of the present application applied to the full-bridge structure, reference can be made to the working process applied to the half-bridge structure described below, and the repeated parts will not be discussed.

[0058] Figure 5 This is a schematic diagram of the structure of a driver chip in an embodiment of the present application, referring to Figure 5In order to obtain the inductor current, a current generating circuit 70 is provided in the driving chip 40, so as to synthesize the inductor current through the current generating circuit 70. Specifically, the current generating circuit 70 includes: a sampling circuit 71, a slope control circuit 72 and a current output circuit 73, the sampling circuit 71 is connected to the rectifier tube Q1 and the current output circuit 73, the slope control circuit 72 is connected to the current output circuit 73, and the current output circuit 73 is connected to the controller 30. Among them, the current output circuit 73 can output the rectifier tube sampling current in the rectifier tube conduction stage of each control cycle, and output the main power tube analog current in the main power tube conduction stage of each control cycle. The sampling circuit 71 can control the current output circuit 73 to generate the rectifier tube sampling current in the rectifier tube conduction stage according to the current flowing through the rectifier tube Q1 in the rectifier tube conduction stage of each control cycle, thereby realizing the rectifier tube sampling current based on the current detection flowing through the rectifier tube Q1, and outputting the rectifier tube sampling current to the controller 30. Furthermore, the slope control circuit 72 can control the current output circuit 73 to output the k+1th main power tube analog current in the main power tube conduction stage in the k+1th control cycle according to the rectifier tube sampling current output by the current output circuit 73 in the rectifier tube conduction stage and the kth main power tube analog current output in the main power tube conduction stage in the kth control cycle, thereby achieving the k+1th main power tube analog current based on the current simulation output by the current output circuit 73 in the rectifier tube conduction stage and the main power tube conduction stage, and outputting the k+1th main power tube analog current to the controller 30. After receiving the rectifier tube sampling current and the k+1th main power tube analog current, the controller 30 synthesizes them to form an inductor current including the rectifier tube sampling current and the k+1th main power tube analog current, thereby achieving the desired inductor current without directly sampling the current flowing through the main power tube Q2, thereby avoiding the problem of inaccurate sampling accuracy caused by sampling the inductor current. Based on this, the controller 30 can regulate the PWM signal according to the synthesized inductor current, and then output the regulated PWM signal to the drive circuit 60, so that the drive circuit 60 can control the conduction and disconnection of the main power tube Q2 and the rectifier tube Q1 according to the regulated PWM signal, thereby improving the control accuracy of the main power tube Q2 and the rectifier tube Q1.

[0059] In specific applications, refer to Figure 2 and Figure 5The controller 30 outputs a PWM signal hin to the first gate drive circuit 61 according to the synthesized inductor current, so that the first gate drive circuit 61 generates a drive signal gh according to the PWM signal hin, thereby improving the control accuracy of controlling the on and off of the main power tube Q2. In addition, the controller 30 outputs a PWM signal lin to the second gate drive circuit 62 according to the synthesized inductor current, so that the second gate drive circuit 62 generates a drive signal gl according to the PWM signal lin, thereby improving the control accuracy of controlling the on and off of the rectifier tube Q1.

[0060] Furthermore, since the current generating circuit in the present application is connected to the rectifier tube, the inductor current can be synthesized, so there is no need to set an additional pin on the driver chip to connect the output voltage VO of the switching power supply 10. This is suitable for mainstream small-size, low-pin package products, which can reduce costs and expand the scope of application.

[0061] Furthermore, the kth main power tube analog current and the rectifier tube sampling current output in the kth control cycle can be used as feedback parameters for outputting the k+1th main power tube analog current in the k+1th control cycle, thereby improving the accuracy of outputting the k+1th main power tube analog current in the k+1th control cycle. In addition, the current generating circuit in the present application can also adapt to the change in the duty cycle of the pulse width modulation signal (such as the drive signal gl, gh), and the fitting time of the slope of the k+1th main power tube analog current tracks the conduction time of the main power tube in real time.

[0062] Continue to refer to Figure 5 The sampling circuit 71 is connected to the first end SW and the second end PGND of the rectifier tube Q1 respectively, and the sampling circuit 71 can also be connected to the control end GL of the rectifier tube Q1, so that the sampling circuit 71 receives the driving signal gl, and thus in response to the driving signal gl, it can control the current output circuit 73 to generate the rectifier tube sampling current according to the current of the first end SW of the rectifier tube Q1 and the current of the second end PGND of the rectifier tube Q1 during the rectifier tube conduction stage. And the slope control circuit 72 can also be connected to the control end GH of the main power tube Q2, so that the slope control circuit 72 receives the driving signal gh, and thus in response to the driving signal gh, in the main power tube conduction stage, the current output circuit 73 is controlled to generate the k+1th main power tube analog current.

[0063] The sampling circuit, slope control circuit and current output circuit in the embodiments of the present application are described below in conjunction with specific embodiments. It is understandable that the following embodiments are for better explanation of the present application, but do not limit the present application.

[0064] Figure 6 This is a schematic diagram of the specific structure of the driver chip in one embodiment of the present application, referring to Figure 6The sampling circuit 71 includes a current detection circuit 711 and a third sampling circuit 712. The current detection circuit 711 is respectively connected to the control terminal GL, the first terminal SW and the second terminal PGND of the rectifier tube Q1. The third sampling circuit 712 is respectively connected to the control terminal GL of the rectifier tube Q1, the current detection circuit 711 and the current output circuit 73. In specific applications, the current detection circuit 711 can respond to the drive signal gl and generate a first control signal according to the current of the first terminal SW of the rectifier tube Q1 and the current of the second terminal PGND of the rectifier tube Q1 during the conduction stage of the rectifier tube. The third sampling circuit 712 can also respond to the drive signal gl and output the first control signal to the current output circuit 73 during the conduction stage of the rectifier tube, so that the control current output circuit 73 can generate a rectifier tube sampling current during the conduction stage of the rectifier tube. With this arrangement, the fitting time of the slope of the rectifier tube sampling current can track the conduction time of the rectifier tube in real time.

[0065] In the present application, the current detection circuit 711 and the third sampling circuit 712 can be implemented using one or more circuit structures. For example, Figure 7 This is a schematic diagram of the specific structure of a driver chip in another embodiment of the present application, referring to Figure 7The current detection circuit 711 includes a first transistor QS1, a second transistor QS2, a third transistor QS3, a fourth transistor QS4 and a second error amplifier (EA) 731. The control end of the first transistor QS1, the control end of the second transistor QS2 and the control end GL of the rectifier Q1 are connected to each other. The first end of the first transistor QS1 is connected to the first end SW of the rectifier Q1, and the second end of the first transistor QS1 is connected to the negative phase input end of the second error amplifier 7111. The first end of the second transistor QS2 is connected to the second end PGND of the rectifier Q1, and the second end of the second transistor QS2 is connected to the positive phase input end of the second error amplifier 7111. The control end of the third transistor QS3, the control end of the fourth transistor QS4 and the output end of the second error amplifier 7111 are connected to each other. The first end of the third transistor QS3 is connected to the second end of the first transistor QS1, and the second end of the third transistor QS3 is connected to the second power supply end VCC. The first end of the fourth transistor QS4 is connected to the second end of the second transistor QS2, and the second end of the fourth transistor QS4 is connected to the second power supply terminal VCC. The output end of the second error amplifier 7111 is also connected to the third sampling circuit 712. In addition, the third sampling circuit 712 includes a third sample and hold circuit (Sample and Hold circuit, S / H) 7121, and the control end of the third sample and hold circuit 7121 is connected to the control end GL of the rectifier tube Q1, so that the third sample and hold circuit 7121 can be controlled by the driving signal gl to work. In addition, the input end of the third sample and hold circuit 7121 is connected to the output end of the error amplifier in the current detection circuit 711, and the output end of the third sample and hold circuit 7121 is connected to the current output circuit 73.

[0066] In specific applications, the first transistor QS1 and the second transistor QS2 are turned on when the driving signal gl is at a low level, the first transistor QS1 connects the current of the first end SW of the rectifier tube Q1 to the negative phase input terminal of the second error amplifier 7111, the second transistor QS2 connects the current of the second end PGND of the rectifier tube Q1 to the positive phase input terminal of the second error amplifier 7111, and the output terminal of the second error amplifier 7111 outputs the first control signal. When the driving signal gl is at a high level, and its output is equal to the input, the third sampling and holding circuit directly outputs the first control signal to the current output circuit 73, and the control current output circuit 73 can generate the rectifier tube sampling current in the rectifier tube conduction stage. When the driving signal gl is at a low level, the first control signal is maintained.

[0067] It is understandable that the current generating circuit can work in K consecutive control cycles, each of which includes a main power tube conduction phase and a rectifier tube conduction phase. The main power tube conduction phase in each control cycle occurs before the rectifier tube conduction phase. K is an integer greater than 1.

[0068] Continue to refer to Figure 6 , the slope control circuit 72 includes a first sampling circuit 721, a second sampling circuit 722 and a control circuit 723, the first sampling circuit 721 is connected to the current output circuit 73, the second sampling circuit 722 is connected to the current output circuit 73, and the control circuit 723 is connected to the first sampling circuit 721, the second sampling circuit 722 and the current output circuit 73 respectively. Among them, the first sampling circuit 721 can collect the first sampling voltage corresponding to the output of the kth main power tube analog current by the current output circuit 73 in the main power tube conduction stage of the kth control cycle, and output the first sampling voltage to the control circuit 723. In addition, the second sampling circuit 722 can collect the second sampling voltage corresponding to the output of the rectifier tube sampling current by the current output circuit 73 in the rectifier tube conduction stage of the kth control cycle, and output the second sampling voltage to the control circuit 723. The control circuit 723 receives the first sampling voltage and the second sampling voltage, and controls the current output circuit 73 to output the k+1th main power tube analog current in the main power tube conduction phase of the k+1th control cycle according to the first sampling voltage and the second sampling voltage. Wherein, and 1≤k≤K. With this arrangement, the voltage corresponding to the kth main power tube analog current output in the kth control cycle and the rectifier tube sampling current can be used as a feedback parameter for outputting the k+1th main power tube analog current in the k+1th control cycle, thereby improving the accuracy of outputting the k+1th main power tube analog current in the k+1th control cycle.

[0069] In a specific implementation, the first sampling circuit can be controlled to collect the analog current of the k+1th main power tube output by the current output circuit during the first period in the main power tube conduction stage, convert the collected current into a first sampling voltage, and directly output the first sampling voltage during the first period. In addition, the first sampling circuit is also controlled to maintain the output of the first sampling voltage during the rectifier tube conduction stage. Among them, the first period is the time period between the first reference moment and the end moment in the main power tube conduction stage. In actual application, the first pulse control signal is input to the first sampling circuit to control the first sampling circuit. Specifically, when the first pulse control signal is at the first level, the first sampling circuit is controlled to collect the analog current of the k+1th main power tube output by the current output circuit, and convert the collected current into the first sampling voltage and then output it. When the first pulse control signal is at the second level, the first sampling voltage is kept output. Among them, a time period in which the first pulse control signal is at the first level is used as the above-mentioned first period.

[0070] In some examples, the first reference time of the first period can be close to the end time of the main power tube conduction stage, so as to collect the first sampled voltage in the time period that is about to end in the main power tube conduction stage. The first reference time is a time between the start time and the end time of the main power tube conduction stage, so that part of the time period in the main power tube conduction stage is set as the first period. For example, Figure 8a This is a signal timing diagram in another embodiment of the present application, refer to Figure 8a , taking the first level as a high level, the second level as a low level, and the T1 stage as an example, the time at which the rising edge corresponding to the high level of the first pulse control signal SH1 is located is the first reference time, and the time at which the falling edge corresponding to the high level of the first pulse control signal SH1 is located is the end time of the main power tube conduction stage, and by bringing the first reference time close to the end time of the main power tube conduction stage, the time period TS1 close to the end time of the main power tube conduction stage is set as the first period. Or, for example, Figure 8c This is a signal timing diagram in another embodiment of the present application, refer to Figure 8c By setting the first reference time close to the start time of the main power tube conduction stage, most of the time period TS1 in the main power tube conduction stage is set as the first period. Alternatively, since the main power tube conduction stage is short, the first reference time can be set to the start time of the main power tube conduction stage, so that the first sampled voltage is collected during the entire main power tube conduction stage, thereby improving the accuracy of the first sampled voltage. For example, Figure 8b This is a signal timing diagram in another embodiment of the present application, refer to Figure 8b , aligning the first reference time with the start time of the main power tube conduction phase, so that the entire main power tube conduction phase is set as the first period. It can be understood that the above description is based on the example of the first level being a high level and the second level being a low level. In actual applications, the first level can also be a low level and the second level can also be a high level.

[0071] In the present application, the first sampling circuit 721 can be implemented by using one or more circuit structures. Figure 7 The first sampling circuit 721 includes a first sample and hold circuit (Sample and Hold circuit, S / H) 7211, wherein the control end of the first sample and hold circuit 7211 is used to receive the first pulse control signal SH1, so that the first sample and hold circuit 7211 can work under the control of the first pulse control signal SH1. In addition, the input end of the first sample and hold circuit 7211 is connected to the output end of the current output circuit 73, and the output end of the first sample and hold circuit 7211 is connected to the control circuit 723.

[0072] In the specific implementation, the second sampling circuit is controlled to collect the rectifier tube sampling current output by the current output circuit during the second period in the rectifier tube conduction stage, convert the collected current into a second sampling voltage, and directly output the second sampling voltage during the second period. In addition, the second sampling circuit is also controlled to maintain the second sampling voltage output during the main power tube conduction stage. Among them, the second period is the time period between the start time and the second reference time in the rectifier tube conduction stage. In actual application, the second pulse control signal is input to the second sampling circuit. When the second pulse control signal is at the first level, the second sampling circuit is controlled to collect the rectifier tube sampling current output by the current output circuit, and convert the collected current into the second sampling voltage and then output it. When the second pulse control signal is at the second level, the second sampling voltage is kept output. Among them, a time period in which the second pulse control signal is at the first level is used as the above-mentioned second period.

[0073] In some examples, the second reference time of the second period can be close to the start time of the rectifier conduction stage, so as to collect the second sampled voltage in the time period just beginning in the rectifier conduction stage. The second reference time is a time between the start time and the end time of the rectifier conduction stage, so that part of the time period in the rectifier conduction stage is set as the second period. In addition, the second sampling circuit 722 needs to be controlled to maintain the second sampled voltage output in the remaining periods except the second period in the rectifier conduction stage. For example, referring to Figure 8a and Figure 8b The moment of the rising edge corresponding to the high level of the second pulse control signal SH2 is the starting moment of the rectifier tube conduction stage, and the moment of the falling edge corresponding to the high level of the second pulse control signal SH2 is the second reference moment. By bringing the second reference moment close to the starting moment of the rectifier tube conduction stage, the time period TS2 close to the starting moment of the rectifier tube conduction stage is made the second period.

[0074] It is understandable that the first period and the second period may be the same, or the first period may be greater than the second period, or the first period may be less than the second period, and this is not limited here.

[0075] In the present application, the second sampling circuit 722 may also be implemented using one or more circuit structures. Figure 7The second sampling circuit 722 includes a second sample and hold circuit (Sample and Hold circuit, S / H) 7221. The control end of the second sample and hold circuit 7221 is used to receive the second pulse control signal SH2, so that the second sample and hold circuit 7221 can work under the control of the second pulse control signal SH2. In addition, the input end of the second sample and hold circuit 7221 is connected to the output end of the current output circuit 73, and the output end of the second sample and hold circuit 7221 is connected to the control circuit 723.

[0076] In the present application, the control circuit 723 can be implemented by one or more circuit structures. Figure 7 , the control circuit 723 includes: a regulation generation circuit 730, a first switch K1 and a first controlled current source 740, wherein the regulation generation circuit 730 is connected to the first sampling circuit 721 and the second sampling circuit 722, the first end of the first switch K1 is connected to the first end of the first controlled current source 740, and the second end of the first switch K1 is connected to the current output circuit 73, that is, the first controlled current source 740 is connected to the current output circuit 73 through the first switch K1, the second end of the first controlled current source 740 is grounded, and the control end of the first controlled current source 740 is connected to the regulation generation circuit 730. In specific applications, the regulation generation circuit 730 can receive the first sampling voltage and the second sampling voltage, and generate a regulation generation signal according to the first sampling voltage and the second sampling voltage. The regulation generation signal is input to the control end of the first controlled current source 740, and can control the first controlled current source 740 to generate a first current. Furthermore, the first switch K1 is in the on state during the main power tube conduction stage, and the first controlled current source 740 is connected to the current output circuit 73, so that during the main power tube conduction stage, the first current can be output to the current output circuit 73, so as to generate the k+1th main power tube analog current through the first current control current output circuit 73. With this arrangement, the fitting time of the slope of the k+1th main power tube analog current can track the conduction time of the main power tube in real time.

[0077] The first controlled current source 740 is set as a voltage controlled current source (Voltage Controlled Current Source, VCCS), and the regulation generation circuit 730 outputs a control voltage to the control terminal of the first controlled current source 740, thereby controlling the first current generated by the first controlled current source 740, and the first current can change according to the magnitude of the control voltage. For example, the first current increases as the control voltage increases. Alternatively, the first controlled current source 740 can also be formed by a current mirror structure, which is not limited here.

[0078] Reference Figure 7, the regulation generation circuit 730 includes a first error amplifier (EA) 731, wherein the negative phase input terminal of the first error amplifier 731 is connected to the first sampling circuit 721, the positive phase input terminal of the first error amplifier 731 is connected to the second sampling circuit 722, and the output terminal of the first error amplifier 731 is connected to the control terminal of the first controlled current source 740. In actual application, the negative phase input terminal of the first error amplifier 731 receives the first sampling voltage output by the first sampling circuit 721, and the positive phase input terminal of the first error amplifier 731 receives the second sampling voltage output by the second sampling circuit 722, so as to output the control voltage according to the first sampling voltage and the second sampling voltage. For example, according to the magnitude relationship between the first sampling voltage and the second sampling voltage, the voltage value of the output control voltage will change.

[0079] Further, refer to Figure 7 The regulation generation circuit 730 further includes a second switch K2, which is connected between the negative phase input terminal of the first error amplifier 731 and the positive phase input terminal of the first error amplifier 731. In practical applications, the second switch K2 is turned on in the third period, which is the period other than the second period in the conduction stage of the rectifier tube. Figures 8a to 8c , the control end of the second switch K2 receives the third pulse control signal SH3, and is turned on when the third pulse control signal SH3 is at a second level (e.g., a low level), so that the negative phase input terminal and the positive phase input terminal of the first error amplifier 731 are turned on. And, when the third pulse control signal SH3 is at a first level (e.g., a high level), the control end of the second switch K2 is turned off, so that the negative phase input terminal and the positive phase input terminal of the first error amplifier 731 are disconnected, that is, the period when the third pulse control signal SH3 is at the second level is the third period. Exemplarily, taking the second level of the third pulse control signal SH3 as a low level and the first level of the third pulse control signal SH3 as a high level as an example, refer to Figures 8a to 8c , the third pulse control signal SH3 is at a low level in the third period TS3. Figure 8a and Figure 8b , the falling edge of the third pulse control signal SH3 is aligned with the falling edge of the second pulse control signal SH2, and the rising edge of the third pulse control signal SH3 and the end of the conduction phase of the rectifier tube have a certain interval length, that is, the second period TS2 ends and the third period TS3 begins. Or, refer to Figure 8c The falling edge of the third pulse control signal SH3 is aligned with the falling edge of the second pulse control signal SH2, and the rising edge of the third pulse control signal SH3 is aligned with the end time of the conduction phase of the rectifier tube. In addition, the third period can be the same as the second period, or the third period is greater than the second period.

[0080] Continue to refer to Figure 7, the current output circuit 73 includes a second controlled current source 750, the control end of the second controlled current source 750 is connected to the sampling circuit 71 and the slope control circuit 72, the first end of the second controlled current source 750 is connected to the second power supply end VCC, and the second end of the second controlled current source 750 is connected to the controller 30. Further, the current output circuit 73 also includes a voltage dividing resistor RS, and the second end of the second controlled current source 750 is grounded through the voltage dividing resistor RS. Based on this, the sampling circuit 71 can input a voltage to the control end of the second controlled current source 750 to control the second controlled current source 750 to output the rectifier tube sampling current in response to the voltage generated by its control end according to the control of the sampling circuit 71 during the conduction stage of the rectifier tube. In addition, the slope control circuit 72 inputs a current to the control end of the second controlled current source 750, and regulates the voltage of the control end of the second controlled current source 750 according to the current, so that in the conduction phase of the main power tube, the second controlled current source 750 can be controlled to respond to the voltage generated by its control end according to the control of the slope control circuit 72, and output the k+1th main power tube analog current.

[0081] The second controlled current source 750 is also set to VCCS, so that the second controlled current source 750 generates a rectifier tube sampling current according to the voltage input to its control end by the sampling circuit 71, and adjusts the voltage of its control end according to the current input to its control end by the slope control circuit 72, so that the second controlled current source 750 generates the k+1th main power tube analog current. The k+1th main power tube analog current changes according to the change of the voltage at its control end. For example, when the voltage at the control end of the second controlled current source 750 decreases, the second controlled current source 750 can generate the k+1th main power tube analog current with an increasing current value, and increase the slope of the k+1th main power tube analog current. Alternatively, the second controlled current source 750 can also be formed by a current mirror structure, which is not limited here.

[0082] Below Figure 7 As an example, combining the structure shown Figure 8a The working process of the current generating circuit provided in the embodiment of the present application is described. Figure 8b and Figure 8cThe working process of can refer to the working process described below, and the repeated parts are not discussed. In addition, IL represents the actual current flowing through the power inductor, IA represents the current generated by the first controlled current source 740, and IMON represents the inductor current output by the current generating circuit 70. In addition, IMON is synthesized by the main power tube analog current in the main power tube conduction stage and the rectifier tube sampling current in the rectifier tube conduction stage. In addition, ZQk represents the kth control cycle, the kth control cycle ZQk includes the main power tube conduction stage T1 and the rectifier tube conduction stage T2, and the main power tube conduction stage T1 outputs the kth main power tube analog current IQ1. ZQk+1 represents the k+1th control cycle, the k+1th control cycle ZQk+1 includes the main power tube conduction stage T3 and the rectifier tube conduction stage T4, and the main power tube conduction stage T3 outputs the k+1th main power tube analog current IQ3. ZQk+2 represents the k+2th control cycle, and the k+2th control cycle ZQk+2 includes the main power tube conduction stage T5 and the rectifier tube conduction stage, and the main power tube conduction stage T5 outputs the k+2th main power tube analog current IQ4.

[0083] In the main power tube conduction phase T1, the main power tube Q2 is turned on and the rectifier tube Q1 is turned off. The current IA with a current value of Ia1 acts on the control end of the second controlled current source 750, discharges the voltage of the control end of the second controlled current source 750, so that the voltage of the control end of the second controlled current source 750 is reduced, so that the second controlled current source 750 can generate the kth main power tube analog current IQ1 with an increasing current value. The first sampling and holding circuit 7211 collects the kth main power tube analog current IQ1 near the end of the conduction of the main power tube Q2, obtains a first sampling voltage, and outputs the first sampling voltage.

[0084] In the rectifier conduction phase T2, the main power tube Q2 is turned off and the rectifier Q1 is turned on. The first transistor QS1 and the second transistor QS2 respectively input the current of the first end SW of the rectifier Q1 and the current of the second end PGND of the rectifier Q1 into the second error amplifier 7111, so that the second error amplifier 7111 outputs the first control signal. The third sampling and holding circuit outputs the first control signal to the control end of the second controlled current source 750, so that the second controlled current source 750 outputs the rectifier sampling current IQ2 in response to the voltage of the first control signal. The second sampling and holding circuit 7221 collects the rectifier sampling current IQ2 near the start of the rectifier Q1 conduction, obtains the second sampling voltage, and outputs the second sampling voltage. Afterwards, the second switch K2 is disconnected under the control of the third pulse control signal SH3, the first sampling voltage is input to the negative phase input terminal of the first error amplifier 731, and the second sampling voltage is input to the positive phase input terminal of the first error amplifier 731, wherein when the first sampling voltage is less than the second sampling voltage, it indicates that the slope of the analog current IQ1 of the kth main power tube is low, so that the first error amplifier 731 outputs a control voltage V1 whose voltage is increased. The first controlled current source 740 is controlled by the control voltage V1 to adjust the current value of the current IA outputted by it (for example, the current value of the current IA is increased from Ia1 to Ia2). Afterwards, the second switch K2 is turned on under the control of the third pulse control signal SH3, the first error amplifier 731 maintains the output control voltage V1, and the current value of the current IA outputted by the first controlled current source 740 is maintained at Ia2.

[0085] In the main power tube conduction phase T3, the main power tube Q2 is turned on, and the rectifier tube Q1 is turned off. The control end of the second controlled current source 750 is turned on with the first controlled current source 740, and the current IA of the current value Ia2 output by the first controlled current source 740 acts on the control end of the second controlled current source 750, discharges the voltage of the control end of the second controlled current source 750, so that the voltage of the control end of the second controlled current source 750 is reduced, so that the second controlled current source 750 can generate the k+1th main power tube analog current IQ3 with an increasing current value, and the slope of the k+1th main power tube analog current IQ3 is increased compared with the kth main power tube analog current IQ1.

[0086] In the rectifier conduction phase T4, the main power tube Q2 is turned off and the rectifier Q1 is turned on. The first transistor QS1 and the second transistor QS2 respectively input the current of the first end SW of the rectifier Q1 and the current of the second end PGND of the rectifier Q1 into the second error amplifier 7111, so that the second error amplifier 7111 outputs the first control signal. The third sampling and holding circuit outputs the first control signal to the control end of the second controlled current source 750, so that the second controlled current source 750 outputs the rectifier sampling current IQ2 in response to the voltage of the first control signal. The second sampling and holding circuit 7221 collects the rectifier sampling current IQ2 near the start of the rectifier Q1 conduction, obtains the second sampling voltage, and outputs the second sampling voltage. Afterwards, the second switch K2 is disconnected under the control of the third pulse control signal SH3, the first sampling voltage is input to the negative phase input terminal of the first error amplifier 731, and the second sampling voltage is input to the positive phase input terminal of the first error amplifier 731, wherein when the first sampling voltage is greater than the second sampling voltage, it indicates that the slope of the analog current IQ3 of the k+1th main power tube is high, so that the first error amplifier 731 outputs a control voltage V2 that reduces the voltage. The first controlled current source 740 is controlled by the control voltage V2 to adjust the current value of the current IA outputted therefrom (for example, reducing the current value of the current IA from Ia2 to Ia3). Afterwards, the second switch K2 is turned on under the control of the third pulse control signal SH3, the first error amplifier 731 maintains the output control voltage V2, and the current value of the current IA outputted by the first controlled current source 740 remains at Ia3.

[0087] In the main power tube conduction stage T5, the main power tube Q2 is turned on, and the rectifier tube Q1 is turned off. The control end of the second controlled current source 750 is turned on with the first controlled current source 740, and the current IA of the current value Ia3 output by the first controlled current source 740 acts on the control end of the second controlled current source 750, discharges the voltage of the control end of the second controlled current source 750, so that the voltage of the control end of the second controlled current source 750 is reduced, so that the second controlled current source 750 can generate the k+2 main power tube analog current IQ4 with an increasing current value, and the slope of the k+2 main power tube analog current IQ4 is reduced compared with the k+1 main power tube analog current IQ3.

[0088] The processes of the remaining stages can be deduced in the same way and will not be elaborated here.

[0089] Based on the above description, the current generating circuit in the embodiment of the present application automatically changes the slope of the main power tube analog current with the change of the inductance value of the power inductor, so that the inductor current output by the current generating circuit can adapt to the change of the inductance value of the power inductor. In addition, the current generating circuit in the present application can also adapt to the change of the duty cycle of the driving signals gl and gh, and the fitting time of the slope of the main power tube analog current tracks the conduction time of the main power tube in real time.

[0090] In addition, by briefly charging and discharging the control terminal of the second controlled current source to dynamically adjust the current output by the second controlled current source, the control speed can be improved, which is more suitable for high-speed scenarios. Moreover, the power consumption can be reduced and the occupied area of ​​the entire current generation circuit can be reduced.

[0091] Fig. 9 This is a schematic diagram of the specific structure of a driver chip in another embodiment of the present application. This embodiment is a modification of the implementation method in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here. Fig. 9 The regulation generation circuit 730 includes a comparator (COMP) 732, a selector 733, and a signal generator 734. The negative phase input terminal of the comparator 732 is connected to the first sampling circuit 721, the positive phase input terminal of the comparator 732 is connected to the second sampling circuit 722, the output terminal of the comparator 732 is connected to the first input terminal of the selector 733, the second input terminal of the selector 733 is used to receive the selection trigger signal SH4, the first output terminal of the selector 733 is connected to the first control terminal of the signal generator 734, the second output terminal of the selector 733 is connected to the second control terminal of the signal generator 734, and the output terminal of the signal generator 734 is connected to the control terminal of the first controlled current source 740. In actual application, the negative phase input terminal of the comparator 732 receives the first sampling voltage, and the positive phase input terminal of the comparator 732 receives the second sampling voltage, so as to output the selection control signal as a voltage signal according to the first sampling voltage and the second sampling voltage. Also, the selector 733 can receive a selection control signal and a selection trigger signal SH4 , so that in response to the selection control signal and the selection trigger signal, the control signal generator 734 outputs a control voltage according to the first reference current or the second reference current.

[0092] Exemplarily, if the trigger signal is selected to be a first level (e.g., a high level), and if the control signal is selected to be a first level (e.g., a high level), the selector may control the signal generator to output a first reference current to the control end of the first controlled current source, so that the control end of the first controlled current source is charged, so that the control voltage of the control end of the first controlled current source is increased. If the control signal is selected to be a second level (e.g., a low level), the selector may control the signal generator to output a second reference current to the control end of the first controlled current source, so that the control end of the first controlled current source is discharged, so that the control voltage of the control end of the first controlled current source is reduced. Furthermore, if the trigger signal is selected to be a second level (e.g., a low level), the selector does not control the output of the signal generator.

[0093] Further, refer to Fig. 9 The regulation generation circuit 730 includes a third switch K3, a fourth switch K4, a first current source IY1, a second current source IY2, and a storage capacitor CS, wherein a first end of the first current source IY1 is connected to a first reference signal end, a second end of the first current source IY1 is connected to a first end of the third switch K3, a second end of the third switch K3 is connected to a control end of the first controlled current source 740, and a control end of the third switch K3 is connected to a first output end of the selector 733. A first end of the fourth switch K4 is connected to a control end of the first controlled current source 740, a second end of the fourth switch K4 is connected to a first end of the second current source IY2, and a control end of the fourth switch K4 is connected to a second output end of the selector 733. A second end of the second current source IY2 is connected to a second reference signal end, a first end of the storage capacitor CS is connected to a control end of the first controlled current source 740, and a second end of the storage capacitor CS is connected to a second reference signal end. Furthermore, the first current source IY1 is used to output a first reference current, and the second current source IY2 is used to output a second reference current. In specific applications, the selector 733 controls the third switch K3 to be turned on, and the first current source IY1 outputs the first reference current to the storage capacitor CS to charge the storage capacitor CS. The voltage after the storage capacitor CS is charged is output as a control voltage to the control end of the first controlled current source 740, so that the voltage of the control end of the first controlled current source 740 is increased. The selector 733 controls the fourth switch K4 to be turned on, and the second current source IY2 outputs the second reference current to the storage capacitor CS to discharge the storage capacitor CS. The voltage after the storage capacitor CS is discharged is output as a control voltage to the control end of the first controlled current source 740, so that the voltage of the control end of the first controlled current source 740 is reduced. In addition, the voltage of the first reference signal terminal is higher than the voltage of the second reference signal terminal. For example, the first reference signal terminal can be the second power supply terminal VCC, and the second reference signal terminal can be grounded.

[0094] In practical application, taking the first level of the selection trigger signal SH4 as a high level and the second level of the selection trigger signal SH4 as a low level as an example, the selection trigger signal SH4 is a high level in the fourth period TS4. Fig.10a and Fig.10b , the rising edge of the trigger signal SH4 is selected to be aligned with the falling edge of the second pulse control signal SH2, and the falling edge of the trigger signal SH4 is selected to have a certain interval with the end of the conduction phase of the rectifier tube, that is, the second period TS2 ends and the third period TS3 begins. Or, refer to Fig.10c The rising edge of the trigger signal SH4 is selected to be aligned with the falling edge of the second pulse control signal SH2, and the falling edge of the trigger signal SH4 is selected to be aligned with the end time of the conduction phase of the rectifier tube. In addition, the fourth period can be the same as the second period, or the fourth period is greater than the second period.

[0095] Below Fig. 9 As an example, combining the structure shown Fig.10a The working process of the current generating circuit provided in the embodiment of the present application is described. Fig.10b and Fig.10c The working process of can refer to the working process described below, and the repeated parts are not discussed. In addition, IL represents the actual current flowing through the power inductor, IA represents the current generated by the first controlled current source 740, and IMON represents the inductor current output by the current generating circuit 70. In addition, IMON is synthesized by the main power tube analog current in the main power tube conduction stage and the rectifier tube sampling current in the rectifier tube conduction stage. In addition, ZQk represents the kth control cycle, the kth control cycle ZQk includes the main power tube conduction stage T1 and the rectifier tube conduction stage T2, and the main power tube conduction stage T1 outputs the kth main power tube analog current IQ1. ZQk+1 represents the k+1th control cycle, the k+1th control cycle ZQk+1 includes the main power tube conduction stage T3 and the rectifier tube conduction stage T4, and the main power tube conduction stage T3 outputs the k+1th main power tube analog current IQ3. ZQk+2 represents the k+2th control cycle, and the k+2th control cycle ZQk+2 includes the main power tube conduction stage T5 and the rectifier tube conduction stage, and the main power tube conduction stage T5 outputs the k+2th main power tube analog current IQ4.

[0096] In the main power tube conduction stage T1, the process is basically the same as that in the above embodiment, and will not be described in detail here.

[0097] In the rectifier conduction phase T2, the main power tube Q2 is turned off and the rectifier Q1 is turned on. The first transistor QS1 and the second transistor QS2 respectively input the current of the first end SW of the rectifier Q1 and the current of the second end PGND of the rectifier Q1 into the second error amplifier 7111, so that the second error amplifier 7111 outputs the first control signal. The third sampling and holding circuit 7121 outputs the first control signal to the control end of the second controlled current source 750, so that the second controlled current source 750 outputs the rectifier sampling current IQ2 in response to the voltage of the first control signal. The second sampling and holding circuit 7221 collects the rectifier sampling current IQ2 near the start of the rectifier Q1 conduction, obtains the second sampling voltage, and outputs the second sampling voltage. The comparator 732 receives the first sampling voltage and the second sampling voltage, and outputs the selection control signal according to the first sampling voltage and the second sampling voltage. Among them, when the first sampling voltage is less than the second sampling voltage, it indicates that the slope of the analog current IQ1 of the kth main power tube is low, and the selection control signal output by the comparator 732 is high. When the trigger signal SH3 is selected to be at a high level, the selector 733 controls the third switch K3 to be turned on, and the first current source IY1 outputs the first reference current to the storage capacitor CS, so that the storage capacitor CS is charged, and the control voltage is output, so that the voltage of the control terminal of the first controlled current source 740 is increased. The first controlled current source 740 is controlled by the control voltage to adjust the current value of the current IA outputted by it (for example, the current value of the current IA is increased from Ia1 to Ia2). Afterwards, the trigger signal SH3 is selected to be at a low level, and the current value of the current IA outputted by the first controlled current source 740 is maintained at Ia2.

[0098] In the main power tube conduction stage T3, the process is basically the same as that in the above embodiment, and will not be described in detail here.

[0099] In the rectifier conduction stage T4, the main power tube Q2 is turned off and the rectifier Q1 is turned on. The first transistor QS1 and the second transistor QS2 respectively input the current of the first end SW of the rectifier Q1 and the current of the second end PGND of the rectifier Q1 into the second error amplifier 7111, so that the second error amplifier 7111 outputs the first control signal. The third sampling and holding circuit 7121 outputs the first control signal to the control end of the second controlled current source 750, so that the second controlled current source 750 outputs the rectifier sampling current IQ2. The second sampling and holding circuit 7221 collects the rectifier sampling current IQ2 near the start of the rectifier Q1 conduction, obtains the second sampling voltage, and outputs the second sampling voltage. The comparator 732 receives the first sampling voltage and the second sampling voltage, and outputs the selection control signal according to the first sampling voltage and the second sampling voltage. When the first sampling voltage is greater than the second sampling voltage, it indicates that the slope of the analog current IQ3 of the k+1th main power tube is high, and the selection control signal output by the comparator 732 is low. When the trigger signal SH3 is selected to be at a high level, the selector 733 controls the fourth switch K4 to be turned on, and the second current source IY2 outputs the second reference current to the storage capacitor CS, so that the storage capacitor CS is discharged, and the output of the control voltage is realized, so that the voltage of the control terminal of the first controlled current source 740 is reduced. The first controlled current source 740 is controlled by the control voltage to adjust the current value of the current IA outputted by it (for example, the current value of the current IA is reduced from Ia2 to Ia3). Afterwards, the trigger signal SH3 is selected to be at a low level, and the current value of the current IA outputted by the first controlled current source 740 is maintained at Ia3.

[0100] In the main power tube conduction stage T5, the main power tube Q2 is turned on, and the rectifier tube Q1 is turned off. The control end of the second controlled current source 750 is turned on with the first controlled current source 740, and the current IA of the current value Ia3 output by the first controlled current source 740 acts on the control end of the second controlled current source 750, discharges the voltage of the control end of the second controlled current source 750, so that the voltage of the control end of the second controlled current source 750 is reduced, so that the second controlled current source 750 can generate the k+2 main power tube analog current IQ4 with an increasing current value, and the slope of the k+2 main power tube analog current IQ4 is reduced compared with the k+1 main power tube analog current IQ3.

[0101] The processes of the remaining stages can be deduced in the same way and will not be elaborated here.

[0102] Based on the above description, the current generating circuit in the embodiment of the present application automatically changes the slope of the main power tube analog current with the change of the inductance value of the power inductor, so that the inductor current output by the current generating circuit can adapt to the change of the inductance value of the power inductor. In addition, the current generating circuit in the present application can also adapt to the change of the duty cycle of the driving signals gl and gh, and the fitting time of the slope of the main power tube analog current tracks the conduction time of the main power tube in real time.

[0103] In addition, by briefly charging and discharging the control terminal of the second controlled current source to dynamically adjust the current output by the second controlled current source, the control speed can be improved, which is more suitable for high-speed scenarios. Moreover, the power consumption can be reduced and the occupied area of ​​the entire current generation circuit can be reduced.

[0104] The embodiment of the present application also provides a power chip, which includes: a power device and a driver chip in the above various embodiments. Among them, the power device includes a main power tube and a rectifier tube, and the driver chip is connected to the main power tube and the rectifier tube respectively. The driver chip can output the rectifier tube sampling current and the main power tube analog current, and control the main power tube and the rectifier tube. Since the driver chip provided in the embodiment of the present application can solve the problem of inaccurate inductor current sampling, it can improve the control effect of the power chip.

[0105] The embodiment of the present application also provides a switching power supply, which includes: a controller and the power chip in the above various embodiments. Wherein, the controller is connected to the power chip, and the controller can receive the rectifier tube sampling current and the main power tube analog current output by the power chip, and output a pulse width modulation signal to the power chip according to the rectifier tube sampling current and the main power tube analog current. The power chip is used to receive the pulse width modulation signal, and according to the pulse width modulation signal, drive the above-mentioned driver chip to control the main power tube and the rectifier tube. Since the driver chip provided in the embodiment of the present application can solve the problem of inaccurate inductor current sampling, the control effect of the switching power supply can be improved.

[0106] The above contents are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be covered by the protection scope of the present application.

Claims

1. A driver chip, characterized in that: include: A driving circuit and a current generating circuit; The driving circuit is used to connect with the main power tube and the rectifier tube, and is used to control the main power tube and the rectifier tube; The current generating circuit comprises: a sampling circuit, a slope control circuit and a current output circuit; The current output circuit is used to output the rectifier tube sampling current when the rectifier tube is turned on, and to output the main power tube analog current when the main power tube is turned on; The sampling circuit is used to control the current output circuit to output the sampling current of the rectifier tube according to the current flowing through the rectifier tube during the conduction phase of the rectifier tube; The slope control circuit is used to control the current output circuit to output the k+1th main power tube analog current in the main power tube conduction stage in the k+1th control cycle according to the rectifier tube sampling current output by the current output circuit in the rectifier tube conduction stage in the kth control cycle and the kth main power tube analog current output by the main power tube conduction stage, where k is an integer greater than 0.

2. The driver chip according to claim 1, characterized in that: The slope control circuit comprises: a first sampling circuit, a second sampling circuit and a regulating circuit; The first sampling circuit is connected to the current output circuit and is used to collect a first sampling voltage corresponding to when the current output circuit outputs the analog current of the kth main power tube during the main power tube conduction phase of the kth control period; The second sampling circuit is connected to the current output circuit and is used to collect a second sampling voltage corresponding to when the current output circuit outputs the rectifier tube sampling current during the rectifier tube conduction phase of the kth control cycle; The control circuit is respectively connected to the first sampling circuit, the second sampling circuit and the current output circuit, and is used to control the current output circuit to output the k+1th main power tube analog current during the main power tube conduction phase of the k+1th control cycle according to the first sampling voltage and the second sampling voltage.

3. The driver chip according to claim 2, characterized in that: The control circuit includes: a regulation generation circuit, a first switch and a first controlled current source; The regulating generation circuit is connected to the first sampling circuit, the second sampling circuit and the control end of the first controlled current source, and is used to control the first controlled current source to generate a first current according to the received first sampling voltage and the second sampling voltage; The first end of the first controlled current source is connected to the current output circuit through the first switch, and the first switch is used to be in an on state during the conduction stage of the main power tube, so that the first current generated by the first controlled current source is input into the current output circuit, and the current output circuit is controlled to output the k+1 main power tube analog current.

4. The driver chip according to claim 3, characterized in that: The regulation generation circuit is used to output a control voltage to a control terminal of the first controlled current source, and the first current increases as the control voltage increases.

5. The driver chip according to claim 4, characterized in that: The regulation generation circuit includes: a first error amplifier; The negative phase input terminal of the first error amplifier is connected to the first sampling circuit for receiving the first sampling voltage; The non-inverting input terminal of the first error amplifier is connected to the second sampling circuit for receiving the second sampling voltage; The output terminal of the first error amplifier is connected to the control terminal of the first controlled current source for outputting the control voltage.

6. The driver chip according to claim 5, characterized in that: The regulation generation circuit further includes: a second switch connected between a negative phase input terminal of the first error amplifier and a positive phase input terminal of the first error amplifier.

7. The driver chip according to claim 4, characterized in that: The regulation generation circuit includes: a comparator, a selector and a signal generator; The negative phase input terminal of the comparator is connected to the first sampling circuit for receiving the first sampling voltage; The non-inverting input terminal of the comparator is connected to the second sampling circuit for receiving the second sampling voltage; The output terminal of the comparator is connected to the first input terminal of the selector for outputting a selection control signal; The second input terminal of the selector is used to receive a selection trigger signal, the first output terminal of the selector is connected to the first control terminal of the signal generator, the second output terminal of the selector is connected to the second control terminal of the signal generator, the output terminal of the signal generator is connected to the control terminal of the first controlled current source, and the selector is used to control the signal generator to output the control voltage according to the first reference current or the second reference current in response to the selection control signal and the selection trigger signal.

8. The driver chip according to claim 7, characterized in that: The signal generator includes: a third switch, a fourth switch, a first current source, a second current source and a storage capacitor; the first current source is used to output the first reference current, and the second current source is used to output the second reference current; The first end of the first current source is connected to the first reference signal end, the second end of the first current source is connected to the first end of the third switch, the second end of the third switch is connected to the control end of the first controlled current source, and the control end of the third switch is connected to the first output end of the selector; A first end of the fourth switch is connected to the control end of the first controlled current source, a second end of the fourth switch is connected to the first end of the second current source, and a control end of the fourth switch is connected to the second output end of the selector; The second terminal of the second current source is connected to the second reference signal terminal; The first end of the storage capacitor is connected to the control end of the first controlled current source, and the second end of the storage capacitor is connected to the second reference signal end.

9. The driver chip according to any one of claims 2 to 8, characterized in that: The first sampling circuit is further used for: During a first period from a first reference time to an end time in the conduction phase of the main power tube, the first sampling voltage is collected and output.

10. The driver chip according to claim 9, characterized in that: The first reference time is the start time of the conduction phase of the main power tube.

11. The driver chip according to any one of claims 2 to 10, characterized in that: The second sampling circuit is further used for: During a second period from the start time to the second reference time in the conduction phase of the rectifier tube, the second sampling voltage is collected and outputted.

12. The driver chip according to any one of claims 1 to 11, characterized in that: The current output circuit comprises: a second controlled current source, a control terminal of the second controlled current source is connected to the sampling circuit and the slope control circuit; The second controlled current source is used to: In the conduction phase of the rectifier tube, in response to the voltage generated by the control terminal according to the control of the sampling circuit, the rectifier tube sampling current is output; During the conduction phase of the main power tube, in response to the voltage generated by the control terminal according to the slope control circuit, the k+1th main power tube analog current is output.

13. The driver chip according to claim 12, characterized in that: The voltage generated in response to the control terminal thereof being controlled according to the slope control circuit comprises: In response to the control of the slope control circuit, the voltage of the control terminal of the second controlled current source decreases, generating the k+1th main power tube analog current with an increasing current value, and the slope of the k+1th main power tube analog current increases.

14. The driver chip according to any one of claims 1 to 13, characterized in that: The sampling circuit comprises: a current detection circuit and a third sampling circuit; The current detection circuit is used to be connected to the first end and the second end of the rectifier tube respectively, and is used to generate a first control signal according to the current at the first end of the rectifier tube and the current at the second end of the rectifier tube during the conduction phase of the rectifier tube; The third sampling circuit is connected to the current detection circuit and the current output circuit, and is used to output the first control signal to the current output circuit during the conduction phase of the rectifier tube, so as to control the current output circuit to generate the rectifier tube sampling current.

15. A power chip, characterized in that: include: Power devices and driver chips; The power device includes a main power tube and a rectifier tube; The driving chip comprises: a driving circuit and a current generating circuit; The driving circuit is used to connect with the main power tube and the rectifier tube, and is used to control the main power tube and the rectifier tube; The current generating circuit comprises: a sampling circuit, a slope control circuit and a current output circuit; The current output circuit is used to output the rectifier tube sampling current when the rectifier tube is turned on, and to output the main power tube analog current when the main power tube is turned on; The sampling circuit is used to control the current output circuit to output the sampling current of the rectifier tube according to the current flowing through the rectifier tube during the conduction phase of the rectifier tube; The slope control circuit is used to control the current output circuit to output the k+1th main power tube analog current in the main power tube conduction stage in the k+1th control cycle according to the rectifier tube sampling current output by the current output circuit in the rectifier tube conduction stage in the kth control cycle and the kth main power tube analog current output by the main power tube conduction stage, where k is an integer greater than 0.

16. A switching power supply, characterized in that: include: Controller and power chip; The power chip includes: a power device and a driver chip; the power device includes a main power tube and a rectifier tube; The driving chip comprises: a driving circuit and a current generating circuit; The driving circuit is used to connect with the main power tube and the rectifier tube, and is used to control the main power tube and the rectifier tube; The current generating circuit comprises: a sampling circuit, a slope control circuit and a current output circuit; The current output circuit is used to output the rectifier tube sampling current when the rectifier tube is turned on, and to output the main power tube analog current when the main power tube is turned on; The sampling circuit is used to control the current output circuit to output the sampling current of the rectifier tube according to the current flowing through the rectifier tube during the conduction phase of the rectifier tube; The slope control circuit is used to control the current output circuit to output the k+1th main power tube analog current in the main power tube conduction stage in the k+1th control cycle according to the rectifier tube sampling current output by the current output circuit in the rectifier tube conduction stage in the kth control cycle and the kth main power tube analog current output by the main power tube conduction stage, where k is an integer greater than 0; The controller is connected to the power chip, and is used to receive the rectifier tube sampling current and the k+1th main power tube simulation current output by the current output circuit, and output a pulse width modulation signal according to the rectifier tube sampling current and the k+1th main power tube simulation current; The power chip is used to receive the pulse width modulation signal, and according to the pulse width modulation signal, drive the driving chip to control the main power tube and the rectifier tube.

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