A compensation circuit

Abstract

An embodiment of the present application discloses a compensation circuit for calibrating the offset voltage of an operational amplifier. The compensation circuit in the embodiment of the present application includes: IN_REF, isolation operational amplifier U1, output isolation operational amplifier circuit, OUT_REF, output acquisition ADC, VOS offset compensation circuit, and resistor error compensation circuit; the isolation operational amplifier U1 is connected to the IN_REF, the output isolation operational amplifier circuit is connected to the isolation operational amplifier U1, the OUT_REF is connected to the output isolation operational amplifier circuit, the output acquisition ADC is connected to the OUT_REF, the VOS offset compensation circuit is connected to the output acquisition ADC, and the VOS offset compensation circuit is connected to the output isolation operational amplifier circuit; the output acquisition ADC is configured to collect the output value of the OUT_REF and feedback it to the VOS offset compensation circuit and the resistor error compensation circuit.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of compensation circuits, and in particular, to a compensation circuit. Background Art

[0002] During the cell dot screen process, generally 120 signal power supplies are required. In previous designs, we usually provided a separate DAC for each power supply so that each power supply could be configured with any voltage independently. However, during the actual dot screen process, only less than 8 different voltages are used for these 120 power supplies, and most of the channel output voltages are the same. To save costs, we share 8 REF voltages for these 120 power supplies, which means that one REF voltage needs to be provided for 120 channels to use. Although each channel uses the same circuit implementation, due to the inconsistent offset voltages of the operational amplifiers used in the circuit and certain deviations in the resistor accuracy, there are large errors when different channels output the same voltage. To solve this problem, we added a compensation and calibration circuit in each REF parallel circuit to calibrate the offset voltage of the operational amplifier and the resistor accuracy problem in the parallel circuit. Summary of the Invention

[0003] The embodiments of the present application provide a compensation circuit that can calibrate the offset voltage of the operational amplifier.

[0004] The embodiments of the present application provide a compensation circuit, including:

[0005] IN_REF, isolation operational amplifier U1, output isolation operational amplifier circuit, OUT_REF, output acquisition ADC, VOS offset compensation circuit, and resistor error compensation circuit;

[0006] The isolation operational amplifier U1 is connected to the IN_REF, the output isolation operational amplifier circuit is connected to the isolation operational amplifier U1, the OUT_REF is connected to the output isolation operational amplifier circuit, the output acquisition ADC is connected to the OUT_REF, the VOS offset compensation circuit is connected to the output acquisition ADC, and the VOS offset compensation circuit is connected to the output isolation operational amplifier circuit; the output acquisition ADC is used to collect the output value of the OUT_REF and feedback it to the VOS offset compensation circuit and the resistor error compensation circuit.

[0007] Optionally, the resistor error compensation circuit includes resistor R1, resistor R2, resistor R3, and MUX multiplexer;

[0008] One end of the resistor R1 is connected to the isolation operational amplifier U1, and the other end is connected to the output isolation operational amplifier circuit;

[0009] One end of the resistor R2 is connected between the resistor R1 and the output isolation operational amplifier circuit, and the other end is connected to the resistor R3;

[0010] The resistor R3 is grounded;

[0011] One end of the MUX multiplexer is connected between the resistor R2 and the resistor R3, and the other end is grounded, forming a parallel connection with the resistor R3, and is used to receive the output value of the OUT_REF collected by the output acquisition ADC; the resistance of the MUX multiplexer is adjustable;

[0012] The VOS offset compensation circuit is connected between the resistor R2 and the resistor R3, forming a parallel connection with the resistor R3.

[0013] Optionally, the MUX multiplexer includes a resistor R4, a resistor R5, a resistor R6, and a resistor R7; the resistor R4, the resistor R5, the resistor R6, and the resistor R7 are connected in parallel; the MUX multiplexer controls the on / off of the resistor R4, the resistor R5, the resistor R6, and the resistor R7 respectively through 4 individual selection switches.

[0014] Optionally, the VOS offset compensation circuit includes an operational amplifier U3 and a DAC;

[0015] The output end of the DAC is connected to the input end of the operational amplifier U3 to receive the output value of the OUT_REF collected by the output acquisition ADC;

[0016] The output end of the operational amplifier U3 is connected between the resistor R2 and the resistor R3.

[0017] Optionally, the output isolation operational amplifier circuit includes an operational amplifier U2, a resistor R8, and a resistor R9;

[0018] One input end of the operational amplifier U2 is connected to the resistor R1, and the output end is connected to the OUT_REF; one end of the resistor R8 is connected between the operational amplifier U2 and the OUT_REF, and the other end is connected to the resistor R9; the other input end of the operational amplifier U2 is connected between the resistor R8 and the resistor R9; one end of the resistor R9 is connected to the resistor R8, and the other end is grounded.

[0019] Optionally, the MUX multiplexer is connected in parallel with the resistor R3, and the MUX multiplexer is used to linearly adjust the resistance value of the resistor R3 by sixteen thousandths.

[0020] Optionally, the IN_REF is set to 0V.

[0021] Optionally, the sum of the resistance values of the resistor R2 and the resistor R3 is one thousand and eight thousandths of the resistance value of the resistor R1.

[0022] As can be seen from the above technical solutions, the embodiments of the present application have the following advantages:

[0023] In the compensation circuit of the embodiment of the present application, through the VOS offset compensation circuit and the resistor error compensation circuit, the deviation of the output reference voltage (OUT_REF) caused by the VOS offset voltage of the operational amplifier and the resistor error can be effectively eliminated. By collecting the output value of OUT_REF in real time through the output acquisition ADC, the system can detect the error caused by the VOS offset or the resistor error, and adjust it through the compensation circuit, so that OUT_REF always remains at the expected ideal value. This dynamic adjustment not only improves the accuracy of the output voltage, but also enhances the stability and robustness of the system, ensuring that OUT_REF is always stable and reliable under different working conditions, thereby improving the performance of the entire system, and is particularly suitable for application scenarios requiring high voltage accuracy. And it can play a role in resistor adjustment, which plays a key role in this compensation circuit and is used to compensate for the output voltage deviation caused by resistor error. The resistor error compensation circuit in the circuit can detect the change or mismatch of the resistor value in real time, and reduce the influence of the resistor error on the output reference voltage (OUT_REF) by adjusting the resistor value in the circuit or through other means. This resistor adjustment mechanism ensures that the output voltage of the circuit is closer to the ideal value, improves the voltage accuracy, especially in application scenarios where resistor accuracy is important, and can significantly improve the stability and overall performance of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a schematic structural diagram of an embodiment of the compensation circuit in the embodiment of the present application;

[0025] Figure 2 is a schematic structural diagram of another embodiment of the compensation circuit in the embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0026] The embodiment of the present application provides a compensation circuit for calibrating the offset voltage of an operational amplifier.

[0027] Next, the embodiments in the present application will be described with reference to the drawings.

[0028] Please refer to Figures 1 to 2 , an embodiment of the compensation circuit in the embodiment of the present application includes:

[0029] IN_REF, isolation operational amplifier U1, output isolation operational amplifier circuit, OUT_REF, output acquisition ADC, VOS offset compensation circuit and resistor error compensation circuit;

[0030] The isolated operational amplifier U1 is connected to IN_REF, the output isolation operational amplifier circuit is connected to the isolated operational amplifier U1, OUT_REF is connected to the output isolation operational amplifier circuit, the output acquisition ADC is connected to OUT_REF, the VOS offset compensation circuit is connected to the output acquisition ADC, and the VOS offset compensation circuit is connected to the output isolation operational amplifier circuit; the output acquisition ADC is used to acquire the output value of OUT_REF and feedback it to the VOS offset compensation circuit and the resistance error compensation circuit.

[0031] Circuit composition and connection relationship:

[0032] IN_REF and the isolated operational amplifier U1:

[0033] Connection: IN_REF is the input reference voltage and is directly connected to the input terminal of the isolated operational amplifier U1.

[0034] Function: The function of the isolated operational amplifier U1 is to isolate the IN_REF signal from other parts of the circuit, prevent external interference from affecting the input signal, and ensure the stability of the input voltage.

[0035] The isolated operational amplifier U1 and the output isolation operational amplifier circuit:

[0036] Connection: The output terminal of the isolated operational amplifier U1 is connected to the input terminal of the output isolation operational amplifier circuit.

[0037] Function: The output isolation operational amplifier circuit further amplifies or adjusts the signal from U1 to generate the required output reference voltage (OUT_REF).

[0038] The output isolation operational amplifier circuit and OUT_REF:

[0039] Connection: The output terminal of the output isolation operational amplifier circuit is connected to OUT_REF.

[0040] Function: OUT_REF is the output reference voltage of the circuit, and it is usually necessary to ensure its accuracy and stability for use by subsequent circuits.

[0041] The output acquisition ADC and OUT_REF:

[0042] Connection: The output reference voltage (OUT_REF) is input to the output acquisition ADC.

[0043] Function: The ADC acquires the output voltage of OUT_REF, converts it into a digital signal, and feeds this value back to the compensation circuit. This signal is used to calculate and adjust the errors existing in the circuit.

[0044] The output acquisition ADC and the VOS offset compensation circuit:

[0045] Connection: The output signal of the ADC is connected to the VOS offset compensation circuit.

[0046] Function: The VOS offset compensation circuit calculates the required adjustment amount according to the output signal fed back by the ADC, aiming to correct the error caused by the input offset voltage (VOS) of the operational amplifier.

[0047] VOS offset compensation circuit and output isolation operational amplifier circuit:

[0048] Connection: The VOS offset compensation circuit is connected to the output isolation operational amplifier circuit.

[0049] Function: The compensation circuit adjusts the output isolation operational amplifier circuit according to the result of VOS offset compensation to reduce or eliminate the deviation caused by VOS and ensure the accuracy of OUT_REF.

[0050] Output acquisition ADC and resistor error compensation circuit:

[0051] Connection: The output signal of the ADC is also fed back to the resistor error compensation circuit.

[0052] Function: The resistor error compensation circuit is used to correct the signal deviation caused by resistor error and further improve the accuracy of the output voltage.

[0053] Circuit working principle:

[0054] Processing of IN_REF input signal: The circuit isolates the IN_REF signal through the isolation operational amplifier U1 and transmits it to the output isolation operational amplifier circuit. The output isolation operational amplifier circuit generates the required output reference voltage OUT_REF.

[0055] Output acquisition and feedback: The output acquisition ADC is responsible for acquiring the actual output voltage of OUT_REF and feeding it back to the VOS offset compensation circuit and the resistor error compensation circuit.

[0056] Compensation circuit adjustment: The VOS offset compensation circuit calculates and adjusts the output isolation operational amplifier circuit according to the information fed back by the ADC to compensate for the deviation caused by the input offset voltage (VOS) of the operational amplifier. At the same time, the resistor error compensation circuit eliminates the influence of resistor error according to the feedback adjustment.

[0057] Feedback regulation: By adjusting the working state of the output isolation operational amplifier circuit, it is finally ensured that the output voltage of OUT_REF is consistent with the expected value, thus ensuring the accuracy and stability of the circuit.

[0058] This compensation circuit can effectively eliminate the deviation of the output reference voltage (OUT_REF) caused by the VOS offset voltage of the operational amplifier and the resistor error through the VOS offset compensation circuit and the resistor error compensation circuit. By collecting the output value of OUT_REF in real time through the output acquisition ADC, the system can detect the error caused by the VOS offset or resistor error and adjust it through the compensation circuit, so that OUT_REF always remains at the expected ideal value. This dynamic regulation not only improves the accuracy of the output voltage, but also enhances the stability and robustness of the system, ensuring that OUT_REF is always stable and reliable under different working conditions, thus improving the performance of the entire system, especially suitable for application scenarios requiring high voltage accuracy. And it can play the role of resistor adjustment, which plays a key role in this compensation circuit for compensating the output voltage deviation caused by the resistor error. The resistor error compensation circuit in the circuit can detect the change or mismatch of the resistor value in real time, and reduce the influence of the resistor error on the output reference voltage (OUT_REF) by adjusting the resistor value in the circuit or through other means of compensation. This resistor adjustment mechanism ensures that the output voltage of the circuit is closer to the ideal value, improving the voltage accuracy. Especially in application scenarios where resistor accuracy is important, it can significantly enhance the stability and overall performance of the system.

[0059] Optionally, the resistor error compensation circuit includes resistor R1, resistor R2, resistor R3 and a MUX multiplexer;

[0060] One end of resistor R1 is connected to isolation operational amplifier U1, and the other end is connected to the output isolation operational amplifier circuit;

[0061] One end of resistor R2 is connected between resistor R1 and the output isolation operational amplifier circuit, and the other end is connected to resistor R3;

[0062] Resistor R3 is grounded;

[0063] One end of the MUX multiplexer is connected between resistor R2 and resistor R3, and the other end is grounded, forming a parallel connection with resistor R3, and is used to receive the output value of OUT_REF collected by the output acquisition ADC; the resistance of the MUX multiplexer is adjustable;

[0064] The VOS offset compensation circuit is connected between resistor R2 and resistor R3, forming a parallel connection with resistor R3.

[0065] The design of the resistor error compensation circuit precisely adjusts the resistor value by including resistor R1, resistor R2, resistor R3, and a MUX multiplexer, eliminating the output voltage deviation caused by resistor errors. Specifically, resistor R1 is connected between the isolation operational amplifier U1 and the output isolation operational amplifier circuit, resistor R2 is connected between resistor R1 and the output isolation operational amplifier circuit, and resistor R3 is grounded. The MUX multiplexer is used to select between resistor R2 and resistor R3, and its resistance is adjustable. It dynamically adjusts the resistor value by receiving the OUT_REF output value collected by the output acquisition ADC. The VOS offset compensation circuit is also connected between resistor R2 and resistor R3 to further optimize the adjustment of the circuit. With this configuration, the circuit can adjust the resistor value according to the actually collected output voltage value, effectively compensating for resistor errors, thereby ensuring the accuracy and stability of the output reference voltage (OUT_REF).

[0066] Optionally, the MUX multiplexer includes resistor R4, resistor R5, resistor R6, and resistor R7; resistor R4, resistor R5, resistor R6, and resistor R7 are in parallel; the MUX multiplexer controls the on / off states of resistor R4, resistor R5, resistor R6, and resistor R7 respectively through 4 individual selection switches.

[0067] The MUX multiplexer precisely realizes the dynamic adjustment of the resistor by including the parallel-connected resistor R4, resistor R5, resistor R6, and resistor R7, and the corresponding 4 selection switches. Each selection switch controls the on / off states of resistor R4, R5, R6, and R7 respectively, and adjusts the equivalent resistance value of the MUX multiplexer by changing the parallel combination of resistors. Such a design enables the circuit to flexibly select different resistor combinations according to the OUT_REF value fed back by the output acquisition ADC, thereby achieving precise compensation for the output reference voltage, further reducing the influence of resistor errors on the circuit output, and improving the adjustment range and accuracy of the compensation circuit.

[0068] Optionally, the VOS offset compensation circuit includes operational amplifier U3 and DAC;

[0069] The DAC, with its output terminal connected to the input terminal of operational amplifier U3, receives the OUT_REF output value collected by the output acquisition ADC;

[0070] The output terminal of operational amplifier U3 is connected between resistor R2 and resistor R3.

[0071] The VOS offset compensation circuit includes an operational amplifier U3 and a DAC, which accurately calibrates the error caused by the operational amplifier offset voltage (VOS). Specifically, the output terminal of the DAC is connected to the input terminal of the operational amplifier U3, which is used to receive the output value of OUT_REF fed back by the output acquisition ADC, and generates a corresponding compensation voltage signal according to this value. The output terminal of the operational amplifier U3 is connected between the resistor R2 and the resistor R3, and the compensation signal is directly introduced into the circuit, thereby dynamically adjusting the error caused by the operational amplifier offset voltage, and ensuring the accuracy and stability of the OUT_REF output voltage. Through this design, the deviation caused by the operational amplifier VOS is effectively eliminated, and the circuit performance and output accuracy are further improved.

[0072] Optionally, the output isolation operational amplifier circuit includes an operational amplifier U2, a resistor R8, and a resistor R9;

[0073] One input terminal of the operational amplifier U2 is connected to the resistor R1, and the output terminal is connected to OUT_REF; one end of the resistor R8 is connected between the operational amplifier U2 and OUT_REF, and the other end is connected to the resistor R9; the other input terminal of the operational amplifier U2 is connected between the resistor R8 and the resistor R9; one end of the resistor R9 is connected to the resistor R8, and the other end is grounded.

[0074] The output isolation operational amplifier circuit ensures the stability and accuracy of the output reference voltage (OUT_REF) through the precise design of the operational amplifier U2, the resistor R8, and the resistor R9. One input terminal of the operational amplifier U2 is connected to the isolation operational amplifier U1 through the resistor R1, and its output terminal is directly connected to OUT_REF. One end of the resistor R8 is connected between the output terminal of the operational amplifier U2 and OUT_REF, and the other end is connected to the resistor R9. One end of the resistor R9 is connected to the resistor R8, and the other end is grounded. The other input terminal of the operational amplifier U2 is connected to the connection point of the resistor R8 and the resistor R9. Through this resistor network structure, a feedback loop of the operational amplifier is formed, which not only realizes the isolation and amplification of the output voltage, but also precisely controls and stabilizes the voltage output, further reducing the output fluctuation caused by circuit interference or load change, and improving the stability and linearity of OUT_REF.

[0075] Optionally, the MUX multiplexer is connected in parallel with the resistor R3, and the MUX multiplexer is used to linearly adjust the resistance value of the resistor R3 by sixteen thousandths.

[0076] The MUX multiplexer is designed in parallel with resistor R3, enabling the circuit to linearly adjust the resistance value of resistor R3 by sixteen thousandths. Specifically, by adjusting the combined states of the parallel resistors (such as resistors R4, R5, R6, and R7) in the MUX multiplexer, the equivalent resistance value of the MUX multiplexer can be changed, thereby forming a precise adjustment mechanism in parallel combination with resistor R3. Such a design greatly improves the accuracy of resistance adjustment in the circuit, enabling the output reference voltage (OUT_REF) to perform a small linear compensation based on the ADC feedback value collected from the output, effectively reducing the impact of resistance errors on the circuit performance, ensuring the high-precision output of OUT_REF, and meeting the requirements for precise circuit adjustment.

[0077] Optionally, IN_REF is set to 0V.

[0078] IN_REF is set to 0V, which simplifies the reference setting of the circuit and provides a clear reference point for subsequent compensation operations. When IN_REF is 0V, theoretically OUT_REF should also be 0V, but due to issues such as VOS and resistance errors in the operational amplifier, the actual output may deviate from 0V. By using the output-collecting ADC to monitor the deviation value of OUT_REF in real time and combining it with the VOS offset compensation circuit and the resistance error compensation circuit for precise adjustment, these deviations can be effectively eliminated, ultimately making OUT_REF consistent with IN_REF. This design further enhances the compensation effect and output stability of the circuit, especially suitable for the application scenarios of high-precision reference circuits.

[0079] Optionally, the sum of the resistance values of resistor R2 and resistor R3 is one thousand and eight thousandths of the resistance value of resistor R1.

[0080] The sum of the resistance values of resistor R2 and resistor R3 is precisely set to one thousand and eight thousandths of the resistance value of resistor R1. This precise resistance ratio design aims to optimize the feedback characteristics and compensation performance of the circuit, ensuring high linearity and stability when the circuit performs voltage regulation and error compensation. Through this specific resistance configuration, the voltage distribution and feedback response in the circuit can be effectively balanced, further improving the control accuracy of the compensation circuit for the OUT_REF output voltage, meeting the performance requirements of high-precision circuits, and reducing the compensation errors caused by resistance ratio deviations.

[0081] Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated here.

[0082] In several embodiments provided in the present application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling, direct coupling, or communication connection between each other can be through some interfaces. The indirect coupling or communication connection of the device or unit can be in electrical, mechanical, or other forms.

[0083] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0084] In addition, in each embodiment of the present application, the functional units can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

[0085] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in each embodiment of the present application. The foregoing storage medium includes: USB flash drives, mobile hard disks, read-only memories (ROM, read-only memory), random access memories (RAM, random access memory), magnetic disks, or optical discs and other various media that can store program codes.

Claims

1. A compensation circuit, characterized in that, Including: IN_REF, isolation operational amplifier U1, output isolation operational amplifier circuit, OUT_REF, output acquisition ADC, VOS offset compensation circuit, and resistor error compensation circuit; The isolation operational amplifier U1 is connected to the output terminal of the IN_REF. The input terminal of the output isolation operational amplifier circuit is connected to the output terminal of the isolation operational amplifier U1. The input terminal of the OUT_REF is connected to the output terminal of the output isolation operational amplifier circuit. The input terminal of the output acquisition ADC is connected to the output terminal of the OUT_REF. The input terminal of the VOS offset compensation circuit is connected to the output terminal of the output acquisition ADC. The output terminal of the VOS offset compensation circuit is connected to the input terminal of the output isolation operational amplifier circuit. The output acquisition ADC is used to collect the output value of the OUT_REF and feedback it to the VOS offset compensation circuit and the resistor error compensation circuit; The resistor error compensation circuit includes resistor R1, resistor R2, resistor R3, and MUX multiplexer; The input terminal of the resistor R1 is connected to the output terminal of the isolation operational amplifier U1, and the output terminal is connected to the first input terminal of the output isolation operational amplifier circuit; The input terminal of the resistor R2 is connected between the resistor R1 and the output isolation operational amplifier circuit, and the output terminal is connected to the input terminal of the resistor R3; The output terminal of the resistor R3 is grounded; The input terminal of the MUX multiplexer is connected between the resistor R2 and the resistor R3, and the output terminal is grounded, forming a parallel connection with the resistor R3, and is used to receive the output value of the OUT_REF collected by the output acquisition ADC. The resistance of the MUX multiplexer is adjustable; The VOS offset compensation circuit is connected between the resistor R2 and the resistor R3, forming a parallel connection with the resistor R3; The MUX multiplexer is in parallel with the resistor R3, and the MUX multiplexer is used to linearly adjust the resistance value of the resistor R3 by sixteen per thousand; The IN_REF is set to 0V; The sum of the resistance values of the resistor R2 and the resistor R3 is one thousand and eight per thousand of the resistance value of the resistor R1; The MUX multiplexer includes resistor R4, resistor R5, resistor R6, and resistor R7. The resistor R4, the resistor R5, the resistor R6, and the resistor R7 are in parallel. The MUX multiplexer controls the on / off of the resistor R4, the resistor R5, the resistor R6, and the resistor R7 respectively through 4 separate selection switches.

2. The compensation circuit according to claim 1, wherein The VOS offset compensation circuit includes operational amplifier U3 and DAC; The DAC, the output terminal is connected to the input terminal of the operational amplifier U3, and receives the output value of the OUT_REF collected by the output acquisition ADC; The output terminal of the operational amplifier U3 is connected between the resistor R2 and the resistor R3.

3. The compensation circuit according to claim 1, wherein The output isolation operational amplifier circuit includes operational amplifier U2, resistor R8, and resistor R9; The first input terminal of the operational amplifier U2 is connected to the resistor R1, and the output terminal is connected to the OUT_REF; the input terminal of the resistor R8 is connected between the output terminal of the operational amplifier U2 and the OUT_REF, and the output terminal is connected to the input terminal of the resistor R9; the second input terminal of the operational amplifier U2 is connected between the resistor R8 and the resistor R9; the input terminal of the resistor R9 is connected to the output terminal of the resistor R8, and the output terminal is grounded.

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