Device for improving switching linearity and bandwidth of sample-and-hold circuit

Abstract

The present invention discloses a device for improving the switching linearity and bandwidth of a sample-and-hold circuit. The device includes a sample-and-hold circuit and an output buffer. The output buffer includes a first voltage signal output structure and a second voltage signal output structure. The first voltage signal output structure includes: a first switch control unit for disconnecting a first bias load unit from a first signal output unit when the sample-and-hold circuit operates in tracking mode, and for connecting the first bias load unit to the first signal output unit in hold mode; a first bias load unit for receiving an externally supplied bias voltage and providing a load; and a first signal output unit for disconnecting the output of the first voltage signal in tracking mode and outputting the first voltage signal in hold mode. By controlling the output buffer to operate only in hold mode, the present invention reduces harmonic distortion, improves linearity, and expands the overall bandwidth of the sample-and-hold circuit.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to a device for improving the linearity and bandwidth of a sampling and holding circuit switch. Background Art

[0002] In advanced semiconductor process nodes, such as 28nm CMOS and FinFET processes, a sample and hold (T / H) circuit generally uses a single NMOS transistor as a sampling switch.

[0003] To optimize the output performance of T / H circuits, traditional designs typically incorporate a source follower as an output buffer. This buffer operates in both tracking and hold modes, maintaining a relatively constant gate-source voltage. Consequently, it maintains a relatively constant transconductance and exhibits good linearity. However, when the input frequency reaches tens of gigahertz (GHz), the subchannel buffer's bandwidth limits the buffer's output, preventing it from tracking the input signal. Consequently, a partially distorted signal is generated that is proportional to the input frequency. This nonlinear distortion not only degrades signal integrity but can also negatively impact overall system performance, such as increasing bit error rates and reducing signal processing capabilities. Summary of the Invention

[0004] In view of the above-mentioned deficiencies in the prior art, the technical problem to be solved by the present invention is to provide a device that can solve the nonlinear problem caused by the switching of the sampling and holding circuit and improve the linearity and bandwidth of the sampling and holding circuit switch.

[0005] To solve the above technical problems, the present invention adopts a technical solution: providing a device for improving the switching linearity and bandwidth of a sample-and-hold circuit, comprising a sample-and-hold circuit and an output buffer electrically connected to a sampling signal output terminal of the sample-and-hold circuit, wherein the output buffer is a differential structure including a first voltage signal output structure and a second voltage signal output structure, wherein the first voltage signal output structure includes:

[0006] a first switch control unit, configured to disconnect the first bias load unit from the first signal output unit when the operating mode of the sample-and-hold circuit is a tracking mode, and to connect the first bias load unit to the first signal output unit when the operating mode of the sample-and-hold circuit is a holding mode;

[0007] a first bias load unit, configured to receive an externally supplied bias voltage and provide a load; and

[0008] a first signal output unit, configured to disconnect the output of the first voltage signal when the operating mode of the sample and hold circuit is the tracking mode, and output the first voltage signal when the operating mode of the sample and hold circuit is the holding mode;

[0009] The second voltage signal output structure includes:

[0010] a second switch control unit, configured to disconnect the second bias unit from the second signal output unit when the operation mode of the sample-and-hold circuit is the tracking mode, and to connect the second bias load unit to the second signal output unit when the operation mode of the sample-and-hold circuit is the holding mode;

[0011] a second bias load unit, configured to receive an externally supplied bias voltage and provide a load; and

[0012] The second signal output unit is used to disconnect the output of the second voltage signal when the working mode of the sampling and holding circuit is the tracking mode, and output the second voltage signal when the working mode of the sampling and holding circuit is the holding mode.

[0013] Furthermore, the first switch control unit is defined as a first MOSFET M1, the gate of the first MOSFET M1 is connected to the clock signal, the source of the first MOSFET M1 is electrically connected to the first bias load unit, and the drain of the first MOSFET M1 is electrically connected to the first signal output unit; when the clock signal is at a high level, the first MOSFET M1 is turned off, and when the clock signal is at a low level, the first MOSFET M1 is turned on.

[0014] Furthermore, the first bias load unit is defined as a second MOSFET M2, a gate of the second MOSFET M2 is connected to an externally supplied bias voltage, a source of the second MOSFET M2 is connected to a power supply voltage, and a drain of the second MOSFET M2 is electrically connected to the source of the first MOSFET M1.

[0015] Furthermore, the first signal output unit includes a third MOSFET M3, a gate of the third MOSFET M3 is connected to the sampling signal, a drain of the third MOSFET M3 is grounded, and a source of the third MOSFET M3 is electrically connected to the drain of the first MOSFET M1; when the first MOSFET M1 is turned on, the third MOSFET M3 is turned on, and the source of the third MOSFET M3 outputs a first voltage signal; when the first MOSFET M1 is turned off, the third MOSFET M3 is turned off, and the source of the third MOSFET M3 disconnects the output of the first voltage signal.

[0016] Furthermore, the first signal output unit also includes a fourth MOSFET M4, the gate of the fourth MOSFET M4 is connected to the clock signal, the source of the fourth MOSFET M4 is grounded, and the drain of the fourth MOSFET M4 is electrically connected to the source of the third MOSFET M3. When the clock signal is at a high level, the fourth MOSFET M4 is turned on, and the source of the third MOSFET M3 outputs the first voltage signal. When the clock signal is at a low level, the fourth MOSFET M4 is turned off, and the drain of the fourth MOSFET M4 is short-circuited to GND.

[0017] Furthermore, it also includes a first step-down unit for reducing the common-mode voltage increased when switching to the hold mode; the first step-down unit is defined as a fifth MOSFET M5, the gate of the fifth MOSFET M5 is connected to the clock signal, the source of the fifth MOSFET M5 is electrically connected to the sampling signal output end of the sample-and-hold circuit to receive the sampling signal, the drain of the fifth MOSFET M5 is electrically connected to the gate of the third MOSFET M3, and the source and drain of the fifth MOSFET M5 are electrically connected.

[0018] Furthermore, the second switch control unit is defined as a sixth MOSFET M6, a gate of the sixth MOSFET M6 is connected to the clock signal, a source of the sixth MOSFET M6 is electrically connected to the second bias load unit, and a drain of the sixth MOSFET M6 is electrically connected to the second signal output unit; when the clock signal is at a high level, the sixth MOSFET M6 is turned off, and when the clock signal is at a low level, the sixth MOSFET M6 is turned on;

[0019] The second bias load unit is defined as a seventh MOSFET M7, a gate of the seventh MOSFET M7 is connected to an externally supplied bias voltage, a source of the seventh MOSFET M7 is connected to a power supply voltage, and a drain of the seventh MOSFET M7 is electrically connected to the source of the sixth MOSFET M6.

[0020] Furthermore, the second signal output unit includes an eighth MOSFET M8, a gate of the eighth MOSFET M8 is connected to the sampling signal, a drain of the eighth MOSFET M8 is grounded, and a source of the eighth MOSFET M8 is electrically connected to the drain of the sixth MOSFET M6; when the sixth MOSFET M6 is turned on, the eighth MOSFET M8 is turned on, and the source of the eighth MOSFET M8 outputs a second voltage signal; when the sixth MOSFET M6 is turned off, the eighth MOSFET M8 is turned off, and the source of the eighth MOSFET M8 disconnects the output of the second voltage signal.

[0021] Furthermore, the second signal output unit also includes a ninth MOSFET M9, a gate of the ninth MOSFET M9 being connected to the clock signal, a source of the ninth MOSFET M9 being grounded, and a drain of the ninth MOSFET M9 being electrically connected to the source of the eighth MOSFET M8; when the clock signal is at a high level, the ninth MOSFET M9 is turned on, and the source of the eighth MOSFET M8 outputs a second voltage signal; when the clock signal is at a low level, the ninth MOSFET M9 is turned off, and the drain of the ninth MOSFET M9 is short-circuited to GND.

[0022] Furthermore, it also includes a second step-down unit for reducing the common-mode voltage increased when switching to the hold mode; the second step-down unit is defined as a tenth MOSFET M10, the gate of the tenth MOSFET M10 is connected to the clock signal, the source of the tenth MOSFET M10 is electrically connected to the sampling signal output end of the sample-and-hold circuit to receive the sampling signal, the drain of the tenth MOSFET M10 is electrically connected to the gate of the eighth MOSFET M8, and the source and drain of the tenth MOSFET M10 are electrically connected.

[0023] The present invention provides a device for improving the switching linearity and bandwidth of a sample-and-hold circuit, and has at least the following beneficial effects: The present invention employs time-sharing control to disable the output buffer when the sampling circuit operates in tracking mode and to enable it when the sampling circuit operates in hold mode, thereby reducing charge injection during the sampling process and improving linearity and bandwidth. By adding a fourth MOSFET and a ninth MOSFET to the output buffer, the voltage at the output point is pulled close to zero during the tracking phase, thereby reducing harmonic distortion and, in particular, avoiding the introduction of additional harmonic distortion when switching from tracking mode to hold mode. By cleverly designing the first and second step-down units, effective control of the common-mode voltage is achieved, thereby avoiding unstable circuit performance or increased noise caused by increased output voltage. The use of device capacitors and parasitic capacitors as sampling capacitors reduces the use of additional components, reducing the volume and weight of the circuit and lowering costs, while also reducing parasitic effects and significantly improving the bandwidth of the overall circuit. The present invention is suitable for high-speed signal processing scenarios, such as high-frequency communications and radar signal processing, and can meet the high requirements of high-speed A / D converters for front-end circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0025] Figure 1 This is a circuit diagram of an embodiment of an output buffer in a device for improving the switching linearity and bandwidth of a sample-and-hold circuit according to the present invention.

[0026] Figure 2 for Figure 1 The output curve of the output buffer is shown.

[0027] Figure 3 The figure is a comparison of the bandwidth of the front-end circuit using a traditional source follower buffer and the output buffer of the present invention.

[0028] Figure 4 4 is a curve comparison diagram of the THD of the output buffer of the present invention and the conventional continuous working buffer as the input signal fi n changes. DETAILED DESCRIPTION

[0029] The present invention will be further described below with reference to the accompanying drawings.

[0030] The device for improving the switching linearity and bandwidth of a sample-and-hold circuit of the present invention comprises a sample-and-hold circuit and an output buffer electrically connected to the sampling signal output terminal of the sample-and-hold circuit. In order to reduce the influence of interference on signal transmission and reduce signal distortion and error, in this embodiment, the output buffer is a differential structure. Figure 1 The output buffer includes a first voltage signal output structure and a second voltage signal output structure. The first voltage signal output structure includes a first switch control unit 100, a first bias load unit 200, and a first signal output unit 300. The first switch control unit 100 is used to disconnect the first bias load unit 200 from the first signal output unit 300 when the operating mode of the sample and hold circuit is the tracking mode (sampling mode), and is used to connect the first bias load unit 200 to the first signal output unit 300 when the operating mode of the sample and hold circuit is the holding mode; the first bias load unit 200 is used to receive an externally supplied bias voltage and provide a load; the first signal output unit 300 is used to disconnect the first voltage signal V when the operating mode of the sample and hold circuit is the tracking mode. buf_outn The output of the sampling and holding circuit is a first voltage signal V when the working mode of the sampling and holding circuit is a holding mode. buf_outnTo drive the subsequent ADC circuit (A / D converter circuit). The second voltage signal output structure includes a second switch control unit 500, a second bias load unit 600, and a second signal output unit 700. The second switch control unit 500 is used to disconnect the second bias unit from the second signal output unit 700 when the operating mode of the sample and hold circuit is the tracking mode, and to connect the second bias load unit 600 to the second signal output unit 700 when the operating mode of the sample and hold circuit is the hold mode; the second bias load unit 600 is used to connect the externally supplied bias voltage and provide a load; the second signal output unit 700 is used to disconnect the second voltage signal V when the operating mode of the sample and hold circuit is the tracking mode. buf_outp The output of the second voltage signal V is output when the working mode of the sampling and holding circuit is the holding mode. buf_outp The first voltage signal V buf_outn and the second voltage signal V buf_outp They are differential signals with a phase difference of 180 degrees. Their amplitudes are equal but their phases are opposite. When external interference affects one of the differential signals, the interference will be canceled out at the receiving end of the differential signal because the other signal has a phase difference of 180 degrees.

[0031] When the output buffer is operating in tracking mode, it may introduce additional charge injection, affecting the voltage of the sampling capacitor and reducing the bandwidth. If the output buffer is only operating in hold mode, it can reduce the charge injection during the sampling process, thereby improving linearity and increasing bandwidth. In addition, when the output buffer is operating in hold mode, it can effectively isolate the noise and interference between the input and output signals, which helps maintain the stability and accuracy of the output voltage, thereby further improving the linearity of the circuit. Figure 2 In the hold mode, the output buffer switches to the working state and drives the subsequent A / D converter circuit. Figure 2 shows the operation of the output buffer in hold mode.

[0032] The first switch control unit 100 is defined as a first MOSFET M1 , the gate of which is connected to the clock signal CLK <2> The source of the first MOS tube M1 is electrically connected to the first bias load unit 200, and the drain of the first MOS tube M1 is electrically connected to the first signal output unit 300. In this embodiment, the first MOS tube M1 is a pmos tube. When the clock signal CLK <2> When the clock signal CLK is low, the first MOS tube M1 is turned on. <2> When the voltage is high, the first MOSFET M1 is turned off. The first bias load unit 200 is defined as a second MOSFET M2. In this embodiment, the second MOSFET M2 is a pmos transistor. The gate of the second MOSFET M2 is connected to an externally supplied bias voltage, the drain of the second MOSFET M2 is electrically connected to the source of the first MOSFET M1, and the source of the second MOSFET M2 is connected to a power supply voltage. In this embodiment, the power supply voltage is 850mV. The first signal output unit 300 includes a third MOSFET M3. In this embodiment, the third MOSFET M3 is a pmos transistor. The gate of the third MOSFET M3 is connected to a sampling signal, the drain of the third MOSFET M3 is grounded, and the source of the third MOSFET M3 is electrically connected to the drain of the first MOSFET M1. When the first MOSFET M1 is turned on, the current of the second MOSFET M2 flows into the third MOSFET M3, the third MOSFET M3 is turned on, and the source of the third MOSFET M3 outputs a first voltage signal V buf_outn When the first MOSFET M1 is turned off, the DC current of the circuit is cut off, and the third MOSFET M3 is turned off. The source of the third MOSFET M3 is disconnected from the first voltage signal V buf_outn Output.

[0033] The second switch control unit 500 is defined as a sixth MOSFET M6, the gate of which is connected to the clock signal CLK <2> The source of the sixth MOS transistor M6 is electrically connected to the second bias load unit 600, and the drain of the sixth MOS transistor M6 is electrically connected to the second signal output unit 700. In this embodiment, the sixth MOS transistor M6 is a pmos transistor. When the clock signal CLK <2> When the clock signal CLK is low, the sixth MOS tube M6 is turned on. <2> When the voltage is high, the sixth MOSFET M6 is turned off. The second bias load unit 600 is defined as the seventh MOSFET M7. In this embodiment, the seventh MOSFET M7 is a pmos transistor. The gate of the seventh MOSFET M7 is connected to the externally supplied bias voltage, the source of the seventh MOSFET M7 is connected to the power supply voltage, and the drain of the seventh MOSFET M7 is electrically connected to the source of the sixth MOSFET M6. The second signal output unit 700 includes an eighth MOSFET M8. In this embodiment, the eighth MOSFET M8 is a pmos transistor. The gate of the eighth MOSFET M8 is connected to the sampling signal, the drain of the eighth MOSFET M8 is grounded, and the source of the eighth MOSFET M8 is electrically connected to the drain of the sixth MOSFET M6. When the sixth MOSFET M6 is turned on, the current of the seventh MOSFET M7 flows into the eighth MOSFET M8, the eighth MOSFET M8 is turned on, and the source of the eighth MOSFET M8 outputs the second voltage signal V buf_outp When the sixth MOSFET M6 is turned off, the DC current of the circuit is cut off, the eighth MOSFET M8 is turned off, and the source of the eighth MOSFET M8 is disconnected from the second voltage signal V buf_outp Output.

[0034] In order to reduce harmonic distortion and improve linearity, as a preferred embodiment, the first signal output unit 300 is further provided with a fourth MOS tube M4. In this embodiment, the fourth MOS tube M4 is an NMOS tube. The gate of the fourth MOS tube M4 is connected to the clock signal CLK <2> The source of the fourth MOSFET M4 is grounded, and the drain of the fourth MOSFET M4 is electrically connected to the source of the third MOSFET M3. <2> When the voltage is low, the fourth MOS tube M4 is turned off, and the source of the third MOS tube M3 outputs the first voltage signal V buf_outn , when the clock signal CLK <2> When the voltage is high, the fourth MOSFET M4 is turned on, and the drain of the fourth MOSFET M4 is short-circuited to GND. During the tracking phase, the fourth MOSFET M4 pulls the voltage at the output point to close to 0. This reduces the feedthrough effect caused by the input signal passing through the source-drain parasitic capacitance (Cgs) during the clock switching process, that is, the transition from tracking mode to hold mode. This reduces the harmonic distortion of the overall structure and improves linearity.

[0035] Similarly, the second signal output unit 700 is further provided with a ninth MOSFET M9. In this embodiment, the ninth MOSFET M9 is an NMOS transistor. The gate of the ninth MOSFET M9 is connected to the clock signal CLK <2> , the source of the ninth MOSFET M9 is grounded, and the drain of the ninth MOSFET M9 is electrically connected to the source of the eighth MOSFET M8; when the clock signal CLK <2> When the voltage is low, the ninth MOSFET M9 is turned off, and the source of the eighth MOSFET M8 outputs the second voltage signal V buf_outp , when the clock signal CLK <2> When the voltage is high, the ninth MOSFET M9 is turned on, and the drain of the ninth MOSFET M9 is short-circuited to GND.

[0036] In order to avoid introducing harmonic distortion when switching from tracking mode to holding mode, as a preferred embodiment, a first step-down unit 400 is provided for reducing the common-mode voltage increased when switching to holding mode; the first step-down unit 400 is defined as a fifth MOSFET M5. In this embodiment, the fifth MOSFET M5 is an NMOS transistor. The gate of the fifth MOSFET M5 is connected to the clock signal CLK <2> The source of the fifth MOSFET M5 is electrically connected to the sampling signal output terminal of the sample-and-hold circuit to receive the sampling signal. The drain of the fifth MOSFET M5 is electrically connected to the gate of the third MOSFET M3. The source and drain of the fifth MOSFET M5 are electrically connected. When switching to hold mode, the increase in output voltage will couple to the node of the sampling capacitor, thereby increasing the output common-mode voltage. This increase may cause unstable circuit performance or increase noise, adversely affecting the overall performance of the circuit. This embodiment cleverly designs the fifth MOSFET M5 to reduce the clock feedthrough effect and offset the increase in common-mode voltage caused by the increase in output voltage, thereby avoiding the introduction of harmonic distortion and ensuring the output quality of the circuit.

[0037] In the tracking mode, the first MOSFET M1 is turned off, cutting off the DC current of the circuit and disconnecting the first voltage signal V buf_outn At the sampling point, the total charge Q stored on the sampling node is obtained by the following formula:

[0038] Q=(V TH_in +V0)(C S +C gs )(one)

[0039] Where V0 represents the input sampling voltage V TH_in The DC voltage. C S Represents all parasitic capacitances on the gate of M5 except Cgs.

[0040] In the hold mode, the first MOSFET M1 is turned on, causing the current of the second MOSFET M2 to flow into the third MOSFET M3, and the fourth MOSFET M4 is turned off. The source output voltage signal of the third MOSFET M3 drives the subsequent A / D converter circuit. T / H,infinal and V buf,outfinal After charge redistribution, V TH,in and V buf,out The final value of V T / H,infinal Obtained by the following formula:

[0041]

[0042] V buf,outfinal Obtained by the following formula:

[0043]

[0044] Where V gs0 Indicates V gs DC voltage, enters the hold mode, the output voltage V buf,out The increase in will couple to the sampling capacitor node, increasing the output common-mode voltage, as shown in the last term of Equation (2). To mitigate this, a fifth MOSFET is added to use its falling-edge clock feedthrough to offset the increase in common-mode voltage. Compared to a conventional continuously operating output buffer, Equations (2) and (3) demonstrate that the output buffer of the present invention introduces no harmonic distortion.

[0045] Similarly, a second step-down unit 800 is provided for reducing the common mode voltage increased when switching to the hold mode; the second step-down unit 800 is defined as the tenth MOSFET M10. In this embodiment, the tenth MOSFET M10 is an NMOS transistor. The gate of the tenth MOSFET M10 is connected to the clock signal CLK <2> The source of the tenth MOSFET M10 is electrically connected to the sampling signal output end of the sample-and-hold circuit to receive the sampling signal, the drain of the tenth MOSFET M10 is electrically connected to the gate of the eighth MOSFET M8, and the source and drain of the tenth MOSFET M10 are electrically connected.

[0046] In addition, in this embodiment, there is no need to set a dedicated sampling capacitor. The device capacitance of the third MOSFET M3 and the fifth MOSFET M5, the line capacitance, and the parasitic capacitance between the lines are used as the sampling capacitor. This not only reduces the volume and weight of the circuit and improves the circuit integration, but also reduces additional components, thereby reducing parasitic effects, improving the circuit bandwidth, and eliminating the circuit's limitation on the bandwidth of the subsequent A / D converter.

[0047] The designed A / D converter front-end circuit is based on the PDK of the SMIC 12nm FET process, with an input common-mode voltage Vcom_i n of 125mV, a swing of 500Vpp, a sampling frequency fs=10GS / s, and a power supply voltage of 0.85V. Figure 3 Through circuit simulation, the bandwidth curves of the output buffer and source follower output buffer of the present invention can be obtained. Figure 3 The AC / DC simulation shown shows that the bandwidth of the traditional source follower buffer is only 12.2 GHz, which greatly limits the bandwidth of the front-end circuit of the A / D converter and affects the performance of the A / D converter. However, the output buffer of the present invention expands the bandwidth to 33.5 GHz.

[0048] See also Figure 4 , which is a comparison chart of the total harmonic distortion (THD) changing with the input signal fin. Through joint simulation with the sample-and-hold circuit, the output buffer of the present invention is compared with the conventional continuous working buffer. Figure 4 As shown in the figure, the input signal swing is 500mVppd and the input common-mode voltage is 125mV. It can be seen that, thanks to the output buffer of the present invention, the THD performance is improved by up to 11dB for higher input frequencies (e.g., 7.5GHz).

[0049] The present invention uses time-sharing control to disable the output buffer when the sampling circuit operates in tracking mode, and to operate when the sampling circuit operates in hold mode, thereby reducing charge injection during the sampling process and improving linearity. By adding a fourth MOSFET M4 and a ninth MOSFET M9 to the output buffer to pull the voltage at the output point close to zero during the tracking phase, harmonic distortion is reduced, particularly when switching from tracking mode to hold mode, thereby avoiding the introduction of additional harmonic distortion. By cleverly designing the first step-down unit 400 and the second step-down unit 800, effective control of the common-mode voltage is achieved, avoiding unstable circuit performance or increased noise caused by increased output voltage. By using device capacitors and parasitic capacitors as sampling capacitors, the use of additional components is reduced, which not only reduces the volume and weight of the circuit and reduces costs, but also reduces parasitic effects and significantly improves the bandwidth of the overall circuit. The present invention is suitable for high-speed signal processing scenarios, such as high-frequency communications and radar signal processing, and can meet the high requirements of high-speed A / D converters for front-end circuits.

Claims

1. A device for improving the switching linearity and bandwidth of a sample-and-hold circuit, comprising a sample-and-hold circuit and an output buffer electrically connected to a sampling signal output terminal of the sample-and-hold circuit, characterized in that: The output buffer is a differential structure, including a first voltage signal output structure and a second voltage signal output structure, wherein the first voltage signal output structure includes: a first switch control unit, configured to disconnect the first bias load unit from the first signal output unit when the operating mode of the sample-and-hold circuit is a tracking mode, and to connect the first bias load unit to the first signal output unit when the operating mode of the sample-and-hold circuit is a holding mode; a first bias load unit, configured to receive an externally supplied bias voltage and provide a load; and a first signal output unit, configured to disconnect the output of the first voltage signal when the operating mode of the sample and hold circuit is the tracking mode, and output the first voltage signal when the operating mode of the sample and hold circuit is the holding mode; The second voltage signal output structure includes: a second switch control unit, configured to disconnect the second bias unit from the second signal output unit when the operation mode of the sample-and-hold circuit is the tracking mode, and to connect the second bias load unit to the second signal output unit when the operation mode of the sample-and-hold circuit is the holding mode; a second bias load unit, configured to receive an externally supplied bias voltage and provide a load; and The second signal output unit is used to disconnect the output of the second voltage signal when the working mode of the sampling and holding circuit is the tracking mode, and output the second voltage signal when the working mode of the sampling and holding circuit is the holding mode.

2. The device for improving the switching linearity and bandwidth of a sample-and-hold circuit according to claim 1, wherein: The first switch control unit is defined as a first MOSFET M1, a gate of the first MOSFET M1 is connected to the clock signal, a source of the first MOSFET M1 is electrically connected to the first bias load unit, and a drain of the first MOSFET M1 is electrically connected to the first signal output unit; when the clock signal is at a high level, the first MOSFET M1 is turned off, and when the clock signal is at a low level, the first MOSFET M1 is turned on.

3. The device for improving the switching linearity and bandwidth of a sample-and-hold circuit according to claim 2, wherein: The first bias load unit is defined as a second MOSFET M2, a gate of the second MOSFET M2 is connected to an externally supplied bias voltage, a source of the second MOSFET M2 is connected to a power supply voltage, and a drain of the second MOSFET M2 is electrically connected to the source of the first MOSFET M1.

4. The device for improving the switching linearity and bandwidth of a sample-and-hold circuit according to claim 2, wherein: The first signal output unit includes a third MOSFET M3, a gate of the third MOSFET M3 is connected to the sampling signal, a drain of the third MOSFET M3 is grounded, and a source of the third MOSFET M3 is electrically connected to the drain of the first MOSFET M1; when the first MOSFET M1 is turned on, the third MOSFET M3 is turned on, and the source of the third MOSFET M3 outputs a first voltage signal; when the first MOSFET M1 is turned off, the third MOSFET M3 is turned off, and the source of the third MOSFET M3 disconnects the output of the first voltage signal.

5. The device for improving the switching linearity and bandwidth of a sample-and-hold circuit according to claim 4, wherein: The first signal output unit also includes a fourth MOSFET M4, a gate of the fourth MOSFET M4 is connected to the clock signal, a source of the fourth MOSFET M4 is grounded, and a drain of the fourth MOSFET M4 is electrically connected to the source of the third MOSFET M3. When the clock signal is at a high level, the fourth MOSFET M4 is turned on, and the source of the third MOSFET M3 outputs a first voltage signal. When the clock signal is at a low level, the fourth MOSFET M4 is turned off, and the drain of the fourth MOSFET M4 is short-circuited to GND.

6. The device for improving the switching linearity and bandwidth of a sample-and-hold circuit according to claim 4, wherein: The circuit further includes a first step-down unit for reducing the common-mode voltage increased when switching to the hold mode; the first step-down unit is defined as a fifth MOSFET M5, the gate of the fifth MOSFET M5 is connected to the clock signal, the source of the fifth MOSFET M5 is electrically connected to the sampling signal output end of the sample-and-hold circuit to receive the sampling signal, the drain of the fifth MOSFET M5 is electrically connected to the gate of the third MOSFET M3, and the source and drain of the fifth MOSFET M5 are electrically connected.

7. The device for improving the switching linearity and bandwidth of a sample-and-hold circuit according to claim 1, wherein: The second switch control unit is defined as a sixth MOSFET M6, a gate of the sixth MOSFET M6 is connected to the clock signal, a source of the sixth MOSFET M6 is electrically connected to the second bias load unit, and a drain of the sixth MOSFET M6 is electrically connected to the second signal output unit; when the clock signal is at a high level, the sixth MOSFET M6 is turned off, and when the clock signal is at a low level, the sixth MOSFET M6 is turned on; The second bias load unit is defined as a seventh MOSFET M7, a gate of the seventh MOSFET M7 is connected to an externally supplied bias voltage, a source of the seventh MOSFET M7 is connected to a power supply voltage, and a drain of the seventh MOSFET M7 is electrically connected to the source of the sixth MOSFET M6.

8. The device for improving the switching linearity and bandwidth of a sample-and-hold circuit according to claim 7, wherein: The second signal output unit includes an eighth MOSFET M8, wherein the gate of the eighth MOSFET M8 is connected to the sampling signal, the drain of the eighth MOSFET M8 is grounded, and the source of the eighth MOSFET M8 is electrically connected to the drain of the sixth MOSFET M6; when the sixth MOSFET M6 is turned on, the eighth MOSFET M8 is turned on, and the source of the eighth MOSFET M8 outputs a second voltage signal; when the sixth MOSFET M6 is turned off, the eighth MOSFET M8 is turned off, and the source of the eighth MOSFET M8 disconnects the output of the second voltage signal.

9. The device for improving the switching linearity and bandwidth of a sample-and-hold circuit according to claim 8, wherein: The second signal output unit further includes a ninth MOSFET M9, wherein a gate of the ninth MOSFET M9 is connected to a clock signal, a source of the ninth MOSFET M9 is grounded, and a drain of the ninth MOSFET M9 is electrically connected to the source of the eighth MOSFET M8; when the clock signal is at a high level, the ninth MOSFET M9 is turned on, and the source of the eighth MOSFET M8 outputs a second voltage signal; when the clock signal is at a low level, the ninth MOSFET M9 is turned off, and the drain of the ninth MOSFET M9 is short-circuited to GND.

10. The device for improving the switching linearity and bandwidth of a sample-and-hold circuit according to claim 8, wherein: The circuit further includes a second step-down unit for reducing the common-mode voltage increased when switching to the hold mode; the second step-down unit is defined as a tenth MOSFET M10, the gate of the tenth MOSFET M10 is connected to the clock signal, the source of the tenth MOSFET M10 is electrically connected to the sampling signal output end of the sample-and-hold circuit to receive the sampling signal, the drain of the tenth MOSFET M10 is electrically connected to the gate of the eighth MOSFET M8, and the source and drain of the tenth MOSFET M10 are electrically connected.

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