Information processing method and apparatus, and communication device

Abstract

The invention discloses a coding method, a coding device, communication equipment and a communication system. The method comprises: encoding an input bit sequence using a low density parity check (LDPC) matrix; wherein the LDPC matrix is obtained on the basis of an expansion factor Z and a basis matrix, the basis matrix comprises 0 to 4 rows and 0 to 26 columns in one of the matrixes shown in figures 3b-1 to 3b-10, or the basis matrix comprises a part of columns in the 0 to 4 rows and the 0 to 26 columns in one of the matrixes shown in figures 3b-1 to 3b-10. According to the coding method, the coding device, the communication equipment and the communication system, the channel coding requirement can be met.

Description

[0001] This application is a divisional application. The application number of the original application is 201880043380.3, and the original application date is March 29, 2018. The entire contents of the original application are incorporated into this application by reference. Technical Field

[0002] The embodiments of the present invention relate to the field of communications, and in particular to an information processing method and a communication device. Background Art

[0003] Low density parity check (LDPC) code is a type of linear block code with a sparse check matrix, which has the characteristics of flexible structure and low decoding complexity. Because it uses a partially parallel iterative decoding algorithm, it has a higher throughput than traditional Turbo codes. LDPC codes can be used as error correction codes in communication systems, thereby improving the reliability and power utilization of channel transmission. LDPC codes can also be widely used in space communications, optical fiber communications, personal communication systems, ADSL and magnetic recording equipment. At present, LDPC codes have been considered as one of the channel coding methods in the fifth generation mobile communications.

[0004] In actual use, an LDPC matrix with special structural characteristics can be used. The LDPC matrix H with special structural characteristics can be expanded from an LDPC base matrix with a quasi cycle (QC) structure. QC-LDPC is suitable for hardware with high parallelism and provides a higher throughput. The LDPC matrix can be designed to be applied to channel coding.

[0005] QC-LDPC is suitable for hardware with high parallelism and provides higher throughput. It can be applied to channel coding by designing the LDPC matrix. Summary of the invention

[0006] The embodiments of the present invention provide an information processing method, a communication device and a system, which can support the encoding and decoding of information bit sequences of various lengths.

[0007] In a first aspect, a coding method and an encoder are provided, wherein the encoder encodes an input sequence using a low-density parity check (LDPC) matrix.

[0008] In a second aspect, a decoding method and a decoder are provided, wherein the decoder decodes an input sequence using a low-density parity check (LDPC) matrix.

[0009] In a first implementation of the first aspect or the second aspect above: the LDPC matrix is ​​obtained based on the expansion factor Z and the base matrix.

[0010] Based on the above implementation, the base matrix of the base graph 30a may include the 0th to 4th rows and the 0th to 26th columns of one of the matrices shown in matrices 30b-10, 30b-11, 30b-20, 30b-21, 30b-30, 30b-40, 30b-50, 30b-60, 30b-70 and 30b-80, or the base matrix includes the matrices 30b-10, 30b-11, 30b-20, 30b-21, 30b-30, 30b-40, 30b-50, 30b-60, 30b-70 and 30b-80. The base matrix may be a matrix of rows 0 to 4 and partial columns 0 to 26 in one of the matrices shown in matrices 30b-10 to 30b-80 after row / column transformation, or the base matrix may be a matrix of rows 0 to 4 and partial columns 0 to 26 in one of the matrices shown in matrices 30b-10, 30b-11, 30b-20, 30b-21, 30b-30, 30b-40, 30b-50, 30b-60, 30b-70 and 30b-80 after row / column transformation.

[0011] Further, the base matrix of base graph 30a may also include the 0th row to the (m-1th)th row and the 0th column to the (n-1th)th column in one of the matrices shown in matrices 30b-10, 30b-11, 30b-20, 30b-21, 30b-30, 30b-40, 30b-50, 30b-60, 30b-70 and 30b-80, or the base matrix may be a matrix after row / column transformation of the 0th row to the (m-1th)th row and the 0th column to the (n-1th)th column in one of the matrices shown in matrices 30b-10, 30b-11, 30b-20, 30b-21, 30b-30, 30b-40, 30b-50, 30b-60, 30b-70 and 30b-80. 5≤m≤46,27≤n≤68.

[0012] In order to support different block lengths, LDPC codes require different expansion factors Z. Based on the above implementation, in one possible implementation, a base matrix corresponding to the different expansion factors Z is used. For example, Z = a × 2 j , 0≤j<7, a∈{2,3,5,7,9,11,13,15}.

[0013] If a=2, the base matrix may include rows 0 to 4 and columns 0 to 26 of the matrix 30b-10 or 30b-11, or the base matrix includes rows 0 to 4 and some columns of columns 0 to 26 of the matrix 30b-10 or 30b-11. Further, the base matrix also includes rows 0 to (m-1)th rows and columns 0 to (n-1)th columns of the matrix 30b-10 or 30b-11.

[0014] If a=3, the base matrix may include rows 0 to 4 and columns 0 to 26 of the matrix 30b-20 or 30b-21, or the base matrix may include rows 0 to 4 and some columns 0 to 26 of the matrix 30b-20 or 30b-21. Further, the base matrix may also include rows 0 to (m-1) and columns 0 to (n-1) of the matrix 30b-20 or 30b-21.

[0015] If a=5, the base matrix may include rows 0 to 4 and columns 0 to 26 of the matrix 30b-30, or the base matrix includes rows 0 to 4 and some columns of columns 0 to 26 of the matrix 30b-30. Further, the base matrix also includes rows 0 to (m-1)th rows and columns 0 to (n-1)th columns of the matrix 30b-30.

[0016] If a=7, the base matrix may include rows 0 to 4 and columns 0 to 26 of the matrix 30b-40, or the base matrix includes rows 0 to 4 and some columns of columns 0 to 26 of the matrix 30b-40. Further, the base matrix also includes rows 0 to (m-1)th rows and columns 0 to (n-1)th columns of the matrix 30b-40.

[0017] If a=9, the base matrix may include rows 0 to 4 and columns 0 to 26 of the matrix 30b-50, or the base matrix includes rows 0 to 4 and some columns of columns 0 to 26 of the matrix 30b-50. Further, the base matrix also includes rows 0 to (m-1)th rows and columns 0 to (n-1)th columns of the matrix 30b-50.

[0018] If a=11, the base matrix may include rows 0 to 4 and columns 0 to 26 of the matrix 30b-60, or the base matrix includes rows 0 to 4 and some columns of columns 0 to 26 of the matrix 30b-60. Further, the base matrix also includes rows 0 to (m-1)th rows and columns 0 to (n-1)th columns of the matrix 30b-60.

[0019] If a=13, the base matrix may include rows 0 to 4 and columns 0 to 26 of the matrix 30b-70, or the base matrix includes rows 0 to 4 and some columns of columns 0 to 26 of the matrix 30b-70. Further, the base matrix also includes rows 0 to (m-1)th rows and columns 0 to (n-1)th columns of the matrix 30b-70.

[0020] If a=15, the base matrix may include rows 0 to 4 and columns 0 to 26 of the matrix 30b-80, or the base matrix includes rows 0 to 4 and some columns of columns 0 to 26 of the matrix 30b-80. Further, the base matrix also includes rows 0 to (m-1)th rows and columns 0 to (n-1)th columns of the matrix 30b-80.

[0021] The base matrix may be a matrix obtained by transforming the rows / columns of the corresponding matrix.

[0022] Further, optionally, based on the above implementation, the LDPC matrix can be obtained based on the expansion factor Z and the matrix Hs after compensating the aforementioned base matrices, or based on the expansion factor Z and the matrix Hs after row / column transformation of the matrix Hs after compensating the aforementioned base matrices. Compensating the aforementioned base matrices can be to increase or decrease the compensation value for the offset value greater than or equal to 0 in one or more columns.

[0023] The base graph and base matrix of the LDPC matrix in the above-mentioned implementations can meet the performance requirements of code blocks of various block lengths.

[0024] Based on the above aspects, or any possible implementation of each aspect, in another possible implementation, it also includes: determining the expansion factor Z. For example, the value of the expansion factor Z is determined according to the length K of the input sequence, and the smallest Z0 can be found in the supported expansion factor set as the size of the expansion factor Z, and Kb·Z0≥K is satisfied. In one possible design, Kb can be the number of columns of information bits in the base matrix of the LDPC code. For example, for base graph 30a, Kb=22. In another possible design, the value of Kb can also vary according to the value of K, but does not exceed the number of information bit columns in the base matrix of the LDPC code. For example, when K is greater than the first threshold, Kb=22; when K is less than or equal to the first threshold, Kb=21. Or, when K is greater than the first threshold, Kb=22; when K is less than or equal to the first threshold and K is greater than the second threshold, Kb=21; when K is less than or equal to the second threshold, Kb=20.

[0025] The expansion factor Z may be determined by the encoder or decoder according to the length K of the input sequence, or may be determined by other devices and provided to the encoder or decoder as an input parameter.

[0026] Optionally, an LDPC matrix may be obtained according to the acquired expansion factor Z and a base matrix corresponding to the expansion factor Z.

[0027] In a second implementation of the first aspect or the second aspect above: the LDPC matrix is ​​obtained based on the expansion factor Z and the parameters of the LDPC matrix.

[0028] The parameters of the LDPC matrix may include: row number, column where the non-zero element is located, non-zero element offset value, such as Table 3-10, Table 3-11, Table 3-20, Table 3-21, Table 3-30, Table 3-40, Table 3-50, Table 3-60, Table 3-70 and Table 3-80. Row weight may also be included. Each position in the column where the non-zero element is located and each offset value in the non-zero element offset value are one-to-one corresponding.

[0029] Thus, the encoder encodes the input sequence according to the expansion factor Z and the parameters of the LDPC matrix. The parameters saved according to Table 3-10 correspond to the matrix 30b-10, the parameters saved according to Table 3-11 correspond to the matrix 30b-11, the parameters saved according to Table 3-20 correspond to the matrix 30b-20, the parameters saved according to Table 3-21 correspond to the matrix 30b-21, the parameters saved according to Table 3-30 correspond to the matrix 30b-30, the parameters saved according to Table 3-40 correspond to the matrix 30b-40, the parameters saved according to Table 3-50 correspond to the matrix 30b-50, the parameters saved according to Table 3-60 correspond to the matrix 30b-60, the parameters saved according to Table 3-70 correspond to the matrix 30b-70, and the parameters saved according to Table 3-80 correspond to the matrix 30b-80.

[0030] For a communication device at a transmitting end, encoding the input sequence using an LDPC matrix may include:

[0031] The input sequence is encoded using an LDPC matrix corresponding to the expansion factor Z; or the LDPC matrix corresponding to the expansion factor Z is subjected to a row / column transformation, and the input sequence is encoded using a matrix after the row / column transformation. In the present application, the row / column transformation refers to a row transformation, a column transformation, or a row transformation and a column transformation.

[0032] For the communication device at the receiving end, decoding the input sequence using the LDPC matrix includes:

[0033] The input sequence is decoded using the LDPC matrix corresponding to the expansion factor Z; or the LDPC matrix corresponding to the expansion factor Z is subjected to row / column transformation, and the matrix after the row / column transformation is used to encode the input sequence. In the present application, the row / column transformation refers to row transformation, column transformation, or row transformation and column transformation.

[0034] In a possible implementation, an LDPC matrix may be saved and used to encode an input sequence, or an LDPC matrix that can be used for encoding may be obtained by transforming (row / column transformation) or extending the LDPC matrix.

[0035] In another possible implementation, parameters can be saved, and an LDPC matrix for encoding or decoding can be obtained according to the parameters, so that the input sequence can be encoded or decoded based on the LDPC matrix. The parameters include at least one of the following: a base graph, a base matrix, a transformation matrix after a base graph or base matrix row / column transformation, an extended matrix based on the base graph or base matrix, an offset value of a non-zero element in the base matrix, or any parameter related to obtaining the LDPC matrix.

[0036] In yet another possible implementation, the base matrix of the LDPC matrix may be stored in a memory.

[0037] In yet another possible implementation, a base graph of the LDPC matrix is ​​stored in a memory, and offset values ​​of non-zero elements in the base matrix of the LDPC matrix may be stored in the memory.

[0038] In another possible implementation, the parameters of the LDPC matrix are stored in the memory in the manner shown in Table 3-10 to Table 3-80.

[0039] Based on the above possible implementation methods, in one possible design, at least one of the base graphs and base matrices used for LDPC encoding or decoding is obtained by performing row exchange, column exchange, or row and column exchange on at least one of the base graphs and base matrices of the above LDPC matrix.

[0040] In a third aspect, a communication device is provided that may include a module for executing the corresponding module in the above method design. The module may be software and / or hardware.

[0041] In one possible design, the communication device provided in the third aspect includes a processor and a transceiver component, which can be used to implement the functions of each part of the above-mentioned encoding or decoding method. In this design, if the communication device is a terminal, a base station or other network equipment, its transceiver component can be a transceiver, and if the communication device is a baseband chip or a baseband board, its transceiver component can be an input / output circuit of the baseband chip or the baseband board, which is used to realize the reception / transmission of input / output signals. The communication device can optionally also include a memory for storing data and / or instructions.

[0042] In one implementation, the processor may include an encoder as described in the first aspect and a determination unit. The determination unit is used to determine an expansion factor Z required for encoding an input sequence. The encoder is used to encode the input sequence using an LDPC matrix corresponding to the expansion factor Z.

[0043] In another implementation, the processor may include a decoder and an acquisition unit as described in the second aspect. The acquisition unit is used to acquire the soft value and the expansion factor Z of the LDPC code. The decoder is used to obtain the soft value and the expansion factor Z based on the base matrix H corresponding to the expansion factor Z. B The soft value decoding of the LDPC code obtains the information bit sequence.

[0044] In a fourth aspect, a communication device is provided, comprising one or more processors.

[0045] In one possible design, one or more of the processors may implement the function of the encoder described in the first aspect. In another possible design, the encoder described in the first aspect may be a part of the processor, and the processor may implement other functions in addition to implementing the function of the encoder described in the first aspect.

[0046] In one possible design, one or more of the processors may implement the functionality of the decoder described in the second aspect. In another possible design, the decoder described in the second aspect may be a part of the processor.

[0047] Optionally, the communication device may further include a transceiver and an antenna.

[0048] Optionally, the communication device may also include a device for generating a transmission block CRC, a device for code block segmentation and CRC checking, an interleaver for interleaving, or a modulator for modulation processing, etc.

[0049] Optionally, the communication device may further include a demodulator for demodulation operation, a deinterleaver for deinterleaving, or a device for rate matching, etc. The functions of these devices may be implemented by one or more processors.

[0050] In one possible design, the functions of these devices may be implemented by one or more processors.

[0051] In a fifth aspect, an embodiment of the present invention provides a communication system, which includes the communication device described in the third aspect.

[0052] In a sixth aspect, an embodiment of the present invention provides a communication system, which includes one or more communication devices described in the fourth aspect.

[0053] On the other hand, an embodiment of the present invention provides a computer storage medium on which a program is stored, and when the program is run, the computer executes the method described in the above aspects.

[0054] Another aspect of the present application provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the methods described in the above aspects.

[0055] The information processing method, apparatus, communication device and communication system of the embodiments of the present invention can adapt to the flexible and changeable code length and code rate requirements of the system in terms of coding performance and error level. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 is a schematic diagram of a base graph, a base matrix and a circulant permutation matrix of an LDPC code;

[0057] Figure 2 is a schematic diagram of the structure of a base graph of an LDPC code;

[0058] Figure 3a A schematic diagram of an LDPC code base diagram provided by an embodiment of the present invention;

[0059] Figure 3b-1 A schematic diagram of a base matrix provided by an embodiment of the present invention;

[0060] Figure 3b-2 A schematic diagram of another base matrix provided by an embodiment of the present invention;

[0061] Figure 3b-3 A schematic diagram of another base matrix provided by an embodiment of the present invention;

[0062] Figure 3b-4 A schematic diagram of another base matrix provided by an embodiment of the present invention;

[0063] Figure 3b-5 A schematic diagram of another base matrix provided by an embodiment of the present invention;

[0064] Figure 3b-6 A schematic diagram of another base matrix provided by an embodiment of the present invention;

[0065] Figure 3b-7 A schematic diagram of another base matrix provided by an embodiment of the present invention;

[0066] Figure 3b-8 A schematic diagram of another base matrix provided by an embodiment of the present invention;

[0067] Figure 3b-9 A schematic diagram of another base matrix provided by an embodiment of the present invention;

[0068] Figure 3b-10 A schematic diagram of another base matrix provided by an embodiment of the present invention;

[0069] Figure 4 A performance diagram provided for an embodiment of the present invention;

[0070] Figure 5 A flowchart of an information processing method provided by another embodiment of the present invention;

[0071] Figure 6 A flowchart of an information processing method provided by another embodiment of the present invention;

[0072] Figure 7 A schematic diagram of the structure of an information processing device provided by another embodiment of the present invention;

[0073] Figure 8 A schematic diagram of a communication system provided by another embodiment of the present invention;

[0074] Fig. 9 A schematic diagram of the offset value of a base matrix provided by another embodiment of the present invention. DETAILED DESCRIPTION

[0075] To facilitate understanding, some terms involved in this application are explained below.

[0076] In this application, the terms "network" and "system" are often used interchangeably, and "device" and "equipment" are also often used interchangeably, but those skilled in the art can understand their meanings. "Communication device" can be a chip (such as a baseband chip, or a data signal processing chip, or a general chip, etc.), a terminal, a base station, or other network equipment. A terminal is a device with communication functions, which may include a handheld device with wireless communication functions, a vehicle-mounted device, a wearable device, a computing device, or other processing devices connected to a wireless modem, etc. In different networks, terminals can be called different names, such as: user equipment, mobile station, user unit, station, cellular phone, personal digital assistant, wireless modem, wireless communication device, handheld device, laptop, cordless phone, wireless local loop station, etc. For the convenience of description, it is referred to as a terminal in this application. A base station (BS), also known as a base station device, is a device deployed in a wireless access network to provide wireless communication functions. The names of base stations may be different in different wireless access systems. For example, in the Universal Mobile Telecommunications System (UMTS) network, the base station is called NodeB, and in the LTE network, the base station is called evolved NodeB (eNB or eNodeB), and in the new radio (NR) network, the base station is called a transmission reception point (TRP) or a next generation nodeB (gNB), or the base stations in various other evolved networks may also use other names. The present invention is not limited to this.

[0077] The technical solutions in the embodiments of the present invention will be described below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0078] LDPC codes can usually be represented by a parity check matrix H. The parity check matrix H of the LDPC code can be obtained through a base graph and a shift value. The base graph can usually include m*n matrix elements (entries), which can be represented in the form of a matrix with m rows and n columns. The values ​​of the matrix elements are 0 or 1. The elements with a value of 0 are sometimes also called zero elements, indicating that the element can be replaced by a Z*Z all-zero matrix (zero matrix). The elements with a value of 1 are sometimes also called non-zero elements, indicating that the element can be replaced by a Z*Z circulant permutation matrix (circulant permutation matrix). In other words, each matrix element represents an all-zero matrix or a circulant permutation matrix. For example Figure 1 10a shows the elements in the base graph of an exemplary m=5, n=27 LDPC code with a QC structure. It should be noted that in this article, the row and column numbers of the base graph and the matrix are numbered from 0, just for the convenience of explanation, for example, the 0th column represents the first column of the base graph and the matrix, the 1st column represents the second column of the base graph and the matrix, the 0th row represents the first row of the base graph and the matrix, the 1st row represents the second row of the base graph and the matrix, and so on.

[0079] It can be understood that the row and column numbers can also be numbered starting from 1, and the corresponding row and column numbers are added by 1 based on the row and column numbers shown in this article. For example, if the row or column numbers are numbered starting from 1, the 1st column represents the first column of the base graph and the matrix, the 2nd column represents the second column of the base graph and the matrix, the 1st row represents the first row of the base graph and the matrix, the 2nd row represents the second row of the base graph and the matrix, and so on.

[0080] If the value of the element in the i-th row and j-th column of the base graph is 1, its offset value is P i,j , P i,j is an integer greater than or equal to 0, which means that the element with a value of 1 in the i-th row and j-th column can be i,j The corresponding Z*Z circulant permutation matrix is ​​replaced by the circulant permutation matrix, which can be obtained by P-ing the Z*Z identity matrix i,jIt is obtained by cyclic shifting to the right times. It can be seen that by replacing each element with a value of 0 in the base graph with a Z*Z all-zero matrix, and replacing each element with a value of 1 with a Z*Z cyclic permutation matrix corresponding to its offset value, the parity check matrix of the LDPC code can be obtained. The base graph can be used to indicate the position of the offset value, and the non-zero elements in the base graph correspond to the offset value. Z is a positive integer, which can also be called a lifting factor, sometimes also called a lifting size, or lifting factor, etc., which can be determined according to the code block size supported by the system and the size of the information data. It can be seen that the size of the parity check matrix H is (m*Z)*(n*Z). For example, if the expansion factor Z=4, each zero element is replaced by a 4*4 all-0 matrix 11a. If P 2,3 =2, then the non-zero elements in the 2nd row and 3rd column are replaced by the 4*4 circulant permutation matrix 11d, which is obtained by 2 right circulant shifts of the 4*4 identity matrix 11b. If P 2,4 =0, then the non-zero element in the 2nd row and the 4th column is replaced by the unit matrix 11b. It should be noted that this is only an example and is not intended to be limiting.

[0081] Because P i,j It can be obtained based on the expansion factor Z. For the element with a value of 1 at the same position, different P values ​​may exist when different expansion factors Z are used. i,j . To simplify the implementation, the system usually defines a base matrix with m rows and n columns, sometimes also called PCM (parity check matrix). Each element in the base matrix corresponds to each element in the base graph. The zero element in the base graph remains in the same position in the base matrix, which can be represented by -1 or null value "null". The non-zero element in the base graph with the value of 1 in the i-th row and j-th column remains in the same position in the base matrix, which can be represented as P i,j , P i,j It may be an offset value defined relative to a predetermined or specific expansion factor Z. In the embodiment of the present application, the base matrix is ​​sometimes referred to as an offset matrix of the base matrix.

[0082] like Figure 1 10b shows a basis matrix corresponding to the basis graph 10a.

[0083] Usually, the base graph or base matrix of the LDPC code can also include p columns of built-in puncture bit columns, where p can be an integer from 0 to 2. These columns participate in the encoding, but the system bits corresponding to their encoding are not sent. Then the code rate of the LDPC code base matrix satisfies R = (nm) / (np). Taking base graph 10a as an example, if there are 2 columns of built-in puncture bit columns, the code rate is (27-5) / (27-2) = 0.88, which is approximately 8 / 9.

[0084] The LDPC code used in wireless communication systems is QC-LDPC code, whose check bit part has a dual diagonal structure or raptor-like structure, which can simplify coding and support incremental redundant hybrid retransmission. The decoder of QC-LDPC code usually uses QC-LDPC shift network (QSN), Banyan network or Benes network to realize the cyclic shift of information.

[0085] The matrix size of the base graph of a QC-LDPC code with a raptor-like structure is m rows and n columns, and may include five sub-matrices A, B, C, D, and E, where the weight of the matrix is ​​determined by the number of non-zero elements, the row weight (row weight) refers to the number of non-zero elements included in a row, and the column weight (column weight) refers to the number of non-zero elements included in a column. Figure 2 As shown in 200, wherein:

[0086] Submatrix A is m A Line A A matrix of columns, whose size can be m A *n A , where each column corresponds to Z systematic bits in the LDPC code, and the systematic bits are sometimes also called information bits.

[0087] Submatrix B is m A Line m A A square matrix of columns, whose size can be m A *m A , each column corresponds to Z check bits in the LDPC code. The submatrix B includes a dual diagonal submatrix B' and a matrix column with a weight of 3 (referred to as a 3-column column), where the matrix column with a weight of 3 can be located before the submatrix B', such as Figure 2 As shown in 20a; the submatrix B may also include one or more matrix columns with a column weight of 1 (referred to as single column weight), for example, a possible implementation is as follows Figure 2 As shown in 20b or 20c.

[0088] Usually, a matrix generated based on sub-matrices A and B can be called a core matrix, which can be used to support high-rate encoding.

[0089] Submatrix C is an all-zero matrix with a size of m A ×m D .

[0090] Submatrix E is the identity matrix, whose size is m D ×m D .

[0091] The size of the submatrix D is m D ×(n A +m A ), which is usually used to generate low-rate check bits.

[0092] It can be understood that the above description of the base graph is from the perspective of mathematical definition. Since C is an all-zero matrix and E is a unit matrix, in a possible implementation, the base graph of the encoding or decoding matrix can also be simplified by a matrix composed of sub-matrices A and B, or a matrix composed of sub-matrices A, B and D.

[0093] Since the structures of the sub-matrices C and E are relatively certain, the structure of the sub-matrices A, B and D is one of the factors affecting the encoding and decoding performance of the LDPC code.

[0094] When using the LDPC matrix of the raptor-like structure for encoding, one possible implementation method is to first encode the matrix of the submatrix A and B parts, that is, the core matrix, to obtain the check bits corresponding to the submatrix B, and then encode the entire matrix to obtain the check bits corresponding to the submatrix E part. Since the submatrix B can include a submatrix B' of a dual diagonal structure and a single-column re-column, in the encoding, the check bits corresponding to the dual diagonal structure can be obtained first, and then the check bits corresponding to the single-column re-column can be obtained.

[0095] The following is an example of encoding. Assume that the core matrix composed of submatrices A and B is H core , H core Remove the last row and the last column from the matrix, that is, remove the single column and the row where the non-zero elements of the column are located, and the resulting matrix is ​​H core-dual , H core-dual The check bit part in is represented by H e =[H e1 H e2 ],H e1 For 3 columns, H e2 It is a dual diagonal structure. According to the definition of LDPC code matrix, H core-dual ·[SP e ] T =0, where S is the input sequence, represented by a vector consisting of information bits, and P eis the vector composed of check bits, [SP e ] T Represented by the input sequence S and P e The matrix is ​​transposed. Therefore, we can first core-dual Calculate H core-dual The corresponding check bits, the input sequence S includes all information bits; then according to H core-dual The corresponding check bits and the input sequence S are used to calculate the check bits corresponding to the single column re-arrangement in the submatrix B. At this time, all the check bits corresponding to the submatrix B can be obtained. Then, according to the input sequence S and the check bits corresponding to the submatrix B, the submatrix D is partially encoded to obtain the check bits corresponding to the submatrix E, thereby obtaining all the information bits and all the check bits. These bits constitute the encoded sequence, which is an LDPC code sequence.

[0096] Optionally, LDPC code encoding may also include shortening and puncturing operations, and shortened bits and punctured bits are not sent.

[0097] Among them, truncation generally starts from the last bit of the information bit and truncates forward. The truncation can be performed in different ways. For example, the number of truncated bits s0 can be obtained by setting the last s0 bits in the input sequence S to known bits to obtain the input sequence S', such as setting them to 0 or null, or some other values, and then encoding the input sequence S' through the LDPC matrix. For another example, the last (s0 mod Z) bits in the input sequence S can be set to known bits to obtain the input sequence S', such as setting them to 0 or null, or some other values, and the last (s0 mod Z) bits in the submatrix A can be set to known bits to obtain the input sequence S'. Column deletion obtains the LDPC matrix H', and uses the LDPC matrix H' to encode the input sequence S', or the last The columns do not participate in the encoding of the input sequence S'. After the encoding is completed, the truncated bits are not sent.

[0098] Among them, puncturing can be puncturing built-in puncturing bits or check bits in the input sequence. When puncturing the check bits, puncturing is usually performed from the last bit of the check bits. Of course, puncturing can also be performed according to the puncturing sequence preset by the system. One possible implementation method is to first encode the input sequence, and then select the last p bits of the check bits according to the number of bits p to be punctured, or select p bits according to the puncturing sequence preset by the system, and these p bits are not sent. In another possible implementation method, the p columns of the matrix corresponding to the punctured bits and the p rows where the non-zero elements in these columns are located can also be determined. These rows and columns do not participate in the encoding, and no corresponding check bits are generated.

[0099] It should be noted that the encoding method here is only an example. Based on the base graph and / or base matrix provided in this application, other encoding methods known to those skilled in the art can also be used, and this application is not limited. The decoding involved in this application can be a variety of decoding methods, for example, a min-sum (MS) decoding method can be used, or a belief propagation decoding method can be used. The MS decoding method is sometimes also called the Flood MS decoding method. For example, the input sequence is initialized and iterative processing is performed. After the iteration, a hard decision detection is performed, and the hard decision result is verified. If the decoding result meets the verification equation, the decoding is successful, the iteration is terminated, and the judgment result is output. If it does not meet the verification equation, the iterative processing is performed again within the maximum number of iterations. If the maximum number of iterations is reached and the verification still fails, the decoding fails. It can be understood that those skilled in the art can understand the principle of MS decoding, which will not be described in detail here.

[0100] It should be noted that the decoding method is only an example. Other decoding methods known to those skilled in the art may also be used based on the base graph and / or base matrix provided in this application. This application does not limit the decoding method.

[0101] LDPC codes can usually be obtained by designing a base graph or base matrix. For example, the density evolution method can be used to determine the performance upper limit of the LDPC code, and the error floor of the LDPC code can be determined based on the offset value in the base matrix. By designing the base graph or base matrix, the encoding or decoding performance can be improved, and the error floor can be reduced. The code length in the wireless communication system is flexible and changeable, for example, it can be 2560 bits, 38400 bits, etc. Figure 3a is an example of a base graph 30a of an LDPC code, Figure 3b-1 to Figure 3b-10 are examples of base matrices of base graph 30a, which can meet the performance requirements of various block lengths. Figure 3b-1 to Figure 3b-10 Column numbers and row numbers are shown at the top and left, respectively.

[0102] Figure 3a The figure shows an example of a base graph 30a of an LDPC code, in which the top row 0 to 67 (i.e., columns 0 to 67) in the figure represent column numbers, and the leftmost column 0 to 45 (i.e., rows 0 to 45) represent row numbers, that is, the matrix size of the base graph 30a is 46 rows and 68 columns.

[0103] In one implementation, submatrix A and submatrix B can be regarded as the core matrix of the base graph of the LDPC code, which can be used for high code rate coding. A matrix with 5 rows and 27 columns is formed, such as the matrix with 5 rows and 27 columns shown in base graph 10a, which can be used as the core matrix of the base graph.

[0104] In one implementation, the submatrix A may include one or more columns of built-in punctured bit columns, for example, may include 2 columns of built-in punctured bit columns. After puncturing, the core matrix may support a code rate of 0.88.

[0105] Among them, submatrix B can include 1 column and 3 columns of weight, that is, the 0th column of submatrix B (the 22nd column of the core matrix) has a column weight of 3, the 1st to 3rd columns of submatrix B (the 23rd to 25th columns of the core matrix), the 0th to 3rd rows have a dual diagonal structure, and submatrix B also includes 1 column with a single column weight (the 26th column of the core matrix).

[0106] In one implementation, the submatrix A may correspond to system bits, sometimes also referred to as information bits, and may have a size of m A 22 rows and 22 columns, among which, m A =5, which is composed of the elements from row 0 to row 4 and column 0 to column 21 in base graph 30a;

[0107] In one implementation, the submatrix B may correspond to the check bits, and its size is m A Line m A Columns, in the base graph 30a, are composed of elements from the 0th to the 4th rows and the 22nd to the 26th columns.

[0108] In order to obtain a flexible bit rate, sub-matrix C, sub-matrix D and sub-matrix E of corresponding sizes can be added based on the core matrix to obtain different bit rates. Since sub-matrix C is an all-zero matrix and the sub-matrix is ​​a unit matrix, its size is mainly determined by the bit rate and the structure is relatively fixed. The core matrix and sub-matrix D are the main parts that affect the encoding and decoding performance. Adding rows and columns on the basis of the core matrix to form the corresponding C, D and E parts can obtain different bit rates.

[0109] The number of columns m of the submatrix D D is the sum of the number of columns of submatrices A and B, and the number of rows is mainly related to the code rate. Taking base graph 30a as an example, the number of columns of submatrix D is 27. If the code rate supported by the LDPC code is R m , then the size of its base graph or base matrix is ​​m rows and n columns, where n = n A R m +p,m=nn A =n A R m +pn A If the minimum bit rate R m = 1 / 3, the number of built-in puncturing columns p = 2, taking base image 30a as an example, n = 68, m = 46, and the number of rows of submatrix D is m D Maximum size can be mm A =46-5=41, so 0≤m D≤41.

[0110] Taking the base graph 30a as an example, the submatrix D may include the m in the 5th to 41st rows of the base graph 30a. D OK.

[0111] In the present application, if the same column of two adjacent rows in the base graph has at most one non-zero element, the two rows are orthogonal to each other. If the same column of two adjacent rows in the base graph, except for some columns, has at most one non-zero element, the two adjacent rows are quasi-orthogonal. For example, for two adjacent rows, if there is only one non-zero element in the columns other than the built-in puncturing bit column, the two adjacent rows can be considered to be quasi-orthogonal.

[0112] The 5th to 41st rows in the base graph 30a may include multiple rows of quasi-orthogonal structures and at least two rows of orthogonal structures. For example, the 5th to 41st rows in the base graph 30a include at least 15 rows that conform to the quasi-orthogonal structure, and in any two adjacent rows of the 15 rows, except for the built-in punctured bit columns, there is at most one non-zero element in the same column. The 5th to 41st rows in the base graph 30a may also include 10 to 26 rows that conform to the orthogonal structure, that is, in these rows, there is at most one non-zero element in the same column in any two adjacent rows, that is, there is at most one non-zero element in the built-in punctured bit columns.

[0113] If m D =15, the size of the submatrix D in the LDPC code base graph is 15 rows and 27 columns, which can be composed of the matrix of the 5th row to the 19th row and the 0th column to the 26th column of the base graph 30a, and the code rate supported by the corresponding LDPC code is 22 / 40=0.55, that is, at this code rate, the base graph of the LDPC code corresponds to the matrix part composed of the 0th row to the 19th row and the 0th column to the 41st column of the base graph 30a, wherein the submatrix E is a unit matrix of 15 rows and 15 columns, and the submatrix C is a matrix of all zeros of 5 rows and 15 columns;

[0114] If m D =19, the size of the submatrix D in the LDPC code base graph is 19 rows and 27 columns, which can be composed of the matrix of the 5th to 23rd rows and the 0th to 26th columns of the base graph 30a, and the code rate supported by the corresponding LDPC code is 22 / 44=1 / 2, that is, at this code rate, the base graph of the LDPC code corresponds to the matrix part composed of the 0th to 23rd rows and the 0th to 45th columns of the base graph 30a, where the submatrix E is a unit matrix of 19 rows and 19 columns, and the submatrix C is a matrix of all 0s of 5 rows and 19 columns.

[0115] And so on, I won’t elaborate on them one by one.

[0116] In one design, the base graph and / or base matrix can be subjected to row / column exchange, that is, row exchange, column exchange, or row exchange and column exchange. The row / column exchange operation does not change the row weight and column weight, and the number of non-zero elements does not change. Therefore, the base graph and / or base matrix after row / column exchange has limited impact on system performance. That is to say, overall, the impact on system performance is acceptable and within the tolerance range. For example, the performance may decrease within the allowable range for some scenes or in some ranges, but the performance is improved in some scenes or in some ranges, and the overall performance is not greatly affected.

[0117] For example, the 34th row and the 36th row of the base graph 30a may be swapped, and the 44th column and the 45th column may be swapped. For another example, the submatrix D includes the matrix F in m D OK, this D The rows can be swapped without swapping, or one or more rows can be swapped. The submatrix E is still a diagonal structure, and rows and columns are not swapped. For example, the 27th and 29th rows of the matrix F are swapped, and the submatrix D includes the m rows in the matrix F. D The submatrix E still has a diagonal structure. It can be understood that if the base graph or base matrix includes the submatrix D, when the columns of the core matrix are exchanged, the columns in the corresponding submatrix D also need to be exchanged.

[0118] like Figure 3b-1 to Figure 3b-10 The matrices 30b-10 to 30b-80 shown are respectively designs of multiple base matrices of the base graph 30a. The non-zero elements in the i-th row and j-th column of the base graph 30a remain in the same position in the matrices 30b-10 to 30b-80, and the values ​​are offset values ​​V i,j , zero elements are represented by -1 or null in the offset matrix. The corresponding part of the submatrix D in the base matrix may include m in the 5th to 45th rows of any base matrix. D You can choose m according to the bit rate. D It can be understood that if the base graph is a matrix after row / column transformation relative to the base graph 30a, the base matrix is ​​also a matrix after row / column transformation of any one of the corresponding matrices 30b-10 to 30b-80.

[0119] In one possible design, the basis matrix of the LDPC code may include Figure 3b-1 to Figure 3b-10 The 0th to 4th rows and the 0th to 26th columns of any matrix 30b-10 to 30b-80 shown in FIG. 3 are shown in FIG. Figure 3b-1 to Figure 3b-10 The matrix composed of rows 0 to 4 and columns 0 to 26 of the matrix shown can be used as the core part of the base matrix. In this design, the structure of other parts of the base matrix of the LDPC code, such as matrix C, D, and E, is not limited. For example, Figure 3b-1 to Figure 3b-10 Any of the structures shown may also be used in other matrix designs.

[0120] In another possible design, the basis matrix of the LDPC code may include: Figure 3b-1 to Figure 3b-10 The matrix is ​​composed of the 0th to (m-1)th rows and the 0th to (n-1)th columns in any matrix 30b-10 to 30b-80 shown, where 5≤m≤46, m is an integer, and 27≤n≤68, n is an integer.

[0121] In this design, the structure of other parts of the base matrix of the LDPC code is not limited. For example, Figure 3b-1 to Figure 3b-10 Any of the structures shown may also be used in other matrix designs.

[0122] In yet another possible design, a base matrix of an LDPC code may include: Figure 3b-1 to Figure 3b-10 For example, some of the rows 0 to 4 and columns 0 to 26 of any of the matrices 30b-10 to 30b-80 shown in FIG. Figure 3b-1 to Figure 3b-10 The core part (rows 0 to 4 and columns 0 to 26) of the matrix shown is shortened and / or punctured. In one implementation, the base matrix of the LDPC code may not include columns corresponding to the shortened and / or punctured bits.

[0123] In this design, other parts of the base matrix of the LDPC code are not limited. For example, Figure 3b-1 to Figure 3b-10 The structure shown can also be used in other structures.

[0124] In yet another possible design, a base matrix of an LDPC code may include: Figure 3b-1 to Figure 3b-10 A matrix consisting of some of the columns in the 0th to (m-1)th rows and the 0th to (n-1)th columns in any of the matrices 30b-10 to 30b-80 shown, where 5≤m≤46, m is an integer, and 27≤n≤68, n is an integer. For example, Figure 3b-1 to Figure 3b-10 The 0th to (m-1)th rows and the 0th to (n-1)th columns in any of the matrices 30b-10 to 30b-80 shown are truncated and / or punctured. In one implementation, the base matrix of the LDPC code may not include columns corresponding to the truncated and / or punctured bits. In this design, there is no limitation on other parts of the base matrix of the LDPC code, for example, Figure 3b-1 to Figure 3b-10 The structure shown can also be used in other structures.

[0125] In one implementation, the truncation operation may be to truncate the information bits. Figure 3b-1 to Figure 3b-10Taking any matrix shown in the figure as an example, one or more columns from 0 to 21 are truncated, then the base matrix of the LDPC code may not include Figure 3b-1 to Figure 3b-10 The truncated column or columns in the matrix shown. For example, if the 21st column is truncated, the base matrix of the LDPC code may include: columns 0 to 20 and columns 22 to 26 of any matrix from 30b-10 to 30b-80. For rows 0 to 4, columns 0 to 20 and columns 22 to 26, the code rate is 7 / 8.

[0126] In another implementation, the puncturing may be puncturing of the check bits. Figure 3b-1 to Figure 3b-10 Take any matrix shown in the figure as an example, and puncture one or more columns from the 22nd to the 26th columns. Then the base matrix of the LDPC code may not include Figure 3b-1 to Figure 3b-10 The punctured column or columns in the matrix shown. For example, if the 26th column is punctured, the base matrix of the LDPC code may include the 0th to 25th columns of any matrix from 30b-10 to 30b-80.

[0127] Different expansion factors Z are designed for LDPC codes to support information bit sequences of different lengths. In one possible design, different base matrices can be used for different expansion factors to achieve better performance. For example, expansion factor Z = a × 2 j , 0≤j<7, a∈{2,3,5,7,9,11,13,15}. Table 1 shows a possible set of expansion factors {2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,18,20,22,24,26,28,30,32,36,40,44,48,52,56,60,64,72,80,88,96,104,112,120,128,144,160,176,192,208,224,240,256,288,320,352,384}, where except for the top row and the leftmost column, each cell represents the value of Z corresponding to the corresponding values ​​of a and j, for example, a=2 in this column and j=1 in this row, Z=4, and for another example, a=11 and j=3, Z=88. And so on, I won’t go into details.

[0128] Table 1

[0129]

[0130] Since the set of expansion factors supported by the base graph can be all the expansion factors in Table 1 or a part of the expansion factors, for example, it can be {24,26,28,30,32,36,40,44,48,52,56,60,64,72,80,88,96,104,112,120,128,144,160,176,192,208,224,240,256,288,320,352,384}, that is, Z is greater than or equal to 24. For another example, it can be the union of one or more of {2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,18,20,22} and {24,26,28,30,32,36,40,44,48,52,56,60,64,72,80,88,96,104,112,120,128,144,160,176,192,208,224,240,256,288,320,352,384}. It should be noted that this is only an example. The set of expansion factors supported by the base graph can be divided into different subsets according to the value of a. For example, a=2, the subset of the expansion factor Z may include one or more of {2, 4, 8, 16, 32, 64, 128, 256}. For another example, a=3, the subset of the expansion factor Z may include one or more of {3, 6, 12, 24, 48, 96, 192, 384}, and so on.

[0131] The set of expansion factors supported by the base graph can be divided according to different values ​​of a to determine the corresponding basis matrix:

[0132] If a=2, or the expansion factor Z takes a value of one of {2, 4, 8, 16, 32, 64, 128, 256}, the base matrix may include rows 0 to 4 and columns 0 to 26 in the matrix 30b-10 or 30b-11, or the base matrix includes rows 0 to (m-1) and columns 0 to (n-1) in the matrix 30b-10 or 30b-11, where 5≤m≤46, m is an integer, 27≤n≤68, n is an integer; or the base matrix includes rows 0 to (m-1) and part of the columns 0 to (n-1) in the matrix 30b-10 or 30b-11, where 5≤m≤46, m is an integer, 27≤n≤68, n is an integer.

[0133] If a=3, or the expansion factor Z takes a value of one of {3, 6, 12, 24, 48, 96, 192, 384}, the base matrix may include rows 0 to 4 and columns 0 to 26 in the matrix 30b-20 or 30b-21, or the base matrix may include rows 0 to (m-1) and columns 0 to (n-1) in the matrix 30b-20 or 30b-21, where 5≤m≤46, m is an integer, 27≤n≤68, n is an integer; or the base matrix may include rows 0 to (m-1) and part of the columns 0 to (n-1) in the matrix 30b-20 or 30b-21, where 5≤m≤46, m is an integer, 27≤n≤68, n is an integer.

[0134] If a=5, or the expansion factor Z takes a value of one of {5, 10, 20, 40, 80, 160, 320}, the base matrix may include rows 0 to 4 and columns 0 to 26 in the matrix 30b-30, or the base matrix includes rows 0 to (m-1) and columns 0 to (n-1) in the matrix 30b-30, where 5≤m≤46, m is an integer, 27≤n≤68, n is an integer; or the base matrix includes rows 0 to (m-1) and part of the columns 0 to (n-1) in the matrix 30b-30, where 5≤m≤46, m is an integer, 27≤n≤68, n is an integer.

[0135] If a=7, or the expansion factor Z takes a value of one of {7, 14, 28, 56, 112, 224}, the base matrix may include rows 0 to 4 and columns 0 to 26 in the matrix 30b-40, or the base matrix includes rows 0 to (m-1) and columns 0 to (n-1) in the matrix 30b-40, where 5≤m≤46, m is an integer, 27≤n≤68, n is an integer; or the base matrix includes rows 0 to (m-1) and part of the columns 0 to (n-1) in the matrix 30b-40, where 5≤m≤46, m is an integer, 27≤n≤68, n is an integer.

[0136] If a=9, or the expansion factor Z takes a value of one of {9, 18, 36, 72, 144, 288}, the base matrix may include rows 0 to 4 and columns 0 to 26 in the matrix 30b-50, or the base matrix includes rows 0 to (m-1) and columns 0 to (n-1) in the matrix 30b-50, where 5≤m≤46, m is an integer, 27≤n≤68, n is an integer; or the base matrix includes rows 0 to (m-1) and part of the columns 0 to (n-1) in the matrix 30b-50, where 5≤m≤46, m is an integer, 27≤n≤68, n is an integer.

[0137] If a=11, or the expansion factor Z takes a value of one of {11, 22, 44, 88, 176, 352}, the base matrix may include rows 0 to 4 and columns 0 to 26 in the matrix 30b-60, or the base matrix includes rows 0 to (m-1) and columns 0 to (n-1) in the matrix 30b-60, where 5≤m≤46, m is an integer, 27≤n≤68, n is an integer; or the base matrix includes rows 0 to (m-1) and part of the columns 0 to (n-1) in the matrix 30b-60, where 5≤m≤46, m is an integer, 27≤n≤68, n is an integer.

[0138] If a=13, or the expansion factor Z takes a value of one of {13, 26, 52, 104, 208}, the base matrix may include rows 0 to 4 and columns 0 to 26 in the matrix 30b-70, or the base matrix includes rows 0 to (m-1) and columns 0 to (n-1) in the matrix 30b-70, where 5≤m≤46, m is an integer, 27≤n≤68, n is an integer; or the base matrix includes rows 0 to (m-1) and part of the columns 0 to (n-1) in the matrix 30b-70, where 5≤m≤46, m is an integer, 27≤n≤68, n is an integer.

[0139] If a=15, or the expansion factor Z takes a value of one of {15, 30, 60, 120, 240}, the base matrix may include rows 0 to 4 and columns 0 to 26 in the matrix 30b-80, or the base matrix includes rows 0 to (m-1) and columns 0 to (n-1) in the matrix 30b-80, where 5≤m≤46, m is an integer, 27≤n≤68, n is an integer; or the base matrix includes rows 0 to (m-1) and part of the columns 0 to (n-1) in the matrix 30b-80, where 5≤m≤46, m is an integer, 27≤n≤68, n is an integer.

[0140] Optionally, for a given base matrix of an LDPC code, the offset value Offset may be increased or decreased for the offset values ​​of one or more columns of non-zero elements in the matrix. s， The system performance is not greatly affected. The compensation values ​​of non-zero elements in different columns can be the same or different. For example, when compensating one or more columns of a matrix, the compensation values ​​of different columns can be the same or different, which is not limited in this application.

[0141] The impact on system performance is not significant, which means that the impact on system performance is acceptable and within the tolerance range. For example, in some scenarios or within some ranges, the performance may decrease within the allowable range, but in some scenarios or within some ranges, the performance may improve. Overall, the impact on performance is not significant.

[0142] For example, the offset value Offset is increased or decreased for each offset value greater than or equal to 0 in the sth column of any matrix in matrices 30b-10 to 30b-80. s The compensation matrix Hs of the matrix can be obtained, where Offset s is an integer greater than or equal to 0, 0≤s<23. The offset values ​​Offsets of one or more columns may be the same or different.

[0143] Figure 4 The performance graph shown is the performance curve of the LDPC code based on the matrix 30b-10 to 30b-80 encoding. The horizontal axis represents the length of the information bit sequence in bits, and the vertical axis is the symbol signal-to-noise ratio (Es / N0) required to achieve the corresponding BLER. The two lines for each code rate correspond to the BLER of 0.01 and 0.0001. At the same code rate, 0.01 corresponds to the upper curve and 0.0001 corresponds to the lower curve. The smoothness of each curve shows that the matrix has better performance at different block lengths.

[0144] Attached Figures 1 to 3a , Figure 3b-1 to Figure 3b-10 The structures of the base graph and base matrix involved in the LDPC code are shown. In order to fully illustrate the design of the base graph and / or base matrix in the embodiments of the present invention, further explanation can be given by the following Tables 2-10 to 2-11.

[0145] In one design, Figure 1 The base graph 10a is a matrix of 5 rows and 27 columns, and the parameters involved can be expressed by Table 2-10.

[0146] Table 2-10

[0147]

[0148] In one design, Figure 1 The size of the base matrix shown in 10b is a matrix of 5 rows and 27 columns, and the parameters involved can be expressed by Table 2-11.

[0149] Table 2-11

[0150]

[0151] In one design, Figure 3b-1 The matrix 30b-10 in can be represented by Table 3-10.

[0152] Table 3-10

[0153]

[0154]

[0155]

[0156] In one design, Figure 3b-2 The matrix 30b-11 in can be represented by Table 3-11.

[0157] Table 3-11

[0158]

[0159]

[0160] In one design, Figure 3b-3 The matrix 30b-20 in can be represented by Table 3-20.

[0161] Table 3-20

[0162]

[0163]

[0164] In one design, Figure 3b-4 The matrix 30b-21 in can be represented by Table 3-21.

[0165] Table 3-21

[0166]

[0167]

[0168] In one design, Figure 3b-5 The matrix 30b-30 in can be represented by Table 3-30.

[0169] Table 3-30

[0170]

[0171]

[0172] In one design, Figure 3b-6 The matrix 30b-40 in can be represented by Table 3-40.

[0173] Table 3-40

[0174]

[0175]

[0176] In one design, Figure 3b-7 The matrix 30b-50 in can be represented by Table 3-50.

[0177] Table 3-50

[0178]

[0179]

[0180] In one design, Figure 3b-8 The matrix 30b-60 in can be represented by Table 3-60.

[0181] Table 3-60

[0182]

[0183]

[0184] In one design, Figure 3b-9 The matrix 30b-70 in can be represented by Table 3-70.

[0185] Table 3-70

[0186]

[0187]

[0188] In one design, Figure 3b-10 The matrix 30b-80 in can be represented by Table 3-80.

[0189] Table 3-80

[0190]

[0191]

[0192]

[0193] It is understandable that the above Figures 1 to 3a , Figure 3b-1 to Figure 3b-10 Tables 2-10, 2-11, and 3-10 to 3-80 are intended to help understand the design of base graphs and matrices, and their representation is not limited to Figures 1 to 3a , Figure 3b-1 to Figure 3b-10 Or the above-mentioned Table 2-10, Table 2-11, Table 3-10 to Table 3-80. Other possible variations may also be included.

[0194] In one implementation, the parameter "row weight" in Table 2-10, Table 2-11, and Tables 3-10 to 3-80 can also be omitted. The number of non-zero elements in a row can be known by the column where the non-zero elements in the row are located, so the row weight is also known.

[0195] In one implementation, the parameter values ​​in the “columns where non-zero elements are located” in Tables 2-10, 2-11, and 3-10 to 3-80 may not be arranged in ascending order, as long as the parameter values ​​index the columns where non-zero elements are located. In addition, the parameter values ​​in the “non-zero element offset values” in Tables 2-10, 2-11, and 3-10 to 3-80 may not necessarily be arranged in the order of columns, as long as the parameter values ​​in the “non-zero element offset values” correspond one-to-one with the parameter values ​​in the “columns where non-zero elements are located”.

[0196] In one design, in order to save storage space, for parts of the base graph or base matrix with relatively fixed structures, the positions of the non-zero elements can be calculated based on the row and column positions, and the positions of these non-zero elements may not be saved.

[0197] For example, submatrix E is a diagonal matrix with non-zero elements only on the diagonal. The offset values ​​of the non-zero elements on the diagonal are all 0. The column positions of the non-zero elements can be calculated based on the row numbers, and the row positions of the non-zero elements can be calculated based on the column numbers. Figure 3b-7 As an example, for the mth e Line, m e ≥4, the column where the non-zero element is located is the mth e +K b Column, here K b =22, for example, the column where the non-zero element in the 7th row is located is the 29th column, and the offset value is 0.

[0198] For another example, the dual diagonal structure B' in the submatrix B is located in the 0th to 3rd rows and the 23rd to 25th columns of the matrix 30b-50. The position of the column where the non-zero element is located can be calculated according to the row number, and the position of the row where the non-zero element is located can also be calculated according to the column number. For the mth B If 0 <m B <3, the positions of non-zero elements in this row include the mth B +K b Column, and mth B +K b +1 column, if m B =0 or m B =3, the positions of non-zero elements in this row include the mth B +K b The offset values ​​of the non-zero elements in the double diagonal structure of the submatrix B are also 0. Of course, it can be seen that in the 23rd to 25th columns, the positions of the non-zero elements in the part of the submatrix D, that is, the 5th to 47th rows, are not fixed, and their offset values ​​are not 0. The positions and offset values ​​of the non-zero elements in this part still need to be saved.

[0199] For another example, a single column in submatrix B is re-arranged, that is, column 26 in matrix 30b-50, if m B =4, the positions of non-zero elements in this row include the mth B +K b The offset value of non-zero elements is also 0.

[0200] Table 3-90 shows the parameters involved in each row of the matrix 30b-50. The column positions of the non-zero elements in the 0th to 25th columns can be saved, while the column positions of the non-zero elements in the 26th to 68th columns are not saved, that is, the columns of the non-zero elements in the single-column rearrangement of the submatrix E and the submatrix B are not saved:

[0201] Table 3-90

[0202]

[0203]

[0204] Table 3-91 shows the parameters involved in each row of matrix 3b-50. The column positions of the non-zero elements in columns 0 to 26 can be saved, while the column positions of the non-zero elements in columns 27 to 68 are not saved, that is, the columns of the non-zero elements in submatrix E are not saved:

[0205] Table 3-91

[0206]

[0207]

[0208]

[0209] In Tables 3-10 to 3-91, row weight is optional, and the row number and the column where the non-zero element is located indicate the location of the non-zero element in each row, that is, the information of the base graph of the LDPC matrix. In one design, the base graph and offset value information of the LDPC matrix can be saved in the manner of Tables 3-10 to 3-91.

[0210] In another design, the base graph of the LDPC matrix and the offset value of the LDPC matrix can be saved separately. The offset value information of the LDPC matrix can be saved by the row number and the non-zero element offset value in Tables 3-10 to 3-91. The base graph of the LDPC can be saved in various forms, for example, Figure 3aThe matrix form of the base graph 30a shown, or the row numbers and positions of non-zero elements in Tables 3-10 to 3-91, or, for the base graph, the 1s and 0s in each row or column are regarded as binary numbers, and the storage space can be saved by using decimal or hexadecimal numbers. Taking the base graph 30a as an example, each row can use 4 hexadecimal numbers to save the positions of the non-zero elements in the first 26 columns or the first 27 columns. For example, the first 26 columns of the 0th row are 11110110 01111101 10111111 00, then the positions of the non-zero elements in the 0th row can be recorded as 0xF6, 0x7D, 0xBF, 0x00, that is, every 8 columns form a hexadecimal number. For the last 2 or 3 columns, the corresponding hexadecimal numbers can be obtained by filling 0 to 8 bits, and the other rows are similar, which will not be repeated here.

[0211] Optionally, in the above various designs, the LDPC offset value may also be saved in other transformed forms. For example, in order to facilitate the processing of cyclic shifts, the difference between the offset value and the previous offset value in the column where the offset value is located may be saved. Fig. 9 The figure shows the offset values ​​of rows 0 to 4 and columns 0 to 26 after transformation in matrix 3b-50. The example starts with row 0, the offset value of row 0 remains unchanged, the zero elements in each row remain unchanged, and the offset value of the non-zero elements in each row is the difference between the offset value at the same position in matrix 30b-50 and the previous non-zero element in the column where the offset value is located. If there is no non-zero element before the row in the column where the offset value is located, the offset value remains unchanged. For example, the offset value of row 1 and column 0 in matrix 30b-50 is 179, and Fig. 9 The difference between the offset value of 179 in row 1, column 0 and the previous offset value of 211 in column 0 is -32; because Fig. 9 The 0th row and 4th column is a zero element, and its 1st row and 4th column offset value is the same as the 1st row and 4th column offset value in the matrix 30b-50; Fig. 9 The 2nd row and 3rd column in the matrix 30b-50 is a zero element, and the 1st row and 3rd column is a non-zero element. Therefore, the offset value of the 3rd row and 3rd column is the difference between the offset value 166 of the 3rd row and 3rd column of the matrix 30b-50 and the offset value 223 of the 1st row and 3rd column, -57, and so on. Due to space limitations, the other rows of the matrix 30b-50 are Fig. 9 It is not shown in the figure, and the same can be said, and no further description is given. Here, the difference of the offset values ​​is positive, indicating that the unit matrix is ​​cyclically shifted to the right, and the difference is negative, indicating that the unit matrix is ​​cyclically shifted to the left. Accordingly, the transformed offset value, that is, the difference of the offset value, can be saved at the non-zero element offset value in the above Tables 3-10 to 3-91. The above is only an example and is not limited to this.

[0212] Figure 5The design of the data processing process is given. The data processing process can be implemented by a communication device, which can be a base station, a terminal or other entities, such as a communication chip, an encoder / decoder, etc.

[0213] Part 501, get the input sequence.

[0214] In one implementation, the encoded input sequence may be an information bit sequence. The information bit sequence is sometimes also referred to as a code block, for example, it may be an output sequence after the transmission block is divided into code blocks. Optionally, the input sequence may include at least one of the following: padding bits or cyclic redundancy check CRC bits. In a possible design, the information bit sequence may be padded to obtain the input sequence, so that the length of the input sequence K = K b ·Z, Z=K / K b The filling of the information bit sequence can be implemented during the code block division or after the code block division.

[0215] In a possible design, Null, or a value of 0, or other system agreed values ​​can be used as the value of the filling bit, so that after encoding, these filling bits can be identified and not sent. The present invention is not limited to this.

[0216] In one implementation, the input sequence for decoding may be a soft value sequence of an LDPC code.

[0217] In part 502, the input sequence is encoded / decoded based on an LDPC matrix; a base matrix of the LDPC matrix may be any base matrix in the aforementioned examples.

[0218] In one implementation, the LDPC matrix H may be obtained based on the expansion factor Z and the base matrix.

[0219] In one implementation, the relevant parameters of the LDPC matrix H may be saved, and the parameters may include one or more of the following:

[0220] a) is used to obtain parameters in any base matrix listed in the above-mentioned implementation methods, and the base matrix can be obtained based on the parameters; for example, the parameters may include one or more of the following: row number, row weight, position of non-zero elements, offset value in the base matrix, non-zero element offset value and corresponding position, compensation value, expansion factor, base map, code rate, etc.

[0221] b) any basis matrix listed in the above implementations;

[0222] c) a compensation matrix Hs after at least one column of any base matrix listed in the above implementations is compensated;

[0223] d) a matrix expanded based on the base matrix or its compensation matrix Hs;

[0224] e) A base matrix after row / column transformation based on any base matrix or compensation matrix Hs listed in the above implementations.

[0225] f) A matrix expanded based on the base matrix or the compensation matrix Hs after the row / column transformation.

[0226] g) A matrix after truncating or puncturing any base matrix or compensation matrix Hs listed in the above implementations.

[0227] In a possible implementation, encoding / decoding the input sequence based on the low-density parity check LDPC matrix may be performed in one or more of the following ways during the encoding / decoding process:

[0228] i. Based on the above a), a base matrix is ​​obtained, and encoding / decoding is performed based on the obtained base matrix; or rows / columns are exchanged based on the obtained base matrix, and encoding / decoding is performed based on the base matrix after row / column transformation, or encoding / decoding is performed based on the compensation matrix of the obtained base matrix, or encoding / decoding is performed based on the matrix after row / column transformation of the compensation matrix Hs of the obtained base matrix. Here, encoding / decoding based on the base matrix or the compensation matrix Hs may optionally include encoding / decoding based on the extended matrix of the base matrix or the extended matrix of the compensation matrix Hs, or encoding / decoding based on the matrix after truncating or puncturing the base matrix or the compensation matrix;

[0229] ii. Encoding / decoding based on the base matrix stored in b), c), d), or e) (storing the base matrix H or Hs, or storing the base matrix after the row / column transformation based on the base matrix H or Hs), or performing row / column transformation based on the stored base matrix, and encoding / decoding based on the base matrix after the row / column transformation. Here, encoding / decoding based on the base matrix or the compensation matrix Hs may optionally include encoding / decoding based on the extended matrix of the base matrix or the extended matrix of the compensation matrix Hs, or encoding / decoding based on the matrix after truncating or puncturing the base matrix or the compensation matrix;

[0230] iii. Encode / decode based on d), f) or g).

[0231] Part 503 outputs the encoded / decoded bit sequence.

[0232] Figure 6 A design for obtaining processed data is given, which can be used for additional Figure 5 502 section.

[0233] Part 601, obtain the expansion factor Z.

[0234] In one implementation, the expansion factor Z can be determined based on the length K of the input sequence. For example, the smallest Z0 can be found in the supported expansion factor set as the size of the expansion factor Z, and Kb·Z0≥K is satisfied. In one possible design, Kb can be the number of columns of information bits in the base matrix of the LDPC code. For base graph 30a, the number of columns of information bits Kb max =22, assuming that the set of expansion factors supported by the base graph 30a is {24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 88, 96, 104, 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288, 320, 352, 384}.

[0235] If the length of the input sequence K=529 bits, Z is 26, and if the length of the input sequence K=5000 bits, Z is 240. It should be noted that this is only an example and is not intended to be limiting.

[0236] For another example, the value of Kb may also vary according to the value of K, but not exceed the number of information bit columns in the base matrix of the LDPC code. For example, when K is greater than the first threshold, Kb=22; when K is less than or equal to the first threshold, Kb=21. Or, when K is greater than the first threshold, Kb=22; when K is less than or equal to the first threshold and K is greater than the second threshold, Kb=21; when K is less than or equal to the second threshold, Kb=20. It should be noted that this is only an example and is not intended to be limiting.

[0237] In addition, based on any of the above implementation methods, a specific information length K can also be selected, for example, for 104≤K≤512, Z can be selected according to the rules defined by the system, and K is other lengths and is still selected according to any of the above implementation methods, such as the minimum Z0 that satisfies Kb·Z0≥K, where Kb is 22 or is determined according to a threshold value.

[0238] In one design, when 104≤K≤512, Z is selected as shown in Table 4-1, and other lengths are selected according to any of the above implementation methods:

[0239] Table 4-1

[0240]

[0241]

[0242] In another possible design, the smallest Z0 that satisfies Kb·Z0≥K is selected, where 104≤K≤512, the value of Kb can also vary according to the value of K, for example, as shown in Table 4-2; when K is other lengths, it is selected according to any of the above implementation methods, such as Kb=22 or determined according to the threshold value:

[0243] Table 4-2

[0244]

[0245] The expansion factor Z may be determined by the communication device according to the length K of the input sequence, or may be obtained by the communication device from other entities (such as a processor).

[0246] In section 602, an LDPC matrix is ​​obtained based on the expansion factor and the base matrix.

[0247] The base matrix is ​​any base matrix exemplified in the aforementioned embodiments, or a compensation matrix obtained by compensating at least one column of any base matrix exemplified in the aforementioned embodiments, or a base matrix in which the row order is changed, the column order is changed, or both the row order and the column order are changed relative to any base matrix or compensation matrix exemplified in the aforementioned embodiments, and its base matrix includes at least submatrix A and submatrix B. Optionally, it may also include submatrix C, submatrix D and submatrix E, and each part may refer to the description in the aforementioned embodiments, which will not be repeated here.

[0248] In a possible implementation, a corresponding base matrix is ​​determined according to the expansion factor Z, and the base matrix is ​​permuted according to the expansion factor Z to obtain an LDPC matrix.

[0249] In one implementation, the correspondence between the extension factor and the base matrix may be stored, and the extension factor Z obtained in part 601 is used to determine the corresponding base matrix.

[0250] For example, Z is 26, a=13, the base matrix may include rows 0 to 4 and columns 0 to 26 of the matrix 30b-70, or the base matrix includes rows 0 to 4 and some columns of columns 0 to 26 of the matrix 30b-70; further, or the base matrix also includes rows 0 to m and columns 0 to n of the matrix, where 5≤m≤46, m is an integer, 27≤n≤68, n is an integer, or the base matrix includes rows 0 to m and columns 0 to n of the matrix 30b-70, where 5≤m≤46, m is an integer, 27≤n≤68, n is an integer, and rows from rows 5 to 45 and columns from columns 27 to 67 of the matrix 30b-70. The base matrix is ​​permuted according to the expansion factor Z to obtain an LDPC matrix.

[0251] It should be noted that here only Z=26, a=13, Figure 3b-7 The matrix shown is used as an example. This is only an example, and the present invention is not limited thereto. It can be understood that different expansion factors will result in different base matrices.

[0252] In a possible implementation, the correspondence between the expansion factor and the base matrix can be shown in Table 5, and the base matrix index corresponding to the expansion factor is determined according to Table 5. In a possible design, PCM1 can be as follows Figure 3b-1 The matrix 30b-10 shown, or Figure 3b-2 The matrix 30b-11 shown; PCM2 can be as follows Figure 3b-3 The matrix 30b-20 shown, or Figure 3b-4 The matrix 30b-21 shown; PCM3 can be as follows Figure 3b-5 The matrix 30b-30 shown; PCM4 can be as follows Figure 3b-6 The matrix 30b-40 shown; PCM5 can be as follows Figure 3b-7 The matrix 30b-50 shown; PCM6 can be as follows Figure 3b-8 The matrix 30b-60 shown; PCM7 can be as follows Figure 3b-9 The matrix 30b-70 shown; PCM8 can be as follows Figure 3b-10 The matrix 30b-80 shown here is only an example and is not intended to be limiting.

[0253] Table 5

[0254]

[0255] In a possible design, as shown in Table 6, the eight expansion factor sets in Table 5 are set to set the set index:

[0256] Table 6

[0257]

[0258] Each set index corresponds to a PCM, for example, 1 corresponds to PCM1, 2 corresponds to PCM2, 3 corresponds to PCM3, ..., 8 corresponds to PCM8, and so on.

[0259] Optionally, in a possible design, for the expansion factor Z, the element P in the i-th row and j-th column of its basis matrix is i,j The following relationship can be satisfied:

[0260]

[0261] Among them, V i,j It can be the offset value of the element in the i-th row and j-th column in the basis matrix of the set where the expansion factor Z is located, or the offset value of the non-zero element in the i-th row and j-th column of the basis matrix of the maximum expansion factor in the set where the expansion factor Z is located.

[0262] For example, taking Z as 13, the element P in the i-th row and j-th column of the basis matrix is i,j satisfy

[0263]

[0264] Among them, V i,j is the offset value of the non-zero element in the i-th row and j-th column of PCM7 matrix 30b-70. For Z=13, the offset value V of the non-zero element in the i-th row and j-th column of matrix 30b-70 needs to be i,j Modulo Z=13.

[0265] It should be noted that this is only an example and the present invention is not limited to this.

[0266] In section 603, the input sequence is encoded / decoded based on the LDPC matrix.

[0267] In one implementation, the input sequence for encoding may be an information bit sequence. In another implementation, the input sequence for decoding may be a soft value sequence of an LDPC code, which may be referred to as Figure 5 Related description in .

[0268] In one possible implementation, the encoded input sequence c = {c0, c1, c2, ..., c K-1}, the length of the input sequence c is K, and the output sequence d obtained after the input sequence c is encoded is {d0, d1, d2, …, d N-1}, K is an integer greater than 0, and K can be an integer multiple of the expansion factor Z.

[0269] The output sequence d includes K0 bits in the input sequence c and the check bits in the check sequence w, where K0 is an integer greater than 0 and less than or equal to K. The length of the check sequence w is N-K0, w={w0,w1,w2,…,w N–K0-1}.

[0270] Among them, the check bit sequence w and the input sequence c satisfy formula (1):

[0271]

[0272] Among them, c T =[c0,c1,c2,…,c K-1 ] T , is the transposed vector of the vector composed of each bit in the input sequence, w T =[w0,w1,w2,…,w N–K0-1 ] T , is the transposed vector of the vector composed of each bit in the check sequence, 0T is a column vector where all elements have the value 0.

[0273] Wherein H is an LDPC matrix obtained based on any base graph or base matrix listed in the aforementioned embodiments, the base graph size of H is m rows and n columns, and it can be any base graph listed in the aforementioned embodiments, for example, base graph 30a.

[0274] In one design, the base graph of H includes p columns of built-in puncturing columns, p is an integer greater than or equal to 0, the information bits corresponding to the p columns of built-in puncturing columns are not output, and the output sequence does not include the information bits corresponding to the p columns of built-in puncturing columns, then K0 = Kp·Z, for example, p = 2, then K0 = K-2·Z, and the length of the check sequence w is N+2·Z-K. If the p columns of built-in puncturing columns participate in the encoding, then K0 = K, and the length of the check sequence w is NK.

[0275] Accordingly, H can be M rows and (N+p·Z) columns or M rows and N columns, and its base graph size m=M / Z,

[0276] The base graph of the LDPC matrix H can be expressed as [H BG H BG,EXT ],in Indicates m c ×n c An all-zero matrix of size , Indicates n c ×n c The identity matrix of size .

[0277] In one possible design, is the submatrix C in the base graph of the above embodiments, is the submatrix E in the above embodiments, then A, B and D are the sub-matrices A, B and D in the base graph of the above-mentioned embodiments respectively, then m c =5,0≤n c ≤41, H BG The number of rows is less than or equal to 46 and greater than or equal to 5, H BG The number of columns is equal to 27.

[0278] In another possible design, since the 26th column is a single column, and the non-zero elements are located in the 5th row, It may also include the first 4 rows of the 26th column of the base diagram of the aforementioned embodiments and the first 4 rows of the submatrix C in the aforementioned embodiments, It may also include the base graph submatrix E in the aforementioned embodiments and the 5th to 46th rows of the 26th column and the last row of the submatrix C, then m c =4,0≤nc ≤42; H BG The matrix H is composed of the submatrices A, B and D in the base diagram of the above embodiments, with the last column removed. BG The number of rows is less than or equal to 46 and greater than or equal to 5, H BG The number of columns of H is equal to 26. Optionally, if the code rate needs to be further increased, H BG The number of rows can be 4, that is, rows 0 to 3.

[0279] Accordingly, the LDPC matrix H can be expressed as H = [H1 H2].

[0280] H1 can be BG Each zero element in is replaced by a Z*Z all-zero matrix, and each non-zero element is replaced by a Z*Z circulant permutation matrix h i,j We get, where the circulant permutation matrix h i,j It is to circularly shift the Z*Z size unit matrix to the right by P i,j Obtained, sometimes also referred to as I(P i,j ) where i is the row number and j is the column number. In one possible design, P i,j =mod(V i,j ,Z),V i,j is the expansion factor set index i corresponding to Z LS The non-zero elements in the i-th row and j-th column of the corresponding basis matrix.

[0281] H2 can be H BG,EXT Each zero element in is replaced by a Z*Z all-zero matrix, and each non-zero element is replaced by a Z*Z unit matrix.

[0282] The encoder can encode and output in a variety of ways. The following is an explanation using the base graph 30a and base matrix 30b-50 cited in the aforementioned embodiment, where the maximum number of rows in the base graph and the base matrix is ​​46, and the maximum number of columns is 68, including 2 built-in punctured columns. For the convenience of description, in the present invention, the base graph with the largest number of rows and the largest number of columns is sometimes referred to as a complete base graph, and the base matrix with the largest number of rows and the largest number of columns is referred to as a complete base matrix.

[0283] Method 1:

[0284] Based on the complete base graph or complete base matrix encoding, as many check bits as possible are obtained. At this time, m=46, n=68, that is, the offset values ​​of the 0th to 45th rows and the 0th to 67th columns of the above base graph 30a, or the 0th to 45th rows and the 0th to 67th columns of the base matrix 30b-50.

[0285] Accordingly, for the LDPC matrix H, M=46·Z, if the output sequence includes information bits corresponding to the built-in puncturing columns, then N=68·Z, and if the output sequence does not include 2·Z information bits corresponding to the built-in puncturing columns, then N=66·Z.

[0286] The information bits and check bits to be sent can be determined from the output sequence generated by the encoder in a subsequent processing step.

[0287] Method 2:

[0288] Partial row and column coding based on the complete base graph or complete base matrix. Row and column coding can be selected from the complete base graph or base matrix according to the required code rate, or the number of information bits and check bits.

[0289] For example, the code rate is 8 / 9, m=5, n=27, that is, partial coding based on rows 0 to 4 and columns 0 to 26 in the base graph 30a, or offset value coding based on rows 0 to 4 and columns 0 to 26 in the base matrix 30b-50.

[0290] Accordingly, for the LDPC matrix H, M=5·Z, if the output sequence includes information bits corresponding to the built-in puncturing columns, then N=27·Z, and if the output sequence does not include information bits corresponding to the built-in puncturing columns, then N=25·Z.

[0291] For another example, the code rate is 1 / 3, m=46, and n=68.

[0292] It can be seen that in this way, the base graph or base matrix size of H is 5≤m≤46,27≤n≤68, and correspondingly for the LDPC matrix H, 5·Z≤M≤46·Z, 27·Z≤N≤68·Z.

[0293] In a possible design, since the 26th column in the base graph 30a is a single-column re-column, the single-column re-column in the core matrix can be punctured, so that the core matrix is ​​reduced by 1 row and 1 column, so that m is 4, n=26, that is, based on the partial encoding of the 0th to 3rd rows and the 0th to 25th columns in the above base graph 30a or base matrix 30b-50. This method can obtain a higher code rate. Therefore, the size of the base graph or base matrix is ​​4≤m≤46,26≤n≤68, and correspondingly for the LDPC matrix H, 4·Z≤M≤46·Z, 26·Z≤N≤68·Z.

[0294] Since decoding is the inverse process of encoding, the description of the LDPC matrix H and its base graph and base matrix can refer to the above encoding method. When decoding, decoding can also be performed based on the complete base graph or the complete base matrix, or decoding can be performed based on partial rows and columns of the complete base graph or the complete base matrix.

[0295] When encoding / decoding the input sequence, the LDPC matrix H can be obtained by expanding the base matrix according to Z. For each non-zero element P in the base matrix i,j , determine the circulant permutation matrix h of size Z*Z i,j , where h i,j The identity matrix is ​​P i,j The cyclic permutation matrix obtained by cyclic shift is h i,j Replace the non-zero elements P i,j , replace the basis matrix H with a Z*Z size all-zero matrix B The zero elements in are removed to obtain the parity check matrix H.

[0296] In a possible implementation, the base matrix of the LDPC code may be stored in a memory, and the communication device obtains the LDPC matrix corresponding to the expansion factor Z, thereby encoding / decoding the input sequence.

[0297] In one possible implementation, since there are multiple basis matrices of the LDPC code, saving them in a matrix structure will take up a large storage space. Alternatively, the base graph of the LDPC code can be saved in a memory, and the offset values ​​of the non-zero elements in each basis matrix can be saved row by row or column by column. Then, the LDPC matrix is ​​obtained according to the offset value of the base matrix corresponding to the base graph and the expansion factor Z.

[0298] The base graph can indicate the position of non-zero elements of each base matrix. The LDPC matrix can be obtained according to the base graph and the offset value of the base matrix corresponding to the expansion factor Z. The LDPC matrix can also be obtained according to the position of each non-zero element and the offset value of the base matrix corresponding to the expansion factor Z.

[0299] In another possible implementation, preserving the base graph may be preserving the position of non-zero elements therein. The position of non-zero elements may be indicated by the row and column where the non-zero elements are located, such as the position of the column where the non-zero elements are located in each row, or the position of the row where the non-zero elements are located in each column. In another possible implementation, preserving the base graph may also be preserving the position of zero elements therein, and similarly, may be indicated by the row and column where the zero elements are located. For example, the position of the column where the zero elements are located in each row, or the position of the row where the zero elements are located in each row, then the position of the corresponding non-zero elements may be obtained by excluding the position where the zero elements are located. It should be noted that this is only an example, and the present invention is not limited thereto.

[0300] In a possible implementation, the offset values ​​of the non-zero elements in each base matrix may be saved as the parameters of the LDPC matrix in the manner of Tables 2-10, 2-11, 3-10 to 3-80, 3-90 and 3-91, wherein the "row weight" column in Tables 2-10, 2-11, 3-10 to 3-80, 3-90 and 3-91 is optional, that is, the "row weight" column may be saved or not saved. By knowing the column where the non-zero elements of a row are located, it is known how many non-zero elements there are in this row, and thus the row weight is also known. In a possible implementation, the parameter values ​​in the "columns where the non-zero elements are located" in the above Tables 2-10, 2-11, 3-10 to 3-80, 3-90 and 3-91 may not be arranged in ascending order, as long as the parameter value indexes the column where the non-zero element is located. In addition, the parameter values ​​in the "non-zero element offset value" in Tables 2-10, 2-11, 3-10 to 3-80, 3-90 and 3-91 are not necessarily arranged in the order of columns. As long as the parameter values ​​in the "non-zero element offset value" correspond one-to-one with the parameter values ​​in the "column where the non-zero element is located", the communication device can know which row and column the non-zero element offset value corresponds to. For example:

[0301] In one possible implementation, reference may be made to Figure 5 The relevant description in saves the relevant parameters of the LDPC matrix.

[0302] In a possible implementation, when saving the relevant parameters of the LDPC matrix, it is also possible not to save Figures 1 to 3a , Figure 3b-1 to Figure 3b-10 , or all rows of the matrices shown in Tables 2-10, 2-11, 3-10 to 3-80, 3-90 and 3-91, the parameters indicated by the corresponding rows in the table can be saved according to the rows included in the base matrix. For example, the matrix composed of the rows and columns included in the base matrix of the LDPC matrix described in the above embodiment, or the relevant parameters involved in the matrix composed of the rows and columns can be saved.

[0303] For example, if the base matrix includes rows 0 to 4 and columns 0 to 26 in any of matrices 30b-10 to 30b-80 and 3-90 and 3-91, then the matrix formed by rows 0 to 4 and columns 0 to 26 can be saved, and / or the relevant parameters of the matrix formed by rows 0 to 4 and columns 0 to 26 can be saved, and reference can be made to the parameters shown in Tables 3-10 to 3-80 and 3-90 and 3-91, as well as the above partial description.

[0304] If the base matrix includes the 0th to (m-1)th rows and the 0th to (n-1)th columns in any of the matrices 30b-10 to 30b-80 and 3-90 and 3-91, where 5≤m≤46, m is an integer, 27≤n≤68, n is an integer, then the matrix composed of the 0th to (m-1)th rows and the 0th to (n-1)th columns can be saved, and / or the relevant parameters of the matrix composed of the 0th to (m-1)th rows and the 0th to (n-1)th columns can be saved, and reference can be made to the parameters shown in Tables 3-10 to 3-80 and 3-90 and 3-91 and the description in the above section.

[0305] In a possible implementation, the compensation value Offset may be increased or decreased for each offset value greater than or equal to 0 indicated by position s in at least one "column where the non-zero element is located" in any of Tables 3-10 to 3-80 and 3-90 and 3-91. s .

[0306] In a possible implementation, the “non-zero element offset value” in any of Tables 3-10 to 3-80 and 3-90 and 3-91 may store the transformed offset value described in the above embodiment, such as Fig. 9 The offset values ​​are shown.

[0307] In another design, the base graph of the LDPC matrix and the offset value of the LDPC matrix can be saved separately. The offset value information of the LDPC matrix can be saved by the row number and the non-zero element offset value in Tables 3-10 to 3-91. The base graph of the LDPC can be saved in various forms, for example, Figure 3a The matrix form of the base graph 30a shown, or the row number and the position of the non-zero element in Table 3-10 to Table 3-91, or, for the base graph, the 1 and 0 of each row or column are regarded as binary numbers, and the storage space can be saved by using decimal or hexadecimal numbers. Taking the base graph 30a as an example, each row can use 4 hexadecimal numbers to save the positions of the non-zero elements of the first 26 columns or the first 27 columns. For example, the first 26 columns of the 0th row are 11110110 01111101 10111111 00, then the position of the non-zero element of the 0th row can be recorded as 0xF6, 0x7D, 0xBF, 0x00, that is, every 8 columns form a hexadecimal number, and for the last 2 or 3 columns, the corresponding hexadecimal number can be obtained by filling 0 to 8 bits, and the other rows are similar, which will not be repeated here. It should be noted that these are just examples and are not limited to this.

[0308] by Figure 1 Take the following as an example, to determine the basis matrix H B After that, we can first pass the input sequence and the 0th to 3rd rows and 0th to 25th columns of the basis matrix, that is, H core-dualThe check bits corresponding to the 22nd to 25th columns are obtained; then according to the input sequence and H core-dual The corresponding check bits are obtained in the 26th column, that is, the check bits corresponding to the single column re-column; then, the check bits corresponding to the submatrix E are obtained according to the input sequence and the check bits corresponding to the 22nd to 26th columns and the partial coding corresponding to the submatrix D, thereby completing the encoding. The encoding process of the LDPC code can be described with reference to the aforementioned implementation method, which will not be repeated here.

[0309] In a possible implementation, the LDPC matrix H may be expanded according to the expansion factor Z before encoding, that is, the corresponding circulant permutation matrix is ​​replaced according to the offset value;

[0310] In another possible implementation, when encoding, a corresponding offset value is obtained according to the position of the non-zero element corresponding to the encoded bit, and the corresponding circulant permutation matrix is ​​replaced for the non-zero element and processed;

[0311] In another possible implementation, the LDPC matrix H is not directly expanded during use, but the connection relationship between the rows and columns of the equivalent matrix is ​​calculated according to the offset value to process the bits in the input sequence;

[0312] In another possible implementation method, the QSN method can be used for encoding. For each non-zero element to be processed, the corresponding bit segment to be encoded is shifted according to the offset value of the non-zero element; then, the encoding operation is directly performed on all the bit segments that have undergone the shift operation.

[0313] In another possible implementation, the generator matrix G of the LDPC matrix H may also be saved, and the input sequence c and the output sequence d satisfy formula (2):

[0314] d = c · G (2)

[0315] If the LDPC matrix H is transformed into H' by row-column transformation, where the right side of H' is the identity matrix I and the left side matrix is ​​P, then H'=[PI], and the generator matrix G satisfies the following formula (3):

[0316] G = [IP T ] (3)

[0317] It should be noted that the above are all examples, and the present invention is not limited thereto.

[0318] Optionally, in a communication system, the above method may be used to encode and obtain an LDPC code. After obtaining the LDPC code, the communication device may also perform one or more of the following operations: rate matching the LDPC code; interleaving the rate-matched LDPC code according to an interleaving scheme; modulating the interleaved LDPC code according to a modulation scheme to obtain a bit sequence X; and sending the bit sequence X.

[0319] Decoding is the inverse process of encoding, and the base matrix used in the decoding process has the same characteristics as the base matrix used in the encoding process. The encoding process of the LDPC code can refer to the aforementioned implementation description and will not be repeated here. In one implementation, before decoding, the communication device may also perform one or more of the following operations: receiving a signal containing LDPC-based coding, demodulating the signal, deinterleaving and rate matching to obtain a soft value sequence of the LDPC code, and decoding the soft value sequence of the LDPC code.

[0320] The storage involved in this application may refer to storage in one or more memories. The one or more memories may be set separately or integrated in an encoder or decoder, a processor, a chip, a communication device, or a terminal. The one or more memories may also be partially set separately and partially integrated in a decoder, a processor, a chip, a communication device, or a terminal. The type of memory may be any form of storage medium, which is not limited by this application.

[0321] Corresponding to Figure 5 , Figure 6 The embodiment of the present invention also provides a corresponding communication device, which includes a communication device for executing Figure 5 or Figure 6 The module may be software, hardware, or a combination of software and hardware. For example, the module may include a memory, an electronic device, an electronic component, a logic circuit, etc., or any combination thereof. Figure 7 A schematic diagram of the structure of a communication device 700 is provided, and the device 700 can be used to implement the method described in the above method embodiment, and the description in the above method embodiment can be referred to. The communication device 700 can be a chip, a base station, a terminal or other network equipment.

[0322] The communication device 700 includes one or more processors 701. The processor 701 may be a general-purpose processor or a dedicated processor, etc. For example, it may be a baseband processor or a central processing unit. The baseband processor may be used to process the communication protocol and communication data, and the central processing unit may be used to control the communication device (such as a base station, a terminal, or a chip, etc.), execute a software program, and process the data of the software program.

[0323] In one possible approach, Figure 5 , Figure 6 One or more modules in the embodiment may be implemented by one or more processors, or one or more processors and memories.

[0324] In one possible design, the communication device 700 includes one or more processors 701, and the one or more processors 701 can implement the above-mentioned encoding / decoding functions. For example, the communication device can be an encoder or a decoder. In another possible design, the processor 701 can implement other functions in addition to implementing the encoding / decoding function.

[0325] The communication device 700 encodes / decodes the input sequence based on the LDPC matrix; the base matrix of the LDPC matrix can be any base matrix in the aforementioned examples, or a base matrix with a row order changed, a column order changed, or both a row order and a column order changed relative to any base matrix in the aforementioned examples, or a base matrix that is truncated or punctured based on any base matrix in the aforementioned examples, or a matrix that is expanded based on any base matrix in the aforementioned examples. For information on the encoding / decoding process, please refer to Figure 5 and Figure 6 The description of the relevant parts will not be repeated here.

[0326] Optionally, in one design, the processor 701 may include instructions 703 (sometimes also referred to as codes or programs), which may be executed on the processor so that the communication device 700 performs the methods described in the above embodiments. In another possible design, the communication device 700 may also include a circuit, which may implement the encoding / decoding functions in the above embodiments.

[0327] Optionally, in one design, the communication device 700 may include one or more memories 702 on which instructions 704 are stored. The instructions may be executed on the processor so that the communication device 700 performs the method described in the above method embodiment.

[0328] Optionally, data may also be stored in the memory. The optional processor may also store instructions and / or data. The processor and memory may be provided separately or integrated together.

[0329] Optionally, the “saving” described in the above embodiment may be saving in the memory 702 , or saving in the memory or storage device of other peripherals.

[0330] For example, one or more memories 702 may store parameters related to the LDPC matrix listed above, for example, parameters related to the base matrix, such as offset values, base graphs, matrix expansion based on the base graph, rows in the base matrix, expansion factors, base matrix or matrix expansion based on the base matrix, etc. For details, see the above Figure 5 Part of the description.

[0331] Optionally, the communication device 700 may further include a transceiver 705 and an antenna 706. The processor 701 may be referred to as a processing unit, which controls the communication device (terminal or base station). The transceiver 705 may be referred to as a transceiver unit, a transceiver, a transceiver circuit, or a transceiver, etc., which is used to implement the transceiver function of the communication device through the antenna 706.

[0332] Optionally, the communication device 700 may further include a device for generating a transport block CRC, a device for code block segmentation and CRC checking, an interleaver for interleaving, a device for rate matching, or a modulator for modulation processing, etc. The functions of these devices may be implemented by one or more processors 701.

[0333] Optionally, the communication device 700 may further include a demodulator for demodulation operation, a deinterleaver for deinterleaving, a device for rate matching, or a device for code block concatenation and CRC check, etc. The functions of these devices may be implemented by one or more processors 701 .

[0334] Figure 8 A schematic diagram of a communication system 800 is provided, wherein the communication system 800 includes a communication device 80 and a communication device 81, wherein information data is received and sent between the communication device 80 and the communication device 81. The communication devices 80 and 81 may be the communication device 700, or the communication devices 80 and 81 may include the communication device 700 respectively, and receive and / or send information data. In one example, the communication device 80 may be a terminal, and the corresponding communication device 81 may be a base station; in another example, the communication device 80 may be a base station, and the corresponding communication device 81 may be a terminal.

[0335] It is also known to those skilled in the art that the various illustrative logical blocks and steps listed in the embodiments of the present invention can be implemented by electronic hardware, computer software, or a combination of the two. Whether such functions are implemented by hardware or software depends on the specific application and the design requirements of the entire system. Those skilled in the art can use various methods to implement the functions described for each specific application, but such implementation should not be understood as exceeding the scope of protection of the embodiments of the present invention.

[0336] The technology described in this application can be realized in various ways. For example, these technologies can be realized in a combination of hardware, software or hardware. For hardware implementation, the processing unit for executing these technologies at a communication device (for example, a base station, a terminal, a network entity or a chip) can be implemented in one or more general-purpose processors, digital signal processors (DSPs), digital signal processing devices (DSPDs), application-specific integrated circuits (ASICs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs) or other programmable logic devices, discrete gates or transistor logic, discrete hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, and optionally, the general-purpose processor can also be any traditional processor, controller, microcontroller or state machine. The processor can also be implemented by a combination of computing devices, such as a digital signal processor and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a digital signal processor core, or any other similar configuration to implement.

[0337] The steps of the method or algorithm described in the embodiments of the present invention may be directly embedded in hardware, instructions executed by a processor, or a combination of the two. The memory may be a RAM memory, a flash memory, a ROM memory, an EPROM memory, an EEPROM memory, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium in the art. For example, the memory may be connected to the processor so that the processor can read information from the memory and write information to the memory. Alternatively, the memory may also be integrated into the processor. The processor and the memory may be arranged in an ASIC, and the ASIC may be arranged in a UE. Alternatively, the processor and the memory may also be arranged in different components in the UE.

[0338] Through the description of the above embodiments, it is clear to those skilled in the art that the present invention can be implemented in hardware, firmware, or a combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product, which includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, the process or function described in accordance with the embodiment of the present invention is generated in whole or in part. When implemented using a software program, the above functions can also be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. Computer-readable media include computer storage media and communication media, wherein the communication medium includes any medium that facilitates the transmission of a computer program from one place to another. The storage medium can be any available medium that a computer can access. By way of example but not limitation: computer readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program codes in the form of instructions or data structures and can be accessed by a computer. In addition. Any connection can be appropriately a computer readable medium. For example, if the software is transmitted from a website, server or other remote source using a coaxial cable, optical fiber cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwave, then coaxial cable, optical fiber cable, twisted pair, DSL or wireless technologies such as infrared, wireless and microwave are included in the definition of the medium. As used in the present invention, disks and discs include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks and blue-ray discs, where disks usually copy data magnetically, while discs use lasers to optically copy data. The above combination should also be included in the scope of protection of computer readable media.

[0339] It should be noted that, in the present application, “ / ” represents and / or, for example, “encoding / decoding (encoding and / or decoding)” refers to encoding, or decoding, or encoding and decoding.

[0340] In short, the above is only a preferred embodiment of the technical solution of the present invention, and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A data processing method, characterized in that: The method comprises: Get the expansion factor Z, where Z is a positive integer; Encoding or decoding an input sequence based on a low density parity check (LDPC) matrix, wherein the LDPC matrix is ​​obtained based on a base matrix and the expansion factor Z; Output the encoded or decoded bit sequence; The base matrix includes elements of m rows in the first matrix, and the row numbers of the m rows are represented by i=0, 1, 2, ... (m-1), 5≤m≤46; The first matrix includes 46 rows and 68 columns, the row numbers are represented by i=0, 1, 2, ... 45, and the column numbers are represented by j=0, 1, 2, ...

67. The first matrix includes the following non-zero elements in the rows and columns, and the non-zero elements correspond to the circulant permutation matrix of size Z*Z in the LDPC matrix, and the circulant permutation matrix of size Z*Z is the unit matrix of size Z*Z carried out P to the right i,j The matrix obtained by cyclic shift is P i,j =mod(V i,j ,Z),V i,j are the values ​​corresponding to the non-zero elements in the following rows and columns of the first matrix: i=0,j=0,1,2,3,5,6,9,10,11,12,13,15,16,18,19,20,21,22,23, V i,j They are 211, 198, 188, 186, 219, 4, 29, 144, 116, 216, 115, 233, 144, 95, 216, 73, 261, 1, 0 respectively; i=1,j=0,2,3,4,5,7,8,9,11,12,14,15,16,17,19,21,22,23,24, V i,j They are 179, 162, 223, 256, 160, 76, 202, 117, 109, 15, 72, 152, 158, 147, 156, 119, 0, 0, 0 respectively; i=2,j=0,1,2,4,5,6,7,8,9,10,13,14,15,17,18,19,20,24,25, V i,j They are 258, 167, 220, 133, 243, 202, 218, 63, 0, 3, 74, 229, 0, 216, 269, 200, 234, 0, 0 respectively; i=3,j=0,1,3,4,6,7,8,10,11,12,13,14,16,17,18,20,21,22,25, V i,j They are 187, 145, 166, 108, 82, 132, 197, 41, 162, 57, 36, 115, 242, 165, 0, 113, 108, 1, 0 respectively; i=4,j=0,1,26,V i,j They are 246, 235, and 0 respectively; i=5,j=0,1,3,12,16,21,22,27,V i,j They are 261, 181, 72, 283, 254, 79, 144, 0 respectively; i=6,j=0,6,10,11,13,17,18,20,28,V i,j They are 80, 144, 169, 90, 59, 177, 151, 108, 0 respectively; i=7,j=0,1,4,7,8,14,29,V i,j They are 169, 189, 154, 184, 104, 164, 0 respectively; i=8,j=0,1,3,12,16,19,21,22,24,30,V i,j They are 54, 0, 252, 41, 98, 46, 15, 230, 54, 0 respectively; i=9,j=0,1,10,11,13,17,18,20,31,V i,j They are 162, 159, 93, 134, 45, 132, 76, 209, 0 respectively; i=10,j=1,2,4,7,8,14,32,V i,j They are 178, 1, 28, 267, 234, 201, 0 respectively; i=11,j=0,1,12,16,21,22,23,33,V i,j They are 55, 23, 274, 181, 273, 39, 26, 0 respectively; i=12,j=0,1,10,11,13,18,34,V i,j They are 225, 162, 244, 151, 238, 243, 0 respectively; i=13,j=0,3,7,20,23,35,V i,j They are 231,0,216,47,36,0 respectively; i=14,j=0,12,15,16,17,21,36,V i,j They are 0,186,253,16,0,79,0 respectively; i=15,j=0,1,10,13,18,25,37,V i,j They are 170, 0, 183, 108, 68, 64, 0 respectively; i=16,j=1,3,11,20,22,38,V i,j They are 270, 13, 99, 54, 0, 0 respectively; i=17,j=0,14,16,17,21,39,V i,j They are 153, 137, 0, 0, 162, 0 respectively; i=18,j=1,12,13,18,19,40,V i,j They are 161, 151, 0, 241, 144, 0 respectively; i=19,j=0,1,7,8,10,41,V i,j They are 0, 0, 118, 144, 0, 0 respectively; i=20,j=0,3,9,11,22,42,V i,j They are 265, 81, 90, 144, 228, 0 respectively; i=21,j=1,5,16,20,21,43,V i,j They are 64, 46, 266, 9, 18, 0 respectively; i=22,j=0,12,13,17,44,V i,j They are 72,189,72,257,0 respectively; i=23,j=1,2,10,18,45,V i,j They are 180, 0, 0, 165, 0 respectively; i=24,j=0,3,4,11,22,46,V i,j They are 236,199,0,266,0,0 respectively; i=25,j=1,6,7,14,47,V i,j They are 205, 0, 0, 183, 0 respectively; i=26,j=0,2,4,15,48,V i,j They are 0, 0, 0, 277, 0 respectively; i=27,j=1,6,8,49,V i,j They are 45, 36, 72, 0 respectively; i=28,j=0,4,19,21,50,V i,j They are 275,0,155,62,0 respectively; i=29,j=1,14,18,25,51,V i,j They are 0,180,0,42,0 respectively; i=30,j=0,10,13,24,52,V i,j They are 0, 90, 252, 173, 0 respectively; i=31,j=1,7,22,25,53,V i,j They are 144, 144, 166, 19, 0 respectively; i=32,j=0,12,14,24,54,V i,j They are 0, 211, 36, 162, 0 respectively; i=33,j=1,2,11,21,55,V i,j They are 0, 0, 76, 18, 0 respectively; i=34,j=0,7,15,17,56,V i,j They are 197,0,108,0,0 respectively; i=35,j=1,6,12,22,57,V i,j They are 199, 278, 0, 205, 0 respectively; i=36,j=0,14,15,18,58,V i,j They are 216,16,0,0,0 respectively; i=37,j=1,13,23,59,V i,j They are 72, 144, 0, 0 respectively; i=38,j=0,9,10,12,60,V i,j They are 190, 0, 0, 0, 0 respectively; i=39,j=1,3,7,19,61,V i,j They are 153, 0, 165, 117, 0 respectively; i=40,j=0,8,17,62,V i,j They are 216, 144, 2, 0 respectively; i=41,j=1,3,9,18,63,V i,j They are 0, 0, 0, 183, 0 respectively; i=42,j=0,4,24,64,V i,j They are 27, 0, 35, 0 respectively; i=43,j=1,16,18,25,65,V i,j They are 52,243,0,270,0 respectively; i=44,j=0,7,9,22,66,V i,j They are 18, 0, 0, 57, 0 respectively; i=45,j=1,6,10,67,V i,j They are 168,0,144,0 respectively; The elements of the first matrix other than the non-zero element (i, j) are zero elements, and the zero elements correspond to an all-zero matrix of size Z*Z in the LDPC matrix.

2. The method according to claim 1, characterized in that The base matrix includes elements of m rows and n columns in the first matrix, and the column numbers of the n columns are expressed as j=0, 1, 2, ... (n-1), 27≤n≤68.

3. The method according to claim 1 or 2, characterized in that: The expansion factor Z is one of 9, 18, 36, 72, 144, and 288.

4. The method according to any one of claims 1 to 3, characterized in that The length K of the input sequence satisfies K=22*Z.

5. The method according to any one of claims 1 to 4, characterized in that The method further comprises: The LDPC matrix is ​​obtained based on the base matrix and the expansion factor Z, wherein each non-zero element in the base matrix is ​​replaced by a circulant permutation matrix of the Z*Z size, and each zero element in the base matrix is ​​replaced by an all-zero matrix of the Z*Z size.

6. A data processing method, characterized in that: The method comprises: Get the expansion factor Z, where Z is a positive integer; Encoding or decoding an input sequence based on a low density parity check (LDPC) matrix, wherein the LDPC matrix is ​​obtained based on a base matrix and the expansion factor Z; Output the encoded or decoded bit sequence; The base matrix includes elements of m rows in the second matrix, and the row numbers of the m rows are represented by i=0, 1, 2, ... (m-1), 5≤m≤46; The second matrix includes 46 rows and 68 columns, the row numbers are represented by i=0, 1, 2, ... 45, and the column numbers are represented by j=0, 1, 2, ... 67, wherein the row weight of each row of the second matrix is: 19,19,19,19,3,8,9,7,10,9,7,8,7,6,7,7,6,6,6,6,6,6,5,5,6,5,5,4,5,5,5,5,5,5,5,5,5,4,5,5,4,5,4,5,5,4。 7. The method according to claim 6, characterized in that The base matrix includes elements of m rows and n columns in the second matrix, and the column numbers of the n columns are expressed as j=0, 1, 2, ... (n-1), 27≤n≤68.

8. The method according to claim 6 or 7, characterized in that: The expansion factor Z is: One of 2,4,8,16,32,64,128,256, One of 3,6,12,24,48,96,192,384, One of 5,10,20,40,80,160,320, One of 7,14,28,56,112,224, One of 11,22,44,88,176,352, One of 13, 26, 52, 104, 208, or One of 15, 30, 60, 120, 240.

9. A communication device, characterized in that: The method comprises a module for executing the method as claimed in any one of claims 1 to 5, or comprises a module for executing the method as claimed in any one of claims 6 to 8.

10. A computer storage medium, characterized in that: A program is stored, and when the program is executed, the method according to any one of claims 1 to 5 is executed, or the method according to any one of claims 6 to 8 is executed.

11. A computer program product, characterized in that The method comprises instructions which, when executed, cause the method according to any one of claims 1 to 5 to be executed, or cause the method according to any one of claims 6 to 8 to be executed.

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