Link modeling method for hardware

Abstract

The invention discloses a hardware link modeling method, which comprises the following steps of: obtaining a total transfer function of a link through a scattering parameter, obtaining a step response of the link through the transfer function, and storing the response in a lookup table; designing a jitter generation circuit by using a hardware description language, obtaining each jitter component injection value, and further obtaining a total jitter injection value; designing a link modeling circuit by using a hardware description language, and interpolating the step response by using the total jitter injection value to complete the total jitter injection to obtain the step response after the jitter injection; and designing a circuit for converting the step response into the pulse response by using a hardware description language, finally obtaining the pulse response after jitter injection, and completing modeling of the inter-symbol interference and jitter hardware circuit of the link. The hardware resource consumption of the method is far lower than that of a traditional algorithm.

Description

Technical Field

[0001] The invention belongs to the technical field of signal processing, and in particular relates to a hardware link modeling method. Background Art

[0002] With the rapid development of technologies such as artificial intelligence, cloud computing, big data and the Internet, high-throughput wired communication technology is the key to realizing the next generation of computing and communication systems. Due to its advantages such as high transmission rate and low transmission delay, high-speed serial communication technology has become the mainstream technology in the field of wired high-speed communication.

[0003] Before the SerDes (Serializer / Deserializer) chip is taped out, it is necessary to verify the algorithm and system with simulation. Software simulation based on Python and other technologies is extremely inefficient and does not support large-scale simulation applications. Hardware simulation based on Field Programmable Gate Array (FPGA) is thousands of times more efficient and supports large-scale simulation applications. However, division and floating-point numbers are difficult to implement in FPGA and consume a lot of resources. Therefore, how to model an analog link in FPGA with low resource consumption, high precision, and high resolution is a key issue in hardware simulation.

[0004] The factors that need to be considered for modeling an analog link are Inter Symbol Interference (ISI) and jitter. As the SerDes rate gradually increases, the tolerance for jitter gradually decreases, and its impact on the communication system becomes increasingly greater. For example, if the Four-Level Pulse Amplitude Modulation (PAM-4) technology is used, in 112 Gbps SerDes, the duration of 1 unit interval (UI) is 17.86 ps; in 224 Gbps SerDes, the duration of 1 UI is 8.93 ps. The traditional link modeling method consumes a lot of hardware resources to complete low-resolution (generally 1 / 32UI) jitter injection, which is difficult to meet the requirements of high-precision, high-resolution, and scalable jitter injection, and it is also difficult to meet the requirements of high-speed, parallelized SerDes hardware simulation.

[0005] Therefore, the existing modeling methods need to be improved and developed. Summary of the invention

[0006] In order to solve the above technical problems, the present invention provides a hardware link modeling method, and proposes a modeling method based on the advantages of FPGA's low resource consumption, high precision and high resolution to further improve the accuracy and efficiency of SerDes hardware simulation.

[0007] To achieve the above object, the present invention adopts the following technical solutions:

[0008] A hardware link modeling method, the method comprising the following steps:

[0009] Step 1, respectively obtain scattering parameter (S parameter) files of the transmitter chip package, channel and receiver chip package; use software language (such as Python) to process the obtained S parameters to obtain the transfer functions of the transmitter chip package, channel and receiver chip package;

[0010] Step 2: Use software language (such as Python) to process the obtained transfer function to obtain a step response of a step signal after passing through the transmitter chip package, channel and receiver chip package. The step response contains parameter information such as signal modulation format, signal baud rate, signal sampling rate, number of pre-cursors of the step response, number of post-cursors of the step response, quantization bit width of the step response and bit width of the link input signal; store the obtained step response in a hardware lookup table;

[0011] Step 3: Use a hardware description language (such as Chisel) to design a hardware generation circuit for each jitter component to obtain an injection value for each jitter component;

[0012] Step 4: Use a hardware description language (such as Chisel) to sum the injected values ​​of each jitter component to obtain a total jitter injection value;

[0013] Step 5: Using the step response and the total jitter injection value as input, a low-resource-consumption, high-precision, high-resolution jitter injection algorithm is implemented in hardware by interpolation to obtain a step response after jitter injection; subtracting the two step responses after jitter injection to obtain a pulse response after jitter injection, thereby completing the modeling of inter-symbol interference and jitter of the link.

[0014] The beneficial effects of the present invention are:

[0015] The present invention can complete high-resolution jitter injection with low resource consumption. The divisor in the calculation formula is 2^n, which can be converted into a shift operation in the hardware circuit. Therefore, the algorithm of the present invention can be implemented in the hardware circuit; the hardware resource consumption of the algorithm of the present invention is much lower than that of the traditional algorithm, and can save about 8 times, 4 times or 2 times according to the needs. With the gradual increase of high-speed serial communication rate, slight changes in jitter will have a greater impact on the system. The high-resolution jitter injection method of the present invention has a wide range of application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A process of a hardware link modeling method of the present invention;

[0017] Figure 2 It is a schematic diagram of a mixed-mode two-port network model;

[0018] Figure 3 This is a schematic diagram of the step response modeling principle of the present invention;

[0019] Figure 4 Schematic diagram of the periodic jitter hardware generation technique;

[0020] Figure 5 Schematic diagram of the technology principle for the duty cycle distortion hardware generation;

[0021] Figure 6 A schematic diagram of the principle of the bounded uncorrelated jitter hardware generation technique;

[0022] Figure 7 Schematic diagram of the relationship between total jitter and each jitter component;

[0023] Figure 8 A schematic diagram of the high-precision, low-resource-consumption jitter injection technology of the present invention;

[0024] Fig. 9 This is a schematic diagram of the test results of the present invention. DETAILED DESCRIPTION

[0025] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0026] Figure 1 The process of a hardware link modeling method of the present invention is shown, which is mainly divided into five steps: extracting S parameters; calculating the step response of the link; generating injection values ​​of each jitter component; obtaining the total jitter injection value; link modeling. The specific process of each step is described below.

[0027] Step 1: Extract S parameters to obtain transfer function. Figure 2A schematic diagram of a mixed-mode two-port network model is shown. Subscripts 1 and 2 represent the first physical port and the second physical port, respectively. Subscript 11 represents the first physical port to the first physical port, and subscript 12 represents the first physical port to the second physical port. Subscripts 21 and 22 are similar. The differential mode incident wave, common mode incident wave, differential mode reflected wave, and common mode reflected wave are defined as , , and , which are related to the differential mode S parameters , Common mode S parameters , cross-mode S parameters and The relationship is:

[0028] (1)

[0029] When only differential signal transmission is used, only differential mode S parameters are generally considered. :

[0030] (2)

[0031] Therefore, formula (1) can be simplified as:

[0032] (3)

[0033] Generally speaking, conjugate matching is satisfied in actual circuit design. Therefore, the transfer function can be obtained through S parameters according to the following formula.

[0034] (4)

[0035] in, is the reference impedance, is the source impedance, is the load impedance, is the source reflection coefficient, is the load reflection coefficient, is the input reflection coefficient.

[0036] According to the above process, the scattering parameters of the transmitter chip package, channel, and receiver chip package, i.e., the S parameter files, can be processed respectively to obtain three transfer functions. The total link transfer function can be obtained by multiplying the three transfer functions in the frequency domain using software languages ​​such as Python. .

[0037] Step 2, get the step response of the link. The traditional solution uses the pulse response and the input signal convolution method to model the inter-symbol interference, but it consumes huge hardware resources to complete low-precision jitter injection, which is not suitable for existing needs. The traditional solution is to calculate the pulse response corresponding to all possible jitter values ​​using software language and store it in the hardware circuit as a lookup table. If you want to improve the resolution or jitter injection range, you need to increase the consumption of hardware resources, and this solution is not scalable, which also hinders the parallelization of SerDes hardware simulation design.

[0038] The present invention uses step response instead of impulse response to model the link, laying the foundation for subsequent high-precision and high-resolution jitter injection algorithms. Figure 3 As shown, this schematic diagram does not consider jitter modeling but only considers inter-symbol interference modeling. The first step signal 1 and the second step signal 2 differ by a unit interval on the time axis, and a pulse signal can be obtained by subtracting the two. Similarly, the first step response 3 and the second step response 4 differ by a unit interval on the time axis, and the corresponding pulse response can be obtained by subtracting the two. Using this relationship, the translation of the first step signal 1 and the second step signal 2 on the time axis represents the signal jitter. Accordingly, the first step response 3 and the second step response 4 complete the translation of the same time axis, thereby obtaining a pulse response injected with a certain jitter value.

[0039] The parameters required to generate the step response of the link using a software language (such as Python) are: signal modulation format, signal baud rate, signal sampling rate, number of pre-cursors of the step response, number of post-cursors of the step response, quantization bit width of the step response, and bit width of the link input signal. First, use the software language to generate a step signal based on the above parameters; second, use the software language's Fast Fourier Transformation (FFT) function to transform the time domain step signal into the frequency domain; third, use the software language to convert the link total transfer function obtained in step 1 Multiply it with the step signal transformed into the frequency domain; fourth, use the Inverse Fast Fourier Transform (IFFT) function of the software language to transform the signal after the frequency domain multiplication into the time domain, so as to obtain the step response of the link.

[0040] Step 3, obtain the injection value of each jitter component. To meet the requirements of efficient and real-time jitter injection, this step needs to be completed in the hardware circuit. The jitter components considered in the present invention are periodic jitter (PJ), duty cycle distortion (DCD), bounded uncorrelated jitter (BUJ) and random jitter (RJ).

[0041] There are three types of periodic jitter: sine wave, triangle wave and square wave. The probability density functions of the three types of periodic jitter are:

[0042] (5)

[0043] in, is the peak value of periodic jitter. Figure 4 A schematic diagram showing the period jitter generation technique is shown, where and are the clock frequency and the frequency of periodic jitter, respectively. Based on the initial parameters and probability density function, the lookup table of each type of periodic jitter can be obtained through Python script, and the lookup table is stored in the random access memory (RAM). A counter is used to generate the read address of each RAM, and the RAM read data obtained is the three types of PJ generation values. Only one type of periodic jitter can be injected at the same time, so a select signal is required to select the current periodic jitter type. If there is a transition edge (low level-high level or high level-low level) at present, the value of the periodic jitter selected by the select signal is output; if there is no transition edge at present, 0 is output.

[0044] Duty cycle distortion refers to a data-dependent jitter in which the ratio of the high-level duration to the low-level duration of a pulse deviates from its ideal value. Its probability density function is:

[0045] (6)

[0046] in, is the peak value of DCD jitter. Figure 5 The schematic diagram of DCD jitter generation technology is shown. The hardware generation of DCD jitter can be completed by the presence or absence of a transition edge and the direction of the transition edge (low level-high level or high level-low level).

[0047] The probability density function of uniformly distributed bounded uncorrelated jitter is shown in equation (7), where: is the peak value of BUJ. Figure 6The schematic diagram of the uniformly distributed BUJ generation technology is shown. According to the initial parameters, the BUJ lookup table can be obtained through the Python script, and the lookup table is stored in the RAM. The storage depth of the RAM is ramDepth. Use the Uniform Random Number Generator (URNG) to generate a uniformly distributed random number as the read address of the RAM. The read address range is 0 to ramDepth-1. The RAM read data obtained is the BUJ generation value. If there is a jump edge (low level-high level or high level-low level) at present, the BUJ generation value is output; if there is no jump edge at present, 0 is output.

[0048] (7)

[0049] The probability density function of random jitter is shown in formula (8), where: is the standard deviation, is the mean. The RJ generation technology is the same as the hardware Gaussian Random Number Generator (GRNG), and there are many publicly available efficient architectures for GRNG technology that can be directly adopted.

[0050] (8)

[0051] Step 4, get the total jitter injection value. The jitter subdivision model can help us deeply understand the impact of each jitter component on the high-speed serial communication system, but when injecting jitter, we only need to get the total jitter injection value composed of the sum of each subdivided jitter component, and use this total jitter injection value to complete the jitter injection modeling of the link.

[0052] The relationship between total jitter and subdivision jitter is linear addition, such as Figure 7 As shown, in the example of the present invention, only periodic jitter, duty cycle distortion, bounded uncorrelated jitter and random jitter are considered, but other subdivided jitters can also be injected using the same method. The total jitter value can be obtained by adding all subdivided jitters in hardware.

[0053] Step 5: Link modeling. According to step 2, a link step response and a total jitter injection value are obtained to model the inter-symbol interference and jitter of the link. Figure 3As shown in the figure, the pulse response after jitter injection can be obtained by translating the step response on the time axis. For inter-symbol interference modeling, it can be completed by subtracting two step responses translated on the time axis; but for jitter modeling, it is necessary to consider how to convert the time information on the horizontal axis into information that can be processed by the FPGA in a hardware system such as an FPGA. Therefore, the key and difficulty of this step lies in jitter modeling, that is, how to implement a low-resource consumption, high-precision, and high-resolution FPGA jitter injection algorithm.

[0054] In traditional solutions, due to hardware resource limitations, the oversampling factor is generally set to 32 times, so the jitter resolution is 1 / 32 UI. Figure 8 Taking 4 times oversampling as an example, a schematic diagram of a low resource consumption, high precision, and high resolution jitter injection algorithm according to an example of the present invention is shown.

[0055] First, how the method of the present invention achieves low resource consumption is explained. In order to increase the resolution of jitter, the traditional method can only increase the oversampling multiple, such as oversampling 32 times. The Nyquist-Shannon sampling theorem points out that if the signal is to be restored without distortion, the sampling frequency needs to be greater than or equal to twice the signal bandwidth. The above sampling theorem can be understood in another way: when a continuous signal is converted into a discrete signal through sampling, and then the discrete signal is restored to a continuous signal, the fidelity of the result depends on the sampling frequency. Oversampling 4 times, 8 times or 16 times in the frequency domain already includes all the frequency domain information that the link can express, meets the requirements of the sampling theorem, and can restore the continuous signal from the discrete signal. Therefore, the necessity of oversampling 32 times is greatly reduced. The oversampling multiple is set to 4 times, 8 times or 16 times, and accordingly, the resource consumption will be reduced by about 8 times, 4 times or 2 times relative to the traditional solution. According to the traditional method, reducing the oversampling multiple will reduce the resolution of jitter. Although the oversampling multiple is reduced, the present invention uses interpolation to improve the resolution of jitter.

[0056] Next, the invention will explain how to achieve high-resolution jitter injection. Oversampling by 4 times can include all frequency domain information that a link can express. The accuracy of jitter modeling is improved by interpolation, such as linear interpolation, sinc interpolation, etc. Figure 8 The high-resolution jitter injection algorithm is demonstrated using linear interpolation as an example. and are the voltage values ​​(amplitude values) of the two transition edges respectively. Jitter is defined as the difference between the actual edge time and the ideal edge time. Figure 8As shown, point A-point B is an ideal edge. If the total jitter injection value is 0.1UI to the right, the edge of point A-point B is shifted to the right by 0.1 UI. The intersection of the shifted edge and the vertical dashed line passing through point B is point C. Point C is the new sampling point after the jitter is injected. Point C is used to replace point B, that is, the vertical axis amplitude value of the sampling point is changed to complete the injection of the horizontal axis jitter. Therefore, the signal edge after the jitter is injected is point A-point C. Equation (9) shows the formula for calculating the amplitude of point C, where , and are the voltage values ​​(amplitude values) at points A, B and C respectively, The maximum value of jitter injection is a positive integer, which is related to the jitter injection resolution. It is also used to quantize decimals such as 0.25 and 0.1 into integers in the FPGA. It needs to be set to 2^n, such as 1024, so the jitter resolution is 1 / 4096 UI. Although this formula involves division, its divisor must be 2^n, so the division can be converted into a shift operation in hardware.

[0057] (9)

[0058] The step response at the current moment is interpolated according to the total jitter injection value to complete the jitter injection of the edge and obtain the step response after the jitter injection. The impulse response after the jitter injection can be obtained by subtracting the two step responses after the jitter injection, completing the inter-symbol interference and jitter modeling of the link.

[0059] Finally, the high-precision indicators of the method of the present invention are demonstrated with actual test results. Fig. 9 The test results of the low resource consumption, high precision and high resolution hardware link modeling method described in the present invention are demonstrated. Fig. 9 The existing algorithm is a software high-precision jitter injection algorithm proposed by the author Wu Tong in his doctoral dissertation "Research on Key Technologies of High-Speed ​​Serial Communication Signal Jitter", but the algorithm involves arbitrary floating-point number division, which is difficult to implement in hardware, and the accuracy of the proposed algorithm is low after testing. It can be seen from the figure that the sampling points of the algorithm proposed by the present invention basically coincide with the control group after the jitter is injected, while the existing algorithm deviates greatly from the control group. Table 1 shows Fig. 9 Middle part zoom Figure 4 Specific data and relative error of each point.

[0060] Table 1

[0061] It can be seen from Table 1 that the algorithm proposed in the present invention highly overlaps with the control group, with relative errors of 0.00%, 0.00%, 0.00% and 0.26%, respectively, while the existing algorithm has a large deviation from the control group, with relative errors of 1.23%, 0.97%, 0.74% and 0.79%, respectively.

[0062] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A hardware link modeling method, characterized in that: The method comprises the following steps: Step 1, respectively obtaining scattering parameter files of the transmitting end chip package, the channel and the receiving end chip package; processing the obtained scattering parameters to obtain the transfer functions of the transmitting end chip package, the channel and the receiving end chip package; Step 2: Process the obtained transfer function to obtain a step response of a step signal after passing through the transmitter chip package, the channel and the receiver chip package, and store the obtained step response in a hardware lookup table; Step 3: Use hardware description language to design hardware generation circuits for each jitter component to obtain injection values ​​for each jitter component; Step 4: Use the hardware description language to sum the injection values ​​of the obtained jitter components to obtain a total jitter injection value; Step 5: Using the step response and the total jitter injection value as input, complete the jitter injection algorithm in hardware by interpolation to obtain the step response after jitter injection; subtract the two step responses after jitter injection to obtain the pulse response after jitter injection, and complete the modeling of inter-symbol interference and jitter of the link.

2. A hardware link modeling method according to claim 1, characterized in that: In the step 1, the scattering parameter files of the transmitting chip package, the channel and the receiving chip package are processed respectively to obtain three transfer functions corresponding to the transmitting chip package, the channel and the receiving chip package, and the three transfer functions are multiplied in the frequency domain to obtain the total link transfer function.

3. A hardware link modeling method according to claim 2, characterized in that: The parameter information required for generating the step response in step 2 includes signal modulation format, signal baud rate, signal sampling rate, number of front cursors of the step response, number of rear cursors of the step response, quantization bit width of the step response and bit width of the link input signal.

4. A hardware link modeling method according to claim 3, characterized in that: The steps for obtaining the step response in step 2 are as follows: Step 2.1, generating a time domain step signal according to the parameter information; Step 2.2, transforming the time domain step signal into the frequency domain using a fast Fourier transform function; Step 2.3, multiplying the link total transfer function by the step signal transformed into the frequency domain; Step 2.4: transform the multiplied signal into the time domain using an inverse fast Fourier transform function to obtain a step response of the link.

5. A hardware link modeling method according to claim 4, characterized in that: The jitter components in step 3 include periodic jitter, duty cycle distortion, bounded uncorrelated jitter and random jitter.

6. A hardware link modeling method according to claim 5, characterized in that: The periodic jitter includes sine wave, triangle wave and square wave jitter.

7. A hardware link modeling method according to claim 6, characterized in that: In the step 3, the probability density function of each jitter component is calculated, and the hardware generation circuit of each jitter component is designed according to the probability density function.

8. A hardware link modeling method according to claim 7, characterized in that: The summing method in step 4 is linear addition.

9. A hardware link modeling method according to claim 8, characterized in that: The interpolation method of step 5 includes linear interpolation and sinc interpolation; the maximum value of the total jitter injection value is related to the jitter injection resolution, which is set to 2^n and is a positive integer.

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