Three-dimensional memory, manufacturing method thereof and memory system

Abstract

The embodiment of the invention discloses a three-dimensional memory, a manufacturing method thereof and a memory system, and the three-dimensional memory comprises a stacking structure which comprises gate layers and first dielectric layers which are alternately stacked; the first channel structure penetrates through the stacking structure in the first direction; the conductive part is positioned at one end of the first channel structure in the first direction; the insulating layer and the selection gate layer are sequentially stacked on the conductive part; the second channel structure penetrates through the selection gate layer and the insulating layer; the isolation structure penetrates through the selection grid layer; wherein in a second direction perpendicular to the first direction, the isolation structure is located between two adjacent second channel structures; the distance between the center line of the second channel structure in the first direction and the isolation structure is a first distance, and the distance between the center line of the conductive part in the first direction and the isolation structure is a second distance; wherein the first distance is different from the second distance.

Description

Technical Field

[0001] The disclosed embodiments relate to the field of semiconductor technology, and more particularly to a three-dimensional memory, a manufacturing method thereof, and a memory system. Background Art

[0002] Memory devices are storage devices used to store information in modern information technology. As a typical non-volatile semiconductor memory, three-dimensional NAND (Not-And) memory has gradually become a mainstream product in the storage market due to its high storage density, controllable production cost, suitable editing and erasing speed and retention characteristics.

[0003] However, as people's requirements for storage capacity continue to increase and the storage density of three-dimensional memories continues to increase, there are many problems in the structure and manufacturing process of three-dimensional memories that need to be improved. Summary of the invention

[0004] According to some aspects of the embodiments of the present disclosure, a three-dimensional memory is provided, including:

[0005] A stacked structure, the stacked structure comprising alternately stacked gate layers and first dielectric layers;

[0006] a first channel structure, the first channel structure penetrating the stacked structure along a first direction; a conductive portion, located at one end of the first channel structure in the first direction; and an insulating layer and a selection gate layer sequentially stacked on the conductive portion;

[0007] A second channel structure passes through the selection gate layer and the insulating layer; an isolation structure passes through the selection gate layer; wherein, along a second direction perpendicular to the first direction, the isolation structure is located between two adjacent second channel structures; a distance between a center line of the second channel structure in the first direction and the isolation structure is a first distance, and a distance between a center line of the conductive portion in the first direction and the isolation structure is a second distance; wherein the first distance is different from the second distance.

[0008] In some embodiments, the first distance is greater than the second distance.

[0009] In some embodiments, the first distance of the second channel structure adjacent to the isolation structure is greater than the second distance of the conductive portion adjacent to the isolation structure.

[0010] In some embodiments, a size of the second channel structure in the second direction is smaller than a size of the conductive portion in the second direction.

[0011] In some embodiments, an orthographic projection of the second channel structure in the first direction falls within an orthographic projection of the conductive portion in the first direction.

[0012] In some embodiments, the three-dimensional memory further includes: a second dielectric layer penetrating the selection gate layer and surrounding the second channel structure.

[0013] In some embodiments, the first channel structure includes:

[0014] A barrier layer, a storage layer, a tunnel layer and a channel layer are sequentially arranged along the second direction; wherein,

[0015] The conductive portion is coupled to the channel layer, and the conductive portion is coupled to the second channel structure.

[0016] In some embodiments, the conductive portion is located at one end of the first channel structure close to the second channel structure; one end of the conductive portion in the first direction is coupled to the channel layer, and the other end is coupled to the second channel structure.

[0017] In some embodiments, the conductive portion is within the first channel structure, and a size of the conductive portion in the second direction is smaller than a size of the first channel structure in the second direction.

[0018] In some embodiments, the conductive portion is surrounded by the channel layer, and a sidewall of the conductive portion in the second direction contacts the channel layer.

[0019] In some embodiments, the barrier layer surrounds the conductive portion, and the conductive portion at least covers the channel layer in the first direction.

[0020] In some embodiments, in the first direction, the conductive portion includes: an extension portion extending from a surface of a side of the channel layer close to the selection gate layer and away from the selection gate layer, and the extension portion is surrounded by the channel layer.

[0021] In some embodiments, the three-dimensional memory further includes a peripheral circuit located on a side of the second channel structure away from the first channel structure.

[0022] According to some aspects of the embodiments of the present disclosure, a method for manufacturing a three-dimensional memory is provided, comprising:

[0023] forming a stacked structure, the stacked structure comprising alternately stacked sacrificial layers and first dielectric layers;

[0024] forming a first channel structure penetrating the stacked structure along a first direction;

[0025] forming a conductive portion at one end of the first channel structure along the first direction;

[0026] forming an insulating layer and a selection gate layer in sequence on the conductive portion;

[0027] forming an isolation structure penetrating the selection gate layer;

[0028] A first opening is formed that penetrates the selection gate layer and the insulating layer, and a second channel structure is formed in the first opening; wherein, along a second direction perpendicular to the first direction, the isolation structure is located between two adjacent second channel structures; a distance between a center line of the second channel structure in the first direction and the isolation structure is a first distance, and a distance between a center line of the conductive portion in the first direction and the isolation structure is a second distance; wherein the first distance is different from the second distance;

[0029] The sacrificial layer is replaced with a conductive material to form a gate layer.

[0030] In some embodiments, the first distance is greater than the second distance.

[0031] In some embodiments, the first distance of the second channel structure adjacent to the isolation structure is greater than the second distance of the conductive portion adjacent to the isolation structure.

[0032] In some embodiments, a size of the second channel structure in the second direction is smaller than a size of the conductive portion in the second direction.

[0033] In some embodiments, an orthographic projection of the second channel structure in the first direction falls within an orthographic projection of the conductive portion in the first direction.

[0034] In some embodiments, the manufacturing method further comprises:

[0035] Before forming the second channel structure, a second dielectric layer is formed on the sidewall of the first opening; the second dielectric layer surrounds the second channel structure.

[0036] In some embodiments, a method of forming the first channel structure includes:

[0037] Forming a channel hole penetrating the stacked structure, wherein: a barrier layer, a storage layer, a tunneling layer, a channel layer and a core are sequentially formed in the channel hole;

[0038] The conductive portion is coupled to the channel layer, and the conductive portion is coupled to the second channel structure.

[0039] In some embodiments, the method of forming the conductive portion includes:

[0040] Before forming the insulating layer, a conductive portion is formed between the first channel structure and the second channel structure; the formed insulating layer is located between the conductive portion and the formed selection gate layer; wherein one end of the conductive portion in the first direction is coupled to the channel layer, and the other end is coupled to the second channel structure.

[0041] In some embodiments, the manufacturing method further comprises:

[0042] Before forming the insulating layer, a core portion at one end of the first channel structure is etched to form a first opening.

[0043] In some embodiments, the method of forming the conductive portion includes:

[0044] The conductive portion is formed in the first opening, wherein the conductive portion is surrounded by the channel layer, and a sidewall of the conductive portion in the second direction is in contact with the channel layer.

[0045] In some embodiments, the method of forming the conductive portion includes:

[0046] At least etching the channel layer to enlarge the size of the first opening in the second direction to form a second opening;

[0047] The conductive portion is formed in the second opening; wherein the barrier layer surrounds the conductive portion, and the conductive portion at least covers the channel layer in the first direction.

[0048] In some embodiments, the method of forming the conductive portion includes:

[0049] further etching the core portion exposed from the first opening to enlarge the size of the first opening in the first direction;

[0050] In the first direction, the conductive portion formed further includes: an extending portion extending toward the core portion, wherein the extending portion is surrounded by the channel layer.

[0051] In some embodiments, the manufacturing method further includes: forming a peripheral circuit on a side of the second channel structure away from the first channel structure.

[0052] According to some aspects of the embodiments of the present disclosure, there is provided a memory system, including:

[0053] A memory device comprising one or more of the three-dimensional memories; and

[0054] A memory controller is coupled to the memory device and controls the memory device.

[0055] The second channel structure of the embodiment of the present disclosure is coupled to the first channel structure through the conductive part, the first channel structure penetrates the selection gate layer, the selection gate layer is used as the control gate of the second channel structure to control the conduction and disconnection of the second channel structure, and an isolation structure penetrating the selection gate layer is set between two adjacent second channel structures, and the selection gate layer is divided into different areas that can be independently controlled, which is conducive to refining the partition storage and fine control of the three-dimensional memory, and improving the operation rate and data stability of the three-dimensional memory. The distance between the center line of the second channel structure in the first direction and the isolation structure is the first distance, and the distance between the center line of the conductive part in the first direction and the isolation structure is the second distance. The difference between the first distance and the second distance can reduce the difficulty of aligning the second channel structure with the conductive part, and can reduce the difficulty of aligning the second channel structure with the first channel structure; the first distance can be greater than the second distance, so that the center line of the second channel structure is offset in the direction away from the isolation structure, the spacing distance between the second channel structure and the isolation structure is increased, and the isolation performance of the isolation structure to the two adjacent second channel structures on both sides is improved, the interference between the two adjacent second channel structures on both sides of the isolation structure is reduced, and the offset of the on-voltage and off-voltage of the two second channel structures is reduced, and the device stability is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figures 1 to 8 A schematic diagram of the structure of a three-dimensional memory shown in an embodiment of the present disclosure;

[0057] Fig. 9 A schematic diagram of a process flow of a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure;

[0058] Fig.10a and Fig.10b Schematic diagram of a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure Figure 1 ;

[0059] Figures 11a to 11c Schematic diagram of a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure Figure 2 ;

[0060] Fig.12a and Figure 12b Schematic diagram of a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure Figure 3 ;

[0061] Figures 13a to 13j Schematic diagram of a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure Figure 4 ;

[0062] Fig.14 A schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0063] Fig.15aA schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0064] Fig.15b A schematic diagram of an exemplary solid state drive having a memory system according to an embodiment of the present disclosure;

[0065] Fig.16a A schematic diagram of the distribution of storage units of a three-dimensional NAND memory according to an embodiment of the present disclosure;

[0066] Fig.16b A schematic diagram of an exemplary memory device including peripheral circuits according to an embodiment of the present disclosure;

[0067] Fig.17 FIG. 1 is a schematic diagram of an exemplary memory device including a memory cell array and a peripheral circuit according to an embodiment of the present disclosure.

[0068] In the above drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar components in different views. Similar reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation. DETAILED DESCRIPTION

[0069] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0070] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0071] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0072] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0073] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0074] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0075] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0076] Figures 1 to 5 FIG. 1 is a schematic diagram of the structure of a three-dimensional memory according to an embodiment of the present disclosure. Figures 1 to 5 As shown, the three-dimensional memory includes:

[0077] A stacked structure, the stacked structure includes alternately stacked gate layers 121 and first dielectric layers 122;

[0078] A first channel structure 110, the first channel structure 110 penetrates the stacked structure along a first direction; a conductive portion 117, located at one end of the first channel structure 110 in the first direction; and an insulating layer 123 and a selection gate layer 124 stacked in sequence on the conductive portion 117;

[0079] The second channel structure 142 penetrates the selection gate layer 124 and the insulating layer 123; the isolation structure 131 penetrates the selection gate layer 124; wherein, along the second direction perpendicular to the first direction, the isolation structure 131 is located between two adjacent second channel structures 142; the distance between the center line of the second channel structure 142 in the first direction and the isolation structure 131 is a first distance, and the distance between the center line of the conductive portion 117 in the first direction and the isolation structure 131 is a second distance; wherein the first distance is the same as or different from the second distance. Figure 1 The first distance shown is the same as the second distance, Figures 2 to 5 The first distance shown is different from the second distance, and the first distance may be greater than the second distance.

[0080] Exemplarily, the first direction may be the z direction in the drawings, which may be the thickness direction, and the first channel structure 110 and the second channel structure 142 extend in the z direction; the second direction may be the x direction in the drawings, which may be the radial direction of the first channel structure 110 . Figure 6 and Figure 7 The top view of the three-dimensional memory in the xoy plane is shown. The isolation structure 131 can be arranged in the x direction and extend in the y direction. The embodiment of the present disclosure does not limit the number and arrangement of the first channel structures 110, and does not limit the number and arrangement of the isolation structures 131. A conductive portion 117 is located between a first channel structure 110 and a second channel structure 142, and is used to couple the first channel structure 110 and the second channel structure 142.

[0081] In some embodiments, the first channel structure 110 includes:

[0082] The barrier layer 112, the storage layer 113, the tunnel layer 114 and the channel layer 115 are sequentially arranged along the second direction (x direction, or the radial direction of the first channel structure 110), and the barrier layer 112, the storage layer 113, the tunnel layer 114 and the channel layer 115 are arranged around the core 116; wherein the conductive portion 117 is coupled to the channel layer 115, the conductive portion 117 is coupled to the second channel structure 142, and the core 116 provides support for the first channel structure 110. The storage layer 113 is located between the barrier layer 112 and the tunnel layer 114, and the tunnel layer 114 is located between the storage layer 113 and the channel layer 115. The barrier layer 112 may include silicon oxide, silicon oxynitride, high dielectric or any combination thereof. The storage layer 113 may include silicon nitride, silicon oxynitride, silicon or any combination thereof. The tunnel layer 114 may include silicon oxide, silicon oxynitride or any combination thereof. In the embodiment of the present disclosure, the combination of the barrier layer 112, the storage layer 113, and the tunnel layer 114 is silicon oxide / silicon nitride / silicon oxide (ONO), and the channel layer 115 is a semiconductor material layer. The channel layer 115 may include polysilicon, which may be doped to improve channel conductivity. The second channel structure 142 may include a semiconductor material layer, which may include polysilicon, and the second channel structure 142 may be doped to improve channel conductivity.

[0083] The first channel structure 110 can be used as a storage device of a three-dimensional memory, as a storage column or storage string of the three-dimensional memory, and the storage layer 113 can be used to capture electrons of different electron quantities to achieve the purpose of storing data. The second channel structure 142 can be used as a channel of a selection transistor, and the selection gate layer 124 is used as a control gate of the selection transistor. The second channel structure 142 is turned on or off by applying different operating voltages through the selection gate layer 124 to control the turning on or off of the selection transistor, thereby controlling the selection or non-selection of the first channel structure 110. For the selected first channel structure 110, a read, program (write) or erase operation can be performed. Figure 1 The first channel structure 110 shown may include two sub-channel structures or more sub-channel structures stacked in the z direction, for example, a first sub-channel structure 111 and a second sub-channel structure 112, wherein the second sub-channel structure 112 is located between the first sub-channel structure 111 and the second channel structure 142. The first sub-channel layer of the first sub-channel structure 111 is coupled to the second sub-channel layer of the second sub-channel structure 112; the first sub-channel layer may be completely aligned with the second sub-channel layer, or may have an alignment offset.

[0084] In some embodiments, the three-dimensional memory further includes: a second dielectric layer 141, which penetrates the selection gate layer 124 and surrounds the second channel structure 142. There is a second dielectric layer 141 between the second channel structure 142 and the selection gate layer 124, which serves as a gate dielectric layer of the selection transistor. The second dielectric layer 141 penetrates the selection gate layer 124 and surrounds the second channel structure 142. The second dielectric layer 141 can penetrate the selection gate layer 124 and stop at the surface of the insulating layer 123. After penetrating the selection gate layer 124, the second dielectric layer 141 can extend into the insulating layer 123, or the second dielectric layer 141 can penetrate the selection gate layer 124 and the insulating layer 123 and stop at the surface of the conductive portion 117, so as to increase the manufacturing window of the second dielectric layer 141 and reduce the manufacturing difficulty. Exemplarily, the constituent materials of the first dielectric layer 122, the second dielectric layer 141 and the insulating layer 123 may include but are not limited to: insulating materials such as silicon oxide, silicon nitride, silicon oxynitride or aluminum oxide. The isolation structure 131 may only penetrate the selection gate layer 124 and stop at the surface of the insulating layer 123. The isolation structure 131 may also penetrate the selection gate layer 124 and then extend into the insulating layer 123 or penetrate the insulating layer 123 and stop at the surface of the stacked structure. The three-dimensional memory further includes a stop layer 125 located on the isolation structure 131. The stop layer 125 may include silicon nitride to protect the isolation structure 131 from being damaged by the manufacturing process such as etching. The second channel structure 142 also penetrates the stop layer 125.

[0085] The constituent materials of the gate layer 121, the selection gate layer 124 and the conductive part 117 may include, but are not limited to, conductive materials such as tungsten, gold, silver, copper, aluminum, nickel, chromium, titanium or polysilicon. The constituent material of the selection gate layer 124 may be the same as or different from that of the gate layer 121. Exemplarily, the gate layer 121 may include tungsten, and the selection gate layer 124 may include polysilicon, which may be doped to improve conductivity and voltage load. The conductive part 117, the channel layer 115 and the second channel structure 142 all include polysilicon to reduce the contact resistance caused by different materials, improve adhesion, and improve coupling performance.

[0086] In some embodiments, the three-dimensional memory further includes a common source 161 located on a side of the stacked structure away from the conductive portion 117, and coupled to the channel layer 115 of the plurality of first channel pillars. For example, the common source 161 may be located at Figures 1 to 5 The lower side of the stacking structure, as described later Figure 8As shown. Exemplarily, the constituent material of the common source 161 may include doped polysilicon or other doped semiconductor materials. The gate layer 121 may include an upper selection gate layer, which is located on a side of the stacked structure close to the conductive portion 117 and on a side of the stacked structure away from the common source 161. The gate layer 121 is not configured as an upper selection gate layer, and the gate layer 121 may be configured as a word line, or configured as a word line and a lower selection gate layer, the word line is located between the lower selection gate layer and the upper selection gate layer, and the lower selection gate layer is close to the common source 161. The word line may be configured to apply different operating voltages to control the read, write or erase operation of the memory cell. The lower selection gate layer may be configured to select or deselect the first channel structure 110, and may also be configured to form a gate induced drain leakage current with the common source 161 to perform an erase operation on the first channel structure 110. It can be understood that compared to the memory architecture in which one or more gate layers 121 of the stacked structure are configured as the upper selection gate layer, the selection gate layer 124 of the embodiment of the present disclosure does not occupy the number of gate layers 121. When the stacked structure has the same number of stacked layers, the embodiment of the present disclosure is beneficial to increasing the number of word line layers, increasing the number of storage unit layers, and improving the storage density of the three-dimensional memory.

[0087] The constituent materials of the isolation structure 131 include, but are not limited to, insulating materials such as silicon oxide, silicon nitride, silicon oxynitride or aluminum oxide. The isolation structure 131 penetrates the selection gate layer 124, and divides the selection gate layer 124 into a plurality of selection gate sublayers. A selection gate sublayer is arranged between two isolation structures 131, and an operating voltage can be applied independently to each selection gate sublayer. According to different array modes of the first channel structure 110 and the second channel structure 142, each selection gate sublayer can correspond to a plurality of second channel structures 142, and serve as control gates of the plurality of second channel structures 142. In some embodiments, the three-dimensional memory further includes a gate isolation structure penetrating the stacked structure, and the isolation structure 131 penetrating the selection gate layer 124 can be referred to as an upper selection gate isolation structure, and a selection gate sublayer can be arranged between the gate isolation structure and the upper selection gate isolation structure. Exemplarily, the gate isolation structure can divide the storage array into storage blocks, and the upper selection gate isolation structure further divides the storage blocks, which is conducive to refining the partition storage and fine control of the three-dimensional memory, and improving the operation rate and data stability of the three-dimensional memory.

[0088] Reference Figure 1As shown, the distance between the center line of the second channel structure 142 in the z direction and the isolation structure 131 is the first distance, and the distance between the center line of the conductive part 117 in the z direction and the isolation structure 131 is the second distance. Taking the first distance as an example, the first distance can be the distance between the center line of the second channel structure 142 in the z direction and the side wall of the isolation structure 131 close to the second channel structure 142. The definition of the second distance can refer to the first distance and will not be repeated. It should be pointed out that in some manufacturing embodiments of three-dimensional memory, the first channel structure 110, the conductive part 117 and the isolation structure 131 and other components can be manufactured first, the center line of the conductive part 117 can be determined, and the first distance can be determined; then the isolation structure 131 is used as a fixed reference, so that the second distance is different from the first distance (for example, the first distance is greater than the second distance), to set the second channel structure 142. The above-mentioned center line can be or is the symmetry axis of the corresponding component within a certain error range.

[0089] Figure 1 The first distance and the second distance shown are equal, or equal within a certain measurement error range, which indicates that the center line of the second channel structure 142 in the z direction coincides with the center line of the conductive portion 117 in the z direction. A center line AA′ is used to indicate the center lines of the second channel structure 142 and the conductive portion 117. Figure 1 The conductive portion 117 in the first channel structure 110 may be located within the top of the first channel structure 110, the shape of the conductive portion 117 may be the same as the shape of the top of the first channel structure 110, the center line of the conductive portion 117 may coincide with the center line of the first channel structure 110 in the z direction, and the center line AA' may be used to indicate the center line of the first channel structure 110. The first channel structure 110, the conductive portion 117, and the second channel structure 142 may be symmetrical along AA', or approximately symmetrical.

[0090] Figures 2 to 5 The first distance shown is different from the second distance and the center line is also different. The first distance can be Figure 2 The example D1 in the example indicates that the second distance can be Figure 2The example D2 indicates. The midline of the second channel structure 142 in the z direction is BB', and the midline of the conductive portion 117 in the z direction is CC'. The offset between BB' and CC' can reduce the difficulty of aligning the second channel structure 142 with the conductive portion 117. The first distance between BB' and the isolation structure 131 is greater than the second distance between CC' and the isolation structure 131, which can increase the distance between the second channel structure 142 and the isolation structure 131. Not shown in the figure, the first channel structure 110, the conductive portion 117 and the second channel structure 142 are also provided on one side (right side) of the isolation structure 131. Increasing the distance between the second channel structure 142 and the isolation structure 131 can increase the spacing distance between two adjacent second channels of the isolation structure 131, reduce the interference between the two adjacent second channel structures 142 on both sides of the isolation structure 131, reduce the offset between the on-voltage and off-voltage of the two second channel structures 142, and improve the stability of the device.

[0091] The present disclosure does not limit the number and arrangement of the first channel structures 110, nor does it limit the number and arrangement of the isolation structures 131. Figure 6 shows a top view of a three-dimensional memory in the xoy plane, Figure 6 1 shows a schematic diagram of an array of multiple conductive portions 117, one conductive portion 117 is coupled to one second channel structure 142. The shape of the conductive portion 117 can be the same as the shape of the second channel structure 142, and the size of the conductive portion 117 in the x direction is less than or equal to the size of the first channel structure 110 in the x direction. Figure 1 When the first distance between the midline of the second channel in the z direction and the isolation structure 131 is equal to the second distance between the midline of the second channel in the z direction and the isolation structure 131, it corresponds to Figure 6 The geometric center of the cross section (or projection plane) of the second channel structure 142 and the conductive portion 117 in the xoy plane coincides. For example, the cross section of the second channel structure 142 and the conductive portion 117 in the xoy plane may include a circular shape, an elliptical shape, or the like.

[0092] In some embodiments, the first distance is greater than the second distance.

[0093] In some embodiments, a first distance between the second channel structure 142 and the isolation structure 131 is greater than a second distance between the conductive portion 117 and the isolation structure 131 .

[0094] In some embodiments, Figure 7 shows a top view of another three-dimensional memory in the xoy plane, Figure 7 FIG. 1 shows a schematic diagram of an array of a plurality of conductive portions 117, wherein one conductive portion 117 is coupled to one second channel structure 142. Figures 2 to 5The first distance between the midline of the second channel structure 142 in the z direction and the isolation structure 131 is not equal to the second distance between the midline of the conductive portion 117 in the z direction and the isolation structure 131, and the first distance is greater than the second distance, corresponding to Figure 7 There is an offset between the geometric center of the cross section of the second channel structure 142 and the conductive portion 117 in the xoy plane. When the first distance is different from the second distance, the difficulty of aligning the second channel structure 142 and the conductive portion 117 can be reduced. The first distance of the second channel structure 142 adjacent to the isolation structure 131 is greater than the second distance of the conductive portion 117 adjacent to the isolation structure 131, that is, the second channel structure 142 adjacent to the isolation structure 131 is offset in a direction away from the isolation structure 131, thereby increasing the spacing distance between the two adjacent second channel structures 142 of the isolation structure 131, reducing the interference between the two adjacent second channel structures 142 on both sides of the isolation structure 131, reducing the offset of the on-voltage and off-voltage of the two second channel structures 142, and improving the stability of the device.

[0095] In some embodiments, for the array-arranged first channel structures 110, a plurality of conductive portions 117 are arranged in an array. For example, a plurality of rows of first channel structures 110 may be arranged between two isolation structures 131, and a plurality of rows of second channel structures 142 may be arranged correspondingly. Figure 7 In the example shown, four rows of second channel structures 142 arranged along the y direction are included between the two isolation structures 131, and each row of second channel structures 142 may include multiple second channel structures 142 arranged along the y direction; the midlines of a row or two rows of second channel structures 142 adjacent to the isolation structure 131 in the z direction are offset away from the isolation structure 131 compared to their corresponding conductive portions 117, so as to increase the spacing distance between two adjacent rows of second channel structures 142 of the isolation structure 131, reduce the interference between two adjacent rows of second channel structures 142 on both sides of the isolation structure 131, reduce the offset of the on-voltage and off-voltage of the two rows of second channel structures 142, and improve the device stability.

[0096] In some embodiments, for other second channel structures 142 that are not adjacent to the isolation structure 131, their first distance may be equal to or unequal to the second distance of the conductive portion 117. Generally, the number of rows of the second channel structures 142 between two isolation structures 131 may be an even number to adapt to the binary algorithm of the host, and the total number of rows may be evenly divided into two parts, and the part close to the isolation structure 131 belongs to the multiple rows of second channel structures 142 adjacent to the isolation structure 131. For odd rows, the first distance of the remaining row of second channel structures 142 that cannot be evenly divided may be equal to or unequal to the second distance of the conductive portion 117. For example Figure 7There are 4 rows of second channel structures 142 between two isolation structures 131, the first distance of the two rows of second channel structures 142 close to one isolation structure 131 is greater than the second distance of the corresponding conductive portion 117, and the first distance of the other two rows of second channel structures 142 close to the other isolation structure 131 is greater than the second distance of the corresponding conductive portion 117. In some other embodiments, except that the first distance of the two rows of second channel structures 142 adjacent to the isolation structure 131 is greater than the second distance of the corresponding conductive portion 117, the first distance of the other second channel structures 142 non-adjacent to the isolation structure 131 is equal to the second distance of the conductive portion 117. In some other embodiments, there are more rows of second channel structures 142 between the two isolation structures 131, and the 1st, 2nd, or 3rd rows of second channel structures 142 closest to the isolation structure 131 can be regarded as the second channel structures 142 adjacent to the isolation structure 131, and the first distance of the second channel structures 142 is greater than the second distance of the conductive portion 117.

[0097] In some embodiments, reference Figure 6 and Figure 7 As shown, the isolation structure 131 includes an arc structure; wherein the arc structure faces the second channel structure 142 adjacent to the isolation structure 131 and surrounds part of the side wall of the second channel structure 142 adjacent to the isolation structure 131, which is beneficial to improving the integration density of the second channel structure 142 and the first channel structure 110.

[0098] In some embodiments, in addition to using the center line of the conductive portion 117 in the z direction and the size of the isolation structure 131 in the z direction as a comparison reference, the first channel structure 110 can also be used as a comparison reference. For example, the distance between the center line of the first channel structure 110 in the z direction and the isolation structure 131 is the third distance, and the distance between the center line of the second channel structure 142 in the z direction is the first distance, and the first distance may be different from the third distance. Under the premise of achieving coupling between the second channel structure 142 and the conductive portion 117, the first distance may be greater than the third distance to increase the spacing distance between two adjacent second channel structures 142 of the isolation structure 131, reduce interference between two adjacent second channel structures 142 on both sides of the isolation structure 131, reduce the offset of the on-voltage and off-voltage of the two second channel structures 142, and improve device stability. It should be noted that this embodiment may include a plurality of isolation structures 131 and a plurality of first channel structures 110 and second channel structures 142. When the first distance is greater than the third distance, the array pattern of the first channel structure 110 between the two isolation structures 131 may be similar to Figure 7As shown, at this time, the size of the top of the first channel structure 110 in the x direction is equal to the size of the conductive portion 117 in the x direction, and the projection of the conductive portion 117 on the xoy plane coincides with the projection of the first channel structure 110 on the xoy plane.

[0099] In some embodiments, the size of the second channel structure 142 in the second direction (x direction) is smaller than the size of the conductive portion 117 in the second direction, which facilitates the alignment of the second channel structure 142 and the conductive portion 117, increases the spacing between adjacent second channel structures 142, and reduces mutual interference.

[0100] In some embodiments, the orthographic projection of the second channel structure 142 in the first direction (z direction) falls within the orthographic projection of the conductive portion 117 in the z direction. This improves the alignment of the second channel structure 142 and the conductive portion 117, increases the contact area between the second channel structure 142 and the conductive portion 117, and improves coupling performance.

[0101] The conductive portion 117 may be located between the first channel structure 110 and the second channel structure 142 , may be located outside the first channel structure 110 , or may be located inside the first channel structure 110 .

[0102] In some embodiments, reference Figure 2 As shown, the conductive portion 117 is located outside the first channel structure 110, and the conductive portion 117 is located at one end of the first channel structure 110 close to the second channel structure 142; one end of the conductive portion 117 in the z direction is coupled to the channel layer 115, and the other end is coupled to the second channel structure 142. The conductive portion 117 may be located outside the first channel structure 110, and the size of the conductive portion 117 in the x direction may be the same as the size of the first channel structure 110 in the x direction.

[0103] In some embodiments, reference Figures 3 to 5 As shown, the conductive portion 117 may be within the first channel structure 110 , and a dimension of the conductive portion 117 in the x-direction is smaller than a dimension of the first channel structure 110 in the x-direction.

[0104] In some embodiments, reference Figure 3As shown, the conductive portion 117 is located in the first channel structure 110, the conductive portion 117 is surrounded by the channel layer 115, and the sidewall of the conductive portion 117 in the x direction is in contact with the channel layer 115. In the z direction, the surface of the conductive portion 117 close to the second channel structure 142, the surface of the channel layer 115 close to the second channel structure 142, the surface of the tunneling layer 114 close to the second channel structure 142, the surface of the storage layer 113 close to the second channel structure 142, and the surface of the barrier layer 112 close to the second channel structure 142 may be flush, and the sidewall of the conductive portion 117 in the x direction is in contact and coupled with the side surface of the channel layer 115 in the x direction, thereby increasing the contact area and improving the coupling performance.

[0105] In some embodiments, reference Figure 4 As shown, the conductive portion 117 is located in the first channel structure 110, the barrier layer 112 surrounds the conductive portion 117, and the conductive portion 117 at least covers the channel layer 115 in the first direction. In the z direction, the surface of the conductive portion 117 close to the second channel structure 142 may be flush with the surface of the barrier layer 112 close to the second channel structure 142, and the conductive portion 117 covers the storage layer 113, the tunneling layer 114, and the channel layer 115 in the first direction. The surface of the conductive portion 117 away from the second channel structure 142 contacts the surface of the storage layer 113 close to the second channel structure 142, contacts the surface of the tunneling layer 114 close to the second channel structure 142, and contacts and couples with the surface of the channel layer 115 close to the second channel structure 142. The sidewall of the conductive portion 117 in the x direction contacts the surface of the barrier layer 112 in the x direction.

[0106] In some embodiments, reference Figure 5 As shown, in the z direction, the conductive portion 117 includes: an extension portion extending from a side surface of the channel layer 115 close to the selection gate layer 124 away from the selection gate layer 124, and the extension portion is surrounded by the channel layer 115. The cross-sectional (or projection) shape of the conductive portion 117 in the xoz plane may include a T-shape, and the conductive portion 117 includes three surfaces extending along a plane perpendicular to the z direction in the z direction; wherein, the surface closest to the second channel structure 142 is flush with the surface of the blocking layer 112 close to the second channel structure 142 in the z direction, the surface farthest from the second channel structure 142 extends away from the second channel structure 142 toward the core 116, and the middle surface covers the storage layer 113, the tunneling layer 114 and the channel layer 115 in the z direction. For ease of explanation, in Figure 5The dotted line perpendicular to the z direction is shown in the figure to divide the extension part and other parts of the conductive part 117. The sidewall of the extension part in the x direction is in contact and coupled with the channel layer 115 in the x direction. The other part of the conductive part 117 is in contact and coupled with the channel layer 115 in the z direction, and covers the storage layer 113, the tunneling layer 114 and the channel layer 115 in the z direction. It should be pointed out that in the actual physical device of the conductive part 117, the conductive part 117 is a whole, and there is no dividing line between the extension part and other parts shown in the figure.

[0107] In some embodiments, reference Figure 8 As shown, the three-dimensional memory device further includes a common source 161 located on a side of the first channel structure 110 away from the second channel structure 142, and the common source 161 is coupled to the channel layers 115 of the plurality of first channel structures 110. The common source 161 may be a semiconductor layer, and the semiconductor layer may include polysilicon, or the semiconductor layer may be doped. At one end of the first channel structure 110 away from the second channel structure 142, the barrier layer 112, the storage layer 113, and the tunneling layer 114 expose the channel layer 115, or the channel layer 115 penetrates the barrier layer 112, the storage layer 113, and the tunneling layer 114 and extends toward the common source 161, and is in contact with and coupled to the common source 161. In some other embodiments, the three-dimensional memory further includes a first terminal 162, located on a side of the semiconductor layer away from the first channel structure 110, and coupled to the semiconductor layer to supply power to the common source 161. The first terminal 162 may be a multi-layer conductive structure, including but not limited to a conductive plug, a conductive pad, and other structures.

[0108] In some embodiments, reference Figure 8 As shown, the three-dimensional memory further includes a peripheral circuit 190, which is located on a side of the second channel structure 142 away from the first channel structure 110. The peripheral circuit 190 may include circuits such as logic control, voltage generator, word line driver, and bit line driver to control the read, write, or erase operation of the first channel structure 110. A bit line 128 is further provided between the peripheral circuit 190 and the second channel structure 142, and a conductive plug 127 is provided between the bit lines 128, one end of the conductive plug 127 is coupled to the bit line 128, and the other end is coupled to the second channel structure 142. The conductive plug 127 may include a plurality of stacked sub-conductive plugs.

[0109] In some embodiments, reference Figure 8 As shown, components such as the first channel structure 110, the conductive portion 117, the second channel structure 142 and the bit line 128 may be located in the first semiconductor structure, the peripheral circuit 190 may be located in the second semiconductor structure, and the first semiconductor structure and the second semiconductor structure may be bonded and connected via a bonding layer including a plurality of bonding contacts 163, and electrical signals may be interconnected via the bonding contacts 163.

[0110] According to some aspects of the embodiments of the present disclosure, Fig. 9 A schematic flow chart of a method for manufacturing a three-dimensional memory is provided, the method comprising:

[0111] forming a stacked structure, the stacked structure comprising alternately stacked sacrificial layers and first dielectric layers;

[0112] forming a first channel structure penetrating the stacked structure along a first direction;

[0113] forming a conductive portion at one end of the first channel structure along the first direction;

[0114] forming an insulating layer and a selection gate layer in sequence on the conductive portion;

[0115] forming an isolation structure penetrating the selection gate layer;

[0116] A first opening is formed that penetrates the selection gate layer and the insulating layer, and a second channel structure is formed in the first opening; wherein, along a second direction perpendicular to the first direction, the isolation structure is located between two adjacent second channel structures; a distance between a center line of the second channel structure in the first direction and the isolation structure is a first distance, and a distance between a center line of the conductive portion in the first direction and the isolation structure is a second distance; wherein the first distance is different from the second distance;

[0117] The sacrificial layer is replaced with a conductive material to form a gate layer. The first direction may include a z-direction, and the second direction may include an x-direction.

[0118] Specifically, refer to Fig.10a As shown, the sacrificial layer 126 and the first dielectric layer 122 are alternately stacked to form a stacked structure, and the constituent material of the first dielectric layer 122 is different from the constituent material of the sacrificial layer 126, so that the sacrificial layer 126 can be removed and replaced with the gate layer 121. For example, the sacrificial layer 126 may include silicon nitride or silicon, and the first dielectric layer 122 may include silicon oxide. Exemplarily, the process of forming the sacrificial layer 126 and the first dielectric layer 122 may include, but is not limited to: chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) or atomic layer deposition (ALD).

[0119] In some embodiments, a method of forming the first channel structure 110 includes:

[0120] A channel hole is formed penetrating the stacked structure, in which the following are formed in sequence: a barrier layer 112 , a storage layer 113 , a tunneling layer 114 , a channel layer 115 and a core portion 116 ; a conductive portion 117 formed subsequently is coupled to the channel layer 115 , and the conductive portion 117 is coupled to the second channel structure 142 .

[0121] In some embodiments, a method of forming the conductive portion 117 includes:

[0122] In the formation Fig.10a After the first channel structure 110 is formed, a conductive portion 117 is formed at one end of the first channel structure 110 in the z direction, and an insulating layer 123 and a selection gate layer 124 are sequentially formed on the side of the conductive portion 117 away from the first channel structure 110 to obtain Fig.10b The device structure shown in FIG. 1 is a conductive portion 117 located outside the first channel structure 110. For example, the method of forming the channel hole may include but is not limited to: dry etching, wet etching, or any combination thereof.

[0123] Reference Fig.10a As shown, the first channel structure 110 may include two sub-channel structures stacked in the z direction, for example, a first sub-channel structure 111 and a second sub-channel structure 112. Fig.10b As shown, at one end of the second sub-channel structure 112, that is, at Fig.10a A conductive portion 117 is formed at the top of the second sub-channel structure 112 in the positive z direction, and the second sub-channel structure 112 is located between the first sub-channel structure 111 and the formed conductive portion 117. The first sub-channel layer of the first sub-channel structure 111 is coupled to the second sub-channel layer of the second sub-channel structure 112. Due to the etching load effect, when etching the stacked structure to form a channel hole, the aperture of the top of the channel hole is larger than the aperture of the bottom of the channel hole; the size of one end of the sub-channel structure in the x direction is larger than the size of the other end in the x direction, so that Fig.10a The size of the bottom of the second sub-channel structure 112 in the x-direction is smaller than the size of the first sub-channel structure 111 in the x-direction. The first sub-channel layer and the second sub-channel layer may have an alignment offset due to the size difference.

[0124] Reference Fig.10bAs shown, after the first channel structure 110 is formed, a dielectric material layer is formed on the first channel structure 110, the dielectric material layer is etched to form a groove, and the groove is filled with a conductive material to form a conductive portion 117, and the conductive portion 117 is located outside the first channel structure 110. The size of the conductive portion 117 in the x-direction may be less than or equal to the size of the end of the first channel structure 110 close to the conductive portion 117 in the x-direction. An insulating layer 123 and a selection gate layer 124 are sequentially formed on the conductive portion 117. In some embodiments, the insulating layer 123 and the dielectric material layer are made of the same material, and there is no physical boundary between the insulating layer 123 and the dielectric material layer, or there is no obvious physical boundary, and they can be regarded as a membrane structure. Fig.10b Based on the structure shown in FIG. 1 , an isolation structure 131 is formed to penetrate the selection gate layer 124, a first opening 155 is formed to penetrate the selection gate layer 124 and the insulating layer 123, a second dielectric layer 141 is formed on the sidewall of the first opening 155, and a remaining space of the first opening 155 with the second dielectric layer 141 is filled to form a second channel structure 142, and a Figure 2 The conductive portion 117 is located outside the first channel structure 110 , with one end coupled to the channel layer 115 of the first channel structure 110 and the other end coupled to the second channel structure 142 . In some other embodiments, the conductive portion 117 may be formed inside the first channel structure 110 .

[0125] In some embodiments, the manufacturing method further comprises:

[0126] Before forming the insulating layer 123 , the core portion 116 at one end of the first channel structure 110 is etched to form a first opening 151 .

[0127] Reference Fig.11a As shown, during the process of forming the first channel structure 110, the barrier layer 112, the storage layer 113, the tunnel layer 114 and the channel layer 115 are formed to cover the surface of the stacked structure, and the barrier layer 112, the storage layer 113 and the channel layer 115 on the stacked structure can be removed by etching or mechanical chemical grinding process. Fig.11a In the process, the core portion 116 at one end of the first channel structure 110 is etched to form an opening, and then the barrier layer 112, the storage layer 113 and the channel layer 115 on the stacked structure are removed to form Fig.11b The first opening 151 is shown. Alternatively, the barrier layer 112, the storage layer 113, the tunnel layer 114 and the channel layer 115 on the surface of the stacked structure may be removed first, and then the core portion 116 may be etched to form Fig.11b The first opening 151 is shown. The sidewall of the first opening 151 exposes the channel layer 115 .

[0128] In some embodiments, a method of forming the conductive portion 117 includes:

[0129] Reference Fig.11c As shown, a conductive portion 117 is formed in the first opening 151; wherein the conductive portion 117 is surrounded by the channel layer 115, and the sidewall of the conductive portion 117 in the x direction is in contact with the channel layer 115. Fig.11c An insulating layer 123 and a selection gate layer 124 are sequentially formed on the conductive portion 117 of the embodiment of the present invention, an isolation structure 131 penetrating the selection gate layer 124 is formed, a first opening 155 penetrating the selection gate layer 124 and the insulating layer 123 is formed, a second dielectric layer 141 is formed on the sidewall of the first opening 155, and a remaining space of the first opening 155 with the second dielectric layer 141 is filled to form a second channel structure 142, and a second dielectric layer 141 is formed on the sidewall of the first opening 155. Figure 3 The device structure shown.

[0130] In some embodiments, a method of forming the conductive portion 117 includes:

[0131] At least etching Fig.11b The channel layer 115 shown in FIG. 1 expands the size of the first opening 151 in the x direction to form a second opening 152; Fig.12a As shown, the tunneling layer 114 is exposed at the sidewall of the second opening 152 , and the channel layer 115 is exposed at the bottom of the second opening 152 .

[0132] Reference Figure 12b As shown, a conductive portion 117 is formed in the second opening 152, wherein the barrier layer 112 surrounds the conductive portion 117, and the conductive portion 117 at least covers the channel layer 115 in the x direction. The sidewall of the conductive portion 117 in the x direction contacts the surface of the barrier layer 112 in the x direction, and the conductive portion 117 covers the channel layer 115 near the surface of the first channel structure 110 in the z direction and is in contact and coupled with the channel layer 115.

[0133] exist Figure 12b An insulating layer 123 and a selection gate layer 124 are sequentially formed on the conductive portion 117 of the embodiment of the present invention, an isolation structure 131 penetrating the selection gate layer 124 is formed, a first opening 155 penetrating the selection gate layer 124 and the insulating layer 123 is formed, a second dielectric layer 141 is formed on the sidewall of the first opening 155, and a remaining space of the first opening 155 with the second dielectric layer 141 is filled to form a second channel structure 142, and a second dielectric layer 141 is formed on the sidewall of the first opening 155. Figure 4 The device structure shown.

[0134] In some embodiments, a method of forming the conductive portion 117 includes:

[0135] The core portion 116 exposed from the first opening 151 is also etched to enlarge the size of the first opening 151 in the first direction;

[0136] In the first direction, the formed conductive portion 117 further includes an extending portion extending toward the core portion 116 , and the extending portion is surrounded by the channel layer 115 .

[0137] Etching Fig.11b After the first opening 151 is formed in the channel layer 115 shown in the figure, the core portion 116 exposed from the first opening 151 is further etched to expand the size of the first opening 151 in the z direction; Fig.13a The third opening 153 shown in FIG. Fig.13b The conductive portion 117 is shown;

[0138] In the z direction, Fig.13b The formed conductive portion 117 further includes: an extension portion extending toward the core portion 116, and the extension portion is surrounded by the channel layer 115. The cross-sectional shape (or projection) of the conductive portion 117 in the xoz plane may include a T-shape. Fig.13b The dotted line perpendicular to the z direction is used to divide the extension part and other parts of the conductive part 117. The sidewall of the extension part in the x direction is in contact and coupled with the channel layer 115 in the x direction, and the other part of the conductive part 117 is in contact and coupled with the channel layer 115 in the z direction. It should be pointed out that in the actual physical device of the conductive part 117, the conductive part 117 is a whole, and there is no dividing line between the extension part and other parts shown in the figure.

[0139] exist Fig.13b An insulating layer 123 and a selection gate layer 124 are sequentially formed on the conductive portion 117 of the embodiment of the present invention, an isolation structure 131 penetrating the selection gate layer 124 is formed, a first opening 155 penetrating the selection gate layer 124 and the insulating layer 123 is formed, a second dielectric layer 141 is formed on the sidewall of the first opening 155, and a remaining space of the first opening 155 with the second dielectric layer 141 is filled to form a second channel structure 142, and a second dielectric layer 141 is formed on the sidewall of the first opening 155. Figure 5 The device structure shown.

[0140] Taking the structure shown in FIG13 b as an example, the method for manufacturing the second channel structure 142 and the isolation structure 131 is specifically described. Fig.13c As shown, an insulating layer 123 and a selection gate layer 124 are sequentially formed on the conductive portion 117; Fig.13d As shown, a groove 154 is formed through the selection gate layer 124. The groove 154 can extend in a direction perpendicular to the plane xoz. The groove 154 can stop at the surface of the insulating layer 123, or extend into the insulating layer 123 or even penetrate the insulating layer 123; refer to Fig.13e As shown, the trench 154 is filled with a dielectric material to form an isolation structure 131 .

[0141] Reference Fig.13fAs shown, a stop layer 125 is formed on the selection gate layer 124, and the selection gate layer 124 is etched using the patterned stop layer 125 as an etching mask to form a first opening 155 that penetrates the selection gate layer 124 and the insulating layer 123 and exposes the conductive portion 117. The constituent material of the stop layer 125 is different from that of the isolation structure 131, so as to protect the isolation structure 131 from being damaged by etching. Exemplarily, the stop layer 125 may include silicon nitride, and the isolation structure 131 may include silicon oxide.

[0142] In some embodiments, the manufacturing method further comprises:

[0143] Before forming the second channel structure 142 , a second dielectric layer 141 is formed on the sidewall of the first opening 155 ; the second dielectric layer 141 surrounds the second channel structure 142 .

[0144] exist Fig.13f The second dielectric layer 141 is formed on the sidewall of the first opening 155, and the remaining space of the first opening 155 with the second dielectric layer 141 is filled to form Fig.13h A second channel structure 142 is shown.

[0145] In some embodiments, the first distance is greater than the second distance.

[0146] In some embodiments, a first distance between the second channel structure 142 and the isolation structure 131 is greater than a second distance between the conductive portion 117 and the isolation structure 131. Figures 2 to 5 As shown, the distance between the middle line of the second channel structure 142 in the z direction and the isolation structure 131 is a first distance, and the distance between the middle line of the conductive portion 117 in the z direction and the isolation structure 131 is a second distance, and the first distance and the second distance may be different to reduce the difficulty of aligning the second channel structure 142 with the conductive portion 117. The first distance may be greater than the second distance, and the second channel structure 142 adjacent to the isolation structure 131 is offset in a direction away from the isolation structure 131, thereby increasing the spacing distance between the two second channel structures 142 adjacent to the isolation structure 131, reducing the interference between the two second channel structures 142 adjacent to the isolation structure 131, reducing the offset of the on-voltage and off-voltage of the two second channel structures 142, and improving the stability of the device.

[0147] In some embodiments, the size of the second channel structure 142 in the x direction is smaller than the size of the conductive portion 117 in the x direction, which facilitates the alignment of the second channel structure 142 and the conductive portion 117, increases the spacing distance between adjacent second channel structures 142, and reduces mutual interference.

[0148] In some embodiments, the orthographic projection of the second channel structure 142 in the z direction falls within the orthographic projection of the conductive portion 117 in the z direction, thereby improving the alignment of the second channel structure 142 and the conductive portion 117, increasing the contact area between the second channel structure 142 and the conductive portion 117, and improving the coupling performance.

[0149] In some embodiments, reference Fig.13i As shown, the sacrificial layer 126 is etched away, and the gap generated after removing the sacrificial layer 126 is filled with a conductive material to form a gate layer 121 between two adjacent first dielectric layers 122. A conductive plug 127 and a bit line 128 are sequentially formed on the side of the second channel structure 142 away from the first channel structure 110, one end of the conductive plug 127 is coupled to the bit line 128, and the other end is coupled to the second channel structure 142. The conductive plug 127 may include a plurality of stacked sub-conductive plugs. Other conductive plugs or conductive lines and other interconnection structures are formed on the side of the bit line 128 away from the second channel structure 142. The embodiment of the present disclosure does not limit the number of layers and arrangement of the interconnection structure. The conductive plug extends along the z direction, and the conductive line (or bit line 128) extends in a direction perpendicular to the z direction.

[0150] Reference Fig.13j As shown, the first channel structure 110 is etched away from the end of the second channel structure 142, and a portion of the blocking layer 112, a portion of the storage layer 113, and a portion of the tunneling layer 114 are removed to expose the channel layer 115; a semiconductor layer covering the channel layer 115 is formed, and the channel layer 115 extends into the semiconductor layer, and the semiconductor layer can be doped. Figure 8 As shown, the common source 161 is coupled to the channel layer 115 .

[0151] In some embodiments, the manufacturing method further comprises: referring to Figure 8 As shown, a peripheral circuit 190 is formed on a side of the second channel structure 142 away from the first channel structure 110. The peripheral circuit 190 may include circuits such as logic control, voltage generator, word line driver, bit line 128 driver, etc., to control the read, write or erase operation of the first channel structure 110.

[0152] In some embodiments, reference Figure 8 As shown, the first channel structure 110, the conductive portion 117, the second channel structure 142, the bit line 128 and other components may be located in the first semiconductor structure, the peripheral circuit 190 may be located in the second semiconductor structure, the first semiconductor structure and the second semiconductor structure may be bonded and connected through a bonding layer including a plurality of bonding contacts 163, and electrical signals are interconnected through the bonding contacts 163. The bonding process may include hybrid bonding, the bonding layer includes the bonding contacts 163 and the dielectric layer, the dielectric layer bonding increases the bonding area and improves the bonding force, and the bonding contacts 163 are coupled to provide electrical signal interaction.

[0153] According to some aspects of the embodiments of the present disclosure, there is provided a memory system, including:

[0154] a memory device comprising one or more three-dimensional memories; and

[0155] A memory controller is coupled to the memory device and controls the memory device. The three-dimensional memory may include Figures 1 to 5 , Figure 8 The three-dimensional memory structure shown.

[0156] The memory device in the embodiments of the present disclosure includes but is not limited to a three-dimensional NAND memory. For ease of understanding, a three-dimensional NAND memory is taken as an example for description.

[0157] Fig.14 A block diagram of an exemplary system 100 having a memory device according to some aspects of the present disclosure is shown. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. Fig.14 As shown in , system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 may be configured to send data to the memory device 104 or receive data from the memory device 104.

[0158] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108, and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment SSD or embedded multimedia card (eMMC), which is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0159] The memory controller 106 may be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory device 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with an external device (e.g., a host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI Express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer mini interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, Firewire protocol, etc.

[0160] The memory controller 106 and the one or more memory devices 104 may be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 102 may be implemented and packaged into different types of terminal electronic products. Fig.15a In one example shown in , the memory controller 106 and the single memory device 104 can be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a processor that connects the memory card 202 to a host (e.g., Fig.14 The memory card connector 204 is coupled to the host 108 in the embodiment. Fig.15b In another example shown in , the memory controller 106 and the plurality of memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include a processor that interfaces the SSD 206 with a host (e.g., Fig.14 In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0161] Fig.16a A schematic diagram of the structure of a storage cell array of a three-dimensional NAND memory is given as an example. Fig.16a As shown, the memory cell array of the three-dimensional NAND memory is composed of several parallel and staggered rows of memory cell rows parallel to the gate isolation structure, every two rows of memory cell rows are separated by the gate isolation structure and the upper selection gate isolation structure, and each memory cell row includes a plurality of memory cells. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure, the first gate isolation structure divides the memory cell array into a plurality of memory blocks (expressed in English as Blocks), the plurality of second gate isolation structures may divide the memory blocks into a plurality of finger storage areas (expressed in English as Finger), and the upper selection gate isolation structure provided in the middle of each finger storage area may divide the finger storage area into two parts, thereby dividing the finger storage area into two memory slices. Fig.16a The memory block shown in FIG. 1 includes 6 memory cells. In practical applications, the number of memory cells in a memory block is not limited thereto. The memory cells in a memory block coupled to a certain word line can be called a memory page (expressed in English as Page).

[0162] It should be noted that Fig.16a The number of memory cell rows between the gate isolation structure and the upper selection gate isolation structure given in the disclosure is only an exemplary demonstration and is not used to limit the number of memory cell rows contained in a finger storage area of ​​the three-dimensional NAND memory in the present disclosure. In actual applications, the number of memory cell rows contained in a finger storage area can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0163] Fig.16b 1 is a schematic circuit diagram of an exemplary memory device 300 including peripheral circuits according to some aspects of the present disclosure. The memory device 300 may be Fig.14 300 is an example of a memory device 104 in FIG. The memory device 300 may include a memory cell array 301 and a peripheral circuit 302 coupled to the memory cell array 301. The memory cell array 301 is taken as a three-dimensional NAND-type memory cell array for illustration, wherein the memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0164] In some embodiments, each memory cell 306 is a single-level cell (SLC) having two possible memory states and can therefore store one bit of data. For example, a first memory state "0" can correspond to a first voltage range, and a second memory state "1" can correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC can store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed by writing one of three possible nominal storage values ​​to the cell, and a fourth nominal storage value in addition to the three nominal storage values ​​can be used to represent an erased state.

[0165] like Fig.16b As shown in , each NAND memory string 308 may include a lower select gate (BSG) 310 at its source terminal and an upper select gate (TSG) 312 at its drain terminal. BSG 310 and TSG 312 may be configured to activate a selected NAND memory string 308 during read and program operations. In some embodiments, the sources of the NAND memory strings 308 in the same memory block 304 are coupled by the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each NAND memory string 308 is coupled to a corresponding bit line (BL) 316, and data can be read from or written to the bit line 316 via an output bus (not shown). In some embodiments, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of a transistor having TSG 312) or a deselect voltage (e.g., 0 V) ​​to a corresponding TSG 312 via one or more TSG lines 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of a transistor having BSG 310) or a deselect voltage (e.g., 0 V) ​​to a corresponding BSG 310 via one or more BSG lines 315.

[0166] like Fig.16bAs shown in , the NAND memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for an erase operation, that is, all memory cells 306 on the same memory block 304 are erased at the same time. In order to erase the memory cells 306 in the selected memory block 304a, the source lines 314 coupled to the selected memory block 304a and the unselected memory blocks 304b in the same plane as the selected memory block 304a can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, the erase operation can be performed at the half-memory block level, at the quarter-memory block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 306 of adjacent NAND memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, in combination with the above Fig.16a , a plurality of memory cells are isolated by an upper selection gate isolation structure and a gate isolation structure, and a plurality of memory cells between the upper selection gate isolation structure and the gate isolation structure are arranged into a plurality of memory cell rows, and each memory cell row is parallel to the gate isolation structure and the upper selection gate isolation structure. The memory cells in the memory slices sharing the same word line form a physical page 320. Each physical page 320 can be mapped to at least one logical page according to the storage mode of the corresponding memory cell 306 (for example, SLC or MLC as mentioned above), and the logical page can constitute the basic data unit of the programming operation and the reading operation. The word line 318 may include Figures 1 to 5 , Figure 8 The gate layer 121. The bit line 316 may include Figure 8 The bit line 128 is shown. The upper select gate (TSG) 312 may include Figures 1 to 5 , Figure 8 The select gate layer 124 is shown. The upper select gate isolation structure may include Figures 1 to 5 , Figure 8 An isolation structure 131 is shown.

[0167] In some embodiments, the NAND memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with (one or more) semiconductor materials (e.g., as a semiconductor channel) and (one or more) dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a column shape). According to some embodiments, the semiconductor channel, the tunneling layer, the storage layer, and the barrier layer are arranged radially from the center of the column toward the outer surface of the column in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0168] Return to reference Fig.16b , the peripheral circuit 302 may be coupled to the memory cell array 301 through the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 301 by applying a voltage signal and / or a current signal to each target memory cell 306 and sensing a voltage signal and / or a current signal from each target memory cell 306 via the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Fig.17 Some exemplary peripheral circuits are shown, and the peripheral circuit 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, it may also include Fig.17 The memory cell array 301 may include additional peripheral circuits not shown. Figures 1 to 5 , Figure 8 The three-dimensional memory structure shown includes at least a portion of the first channel structure 110 and the second channel structure 142, and the peripheral circuit 302 may include Figure 8 The peripheral circuit 190 shown in FIG.

[0169] The page buffer / sense amplifier 504 may be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to a control signal from the control logic 512. In one example, the page buffer / sense amplifier 504 may store a page of programming data (write data) to be programmed into one memory page 320 of the memory cell array 301. In another example, the page buffer / sense amplifier 504 may perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 may also sense a low-power signal from the bit line 316 representing a data bit stored in the memory cell 306, and amplify a small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 506 may be configured to be controlled by the control logic 512, and select one or more NAND memory strings 308 by applying a bit line voltage generated from the voltage generator 510.

[0170] The row decoder / word line driver 508 may be configured to be controlled by the control logic 512 and select / deselect the memory block 304 of the memory cell array 301 and select / deselect the word line 318 of the memory block 304. The row decoder / word line driver 508 may also be configured to drive the word line 318 using the word line voltage generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 may also select / deselect and drive the BSG line 315 and the TSG line 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cell 306 coupled to the (one or more) selected word lines 318. The voltage generator 510 may be configured to be controlled by the control logic 512 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a channel boosting voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory cell array 301.

[0171] In some specific embodiments, the programming operation may include multiple stages. For example, the programming operation may include a channel precharge stage, a channel boosting stage, a programming pulse stage, and a recovery stage. In the channel precharge stage, the voltage generator may generate the voltage required for the next stage, such as the voltage applied to each gate, the channel boosting voltage, etc.; in the channel boosting stage, the channel boosting voltage may be applied to the selected word line; in the programming pulse stage, the target voltage for each programming may be applied to the selected word line. In the recovery stage, the voltage of both the unselected word line and the selected word line may be reduced to the corresponding voltage, such as Vcc, Vdd. In the recovery stage, the voltage may be reduced to the corresponding voltage by one or more step-by-step steps, such as first reducing the voltage to an intermediate voltage, and maintaining the intermediate voltage for a period of time, and then reducing the voltage to the corresponding voltage.

[0172] The control logic 512 may be coupled to each peripheral circuit described above and configured to control the operation of each peripheral circuit. The register 514 may be coupled to the control logic 512 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The interface 516 may be coupled to the control logic 512 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic 512, as well as buffer status information received from the control logic 512 and relay them to the host. The interface 516 may also be coupled to the column decoder / bit line driver 506 via a data bus 518 and act as a data I / O interface and a data buffer to buffer data and relay them to the memory cell array 301 or relay or buffer data from the memory cell array 301.

[0173] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A three-dimensional memory, characterized in that: include: A stacked structure, the stacked structure comprising alternately stacked gate layers and first dielectric layers; A first channel structure, wherein the first channel structure penetrates the stack structure along a first direction; a conductive portion located at one end of the first channel structure in the first direction; and an insulating layer and a selection gate layer sequentially stacked on the conductive portion; A second channel structure, penetrating the selection gate layer and the insulating layer; An isolation structure that penetrates the selection gate layer; wherein, along a second direction perpendicular to the first direction, the isolation structure is located between two adjacent second channel structures; the distance between the center line of the second channel structure in the first direction and the isolation structure is a first distance, and the distance between the center line of the conductive portion in the first direction and the isolation structure is a second distance; wherein the first distance is different from the second distance.

2. The three-dimensional memory according to claim 1, characterized in that: The first distance is greater than the second distance.

3. The three-dimensional memory according to claim 2, characterized in that: The first distance of the second channel structure adjacent to the isolation structure is greater than the second distance of the conductive portion adjacent to the isolation structure.

4. The three-dimensional memory according to claim 1, characterized in that: A size of the second channel structure in the second direction is smaller than a size of the conductive portion in the second direction.

5. The three-dimensional memory according to claim 4, characterized in that: An orthographic projection of the second channel structure in the first direction falls within an orthographic projection of the conductive portion in the first direction.

6. The three-dimensional memory according to claim 1, characterized in that: The three-dimensional memory further includes: a second dielectric layer penetrating the selection gate layer and surrounding the second channel structure.

7. The three-dimensional memory according to claim 1, characterized in that: The first channel structure comprises: A barrier layer, a storage layer, a tunnel layer and a channel layer are sequentially arranged along the second direction; wherein, The conductive portion is coupled to the channel layer, and the conductive portion is coupled to the second channel structure.

8. The three-dimensional memory according to claim 7, characterized in that: The conductive portion is located at one end of the first channel structure close to the second channel structure; one end of the conductive portion in the first direction is coupled to the channel layer, and the other end is coupled to the second channel structure.

9. The three-dimensional memory according to claim 7, characterized in that: The conductive portion is within the first channel structure, and a size of the conductive portion in the second direction is smaller than a size of the first channel structure in the second direction.

10. The three-dimensional memory according to claim 9, characterized in that: The conductive portion is surrounded by the channel layer, and a sidewall of the conductive portion in the second direction is in contact with the channel layer.

11. The three-dimensional memory according to claim 9, characterized in that: The barrier layer surrounds the conductive portion, and the conductive portion at least covers the channel layer in the first direction.

12. The three-dimensional memory according to claim 11, characterized in that: In the first direction, the conductive portion includes: an extension portion extending from a surface of a side of the channel layer close to the selection gate layer and away from the selection gate layer, and the extension portion is surrounded by the channel layer.

13. The three-dimensional memory according to claim 1, characterized in that: The three-dimensional memory further includes a peripheral circuit located on a side of the second channel structure away from the first channel structure.

14. A method for manufacturing a three-dimensional memory, characterized in that: include: forming a stacked structure, the stacked structure comprising alternately stacked sacrificial layers and first dielectric layers; forming a first channel structure penetrating the stacked structure along a first direction; forming a conductive portion at one end of the first channel structure along the first direction; forming an insulating layer and a selection gate layer in sequence on the conductive portion; forming an isolation structure penetrating the selection gate layer; A first opening is formed that penetrates the selection gate layer and the insulating layer, and a second channel structure is formed in the first opening; wherein, along a second direction perpendicular to the first direction, the isolation structure is located between two adjacent second channel structures; a distance between a center line of the second channel structure in the first direction and the isolation structure is a first distance, and a distance between a center line of the conductive portion in the first direction and the isolation structure is a second distance; wherein the first distance is different from the second distance; The sacrificial layer is replaced with a conductive material to form a gate layer.

15. The manufacturing method according to claim 14, characterized in that: The first distance is greater than the second distance.

16. The manufacturing method according to claim 15, characterized in that: The first distance of the second channel structure adjacent to the isolation structure is greater than the second distance of the conductive portion adjacent to the isolation structure.

17. The manufacturing method according to claim 14, characterized in that: A size of the second channel structure in the second direction is smaller than a size of the conductive portion in the second direction.

18. The manufacturing method according to claim 17, characterized in that: An orthographic projection of the second channel structure in the first direction falls within an orthographic projection of the conductive portion in the first direction.

19. The manufacturing method according to claim 14, characterized in that: The production method further comprises: Before forming the second channel structure, a second dielectric layer is formed on the sidewall of the first opening; the second dielectric layer surrounds the second channel structure.

20. The manufacturing method according to claim 14, characterized in that: The method of forming the first channel structure includes: Forming a channel hole penetrating the stacked structure, wherein: a barrier layer, a storage layer, a tunneling layer, a channel layer and a core are sequentially formed in the channel hole; The conductive portion is coupled to the channel layer, and the conductive portion is coupled to the second channel structure.

21. The manufacturing method according to claim 20, characterized in that: The method of forming the conductive portion includes: Before forming the insulating layer, a conductive portion is formed between the first channel structure and the second channel structure; the formed insulating layer is located between the conductive portion and the formed selection gate layer; wherein one end of the conductive portion in the first direction is coupled to the channel layer, and the other end is coupled to the second channel structure.

22. The method according to claim 20, characterized in that: The production method further comprises: Before forming the insulating layer, a core portion at one end of the first channel structure is etched to form a first opening.

23. The manufacturing method according to claim 22, characterized in that: The method of forming the conductive portion includes: The conductive portion is formed in the first opening, wherein the conductive portion is surrounded by the channel layer, and a sidewall of the conductive portion in the second direction is in contact with the channel layer.

24. The method according to claim 22, characterized in that: The method of forming the conductive portion includes: At least etching the channel layer to enlarge the size of the first opening in the second direction to form a second opening; The conductive portion is formed in the second opening; wherein the barrier layer surrounds the conductive portion, and the conductive portion at least covers the channel layer in the first direction.

25. The manufacturing method according to claim 24, characterized in that: The method of forming the conductive portion includes: further etching the core portion exposed from the first opening to enlarge the size of the first opening in the first direction; In the first direction, the conductive portion formed further includes: an extending portion extending toward the core portion, wherein the extending portion is surrounded by the channel layer.

26. The method according to claim 14, characterized in that: The manufacturing method further includes: forming a peripheral circuit on a side of the second channel structure away from the first channel structure.

27. A memory system, characterized in that: include: A memory device comprising one or more three-dimensional memories according to any one of claims 1 to 13; as well as A memory controller is coupled to the memory device and controls the memory device.

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