Semiconductor packaging structure and preparation method thereof

Abstract

The invention discloses a semiconductor packaging structure and a preparation method thereof. The semiconductor package structure includes: a substrate; the multiple stacking structures are sequentially stacked on one side of the substrate in the first direction; and a plastic package body which packages the plurality of stacked structures on the substrate, wherein the plurality of stacking structures are sequentially staggered by a first distance along a second direction, each stacking structure comprises a plurality of chips which are sequentially stacked along the first direction, the plurality of chips are sequentially staggered by a second distance along the second direction, the first distance is greater than the second distance, and the first direction intersects with the second direction.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a semiconductor packaging structure and a method for preparing the same. Background Art

[0002] With the development of semiconductor technology, electronic devices tend to be miniaturized and their storage capacity is also increasing. At present, the semiconductor packaging structure in electronic devices usually uses chip stacking (Stack-Die) technology or chip FOW (Flowover wire) stacking technology to increase storage capacity. However, as the number of stacked chips continues to increase, the ability of the semiconductor packaging structure to resist bending deformation becomes worse.

[0003] Currently, how to improve the ability of a semiconductor packaging structure to resist bending deformation is one of the technical problems that needs to be solved urgently by those skilled in the art. Summary of the invention

[0004] The semiconductor packaging structure and the manufacturing method thereof provided in the embodiments of the present application can solve or partially solve the above-mentioned deficiencies in the related art or other deficiencies in the related art.

[0005] According to the first aspect of the present application, a semiconductor packaging structure is provided, comprising:

[0006] substrate;

[0007] A plurality of stacking structures are sequentially stacked on one side of the substrate along a first direction; and

[0008] A plastic package body, packaging the plurality of stacked structures on the substrate;

[0009] Among them, the multiple stacking structures are staggered by a first distance in sequence along the second direction, the stacking structure includes a plurality of chips stacked in sequence along the first direction, the plurality of chips are staggered by a second distance in sequence along the second direction, the first distance is greater than the second distance, and the first direction intersects with the second direction.

[0010] According to the second aspect of the present application, a method for preparing a semiconductor packaging structure includes:

[0011] forming a plurality of stacked structures along a first direction on a first side of the carrier;

[0012] forming a plastic package body encapsulating the plurality of stacked structures on a first side of the carrier; and

[0013] replacing the carrier with a substrate;

[0014] Among them, the multiple stacking structures are staggered by a first distance in sequence along the second direction, the stacking structure includes a plurality of chips stacked in sequence along the first direction, the plurality of chips are staggered by a second distance in sequence along the second direction, the first distance is greater than the second distance, and the first direction intersects with the second direction.

[0015] The semiconductor packaging structure provided in the embodiment of the present application changes the stacking method of the chips in the semiconductor packaging structure so that the first distance between two adjacent stacking structures along the second direction is greater than the second distance between two adjacent chips in the stacking structure along the second direction. This can increase the volume proportion of the plastic package in the central area of ​​the semiconductor packaging structure, and make the chip farthest from the substrate deviate from the central area of ​​the semiconductor packaging structure, i.e., the stress concentration position. In this way, most of the stress in the stress concentration area of ​​the semiconductor packaging structure can be released with the help of the strain of the plastic package, thereby avoiding deformation and failure of the chip farthest from the substrate due to excessive strain, thereby improving the ability of the semiconductor packaging structure to resist bending deformation and enhancing the mechanical properties of the semiconductor packaging structure. In addition, the bonding process between the chips in the present application remains unchanged, and no additional cost is added.

[0016] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present application, nor is it intended to limit the scope of the present application. Other features of the present application will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Other features, purposes and advantages of the present application will become more apparent by reading the detailed description of the non-limiting embodiments made with reference to the following drawings. The drawings are used to better understand the present solution and do not constitute a limitation of the present application. In the drawings:

[0018] Figure 1 It is a structural schematic diagram of a semiconductor packaging structure in the related art;

[0019] Figure 2 It is a schematic diagram of the force of the semiconductor packaging structure during 3PB detection in the related art;

[0020] Figure 3 is a schematic structural diagram of a semiconductor packaging structure according to one embodiment of the present application;

[0021] Figure 4 It is a schematic diagram of the force of the semiconductor packaging structure during the 3PB test in this application;

[0022] Figure 5 is a dimensional relationship diagram of a semiconductor package structure according to one embodiment of the present application;

[0023] Figure 6is a schematic structural diagram of a semiconductor packaging structure according to another embodiment of the present application;

[0024] Figure 7 It is the strain displacement diagram of the plastic package and the chip farthest from the substrate;

[0025] Figure 8 is the strain cloud diagram of the semiconductor packaging structure, where Figure 8 (a) is the strain cloud diagram of the plastic package of the semiconductor packaging structure in the related art. Figure 8 (b) is a strain cloud diagram of the plastic package of the semiconductor package structure in the embodiment of the present application;

[0026] Fig. 9 is a strain bar graph of the plastic package of the semiconductor package structure under the same stress in the related art and the present application; and

[0027] Fig.10 It is a schematic flow chart of a method for preparing a semiconductor packaging structure according to one embodiment of the present application.

[0028] Reference numerals:

[0029] 100, substrate; 200, stacking structure; 201, first stacking structure;

[0030] 202, second stacking structure; 203, third stacking structure; 210, chip;

[0031] 300, plastic package; 301, first side wall; 302, second side wall; 400, controller;

[0032] 510, first connection structure; 520, second connection structure; 610, first wire;

[0033] 620. Second wire. DETAILED DESCRIPTION

[0034] In order to better understand the present application, a more detailed description will be made of various aspects of the present application with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0035] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature region, but do not represent any limitation on the features, and especially do not represent any order of precedence.

[0036] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0037] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0038] Unless otherwise specified, all words (including engineering terms and scientific and technological terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0039] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method described in the present application are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0040] In addition, in the present application, the term "layer" refers to a material portion including an area with a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is less than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of a continuous structure. A layer may extend horizontally, vertically and / or along an inclined surface. A layer may include multiple sublayers. In addition, in the present application, when "connected" or "coupled" is used, it may indicate direct contact or indirect contact between corresponding parts, unless otherwise clearly defined or inferred from the context.

[0041] With the development of semiconductor technology, electronic devices tend to be miniaturized and their storage capacity is also increasing. Among them, electronic devices can be but are not limited to mobile phones, desktop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, virtual reality devices, augmented reality devices or other devices with memory. The semiconductor packaging structure of electronic devices usually uses chip stacking (Stack-Die) technology or chip FOW (Flow over wire) stacking technology to increase storage capacity. Figure 1 As shown, the semiconductor packaging structure generally includes a plastic package 300, a substrate 100, and a plurality of chips 210 stacked on the substrate 100 in sequence along a first direction (z direction). The plastic package 300 packages the plurality of chips 210 on the substrate 100, and the plurality of chips 210 are staggered in sequence at equal intervals along a second direction (x direction) perpendicular to the first direction (z direction).

[0042] On the premise that the chip 210 of the semiconductor package structure does not fail, in order to accurately determine the strength requirements that the semiconductor package structure can meet, it is necessary to simulate the actual application scenario of the electronic device before leaving the factory and apply a certain bending stress to the semiconductor package structure for bending resistance testing. For example, a three-point bending (3PB) test is performed on the semiconductor package structure. Figure 1 and Figure 2 As shown, the semiconductor package structure is inverted and placed on two support points A and B set at intervals, and then a downward load is applied to the semiconductor package structure at point C, where point C is located on the center line of the line connecting support point A and support point B. As a result, two equal moments are generated on the semiconductor package structure and three-point bending occurs. At this time, the central area of ​​the semiconductor package structure is the area of ​​stress concentration. Since the central area of ​​the semiconductor package structure is the area of ​​stress concentration, the strain gauge is usually attached to the central area of ​​the surface of the plastic package 300 away from the substrate 100. Under the action of the above stress, the semiconductor package structure will bend and deform. However, as the number of chips 210 stacked in the semiconductor package structure continues to increase, the mechanical properties of the semiconductor package structure decrease, and the ability of the semiconductor package structure to resist bending deformation deteriorates. The chip 210 farthest from the substrate 100 is prone to deformation and failure due to excessive strain, which in turn causes the strength of the semiconductor package structure to fail to meet user needs.

[0043] Based on this, in order to solve at least part of the above problems, an embodiment of the present application provides a semiconductor packaging structure. Figures 3 to 6Schematic diagrams of semiconductor packaging structures of different embodiments of the present application are shown. The semiconductor packaging structure includes a substrate 100, a plastic package 300 and a plurality of stacked structures 200, wherein the plurality of stacked structures 200 are sequentially stacked on one side of the substrate 100 along a first direction (z direction), and the plurality of stacked structures 200 are sequentially staggered by a first distance L1 along a second direction (x direction), and the plastic package 300 encapsulates the plurality of stacked structures 200 on the substrate 100. The stacked structure 200 includes a plurality of chips 210 sequentially stacked along a first direction (z direction), and the plurality of chips 210 are sequentially staggered by a second distance L2 along a second direction (x direction), the first distance L1 is greater than the second distance L2, and the first direction intersects with the second direction.

[0044] Therefore, if Figure 4 As shown, when the semiconductor package structure is subjected to 3PB detection, the semiconductor package structure can be first inverted and placed on two support points A and B that are spaced apart, and then a downward load is applied to the semiconductor package structure at point C, where point C is located on the center line of the line connecting support point A and support point B. As a result, two equal moments are generated on the semiconductor package structure and three-point bending occurs, and at this time, the central area of ​​the semiconductor package structure is the area of ​​stress concentration. However, since the first distance L1 between the two adjacent stacked structures 200 in the embodiment of the present application is greater than the second distance L2 between the two adjacent chips 210 in the stacked structure 200 in the second direction (x direction), in other words, all the chips 210 in the embodiment of the present application are not staggered at equal intervals (second distance) along the second direction (x direction), compared to all the chips 210 being staggered at equal intervals in sequence along the second direction (x direction), the chip 210 farthest from the substrate 100 in the embodiment of the present application is further away from the center of the semiconductor package structure, so that the volume of the plastic package 300 in the central area of ​​the semiconductor package structure accounts for a larger proportion. The material of the plastic package 300 is different from that of the chip 210. Under the same stress, the strain of the plastic package 300 is usually greater than that of the chip 210. Therefore, although the central area of ​​the semiconductor package structure is the stress concentration area when the semiconductor package structure is subjected to 3PB detection, the volume proportion of the plastic package 300 in the central area of ​​the semiconductor package structure increases, and the chip 210 farthest from the substrate 100 is further away from the center of the semiconductor package structure. Therefore, most of the stress in the stress concentration area can be released by the strain of the plastic package 300, and the stress applied to each chip 210, especially the stress applied to the chip 210 farthest from the substrate 100, is reduced, thereby preventing the chip 210 farthest from the substrate 100 from deforming and failing due to excessive strain. In this way, the ability of the semiconductor package structure to resist bending deformation can be improved, and the mechanical properties of the semiconductor package structure can be improved.

[0045] As can be seen from the above, the embodiment of the present application changes the stacking method of the chip 210 in the semiconductor packaging structure so that the first distance between two adjacent stacking structures 200 along the second direction is greater than the second distance between two adjacent chips 210 in the stacking structure 200 along the second direction. This can increase the volume share of the plastic package 300 in the central area of ​​the semiconductor packaging structure, and make the chip 210 farthest from the substrate 100 deviate from the central area of ​​the semiconductor packaging structure, i.e., the stress concentration position. In this way, most of the stress in the stress concentration area of ​​the semiconductor packaging structure can be released with the help of the strain of the plastic package 300, thereby avoiding deformation and failure of the chip 210 farthest from the substrate 100 due to excessive strain. In addition, the ability of the semiconductor packaging structure to resist bending deformation can be improved, and the mechanical properties of the semiconductor packaging structure can be improved. In addition, the bonding process between the chips 210 in the present application remains unchanged, and no additional cost is added.

[0046] It should be noted that, in the embodiment of the present application, the first direction is generally the thickness direction of the substrate 100. As an example, the projection of the chip 210 on a plane perpendicular to the first direction may be circular, elliptical, polygonal or other shapes, which is not limited in the present application. For example, if the above-mentioned projection of the chip 210 is a rectangle, the second direction may be the width direction of the chip 210, the third direction may be the length direction of the chip 210, the first direction, the second direction and the third direction are perpendicular to each other, the first direction may be the z direction in the accompanying drawings, the second direction may be the x direction in the accompanying drawings, and the third direction may be the y direction in the accompanying drawings. In addition, in the embodiment of the present application, the number of chips 210 in each stacking structure 200 may be the same or different. As an example, the number of chips 210 in the stacking structure 200 is not less than 3.

[0047] like Figure 3 As shown, in order to further increase the volume proportion of the plastic package 300 in the central area of ​​the semiconductor package structure and keep the chip 210 farthest from the substrate 100 away from the stress concentration area of ​​the semiconductor package structure, the center line of the chip 210 farthest from the substrate 100 and the center line of the chip 210 closest to the substrate 100 are respectively located on both sides of the center line of the plastic package 300 along the second direction (x direction). Figure 3Taking the orientation shown in FIG. 1 as a reference, the centerline of the chip 210 farthest from the substrate 100, i.e., the topmost chip 210, is located on the left side of the centerline of the plastic package 300, and the centerline of the chip 210 closest to the substrate 100, i.e., the bottommost chip 210, is located on the right side of the centerline of the plastic package 300. Furthermore, the chip 210 farthest from the substrate 100 among the multiple chips 210 is located on one side of the centerline of the plastic package 300 along the second direction (x direction). It should be noted that, in addition to the chip 210 farthest from the substrate 100, the centerlines of other chips 210 may also be located on different sides of the centerline of the plastic package 300 from the centerline of the chip 210 closest to the substrate 100. For example, Figure 3 The center lines of the four chips 210 at the top are all located on the left side of the center line of the plastic package 300. Similarly, except for the chip 210 closest to the substrate 100, the center lines of other chips 210 can also be located on different sides of the center line of the plastic package 300 from the center line of the chip 210 farthest from the substrate 100. For example, Figure 3 The center lines of the four chips 210 at the bottom are all located to the right of the center line of the plastic package 300 .

[0048] In addition, two adjacent chips 210 and the chip 210 and the substrate 100 can be connected by a wire bonding process (WireBump, WB) or a through silicon via process (Through Silicon Via, TSV). Figure 6As shown, two adjacent chips 210 are connected by a first wire 610, and the chip 210 closest to the substrate 100 is connected to the substrate 100 by a second wire 620. The materials of the first wire 610 and the second wire 620 may include but are not limited to at least one of gold, silver and copper. In addition, the material of the plastic package 300 in the embodiment of the present application may include but are not limited to at least one of polyimide, silica gel and EMC (Epoxy Molding Compound), and the material of the chip 210 may include but are not limited to semiconductor materials such as single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon on insulator (SOI), germanium on insulator (GOI) or III-V compounds such as gallium arsenide. The chip 210 may include but is not limited to at least one memory array and / or at least one peripheral circuit. The two adjacent chips 210 may be the same or different. If the chip 210 includes multiple memory arrays, the types of at least two memory arrays may be the same or different. The storage array may be a non-volatile storage array, such as a NAND storage array, a PROM (Programmable Read-Only memory) storage array, or a NOR storage array, or a volatile storage array, such as a DRAM (Dynamic Random Access Memory) storage array or an SRAM (Static Random-Access Memory) storage array. The peripheral circuit may include, but is not limited to, at least one of a high-voltage device, a low-voltage device, and an ultra-low-voltage device. The high-voltage device may include, but is not limited to, at least one of a row decoder, a column decoder, a word line driver, and a bit line driver, the low-voltage device may include, but is not limited to, a page buffer or a logic device, and the ultra-low-voltage device may include, but is not limited to, an I / O circuit. The operating voltage of a high-voltage device is generally greater than 3.3V, such as 5V to 30V. As an example, the operating voltage of a high-voltage device may be 5V, 10V, 15V, 20V, 25V or 30V; the operating voltage of a low-voltage device is generally between 1.3V and 3.3V. As an example, the operating voltage of a low-voltage device may be 1.3V, 1.8V, 2.3V, 2.8V or 3.3V; the operating voltage of an ultra-low-voltage device is generally lower than 1.3V, such as 0.9V to 1.2V; as an example, the operating voltage of an ultra-low-voltage device may be 0.9V, 0.95V, 1V, 1.05V, 1.1V, 1.15V or 1.2V. It should be noted that the operating voltage of a high-voltage device, a low-voltage device or an ultra-low-voltage device may also be any value between any two of the above voltage values. Those skilled in the art should understand that the description of the operating voltage ranges of high-voltage devices, low-voltage devices and ultra-low-voltage devices above is for a better understanding of the present solution and does not constitute a limitation on the present application.

[0049] In some embodiments, Figure 5 As shown, the first distance L1 between two adjacent stacking structures 200 along the second direction (x direction) is not less than 0.5 mm, that is, L1 ≥ 0.5 mm. The second distance L2 between two adjacent chips 210 in the stacking structure 200 along the second direction (x direction) is less than 0.5 mm and not less than 0.12 mm, that is, 0.12 mm ≤ L2 < 0.5 mm.

[0050] In some embodiments, Figure 5 As shown, the first distance L1 between two adjacent stack structures 200 staggered along the second direction satisfies: L1≤L0-L3-(n-2)*L2-c; wherein L0 is the size of the semiconductor package structure along the second direction, L2 is the second distance, L3 is the size of the chip 210 along the second direction, n is the number of chips 210 of the semiconductor package structure, and c is a preset constant. As an example, the plastic package 300 includes a first side wall 301 and a second side wall 302 arranged opposite to each other along the second direction, and c in the above text is not greater than the sum of c1 and c2, that is, c≤c1+c2, c1 is the spacing between the first side wall 301 and the chip 210 closest to the first side wall 301 among the multiple chips 210, and c2 is the spacing between the second side wall 302 and the chip 210 closest to the second side wall 302 among the multiple chips 210. Among them, c1 and c2 may be equal or unequal. In addition, in order to reduce the volume of the semiconductor package structure, c1 and c2 are both not greater than 0.5 mm. For example, c1=c2=0.5 mm.

[0051] In some embodiments, the semiconductor package structure further includes a controller 400 encapsulated in the plastic package 300, and the controller 400 is connected to the substrate 100. For example, the controller 400 can be connected to the substrate 100 through a first connection structure 510. The first connection structure 510 can include, but is not limited to, at least one of a solder ball, a solder column, and a conductive adhesive. Compared with the conductive adhesive, the solder ball and the solder column significantly improve the data transmission rate and the quality of the transmission signal of the controller 400. The material of the first connection structure 510 can include, but is not limited to, a tin-based alloy or tin.

[0052] In order to make full use of the space on the side of the controller 400 away from the substrate 100 and make the layout of the stacking structure 200 more reasonable, the stacking structure 200 closest to the substrate 100 among the multiple stacking structures 200 is located on the side of the controller 400 along the second direction (x direction), and the stacking structure 200 farthest from the substrate 100 is located on the side of the controller 400 along the first direction (z direction). In other words, on at least one plane parallel to the first direction (z direction), the projection of the stacking structure 200 closest to the substrate 100 at least partially overlaps with the projection of the controller 400, and on a plane perpendicular to the first direction (z direction), the projection of the stacking structure 200 farthest from the substrate 100 at least partially overlaps with the projection of the controller 400. For example, Figure 3 As shown, the semiconductor packaging structure includes two stacking structures 200, namely a first stacking structure 201 and a second stacking structure 202. The first stacking structure 201 is the stacking structure closest to the substrate 100, and the second stacking structure 202 is the stacking structure 200 farthest from the substrate 100. The first stacking structure 201 is located on the right side of the controller 400 along the second direction (x direction), and the second stacking structure 202 is located on the upper side of the controller 400 along the first direction (z direction). It should be noted that if the number of stacking structures 200 in the semiconductor packaging structure is greater than two, then in addition to the stacking structure 200 closest to the substrate 100 and the stacking structure 200 farthest from the substrate 100, other stacking structures 200 may also be located on one side of the controller 400 along the second direction (x direction) or on one side of the controller 400 along the first direction (z direction). For example, Figure 6 As shown, the semiconductor packaging structure includes three stacking structures 200. For the convenience of description, the three stacking structures 200 are referred to as the first stacking structure 201, the second stacking structure 202 and the third stacking structure 203 in sequence. Along the first direction (z direction), the first stacking structure 201, the second stacking structure 202 and the third stacking structure 203 are stacked in sequence in the direction away from the substrate 100. The first stacking structure 201 is the stacking structure closest to the substrate 100, and the third stacking structure 203 is the stacking structure 200 farthest from the substrate 100. The first stacking structure 201 is located on the right side of the controller 400 along the second direction (x direction), and the second stacking structure 202 and the third stacking structure 203 are located on the upper side of the controller 400 along the first direction (z direction). In other words, on a plane perpendicular to the first direction (z direction), the projection of the second stacking structure 202 and the projection of the third stacking structure 203 both at least partially overlap with the projection of the controller 400.

[0053] In addition, in order to improve the stability of the entire semiconductor package structure, one of the plurality of stacked structures 200 may be in contact with a surface of the controller 400 away from the substrate 100. Figure 3As shown, the semiconductor package structure includes a first stacking structure 201 and a second stacking structure 202, wherein the first stacking structure 201 is located on the right side of the controller 400 along the second direction (x direction), and the second stacking structure 202 is located on the upper side of the controller 400 along the first direction (z direction) and contacts the upper surface of the controller 400. Thus, the controller 400 and the first stacking structure 201 can simultaneously support the second stacking structure 202, thereby improving the stability of the entire semiconductor package structure. For another example, Figure 6 As shown, the semiconductor package structure includes a first stacking structure 201, a second stacking structure 202 and a third stacking structure 203, the first stacking structure 201 is located on the right side of the controller 400 along the second direction (x direction), the second stacking structure 202 and the third stacking structure 203 are located on the upper side of the controller 400 along the first direction (z direction), and the second stacking structure 202 is in contact with the upper surface of the controller 400. Similarly, the controller 400 and the first stacking structure 201 can simultaneously support the second stacking structure 202, thereby improving the stability of the entire semiconductor package structure.

[0054] Below Figure 3 Taking the semiconductor package structure shown in FIG. 1 as an example, the semiconductor package structure in the embodiment of the present application is further described:

[0055] like Figure 3 and Figure 5As shown, the semiconductor packaging structure includes a substrate 100, a first stacking structure 201, a second stacking structure 202, a plastic package 300 and a controller 400. Along a first direction (z direction), the first stacking structure 201 and the second stacking structure 202 are sequentially stacked on one side of the substrate 100 in a direction away from the substrate 100. The second stacking structure 202 is staggered with the first stacking structure 201 by a first distance L1 along the second direction (x direction). The first stacking structure 201 is located on the right side of the controller 400 along the second direction (x direction). The second stacking structure 202 is located on the upper side of the controller 400 along the first direction (z direction). The first stacking structure 201 and the second stacking structure 202 are stacked on the upper side of the controller 400 along the first direction (z direction). The two stacking structures 202 each include four chips 210 stacked in sequence along a first direction (z direction). The four chips 210 of the first stacking structure 201 are staggered in sequence by a second distance L2 along a second direction (x direction). The four chips 210 of the second stacking structure 202 are also staggered in sequence by a second distance L2 along the second direction (x direction). The center line of the chip 210 farthest from the substrate 100, i.e., the top chip 210, is located to the left of the center line of the plastic package 300 along the second direction (x direction), and the center line of the chip 210 closest to the substrate 100, i.e., the bottom chip 210, is located to the right of the center line of the plastic package 300 along the second direction (x direction). Among them, the material of the plastic package 300 may include EMC, the thickness of the substrate 100 along the first direction is 130um, the thickness of the chip 210 closest to the substrate 100 in the first stacking structure 201 along the first direction is 55um, the thickness of the other three chips 210 along the first direction is 40um, and the thickness of the four chips 210 in the second stacking structure 202 along the first direction is 40um.

[0056] like Figure 5 As shown, the first distance L1 between the first stacking structure 201 and the second stacking structure 202 along the second direction (x direction) is much greater than the second distance L2 between the two adjacent chips 210 in the first stacking structure 201 or the second stacking structure 202 along the second direction (x direction). Therefore, compared with all the chips 210 being sequentially staggered along the second direction by the second distance L2, the chip 210 farthest from the substrate 100, i.e., the topmost chip 210, in the embodiment of the present application is further away from the center of the semiconductor package structure, and the space originally occupied by the chip 210 in the central area of ​​the semiconductor package structure is filled with the plastic package 300, thereby increasing the volume proportion of the plastic package 300 in the central area of ​​the semiconductor package structure located to the right of its center line. Thus, as Figure 7As shown, when the semiconductor package structure is subjected to 3PB testing, under the same stress, the strain of the EMC is much greater than the strain of the topmost chip 210. Therefore, most of the stress in the stress concentration area of ​​the semiconductor package structure can be released by the strain of the plastic package body 300, thereby reducing the stress applied to each chip 210, especially the stress applied to the chip 210 farthest from the substrate 100, that is, the topmost chip 210, thereby preventing the chip 210 farthest from the substrate 100 from deforming and failing due to excessive strain.

[0057] Figure 8 (a) shows a strain cloud diagram of the plastic package body 300 of the semiconductor packaging structure in the related art, Figure 8 (b) shows the strain cloud diagram of the plastic package body 300 of the semiconductor package structure in the embodiment of the present application, wherein the y direction is the length direction of the plastic package body 300, and the z direction is the thickness direction of the plastic package body 300. Figure 8 (a) The number of chips 210 and the specifications of the chips 210 in the corresponding semiconductor package structure are Figure 8 (b) The number of chips 210 and the specifications of the chips 210 in the corresponding semiconductor package structure are the same, and the difference between the two is only that: Figure 8 (a) In the corresponding semiconductor package structure, the chips 210 are staggered in sequence along the second direction (x direction) by a second distance L2 (see Figure 1 ),and Figure 8 (b) In the corresponding semiconductor package structure, the fourth chip 210 and the fifth chip 210 are staggered by a first distance L1 along the second direction (x direction) (see Figure 5 ). By comparison Figure 8 (a) and Figure 8 (b) It can be seen that when the same stress is applied at the same position, compared with the related art, the strain of the plastic package 300 in the stress concentration area of ​​the semiconductor packaging structure, that is, the central area, is greater in the embodiment of the present application, so that more stress can be released with the help of the plastic package 300, thereby reducing the stress applied to each chip 210, especially the stress applied to the chip 210 farthest from the substrate 100, that is, the top chip 210. In addition, Fig. 9 The strain bar graph of the plastic package 300 of the semiconductor package structure in the related art and the strain bar graph of the plastic package 300 of the semiconductor package structure in the embodiment of the present application under the same stress along the long side direction of the plastic package 300 is shown. Fig. 9It can be seen that under the same stress, the strain of the central area of ​​the plastic package 300 in the related art can only reach 3709uε, while the strain of the central area of ​​the plastic package 300 in the present application is as high as 5083uε. Compared with the related art, the strain of the central area of ​​the plastic package 300 in the present application is increased by 37%. Therefore, compared with the related art, the present application can release more stress in the stress concentration area of ​​the semiconductor packaging structure with the help of the plastic package 300, thereby reducing the stress applied to each chip 210, especially the stress applied to the chip 210 farthest from the substrate 100, that is, the topmost chip 210, to avoid the chip 210 farthest from the substrate 100 from deformation and failure due to excessive strain.

[0058] like Fig.10 As shown, the embodiment of the present application also provides a method 1000 for preparing a semiconductor packaging structure, the method comprising:

[0059] S100, forming a plurality of stacking structures 200 along a first direction on a first side of a carrier; the plurality of stacking structures 200 are sequentially staggered by a first distance along a second direction, the stacking structures 200 include a plurality of chips 210 sequentially stacked along the first direction, the plurality of chips 210 are sequentially staggered by a second distance along the second direction, the first distance is greater than the second distance, and the first direction intersects the second direction;

[0060] S200, forming a plastic package body 300 encapsulating a plurality of stacked structures 200 on a first side of the carrier;

[0061] S300 , replacing the carrier with the substrate 100 .

[0062] In some embodiments, step S100 may include: forming a first stacking structure 201 on a first side of a carrier; and forming a second stacking structure 202 along a first direction and on a side of the first stacking structure 201 away from the carrier. Figure 3Taking the semiconductor package structure shown in FIG. 2 as an example, the first stacked structure 201 and the second stacked structure 202 each include four chips 210 sequentially arranged along a first direction. For ease of description, the four chips 210 of the first stacked structure 201 may be sequentially referred to as the first chip, the second chip, the third chip, and the fourth chip, and the four chips 210 of the second stacked structure 202 may be sequentially referred to as the fifth chip, the sixth chip, the seventh chip, and the eighth chip. Thus, step S100 may include: forming a 20um thick adhesive layer (not shown) on the first side of the carrier; mounting a first chip with a thickness of 55um on the carrier through the adhesive layer; forming a 7um thick adhesive layer on the side of the first chip away from the carrier; mounting a second chip with a thickness of 40um on the first chip through the adhesive layer after deviating from the first chip by a second distance L2 along the second direction; wherein the second distance L2 is less than 0.5mm and not less than 0.12mm, that is, 0.12mm≤L2<0.5mm; forming a 7um thick adhesive layer on the side of the second chip away from the first chip; mounting a third chip with a thickness of 40um on the second chip through the adhesive layer after deviating from the second chip by the second distance L2 along the second direction; forming a 7um thick adhesive layer on the side of the third chip away from the second chip; mounting a fourth chip with a thickness of 40um on the third chip through the adhesive layer after deviating from the third chip by the second distance L2 along the second direction; On the chip; a 7um thick adhesive layer is formed on the side of the fourth chip away from the third chip; a fifth chip with a thickness of 40um is deviated from the fourth chip along the second direction by the first distance L1 and then mounted on the fourth chip through the above-mentioned adhesive layer; wherein the first distance L1 is not less than 0.5mm, that is, L1≥0.5mm; a 7um thick adhesive layer is formed on the side of the fifth chip away from the fourth chip; a sixth chip with a thickness of 40um is deviated from the fifth chip along the second direction by the second distance L2 and then mounted on the fifth chip through the above-mentioned adhesive layer; a 7um thick adhesive layer is formed on the side of the sixth chip away from the fifth chip; a seventh chip with a thickness of 40um is deviated from the sixth chip along the second direction by the second distance L2 and then mounted on the sixth chip through the above-mentioned adhesive layer; a 7um thick adhesive layer is formed on the side of the seventh chip away from the sixth chip; an eighth chip with a thickness of 40um is deviated from the seventh chip along the second direction by the second distance L2 and then mounted on the seventh chip through the above-mentioned adhesive layer.

[0063] In the above, the first distance L1 may satisfy: L1≤L0-L3-(n-2)*L2-c; wherein L0 is the size of the semiconductor package structure along the second direction, L2 is the second distance, L3 is the size of the chip 210 along the second direction, n is the number of chips 210 of the semiconductor package structure, and c is a preset constant. As an example, the plastic package 300 includes a first side wall 301 and a second side wall 302 arranged opposite to each other along the second direction, wherein c in the above is not greater than the sum of c1 and c2, that is, c≤c1+c2, c1 is the spacing between the first side wall 301 and the chip 210 closest to the first side wall 301 among the multiple chips 210, and c2 is the spacing between the second side wall 302 and the chip 210 closest to the second side wall 302 among the multiple chips 210. wherein c1 and c2 may be equal or unequal. in addition, in order to reduce the volume of the semiconductor package structure, c1 and c2 are both not greater than 0.5 mm. for example, c1=c2=0.5 mm.

[0064] It should be noted that, in the embodiments of the present application, the carrier may be, but not limited to, a quartz sheet, a glass sheet, a metal sheet, a silicon sheet or a ceramic sheet, etc. In addition, the bonding layer may have the characteristics of bonding strength, chemical resistance, acid and alkali resistance and high temperature resistance, etc. The bonding layer may be, but not limited to, a DAF film (Die Attach Film, chip 210 attachment film), a laminating tape or a dry film, and the material of the bonding layer may be, but not limited to, epoxy resin, phenolic epoxy resin or other viscous resin. The bonding layer may also be doped with a bonding aid or a cross-linking agent according to actual process requirements, such as PSA (Pressure Sensitive Adhesive), polybenzoxazole (PBO) or benzocyclobutene (BCB), etc.

[0065] In some embodiments, in order to improve the stability of the semiconductor packaging structure, before performing step S100, the preparation method may further include: fixing the controller 400 on the first side of the carrier through the first connection structure 510. Thus, in step S100, the first stacking structure 201 may be formed on one side of the controller 400 along the second direction (x direction), and the second stacking structure 202 may be formed above the controller 400 and the first stacking structure 201 along the first direction (z direction). Among them, the first connection structure 510 may include but is not limited to at least one of solder balls, solder columns and conductive glue. Compared with conductive glue, solder balls and solder columns significantly improve the data transmission rate and transmission signal quality of the controller 400. The material of the first connection structure 510 may include but is not limited to tin-based alloy or tin.

[0066] In some embodiments, step S300 may include: removing the carrier by laser or thermal stripping process; forming a seed layer (not shown) on the side of the first stacked structure 201 away from the second stacked structure 202 by physical sputtering, magnetron sputtering or evaporation process; patterning the seed layer to form a metal trace; forming a dielectric layer covering the metal trace; forming a solder resist layer on the side of the dielectric layer away from the first stacked structure 201; opening the solder resist layer to expose the pad area of ​​the metal trace, thereby forming the substrate 100. The seed layer may be one layer or multiple layers, and the material of the seed layer may be titanium, copper, silver, tin, nickel, etc. In addition, after executing step S300, a plurality of second connection structures 520 may be formed on the side of the substrate 100 away from the first stacked structure 201, and the second connection structure 520 is electrically connected to the metal trace of the substrate 100. The second connection structure 520 may include, but is not limited to, at least one of a solder ball, a solder column and a conductive adhesive. Compared with the conductive adhesive, the solder ball and the solder column significantly improve the data transmission rate and the quality of the transmission signal of the controller 400. The material of the second connection structure 520 may include, but is not limited to, a tin-based alloy or tin.

[0067] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. As an example, the steps recorded in the disclosure of the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution disclosed in the present application can be achieved, and this document does not limit this.

[0068] The above specific implementations do not constitute a limitation on the protection scope of this application. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of this application should be included in the protection scope of this application.

Claims

1. A semiconductor packaging structure, characterized in that: include: substrate; A plurality of stacking structures are sequentially stacked on one side of the substrate along a first direction; as well as A plastic package body, packaging the plurality of stacked structures on the substrate; Among them, the multiple stacking structures are staggered by a first distance in sequence along the second direction, the stacking structure includes a plurality of chips stacked in sequence along the first direction, the plurality of chips are staggered by a second distance in sequence along the second direction, the first distance is greater than the second distance, and the first direction intersects with the second direction.

2. The semiconductor package structure according to claim 1, wherein: The semiconductor packaging structure also includes a controller encapsulated in the plastic package, the controller is connected to the substrate, the stacking structure closest to the substrate among the multiple stacking structures is located on one side of the controller along the second direction, and the stacking structure farthest from the substrate is located on one side of the controller along the first direction.

3. The semiconductor package structure according to claim 2, wherein: One of the plurality of stack structures is in contact with a surface of the controller away from the substrate.

4. The semiconductor package structure according to claim 1, wherein: A center line of a chip farthest from the substrate and a center line of a chip closest to the substrate among the plurality of chips are respectively located on two sides of a center line of the plastic package along the second direction.

5. The semiconductor package structure according to claim 4, wherein: The chip farthest from the substrate among the plurality of chips is located on one side of the center line of the plastic package body along the second direction.

6. The semiconductor package structure according to any one of claims 1 to 5, wherein: The first distance L1 satisfies: L1≤L0-L3-(n-2)*L2-c; Wherein, L0 is the size of the semiconductor package structure along the second direction, L2 is the second distance, L3 is the size of the chip along the second direction, n is the number of chips in the semiconductor package structure, and c is a preset constant.

7. The semiconductor package structure according to claim 6, wherein: The plastic package body comprises a first side wall and a second side wall which are arranged opposite to each other along the second direction; Among them, c≤c1+c2, c1 is the distance between the first sidewall and the chip closest to the first sidewall among the multiple chips, and c2 is the distance between the second sidewall and the chip closest to the second sidewall among the multiple chips.

8. The semiconductor package structure according to claim 7, wherein: Both c1 and c2 are no greater than 0.5 mm.

9. The semiconductor package structure according to any one of claims 1 to 5, wherein: The first distance is not less than 0.5 mm.

10. The semiconductor package structure according to any one of claims 1 to 5, wherein: The second distance L2 satisfies: 0.12mm≤L2<0.5mm.

11. The semiconductor package structure according to any one of claims 1 to 5, wherein: The number of chips in the stacked structure is not less than 3.

12. The semiconductor package structure according to any one of claims 1 to 5, wherein: Two adjacent chips are connected via a first wire, and the chip closest to the substrate is connected to the substrate via a second wire.

13. A method for preparing a semiconductor packaging structure, characterized in that: include: forming a plurality of stacked structures along a first direction on a first side of the carrier; Forming a plastic package body encapsulating the plurality of stacked structures on a first side of the carrier; as well as replacing the carrier with a substrate; Among them, the multiple stacking structures are staggered by a first distance in sequence along the second direction, the stacking structure includes a plurality of chips stacked in sequence along the first direction, the plurality of chips are staggered by a second distance in sequence along the second direction, the first distance is greater than the second distance, and the first direction intersects with the second direction.

14. The method for preparing a semiconductor package structure according to claim 13, wherein: Before performing the step of forming a plastic package body encapsulating the plurality of stacked structures on one side of the carrier, the preparation method further comprises: The controller is fixed on the first side of the carrier through a first connecting structure.

15. The method for preparing a semiconductor package structure according to claim 14, wherein: The plurality of stacked structures include a first stacked structure and a second stacked structure; Wherein, forming a plurality of stacked structures along a first direction on a first side of the carrier comprises: forming the first stacking structure on one side of the controller along the second direction; and The second stacking structure is formed along the first direction on a side of the first stacking structure and the controller away from the carrier to contact the first stacking structure and the controller.

16. The method for preparing a semiconductor package structure according to any one of claims 13 to 15, wherein: The first distance L1 satisfies: L1≤L0-L3-(n-2)*L2-c; Wherein, L0 is the size of the semiconductor package structure along the second direction, L2 is the second distance, L3 is the size of the chip along the second direction, n is the number of chips in the semiconductor package structure, and c is a preset constant.

17. The method for preparing a semiconductor package structure according to claim 16, wherein: The plastic package body comprises a first side wall and a second side wall which are arranged opposite to each other along the second direction; Among them, c≤c1+c2, c1 is the distance between the first sidewall and the chip closest to the first sidewall among the multiple chips, and c2 is the distance between the second sidewall and the chip closest to the second sidewall among the multiple chips.

18. The method for preparing a semiconductor package structure according to claim 17, wherein: Both c1 and c2 are no greater than 0.5 mm.

19. The method for preparing a semiconductor package structure according to any one of claims 13 to 15, wherein: The first distance is not less than 0.5 mm.

20. The method for preparing a semiconductor package structure according to any one of claims 13 to 15, wherein: The second distance L2 satisfies: 0.12mm≤L2<0.5mm.

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