Transverse plane gate IGBT (Insulated Gate Bipolar Translator) and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, in particular to a transverse plane gate IGBT (Insulated Gate Bipolar Translator) and a preparation method thereof. According to the transverse plane gate IGBT and the preparation method thereof, the first drain electrode is introduced to serve as the cathode of the fly-wheel diode, so that the IGBT forward conductive channel is separated from the fly-wheel conductive channel of the fly-wheel diode, the IGBT forward conductive channel can enter the source electrode only through the second drain electrode and the P + region, the number of hole carriers injected into the P + region is not affected, and the reliability of the IGBT is improved. A freewheeling conductive channel of the freewheeling diode enters the N + region and the first drain through the source and does not enter the P + region to cause other electrical influences, compared with published related patents, the problem that hole carriers injected into the P + region are greatly reduced relative to a normal IGBT device is solved, the process steps are simple, and the cost is low. Only one process step needs to be added, wherein the first drain electrode is introduced to serve as the cathode of the fly-wheel diode, and the process is completely compatible with the existing commercial IGBT preparation process.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a lateral planar gate IGBT and a preparation method thereof. Background Art

[0002] In the field of power electronic device technology, IGBT, as a commonly used power semiconductor, occupies a dominant position in the field of high-power power semiconductors. Due to its special structure, the traditional lateral planar gate IGBT does not have a body diode freewheeling channel and can only connect a diode in parallel as a freewheeling diode, which increases the parasitic parameters between the IGBT and the diode and also increases the power loss of the device.

[0003] At present, one solution to this problem is to integrate a diode freewheeling channel inside the IGBT. Existing patent documents, such as the patent document with publication number CN115101578A, disclose an IGBT device with a reverse recovery diode and a preparation method thereof. By three ion implantations, three regions of N+, N++, and P+ are prepared from the edge to the center at the bottom of the epitaxial wafer, and then a drain metal is prepared at the bottom of the epitaxial wafer. This method integrates a reverse recovery diode in the IGBT, but the three regions of N+, N++, and P+ share a drain metal. When the device is forward-powered, the current flows preferentially from N+ and N++, and the hole carriers injected into the P+ region are greatly reduced relative to normal IGBT devices, which has a huge impact on the forward current carrying capacity of the IGBT; the patent with publication number CN102931216B discloses an IGBT device integrated with Schott The insulated gate bipolar transistor structure of the base diode integrates Schottky metal contacts at the cell spacing at the top of the epitaxial wafer, and prepares N+ and P+ regions at the bottom of the epitaxial wafer. However, the N+ and P+ regions share a drain metal, and there is still a problem that the hole carriers injected into the above-mentioned P+ region will be greatly reduced relative to normal IGBT devices. The patent with publication number CN114373749A discloses a lateral IGBT structure with a freewheeling diode. The structure prepares an isolation layer in the withstand voltage region, and the N+ and P+ regions share a collector. The isolation layer isolates the N+ region from the withstand voltage region. When the IGBT works in the forward direction, the collector current can only flow from the P+ region into the withstand voltage region and the emitter. The structure will not cause the hole carriers injected into the above-mentioned P+ region to be greatly reduced relative to normal IGBT devices, but there is a problem of high technical difficulty in preparing the isolation layer in the withstand voltage region. Summary of the invention

[0004] In view of the above problems, the present invention provides a lateral planar gate IGBT and preparation method which can solve the problem that the hole carriers injected into the P+ region will be greatly reduced compared with normal IGBT devices, and the process steps are simple and fully compatible with the current commercial IGBT preparation process.

[0005] The technical solution of the present invention is: A method for preparing a lateral planar gate IGBT comprises the following steps: Step S100, preparing a first heavily doped body region in an epitaxial wafer having an insulating layer, preparing a plurality of second heavily doped source regions spaced apart in the first heavily doped body region, preparing second heavily doped cathode regions on both sides of the first heavily doped body region, preparing a first heavily doped channel region in the second heavily doped source, and preparing first heavily doped emitter regions on both sides of the first heavily doped body region; Step S200, preparing a gate dielectric on the epitaxial wafer, and preparing polysilicon on the gate dielectric above the first heavily doped channel region; Step S300, depositing an isolation layer on the epitaxial wafer, opening a window to prepare a source metal, wherein the source metal is in contact with the first heavily doped body region and the second heavily doped source region; Step S400, opening a window at the polysilicon, preparing a gate metal, and the gate metal is in contact with the polysilicon; Step S500, opening a window at a first drain window opening position to prepare a first drain; Step S600, a window is opened at the second drain window opening position to prepare the second drain, and the entire device is prepared.

[0006] Specifically, step S100 includes: Step S110, using a photolithography process and a mask to protect the outer area of ​​the first heavily doped body region; forming the first heavily doped body region by a diffusion process or an ion implantation process; Step S120, using a photolithography process and a mask to protect the second heavily doped source region and the outer region of the second heavily doped cathode region; forming a plurality of second heavily doped source regions spaced apart inside the first heavily doped body region and second heavily doped cathode regions on both sides of the first heavily doped body region by a diffusion process or an ion implantation process; Step S130, using a photolithography process and a mask to protect the outer region of the first heavily doped channel region; forming the first heavily doped channel region inside the second heavily doped source region by a diffusion process or an ion implantation process; Step S140, using a photolithography process and a mask to protect the outer area of ​​the first heavily doped emitter region; forming the first heavily doped emitter region on both sides of the first heavily doped body region through a diffusion process or an ion implantation process.

[0007] Specifically, step S200 includes: Step S210, preparing a gate dielectric on the epitaxial wafer using a thermal oxidation technique; Step S220 , using a mask to protect the outer region of the first heavily doped channel region through a photolithography process, and preparing polysilicon on the gate dielectric above the first heavily doped channel region through chemical vapor deposition.

[0008] Specifically, step S300 includes: Step S310, preparing an isolation layer by chemical vapor deposition, protecting the outer area of ​​the source metal by a mask through a photolithography process, and opening a window by an etching process; Step S320, using a stripping process or an etching process to prepare a source metal at the window, and the source metal is in contact with the first heavily doped body region and the second heavily doped source region.

[0009] Specifically, step S400 includes: Step S410, using a photolithography process, using a mask to protect the outer area of ​​the polysilicon window, and using an etching process to open a window in the polysilicon; Step S420: using a stripping process or an etching process, a gate metal is prepared at the window, and the gate metal contacts the polysilicon.

[0010] Specifically, step S500 includes: Step S510, using a mask to protect the outer area of ​​the first drain window through a photolithography process, and opening a window at the first drain window through an etching process; Step S520, preparing a first drain at the first drain window by a stripping process or an etching process.

[0011] Specifically, step S600 includes: Step S610, using a mask to protect the outer area of ​​the second drain window through a photolithography process, and opening a window at the second drain window through an etching process; Step S620, preparing a second drain at the second drain window by a stripping process or an etching process.

[0012] A lateral planar gate IGBT, comprising an epitaxial wafer, a gate dielectric and an isolation layer arranged in sequence from bottom to top; The epitaxial wafer is provided with: An insulating layer, disposed in the epitaxial wafer; A first heavily doped body region extending downward from a top surface of the epitaxial wafer; A pair of second heavily doped source regions are provided, extending downward from the top surface of the first heavily doped body region; A pair of second heavily doped cathode regions are provided, each extending downward from the top surface of the epitaxial wafer; A pair of first heavily doped channel regions are provided, each extending downward from a top surface of the second heavily doped source region; A pair of first heavily doped emitter regions are provided, extending downward from the end of the top surface of the epitaxial wafer; A pair of polysilicon is provided, each of which is located on the top surface of the gate dielectric above the first heavily doped channel region; A source metal extending downward from the top surface of the isolation layer into the first heavily doped body region and the second heavily doped source region; A pair of gate metals are provided, each extending downward from the top surface of the isolation layer into the polysilicon; A pair of first drain electrodes are provided, each extending downward from the top surface of the isolation layer and connected to the second heavily doped cathode region; A pair of second drain electrodes are provided, each extending downward from the top surface of the isolation layer to the first heavily doped emitter region.

[0013] Specifically, a gap is provided between the bottom surface of the first heavily doped body region and the insulating layer.

[0014] Specifically, the bottom surface of the second heavily doped cathode region and the bottom surface of the second heavily doped source region are in the same plane.

[0015] The present invention provides a lateral planar gate IGBT and a preparation method thereof, wherein a first drain electrode is introduced as the cathode of a freewheeling diode, so that the forward conductive channel of the IGBT and the freewheeling conductive channel of the freewheeling diode are separated, and the forward conductive channel of the IGBT can only enter the source electrode through the second drain electrode and the P+ region, which does not affect the number of hole carriers injected into the P+ region, and the freewheeling conductive channel of the freewheeling diode enters the N+ region and the first drain electrode through the source electrode, and will not enter the P+ region to cause other electrical effects. Compared with the related patents that have been published, the present patent will not cause the problem that the hole carriers injected into the P+ region will be greatly reduced relative to a normal IGBT device, and the process steps are simple, and only one process step needs to be added: introducing the first drain electrode as the cathode of the freewheeling diode, which is fully compatible with the current commercial IGBT preparation process. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a process flow chart of the present invention; Figure 2 It is a schematic diagram of the cross-sectional structure of an epitaxial wafer including an insulating layer; Figure 3 is a schematic diagram of the cross-sectional structure of preparing the first heavily doped body region; Figure 4 It is a schematic diagram of the cross-sectional structure of preparing the second heavily doped source region and the second heavily doped cathode region; Figure 5 is a schematic diagram of the cross-sectional structure of preparing the first heavily doped channel region; Figure 6 It is a schematic diagram of the cross-sectional structure of preparing the first heavily doped emitter region; Figure 7 It is a schematic diagram of the cross-sectional structure of preparing polycrystalline silicon; Figure 8 is a schematic diagram of the cross-sectional structure of the preparation isolation layer; Fig. 9 2 is a schematic diagram of the cross-sectional structure of the source trench; Fig.10 It is a schematic diagram of the cross-sectional structure of the source metal; Fig.11 Schematic diagram of the gate window cross-section structure; Fig.12 It is a schematic diagram of the cross-sectional structure of the gate metal preparation; Fig.13 is a schematic diagram of a cross-sectional structure of a first drain window; Fig.14 is a schematic diagram of the cross-sectional structure of preparing the first drain electrode; Fig.15 is a schematic diagram of a cross-sectional structure of a second drain window; Fig.16 is a schematic diagram of the cross-sectional structure of preparing the second drain; In the figure, 1 is the epitaxial wafer, 2 is the insulating layer, 3 is the first heavily doped body region, 4 is the first heavily doped emitter region, 5 is the second heavily doped source region, 6 is the first heavily doped channel region, 7 is the gate dielectric, 8 is polysilicon, 9 is the isolation layer, 10 is the source trench, 11 is the source metal, 12 is the gate window, 13 is the gate metal, 14 is the first drain window, 15 is the first drain, 16 is the second drain window, 17 is the second drain, and 18 is the second heavily doped cathode region. DETAILED DESCRIPTION

[0017] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0018] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0019] Reference below Figure 1-16 describe the invention; Step S100, preparing a first heavily doped body region 3 in the epitaxial wafer 1 containing the insulating layer 2, preparing a plurality of second heavily doped source regions 5 spaced apart in the first heavily doped body region 3, preparing second heavily doped cathode regions 18 on both sides of the first heavily doped body region 3, preparing a first heavily doped channel region 6 in the second heavily doped source 5, and preparing first heavily doped emitter regions 4 on both sides of the first heavily doped body region 3, referring to Figure 2 , 3 , 4, 5, 6; Step S110, using a photolithography process and a mask to protect the outer area of ​​the first heavily doped body region 3; forming the first heavily doped body region 3 by a diffusion process or an ion implantation process; Step S120, using a photolithography process and a mask to protect the second heavily doped source region 5 and the second heavily doped cathode region 18 outside the region; forming a plurality of second heavily doped source regions 5 arranged at intervals inside the first heavily doped body region 3 and second heavily doped cathode regions 18 on both sides of the first heavily doped body region 3 by a diffusion process or an ion implantation process; Step S130, using a photolithography process and a mask to protect the outer region of the first heavily doped channel region 6; forming the first heavily doped channel region 6 inside the second heavily doped source region 5 by a diffusion process or an ion implantation process; Step S140, using a photolithography process and a mask to protect the outer area of ​​the first heavily doped emitter region 4; forming the first heavily doped emitter region 4 on both sides of the first heavily doped body region 3 by a diffusion process or an ion implantation process; Correspondingly, the epitaxial wafer 1 of the present embodiment is a Si-based SOI epitaxial wafer, the doping type is the second doping, the first doping region is a P region, the second doping region is an N region, the thickness of the epitaxial wafer 1 is 100-2000um, the thickness of the first heavily doped body region 3 is 1-10um, the width is 1-10um, the thickness of the second heavily doped source region 5 is set to 0.5-5um, the width is set to 0.5-5um, and the spacing distance is 0.5-5um, the thickness of the second heavily doped cathode region 18 is set to 0.5-5um, the width is set to 0.5-5um, the thickness of the first heavily doped channel region 6 is equal to that of the second heavily doped source region 5, and the width is set to 0.25-2.5um, the thickness of the first heavily doped emitter region 4 is 1-100um, the width is set to 1-10um, and the doping concentration range of the N-type doping is 1e 14 .cm -3 -1e 20 .cm -3 , the doping concentration range of P-type doping is 1e 15 .cm -3 -1e 20 .cm -3 , the relevant parameter settings are related to the electrical design of the device; In this embodiment, the thickness of the epitaxial wafer 1 is 300um, the thickness of the first heavily doped body region 3 is 2um, the width is 5um, and the doping concentration is 3e 18 .cm -3 The second heavily doped source region 5 has a thickness of 1um, a width of 2um, an interval width of 1um, and a doping concentration of 1e 19. cm -3The second heavily doped cathode region 18 has a thickness of 1um and a width of 2um. The first heavily doped channel region 6 has a thickness of 1um and a width of 1um. The doping concentration is 1e 18. cm -3 The first heavily doped emitter region 4 has a thickness of 8um, a width of 4um, and a doping concentration of 5e 19 .cm -3 , a first heavily doped body region 3 , a second heavily doped source region 5 , a second heavily doped cathode region 18 , a first heavily doped channel region 6 , and a first heavily doped emitter region 4 are prepared using an ion implantation process.

[0020] Step S200, preparing a gate dielectric 7 on the epitaxial wafer 1, and preparing polysilicon 8 on the gate dielectric 7 above the first heavily doped channel region 6, referring to Figure 7 As shown; Step S210, preparing a gate dielectric 7 on the epitaxial wafer 1 using a thermal oxidation technique; Step S220, using a mask to protect the outer area of ​​the first heavily doped channel region 6 through a photolithography process, and preparing polysilicon 8 on the gate dielectric 7 above the first heavily doped channel region 6 through chemical vapor deposition; Accordingly, the gate dielectric 7 is made of SiO2, with a thickness of 40-500nm, and the thickness of polysilicon 8 is set to 100nm-5um; In this embodiment, 80 nm SiO2 is prepared as the gate dielectric 7 by using thermal oxidation technology, and 500 nm polysilicon 8 is prepared by using chemical vapor deposition.

[0021] Step S300, depositing an isolation layer 9 on the epitaxial wafer, opening a window to prepare a source metal 11, the source metal 11 is in contact with the first heavily doped body region 3 and the second heavily doped source region 5, refer to Figure 8 , 9 , as shown in 10; Step S310, preparing the isolation layer 9 by chemical vapor deposition, using a mask to protect the outer area of ​​the source metal 11 through a photolithography process, and using an etching process to open a window; Step S320, using a stripping process or an etching process to prepare a source metal 11 at the opening, the source metal 11 is in contact with the first heavily doped body region 3 and the second heavily doped source region 5; Accordingly, the isolation layer 9 plays a protective role, and is made of SiO2 or Si3N4, with a thickness set to 10-5000nm. The ICP dry etching is used to open the window, and the source window 10 extends downward from the top surface of the isolation layer 9 to the inside of the first heavily doped body region 3. The source metal 11 contacts the first heavily doped body region 3 and the second heavily doped source region 5 to form an ohmic contact. The relevant parameter settings are related to the device electrical design; In this embodiment, Si3N4 is used as the isolation layer 9, the thickness is set to 200nm, ICP dry etching is used to open the window, the source window 10 has a depth of 500nm, and a stripping process is used to prepare a 500nm thick Ti / Al two-layer metal as the source metal 11.

[0022] Step S400, opening a window at the polysilicon 8, preparing a gate metal 13, the gate metal 13 is in contact with the polysilicon 8, refer to Fig.11 , 12 As shown; Step S410, using a photolithography process, using a mask to protect the outer area of ​​the polysilicon 8 where the window is opened, and using an etching process to open a window in the polysilicon 8; Step S420, using a stripping process or an etching process to prepare a gate metal 13 at the opening, the gate metal 13 is in contact with the polysilicon 8; Correspondingly, the window depth is greater than the thickness of the isolation layer 9, and the gate metal 13 extends downward from the top surface of the isolation layer 9 into the polysilicon 8, contacts the polysilicon 8 and forms an ohmic contact; In this embodiment, a window is opened by an ICP dry etching process with a window depth of 500 nm. A stripping process is used to prepare a 500 nm thick Ti / Al two-layer metal as the gate metal 13 to form an ohmic contact with the polysilicon 8.

[0023] Step S500, opening a window at the position of the first drain window 14, preparing the first drain 15, referring to Fig.13 , 14 As shown; Step S510, using a mask to protect the outer area of ​​the first drain window 14 through a photolithography process, and opening a window at the first drain window 14 through an etching process; Step S520, preparing the first drain electrode 15 at the first drain electrode window 14 by a stripping process or an etching process; Correspondingly, the first drain window 14 extends downward from the top surface of the isolation layer 9 to the inside of the second heavily doped cathode region 18, the window width is smaller than the width of the second heavily doped cathode region 18, and the first drain 15 forms an ohmic contact with the second heavily doped cathode region 18; In this embodiment, an etching process is used to open a window at the first drain window 14, with a window depth of 0.5um and a window width of 1.5um. A stripping process is used to prepare a 0.5um thick Ti / Al two-layer metal as the first drain 15 to form an ohmic contact with the second heavily doped cathode region 18.

[0024] Step S600, a window is opened at the position of the second drain opening window 16, and a second drain 17 is prepared. The entire device is prepared. Fig.15 , 16 As shown; Step S610, using a mask to protect the outer area of ​​the second drain window 16 through a photolithography process, and opening a window at the second drain window 16 through an etching process; Step S620, preparing a second drain electrode 17 at the second drain electrode opening 16 by a stripping process or an etching process; Correspondingly, the window depth at the second drain window 16 is greater than the isolation layer 9, less than the sum of the isolation layer 9 and the first heavily doped emitter region 4, the window width is less than the width of the first heavily doped emitter region 4, and the second drain 17 extends downward from the top surface of the first isolation layer 9 to the inside of the first heavily doped emitter region 4, forming an ohmic contact with the first heavily doped emitter region 4; In this embodiment, an etching process is used to open a window at the second drain opening 16, with a window depth of 6um and a window width of 2um. A stripping process is used to prepare a 6um thick Ti / Al two-layer metal as the second drain 17 to form an ohmic contact with the first heavily doped emitter region 4.

[0025] A lateral planar gate IGBT, comprising an epitaxial wafer 1, a gate dielectric 7 and an isolation layer 9 arranged in sequence from bottom to top; The epitaxial wafer 1 is provided with: An insulating layer 2 is arranged in the epitaxial wafer 1; A first heavily doped body region 3 extends downward from the top surface of the epitaxial wafer 1, and a gap is provided between the bottom surface of the first heavily doped body region 3 and the insulating layer 2; A pair of second heavily doped source regions 5 are provided, extending downward from the top surface of the first heavily doped body region 3 and having a spacing from the bottom surface of the first heavily doped body region 3; A pair of second heavily doped cathode regions 18 are provided, each extending downward from the top surface of the epitaxial wafer 1, and the bottom surface thereof is in the same plane as the bottom surface of the second heavily doped source region 5; A pair of first heavily doped channel regions 6 are provided, each extending downward from the top surface of the second heavily doped source region 5, and the bottom surface of each first heavily doped channel region 6 is in the same plane as the bottom surface of the second heavily doped source region 5; A pair of first heavily doped emitter regions 4 are provided, extending downward from the end of the top surface of the epitaxial wafer 1, with the bottom surface thereof being located between the top surface of the insulating layer 2 and the bottom surface of the first heavily doped body region 3, and located outside the second heavily doped cathode region 18; A pair of polysilicon 8 is provided, each of which is located on the top surface of the gate dielectric 7 above the first heavily doped channel region 6; The isolation layer 9 is respectively arranged on the top surface of the gate dielectric 7 and the top surface of the polysilicon 8; The source metal 11 extends downward from the top surface of the isolation layer 9 into the first heavily doped body region 3 and the second heavily doped source region 5 to form an ohmic contact with the first heavily doped body region 3 and the second heavily doped source region 5; A pair of gate metals 13 are provided, each extending downward from the top surface of the isolation layer 9 into the polysilicon 8 to form an ohmic contact with the polysilicon 8; A pair of first drain electrodes 15 are provided, each extending downward from the top surface of the isolation layer 9 and connected to the second heavily doped cathode region 18, and the cross-sectional width thereof is smaller than the width of the second heavily doped cathode region 18, and forms an ohmic contact with the second heavily doped cathode region 18; A pair of second drain electrodes 17 are provided, each extending downward from the top surface of the isolation layer 9 to the first heavily doped emitter region 4 , and the side surfaces and bottom surfaces thereof are spaced apart from the first heavily doped emitter region 4 , so that the second drain electrode 17 forms an ohmic contact with the first heavily doped emitter region 4 .

[0026] The epitaxial wafer 1 in this case is an SOI epitaxial wafer with an insulating layer 2 introduced inside. The epitaxial wafer 1 is of the second doping type, and the material can be Si, SiC, GaN and other commonly used semiconductor device epitaxial materials; the first doping region and the second doping region have opposite doping types, which can be a P region and an N region or an N region and a P region.

[0027] The present invention provides a lateral planar gate IGBT and a preparation method thereof, wherein a first drain electrode is introduced as the cathode of a freewheeling diode, so that the forward conductive channel of the IGBT and the freewheeling conductive channel of the freewheeling diode are separated, and the forward conductive channel of the IGBT can only enter the source electrode through the second drain electrode and the P+ region, which does not affect the number of hole carriers injected into the P+ region, and the freewheeling conductive channel of the freewheeling diode enters the N+ region and the first drain electrode through the source electrode, and will not enter the P+ region to cause other electrical effects. Compared with the related patents that have been published, the present patent will not cause the problem that the hole carriers injected into the P+ region will be greatly reduced relative to a normal IGBT device, and the process steps are simple, and only one process step needs to be added: introducing the first drain electrode as the cathode of the freewheeling diode, which is fully compatible with the current commercial IGBT preparation process.

[0028] Regarding the contents disclosed in this case, there are a few points that need to be explained: (1) The drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design; (2) In the absence of conflict, the embodiments and features of the embodiments disclosed in this case may be combined with each other to obtain new embodiments; The above are only specific implementation methods disclosed in this case, but the protection scope of the present disclosure is not limited thereto. The protection scope disclosed in this case should be based on the protection scope of the claims.

Claims

1. A method for preparing a lateral planar gate IGBT, characterized in that: The following steps are involved: Step S100, preparing a first heavily doped body region (3) in an epitaxial wafer (1) containing an insulating layer (2), preparing a plurality of second heavily doped source regions (5) arranged at intervals in the first heavily doped body region (3), preparing second heavily doped cathode regions (18) on both sides of the first heavily doped body region (3), preparing a first heavily doped channel region (6) in the second heavily doped source region (5), and preparing first heavily doped emitter regions (4) on both sides of the first heavily doped body region (3); Step S200, preparing a gate dielectric (7) on the epitaxial wafer (1), and preparing polysilicon (8) on the gate dielectric (7) above the first heavily doped channel region (6); Step S300, depositing an isolation layer (9) on the epitaxial wafer, opening a window to prepare a source metal (11), wherein the source metal (11) is in contact with the first heavily doped body region (3) and the second heavily doped source region (5); Step S400, opening a window at the polysilicon (8), preparing a gate metal (13), and the gate metal (13) is in contact with the polysilicon (8); Step S500, opening a window at the position of the first drain electrode opening window (14) to prepare the first drain electrode (15); Step S600, a window is opened at the position of the second drain window (16), and a second drain (17) is prepared, and the entire device is prepared.

2. The method for preparing a lateral planar gate IGBT according to claim 1, characterized in that: Step S100 includes: Step S110, using a photolithography process and a mask to protect the outer area of ​​the first heavily doped body region (3); forming the first heavily doped body region (3) through a diffusion process or an ion implantation process; Step S120, using a photolithography process and a mask to protect the outer regions of the second heavily doped source region (5) and the second heavily doped cathode region (18); forming a plurality of second heavily doped source regions (5) arranged at intervals inside the first heavily doped body region (3) and second heavily doped cathode regions (18) on both sides of the first heavily doped body region (3) through a diffusion process or an ion implantation process; Step S130, using a photolithography process and a mask to protect the outer region of the first heavily doped channel region (6); forming the first heavily doped channel region (6) inside the second heavily doped source region (5) through a diffusion process or an ion implantation process; Step S140, adopting a photolithography process and using a mask to protect the outer region of the first heavily doped emitter region (4); and forming the first heavily doped emitter region (4) on both sides of the first heavily doped body region (3) through a diffusion process or an ion implantation process.

3. The method for preparing a lateral planar gate IGBT according to claim 1, characterized in that: Step S200 includes: Step S210, preparing a gate dielectric (7) on the epitaxial wafer (1) using a thermal oxidation technique; Step S220: Protect the outer region of the first heavily doped channel region (6) using a mask through a photolithography process, and prepare polysilicon (8) on the gate dielectric (7) above the first heavily doped channel region (6) through chemical vapor deposition.

4. The method for preparing a lateral planar gate IGBT according to claim 1, characterized in that: Step S300 includes: Step S310, preparing an isolation layer (9) by chemical vapor deposition, protecting the outer region of the source metal (11) by using a mask through a photolithography process, and opening a window by an etching process; Step S320, using a stripping process or an etching process to prepare a source metal (11) at the opening, wherein the source metal (11) is in contact with the first heavily doped body region (3) and the second heavily doped source region (5).

5. The method for preparing a lateral planar gate IGBT according to claim 1, characterized in that: Step S400 includes: Step S410, using a photolithography process and a mask to protect the outer area of ​​the polysilicon (8) where the window is opened, and using an etching process to open a window in the polysilicon (8); Step S420: using a stripping process or an etching process to prepare a gate metal (13) at the opening, the gate metal (13) being in contact with the polysilicon (8).

6. The method for preparing a lateral planar gate IGBT according to claim 1, characterized in that: Step S500 includes: Step S510, using a mask to protect the outer area of ​​the first drain window (14) through a photolithography process, and opening a window at the first drain window (14) through an etching process; Step S520, preparing a first drain electrode (15) at the first drain electrode window (14) by a stripping process or an etching process.

7. The method for preparing a lateral planar gate IGBT according to claim 1, characterized in that: Step S600 includes: Step S610, using a mask to protect the outer area of ​​the second drain opening (16) through a photolithography process, and opening a window at the second drain opening (16) through an etching process; Step S620, preparing a second drain electrode (17) at the second drain electrode window (16) by a stripping process or an etching process.

8. A lateral planar gate IGBT, prepared by the method for preparing a lateral planar gate IGBT according to claim 1, characterized in that: It comprises an epitaxial wafer (1), a gate dielectric (7) and an isolation layer (9) which are arranged in sequence from bottom to top; The epitaxial wafer (1) is provided with: An insulating layer (2) is arranged inside the epitaxial wafer (1); A first heavily doped body region (3) extending downward from the top surface of the epitaxial wafer (1); A pair of second heavily doped source regions (5) extending downward from the top surface of the first heavily doped body region (3); A pair of second heavily doped cathode regions (18) are provided, each extending downward from the top surface of the epitaxial wafer (1); A pair of first heavily doped channel regions (6) are provided, each extending downward from the top surface of the second heavily doped source region (5); A pair of first heavily doped emitter regions (4) are provided, extending downward from the end of the top surface of the epitaxial wafer (1); A pair of polysilicon (8) are provided, each located on a top surface of the gate dielectric (7) above the first heavily doped channel region (6); A source metal (11) extending downward from the top surface of the isolation layer (9) into the first heavily doped body region (3) and the second heavily doped source region (5); A pair of gate metals (13) are provided, each extending downward from the top surface of the isolation layer (9) to the inside of the polysilicon (8); A pair of first drain electrodes (15) are provided, each extending downward from the top surface of the isolation layer (9) and connected to the second heavily doped cathode region (18); A pair of second drain electrodes (17) are provided, each extending downward from the top surface of the isolation layer (9) to the first heavily doped emitter region (4).

9. The lateral planar gate IGBT according to claim 8, characterized in that: A gap is provided between the bottom surface of the first heavily doped body region (3) and the insulating layer (2).

10. The lateral planar gate IGBT according to claim 8, characterized in that: The bottom surface of the second heavily doped cathode region (18) and the bottom surface of the second heavily doped source region (5) are on the same plane.

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