Preparation method of power device and power device
By forming an epitaxial layer on the first surface of the substrate and etching to form a trench-like surface, and then forming a frontal structure including a conductive layer and a stable structure thereon, the problem of wafer warping is solved and the power loss of the device is reduced.
Patent Information
- Application Number
- CN202411921040.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-25
- Publication Date
- 2025-03-28
AI Technical Summary
In deep trench processes, wafer warping leads to poor photolithographic accuracy and increased risk of wafer rupture, and how to solve this problem has become an urgent problem.
By forming an epitaxial layer on the first surface of the substrate and etching it to form a plurality of trenches thereon, a trench-like surface is obtained, and a frontal structure is formed on the trench-like surface, including a conductive layer and a stable structure. The stable structure is composed of a passivation layer and a metal layer with through-holes, thereby increasing the thickness of the front surface of the substrate and reducing the risk of warping.
By increasing the thickness of the front surface of the substrate, the risk of wafer warping is effectively reduced, and by thinning the back surface of the wafer to 15~30 um, the resistance between the drain and source of the device in the on state is reduced, thereby reducing the power loss of the device.
Smart Images
Figure CN119730285A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of power semiconductor devices, and in particular to a method for preparing a power device and a power device. Background Art
[0002] Deep trench processes are used in the preparation of shielded gate power devices, insulated gate bipolar transistors, and super junction power devices. In the manufacturing process of the above-mentioned devices with deep trench processes, the deep trenches will cause serious warping of the wafer. The existence of warping will change the shape of the wafer, which will deteriorate the lithography accuracy during lithography. In addition, the lithography machine will not be able to achieve good adsorption of the wafer during the lithography process, and the lithography process cannot be performed. At the same time, the existence of warping will cause the wafer itself to produce greater stress and easily break the wafer during transportation or dicing. Therefore, how to solve the wafer warping caused by the preparation of deep trench structures on the front of the wafer has become an urgent problem to be solved. Summary of the invention
[0003] The present application provides a method for preparing a power device and a power device, which can solve the problem of wafer warping caused by preparing a deep groove structure on the front side of the wafer.
[0004] In order to achieve the above purpose, this application adopts the following technical solutions: In a first aspect of an embodiment of the present application, a method for preparing a power device is provided, the method comprising: forming an epitaxial layer on a first surface of the substrate; After etching a plurality of grooves on the first surface of the epitaxial layer, a grooved surface is obtained; forming a front structure on the grooved surface, the front structure comprising: a conductive layer on the grooved surface, at least one stable structure on the conductive layer; Wherein, the conductive layer includes: a gate region and a source region, and one of the stable structures includes: a passivation layer with a through hole and a metal layer located on the passivation layer; The substrate includes a second surface opposite to the first surface, and a drain is formed on the second surface.
[0005] As a possible implementation manner, forming a front structure on the grooved surface includes: The thickness of the front structure is adjusted by adjusting the number of the stabilizing structures, and the thickness of the front structure after adjustment is 30-180 um.
[0006] As a possible implementation manner, forming a front structure on the grooved surface includes: The thickness of the front structure is adjusted by adjusting the thickness of the passivation layer in the stable structure, and the thickness of the front structure after adjustment is 30-180 um.
[0007] As a possible implementation manner, before forming the epitaxial layer on the first surface of the substrate, the method further includes: The substrate is thinned, and the thickness of the substrate after thinning is 15-30 um.
[0008] As a possible implementation manner, forming a front structure on the grooved surface includes: After the grooved surface is oxidized to form an oxide layer, a target grooved surface is obtained; After filling the grooves of the target groove-shaped surface with polysilicon, an epitaxial structure is obtained; The front structure is formed on the epitaxial structure.
[0009] As a possible implementation manner, forming the front structure on the epitaxial structure includes: After etching the groove position in the epitaxial structure, an etched surface is obtained; After forming an isolation layer at the groove position of the etched surface, an isolation surface is obtained; After forming a gate oxide layer on the isolation surface, and filling polysilicon at the groove position on the gate oxide layer, a plurality of gate regions are formed; forming a source region under the gate oxide layer to obtain the conductive layer; A stabilizing structure is formed on the conductive layer.
[0010] As a possible implementation manner, if the number of the stable structures is 2, forming the stable structure on the conductive layer includes: After forming a first passivation layer on the conductive layer, performing hole etching on the first passivation layer at the position of the second conductive type body region, and then forming a first metal layer on the first passivation layer; A second passivation layer is formed on the metal layer, and after hole etching is performed on the second passivation layer, a second metal layer is formed on the second passivation layer.
[0011] As a possible implementation manner, forming a source region under the gate oxide layer includes: A first conductive type body region is first formed in the substrate under the gate oxide layer by ion implantation, and then a second conductive type doped region is formed on the first conductive type body region.
[0012] As a possible implementation manner, the first conductivity type is N-type, and the second conductivity type is P-type, or the first conductivity type is P-type, and the second conductivity type is N-type.
[0013] In a second aspect of an embodiment of the present application, a power device is provided, the power device comprising: a substrate comprising a first surface and a second surface that are opposite to each other; An epitaxial layer, the epitaxial layer is located on the first surface of the substrate, and the first surface of the epitaxial layer includes a grooved surface formed by a plurality of grooves; A front structure, the front structure comprising: a conductive layer located on the grooved surface, at least one stable structure located on the conductive layer, wherein the conductive layer comprises: a gate region, a source region and a first conductive type body region, and one of the stable structures comprises: a passivation layer having a through hole and a metal layer located on the passivation layer; The drain is located on the second surface of the substrate.
[0014] The beneficial effects brought by the technical solution provided by the embodiment of the present application include at least: The method for preparing a power device provided in an embodiment of the present application comprises the steps of forming an epitaxial layer on a first surface of a substrate; etching a plurality of grooves on the first surface of the epitaxial layer to obtain a grooved surface; forming a front structure on the grooved surface, the front structure comprising: a conductive layer located on the grooved surface, and at least one stable structure located on the conductive layer; wherein the conductive layer comprises: a gate region and a source region, and one of the stable structures comprises: a passivation layer having a through hole and a metal layer located on the passivation layer; the substrate comprises a second surface opposite to the first surface, and a drain is formed on the second surface, so that by adding a stable structure on the front side of the substrate, the thickness of the front side of the substrate can be increased, thereby obtaining a thicker wafer, which can solve the problem of wafer warping caused by preparing a deep groove structure on the front side of the wafer, and in addition, since the thickness of the front side of the substrate is increased, the back side of the wafer can be thinned to 15-30 um, which can also reduce the resistance between the drain and the source of the device in the on state, thereby reducing the power loss of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 A flow chart of a method for preparing a power device provided in an embodiment of the present application; Figure 2 A schematic diagram of a longitudinal section of a power device provided in an embodiment of the present application.
[0016] Reference numerals: 1- oxide layer, 2- polysilicon, 3- gate polysilicon, 4- source region, 5- isolation layer, 6- gate oxide layer, 7- first passivation layer, 8- first metal layer, 9- second passivation layer, 10- second metal layer, 11- drain. DETAILED DESCRIPTION
[0017] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0018] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
[0019] It should be understood that when an element or layer is referred to as being “on,” “adjacent to,” “connected to,” or “coupled to” another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly adjacent to,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers.
[0020] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present application in a schematic manner, and therefore the illustrations only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0021] The present application provides a method for preparing a power device, such as Figure 1 As shown, the method comprises the following steps: Step 101: Form an epitaxial layer on a first surface of a substrate.
[0022] The substrate is used as a carrier of the power device and mainly plays a supporting role. The substrate can be made of silicon, germanium or germanium silicon. In this embodiment, the substrate is preferably made of silicon, which is the most common, cheap and stable semiconductor material.
[0023] The substrate has a first surface and a second surface opposite to each other, wherein the first surface can be understood as the front side of the substrate, and the second surface can be understood as the back side of the substrate. The gate region and the source region of the power device are formed on the first surface. The drain of the power device is formed on the second surface of the substrate.
[0024] Step 102, after etching a plurality of grooves on the first surface of the epitaxial layer, a grooved surface is obtained; The grooves on the first surface are filled with silicon dioxide, the depth of the grooves is 2-10 um, and the opening width of the grooves is 0.5-1 um.
[0025] Step 103, forming a front structure on the grooved surface, the front structure comprising: a conductive layer located on the grooved surface, and at least one stable structure located on the conductive layer; wherein the conductive layer comprises: a gate region and a source region, and one of the stable structures comprises: a passivation layer having a through hole and a metal layer located on the passivation layer.
[0026] Step 104: The substrate includes a second surface opposite to the first surface, and a drain is formed on the second surface.
[0027] Optionally, the process of forming a drain electrode on the second surface in step 104 may include: forming a conductive layer on the second surface of the substrate, and using the conductive layer as the drain electrode of the power device.
[0028] As a possible implementation manner, the process of forming a front structure on the grooved surface in step 103 may include: The thickness of the front structure is adjusted by adjusting the number of the stabilizing structures, and the thickness of the front structure after adjustment is 30-180 um.
[0029] As another possible implementation, the process of forming a front structure on the grooved surface in step 103 may include: The thickness of the front structure is adjusted by adjusting the thickness of the passivation layer in the stable structure, and the thickness of the front structure after adjustment is 30-180 um.
[0030] In addition, the number of the stabilizing structures and the thickness of the passivation layer in the stabilizing structures may be adjusted simultaneously, thereby adjusting the thickness of the front structure.
[0031] Optionally, before forming the epitaxial layer on the first surface of the substrate, the method further includes: thinning the substrate, and the thickness of the substrate after thinning is 15-30 um.
[0032] Specifically, the process of forming the front structure on the grooved surface in step 103 includes: After the grooved surface is oxidized to form an oxide layer, a target grooved surface is obtained; After filling the grooves of the target groove-shaped surface with polysilicon, an epitaxial structure is obtained; The front structure is formed on the epitaxial structure.
[0033] It should be noted that the polysilicon filled in the grooves of the target groove-shaped surface can be used as a shielding gate of a power device.
[0034] Further, forming the front structure on the epitaxial structure includes: After etching the groove position in the epitaxial structure, an etched surface is obtained; After forming an isolation layer at the groove position of the etched surface, an isolation surface is obtained; After forming a gate oxide layer on the isolation surface, and filling polysilicon at the groove position on the gate oxide layer, a plurality of gate regions are formed; forming a source region under the gate oxide layer to obtain the conductive layer; The stabilizing structure is formed on the conductive layer.
[0035] For example, if the number of the stable structures is 2, forming the stable structure on the conductive layer includes: After forming a first passivation layer on the conductive layer, performing hole etching on the first passivation layer at the position of the second conductive type body region, and then forming a first metal layer on the first passivation layer; A second passivation layer is formed on the metal layer, and after hole etching is performed on the second passivation layer, a second metal layer is formed on the second passivation layer.
[0036] It should be noted that a plurality of etching holes are formed by etching in the passivation layer, and each etching hole is connected to a corresponding source region.
[0037] In addition, the forming of a source region under the gate oxide layer comprises: A first conductive type body region is first formed in the substrate under the gate oxide layer by ion implantation, and then a second conductive type doped region is formed on the first conductive type body region.
[0038] The first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.
[0039] The method for preparing a power device provided in an embodiment of the present application comprises the steps of forming an epitaxial layer on a first surface of a substrate; etching a plurality of grooves on the first surface of the epitaxial layer to obtain a grooved surface; forming a front structure on the grooved surface, the front structure comprising: a conductive layer located on the grooved surface, and at least one stable structure located on the conductive layer; wherein the conductive layer comprises: a gate region and a source region, and one of the stable structures comprises: a passivation layer having a through hole and a metal layer located on the passivation layer; the substrate comprises a second surface opposite to the first surface, and a drain is formed on the second surface, so that by adding a stable structure on the front side of the substrate, the thickness of the front side of the substrate can be increased, thereby obtaining a thicker wafer, which can solve the problem of wafer warping caused by preparing a deep groove structure on the front side of the wafer, and in addition, since the thickness of the front side of the substrate is increased, the back side of the wafer can be thinned to 15-30 um, which can also reduce the resistance between the drain and the source of the device in the on state, thereby reducing the power loss of the device.
[0040] The present application embodiment provides a power device, which is prepared by using any one of the power device preparation methods provided in the present application embodiment. Figure 2 As shown, the power device includes: a substrate comprising a first surface and a second surface that are opposite to each other; An epitaxial layer, the epitaxial layer is located on the first surface of the substrate, and the first surface of the epitaxial layer includes a grooved surface formed by a plurality of grooves; A front structure, the front structure comprising: a conductive layer located on the grooved surface, at least one stable structure located on the conductive layer, wherein the conductive layer comprises: a gate region and a source region 4, and one of the stable structures comprises: a passivation layer having a through hole and a metal layer located on the passivation layer; The drain electrode 11 is located on the second surface of the substrate.
[0041] in, Figure 2 An example is given in which a power device includes two stable structures.
[0042] In one embodiment, the power device further includes: A target grooved surface, wherein the target grooved surface is obtained after the grooved surface is oxidized to form an oxide layer 1; An epitaxial structure is obtained by filling polysilicon 2 in the grooves in the target groove-shaped surface.
[0043] The front structure is located on the epitaxial structure.
[0044] In one embodiment, the front structure comprises: An etching surface, wherein the etching surface is obtained by etching the groove position in the epitaxial structure; An isolation surface, wherein the isolation surface is obtained after forming an isolation layer 5 at the groove position of the etched surface; A plurality of gate regions, wherein the gate regions are obtained after a gate oxide layer 61 is formed on the isolation surface and a gate polysilicon 3 is filled at a groove position on the gate oxide layer 6; A conductive layer, the conductive layer comprising a gate region and a source region 4, the source region 4 being located under the gate oxide layer 6; A stabilizing structure is located on the conductive layer.
[0045] In one embodiment, if the number of the stabilizing structures is , the stabilizing structures include: A first passivation layer 7, located on the conductive layer, wherein the first passivation layer 7 comprises an etched hole at the source region 4; A first metal layer 8, located on the first passivation layer 7; A second passivation layer 9, located on the first metal layer 8, wherein the second passivation layer 9 comprises an etched hole; The second metal layer 10 is located on the second passivation layer 9 .
[0046] In one embodiment, the source region 4 includes: a first conductivity type body region and a second conductivity type doped region located on the first conductivity type body region.
[0047] Optionally, the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.
[0048] Regarding the specific limitations of the power device, reference may be made to the limitations of the method for preparing the power device in the embodiments of the present application, and no further details will be given here.
[0049] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.
[0050] In addition, those skilled in the art will appreciate that, although some embodiments herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present application and form different embodiments. For example, in the above claims, any one of the claimed embodiments may be used in any combination. The information disclosed in this background technology section is intended only to deepen the understanding of the overall background technology of the present application and should not be regarded as an admission or in any form of implication that the information constitutes prior art known to those skilled in the art.
Claims
1. A method for preparing a power device, characterized in that: The method comprises: forming an epitaxial layer on a first surface of the substrate; After etching a plurality of grooves on the first surface of the epitaxial layer, a grooved surface is obtained; A front structure is formed on the grooved surface, wherein the front structure comprises: a conductive layer located on the grooved surface, and at least one stable structure located on the conductive layer; wherein the conductive layer comprises: a gate region and a source region, and one of the stable structures comprises: a passivation layer having a through hole and a metal layer located on the passivation layer; The substrate includes a second surface opposite to the first surface, and a drain is formed on the second surface.
2. The method according to claim 1, characterized in that The forming of a front structure on the grooved surface comprises: The thickness of the front structure is adjusted by adjusting the number of the stabilizing structures, and the thickness of the front structure after adjustment is 30-180 um.
3. The method according to claim 1, characterized in that The forming of a front structure on the grooved surface comprises: The thickness of the front structure is adjusted by adjusting the thickness of the passivation layer in the stable structure, and the thickness of the front structure after adjustment is 30-180 um.
4. The method according to claim 1, characterized in that: Before forming the epitaxial layer on the first surface of the substrate, the method further comprises: The substrate is thinned, and the thickness of the substrate after thinning is 15-30 um.
5. The method according to claim 1, characterized in that The forming of a front structure on the grooved surface comprises: After the grooved surface is oxidized to form an oxide layer, a target grooved surface is obtained; After filling the grooves of the target groove-shaped surface with polysilicon, an epitaxial structure is obtained; The front structure is formed on the epitaxial structure.
6. The method according to claim 5, characterized in that The forming of the front structure on the epitaxial structure comprises: After etching the groove position in the epitaxial structure, an etched surface is obtained; After forming an isolation layer at the groove position of the etched surface, an isolation surface is obtained; After forming a gate oxide layer on the isolation surface, and filling gate polysilicon at the groove position on the gate oxide layer, a plurality of gate regions are formed; forming a source region under the gate oxide layer to obtain the conductive layer; A stabilizing structure is formed on the conductive layer.
7. The method according to claim 6, characterized in that If the number of the stable structures is 2, forming the stable structure on the conductive layer includes: After forming a first passivation layer on the conductive layer, after performing hole etching on the first passivation layer at the position of the source region, forming a first metal layer on the first passivation layer; A second passivation layer is formed on the metal layer, and after hole etching is performed on the second passivation layer, a second metal layer is formed on the second passivation layer.
8. The method according to claim 6, characterized in that The forming of a source region under the gate oxide layer comprises: A first conductive type body region is first formed in the substrate under the gate oxide layer by ion implantation, and then a second conductive type doped region is formed on the first conductive type body region.
9. The method according to claim 8, characterized in that The first conductivity type is N type and the second conductivity type is P type, or the first conductivity type is P type and the second conductivity type is N type.
10. A power device, characterized in that: The power device comprises: a substrate comprising a first surface and a second surface that are opposite to each other; An epitaxial layer, the epitaxial layer is located on the first surface of the substrate, and the first surface of the epitaxial layer includes a grooved surface formed by a plurality of grooves; A front structure, the front structure comprising: a conductive layer located on the grooved surface, at least one stable structure located on the conductive layer, wherein the conductive layer comprises: a gate region and a source region, and one of the stable structures comprises: a passivation layer having a through hole and a metal layer located on the passivation layer; The drain is located on the second surface of the substrate.