Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The semiconductor structure comprises a substrate; the drain electrode is located in the substrate, and ions in the drain electrode have the first conduction type; the drift region is located in the substrate and located above the drain electrode, and ions in the drift region have the first conduction type; the control gate structure is located in the substrate and located in the drift region of the first partial thickness; the separation gate structure is located in the drift region of the second partial thickness at the bottom of the control gate structure; the dielectric layer is located between the separation gate structure and the drift region, and the width of the top of the dielectric layer is smaller than that of the bottom of the dielectric layer; and the source electrode is located in the drift region at the side part of the control gate structure and is located at a position close to the top of the substrate, and ions in the source electrode have the first conduction type. According to the embodiment of the invention, the difference between the charge quantity at the bottom of the separation gate structure and the charge quantity at the top of the separation gate structure is reduced, and the uniformity of the electric field intensity in the drift region is improved, so that the breakdown voltage of the dielectric layer is improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the growing demand for electronic consumer products, double diffused power MOSFET (DMOS) has been widely used in high voltage integrated circuits (HVIC) and power integrated circuits (PIC) due to its high operating current density, low on-resistance and good switching characteristics.

[0003] Power field effect transistors mainly include two types: vertical double diffused field effect transistor VDMOS (Vertical Double-Diffused MOSFET) and lateral double diffused field effect transistor LDMOS (Lateral Double-Diffused MOSFET).

[0004] Currently, with the continuous reduction of technology nodes, using vertical channels and VDMOS related to wafer thickness is a good way to reduce chip area.

[0005] However, the structure and performance of VDMOS still need to be improved. Summary of the invention

[0006] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

[0007] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate; a drain, located in the substrate, and ions in the drain have a first conductivity type; a drift region, located in the substrate and above the drain, and ions in the drift region have the first conductivity type; a control gate structure, located in the substrate and in the drift region of a first portion of thickness; a separation gate structure, located in the drift region of a second portion of thickness at the bottom of the control gate structure; a dielectric layer, located between the separation gate structure and the drift region, and the width of the top of the dielectric layer is smaller than the width of the bottom of the dielectric layer; a source, located in the drift region on the side of the control gate structure and close to the top of the substrate, and ions in the source have the first conductivity type.

[0008] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein a drain is formed in the substrate, and ions in the drain have a first conductivity type; forming a drift region located above the drain in the substrate, and ions in the drift region have the first conductivity type; forming a groove in the substrate, the groove comprising a first groove and a second groove that are interconnected, the first groove being located in a drift region of a first portion of thickness, and the second groove being located in a drift region of a second portion of thickness at the bottom of the first groove; forming a dielectric layer on an inner wall of the second groove, the width of the top of the dielectric layer being smaller than the width of the bottom of the dielectric layer; forming a separation gate structure covering the dielectric layer in the remaining space of the second groove; forming a control gate structure in the first groove; forming a source near the top of the substrate in the drift region on the side of the control gate structure, and ions in the source have the first conductivity type.

[0009] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0010] The semiconductor structure provided by the embodiment of the present invention includes a drift region located in the substrate and above the drain, a dielectric layer located between the separation gate structure and the drift region, and the width of the top of the dielectric layer is smaller than the width of the bottom of the dielectric layer, and a separation gate structure located in the drift region of the second portion of the thickness of the bottom of the control gate structure. The separation gate structure, the dielectric layer and the drift region constitute a capacitor, and the separation gate structure serves as a field plate of the capacitor. Due to the charge amount (Q d ), and the capacitance (C SGO ), and the potential at the interface between the dielectric layer and the drift region (V surf ), that is, Q d =C SGO ×V surf Moreover, the amount of electricity (C SGO ) is inversely proportional to the thickness of the dielectric layer, that is, C SGO =ε ox A / t ox , where ε refers to the dielectric constant of the dielectric layer, A refers to the area of ​​the separated gate structure and the drift region, t oxRefers to the distance between the separation gate structure and the drift region (that is, the width of the dielectric layer). When a voltage is applied to the drain, although the potential at the interface between the dielectric layer and the drift region gradually decreases from the bottom position of the separation gate structure to the top position of the separation gate structure, the width of the top of the dielectric layer is smaller than the width of the bottom of the dielectric layer, so that the capacitance near the bottom position of the separation gate structure is smaller than the capacitance near the top position of the separation gate structure, and the difference between the charge amount near the bottom position of the separation gate structure and the charge amount near the top position of the separation gate structure is correspondingly reduced, and the uniformity of the charge amount distribution in the drift region is improved, and the uniformity of the electric field strength in the drift region is correspondingly improved, thereby increasing the breakdown voltage (BV) of the dielectric layer, and then increasing the breakdown voltage of the semiconductor structure.

[0011] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a drift region located above the drain is formed in the substrate, a first groove and a second groove that penetrate each other are formed in the substrate, a dielectric layer is formed on the inner wall of the second groove, the width of the top of the dielectric layer is smaller than the width of the bottom of the dielectric layer, and a separation gate structure covering the dielectric layer is formed in the remaining space of the second groove, the separation gate structure, the dielectric layer and the drift region constitute a capacitor, and the separation gate structure serves as a field plate of the capacitor; due to the charge amount (Q d ), and the capacitance (C SGO ), and the potential at the interface between the dielectric layer and the drift region (V surf ), that is, Q d =C SGO ×V surf Moreover, the amount of electricity (C SGO ) is inversely proportional to the thickness of the dielectric layer, that is, C SGO =ε ox A / t ox , where ε refers to the dielectric constant of the dielectric layer, A refers to the area of ​​the separated gate structure and the drift region, t oxRefers to the distance between the separation gate structure and the drift region (that is, the width of the dielectric layer). When a voltage is applied to the drain, although the potential at the interface between the dielectric layer and the drift region gradually decreases from the bottom position of the separation gate structure to the top position of the separation gate structure, the width of the top of the dielectric layer is smaller than the width of the bottom of the dielectric layer, so that the capacitance at the bottom position of the separation gate structure is smaller than the capacitance near the top position of the separation gate structure, and the difference between the charge at the bottom position of the separation gate structure and the charge near the top position of the separation gate structure is correspondingly reduced, and the uniformity of the charge distribution in the drift region is improved, and the uniformity of the electric field strength in the drift region is correspondingly improved, thereby improving the breakdown voltage of the dielectric layer, and then improving the breakdown voltage of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a schematic diagram of the structure of a semiconductor structure;

[0013] Figure 2 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0014] Figures 3 to 20 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention;

[0015] Fig.21 It is a diagram of the relationship between the cross-sectional view of a semiconductor structure and the electric field distribution;

[0016] Fig. 22 It is a relationship diagram between a cross-sectional view and an electric field distribution of an embodiment of a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0017] At present, the performance of semiconductor structures still needs to be improved. Now, combining a semiconductor structure, we analyze the reasons why the performance of semiconductor structures needs to be improved.

[0018] Figure 1 It is a schematic diagram of the structure of a semiconductor structure; Fig.21 It is a diagram showing the relationship between the cross-sectional view of a semiconductor structure and the surface electric field distribution.

[0019] refer to Figure 1The semiconductor structure includes: a substrate 10; a drain 11, located in the substrate 10, and ions in the drain have a first conductivity type; a drift region 12, located in the substrate 10 and above the drain 11, and ions in the drift region 12 have a first conductivity type; a control gate structure 22, located in the substrate 10 and in the drift region 12 of a first portion of thickness; a separation gate structure 21, located in the drift region of a second portion of thickness at the bottom of the control gate structure 22; a dielectric layer 23, located between the separation gate structure 21 and the drift region 12; a source 14, located in the drift region 12 on the side of the control gate structure 22 and close to the top of the substrate 10, and ions in the source 14 have a first conductivity type.

[0020] refer to Fig.21 It has been found that when a voltage is applied to the drain 11, the electric potential at the interface between the dielectric layer 23 and the drift region 12 gradually decreases from the bottom position of the separation gate structure 21 to the top position of the separation gate structure 21, so that the amount of charge gradually decreases from the bottom position of the separation gate structure 21 to the top position of the separation gate structure 21, thereby making the electric field strength in the drift region 12 poorly uniform, which in turn leads to an unsatisfactory breakdown voltage of the dielectric layer 23, thereby affecting the performance of the semiconductor structure.

[0021] in, Fig.21 The ordinate represents the electric field strength of the semiconductor structure at the interface between the drift region and other film layers. Fig.21 The abscissa represents the size of the semiconductor structure.

[0022] In order to solve the above technical problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate; a drain, located in the substrate, and ions in the drain have a first conductivity type; a drift region, located in the substrate and above the drain, and ions in the drift region have the first conductivity type; a control gate structure, located in the substrate and in the drift region of a first portion of thickness; a separation gate structure, located in the drift region of a second portion of thickness at the bottom of the control gate structure; a dielectric layer, located between the separation gate structure and the drift region, and the width of the top of the dielectric layer is smaller than the width of the bottom of the dielectric layer; a source, located in the drift region on the side of the control gate structure and close to the top of the substrate, and ions in the source have the first conductivity type.

[0023] The semiconductor structure provided by the embodiment of the present invention includes a drift region located in the substrate and above the drain, a dielectric layer located between the separation gate structure and the drift region, and the width of the top of the dielectric layer is smaller than the width of the bottom of the dielectric layer, and a separation gate structure located in the drift region of the second portion of the thickness of the bottom of the control gate structure. The separation gate structure, the dielectric layer and the drift region constitute a capacitor, and the separation gate structure serves as a field plate of the capacitor. Due to the charge amount (Q d ), and the capacitance (C SGO ), and the potential at the interface between the dielectric layer and the drift region (V surf ), that is, Q d =C SGO ×V surf Moreover, the amount of electricity (C SGO ) is inversely proportional to the thickness of the dielectric layer, that is, C SGO =ε ox A / t ox , where ε refers to the dielectric constant of the dielectric layer, A refers to the area of ​​the separated gate structure and the drift region, t ox Refers to the distance between the separation gate structure and the drift region (that is, the width of the dielectric layer). When a voltage is applied to the drain, although the potential at the interface between the dielectric layer and the drift region gradually decreases from the bottom position of the separation gate structure to the top position of the separation gate structure, the width of the top of the dielectric layer is smaller than the width of the bottom of the dielectric layer, so that the capacitance near the bottom position of the separation gate structure is smaller than the capacitance near the top position of the separation gate structure, and the difference between the charge amount near the bottom position of the separation gate structure and the charge amount near the top position of the separation gate structure is correspondingly reduced, and the uniformity of the charge amount distribution in the drift region is improved, and the uniformity of the electric field strength in the drift region is correspondingly improved, thereby improving the breakdown voltage of the dielectric layer, and then improving the breakdown voltage of the semiconductor structure.

[0024] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0025] Figure 2 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention; Fig. 22 It is a relationship diagram between a cross-sectional view and an electric field distribution of an embodiment of a semiconductor structure of the present invention.

[0026] refer to Figure 2In this embodiment, the semiconductor structure includes: a substrate 100; a drain 110, which is located in the substrate 100, and the ions in the drain 110 have a first conductivity type; a drift region 120, which is located in the substrate 100 and above the drain 110, and the ions in the drift region 120 have a first conductivity type; a control gate structure 260, which is located in the substrate 100 and in the drift region 120 of a first portion thickness h1; a separation gate structure 240, which is located in the drift region 120 of a second portion thickness h2 at the bottom of the control gate structure 260; a dielectric layer 220, which is located between the separation gate structure 240 and the drift region 120, and the width w1 of the top of the dielectric layer 220 is smaller than the width w2 of the bottom of the dielectric layer 220; a source 140, which is located in the drift region 120 at the side of the control gate structure 260 and is located near the top of the substrate 100, and the ions in the source 140 have the first conductivity type.

[0027] The substrate 100 provides a process platform for forming a semiconductor structure. In this embodiment, the semiconductor structure is a VDMOS transistor, and the VDMOS transistor can be an N-type transistor or a P-type transistor.

[0028] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0029] The drain electrode 110 is used as a drain terminal of the transistor. In this embodiment, the drain electrode 110 is used as a drain terminal of the VDMOS transistor.

[0030] In this embodiment, the substrate 100 has a first surface 100 a located at the top, and a second surface 100 b disposed opposite to the first surface 100 a , and the drain 110 is located in the substrate 100 close to the second surface 100 b .

[0031] Specifically, the drain 110 is electrically led out from the second surface 100 b of the substrate 100 .

[0032] In this embodiment, the first conductive type of ions may be N-type ions or P-type ions. When the VDMOS transistor is an N-type transistor, the first conductive type of ions are N-type ions, and the N-type ions may be P, As, or Sb; when the VDMOS transistor is a P-type transistor, the first conductive type of ions are P-type ions, and the P-type ions may be B, Ga, or In.

[0033] As an example, the VDMOS transistor is an N-type transistor, and the ions of the first conductivity type are N-type ions.

[0034] The drift region 120 is used to withstand a larger divided voltage. The existence of the drift region 120 is beneficial to improving the breakdown voltage between the source 140 and the drain 110 .

[0035] The drift region 120 is a high resistance layer. Therefore, the doping ion concentration in the drift region 120 is small, and the doping ion concentration in the drift region 120 is lower than the doping ion concentration in the drain 110 .

[0036] The separation gate structure 240 , the dielectric layer 220 and the drift region 120 form a capacitor. The separation gate structure 240 and the drift region 120 serve as field plates of the capacitor, and the dielectric layer 220 serves as an insulating layer of the capacitor.

[0037] The control gate structure 260 is used to control the opening and closing of the channel.

[0038] In this embodiment, the lateral width of the control gate structure 260 is greater than the lateral width of the separation gate structure 240 .

[0039] Here, the lateral width refers to the width in a direction perpendicular to the sidewall of the control gate structure 260 .

[0040] It is understandable that, compared with the lateral width of the control gate structure 260 , the lateral width of the separation gate structure 240 is smaller, which correspondingly reduces the contact area of ​​the separation gate structure 240 , thereby reducing the gate-drain capacitance and improving the frequency characteristics.

[0041] In this embodiment, the material of the control gate structure 260 includes polysilicon. In other embodiments, the control gate structure 260 may also include TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN or TiAlC. As an example, the control gate structure 260 is polysilicon.

[0042] A groove (not shown) is usually formed in the substrate 100, and the groove includes a first groove (not shown) and a second groove (not shown) that penetrate each other. The first groove is located in the drift region 120 with a first partial thickness h1, and the second groove is located in the drift region 120 with a second partial thickness h2 at the bottom of the first groove.

[0043] The first groove is used to provide a space for forming a control gate structure 260 , and the second groove is used to provide a space for forming a dielectric layer 220 and a separation gate structure 240 .

[0044] In this embodiment, the semiconductor structure further includes: a gate dielectric layer 250 located between the control gate structure 260 and the separation gate structure 240 , and on the sidewall of the control gate structure 260 .

[0045] The gate dielectric layer 250 is used to isolate the control gate structure 260 from the separation gate structure 240 .

[0046] Specifically, the material of the gate dielectric layer 250 includes one or more of HfO 2 , ZrO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al 2 O 3 , SiO 2 and La 2 O 3 .

[0047] The separation gate structure 240 serves as a field plate of the capacitor. When a voltage is applied to the drain 110, although the potential at the interface between the dielectric layer 220 and the drift region 120 gradually decreases from the bottom position of the separation gate structure 240 to the top position of the separation gate structure 240, the width of the top of the dielectric layer 220 is smaller than the width of the bottom of the dielectric layer 220, so that the capacitance near the bottom position of the separation gate structure 240 is smaller than the capacitance near the top position of the separation gate structure 240, and the difference between the charge amount near the bottom position of the separation gate structure 240 and the charge amount near the top position of the separation gate structure 240 is correspondingly reduced, and the uniformity of the charge amount distribution in the drift region 120 is improved, and the uniformity of the electric field strength in the drift region 120 is correspondingly improved, thereby improving the breakdown voltage of the dielectric layer 220, and then improving the breakdown voltage of the semiconductor structure.

[0048] In this embodiment, the material of the separation gate structure 240 includes polysilicon. In other embodiments, the separation gate structure 240 may also include TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN or TiAlC. As an example, the separation gate structure 240 is polysilicon.

[0049] Here, the width of the dielectric layer 220 refers to the thickness in a direction perpendicular to the sidewall of the separation gate structure 240 .

[0050] refer to Fig. 22 , the separation gate structure 240, the dielectric layer 220 and the drift region 120 form a capacitor, the separation gate structure 240 and the drift region 120 serve as the field plate of the capacitor, and the dielectric layer 220 serves as the insulating layer of the capacitor. d ), and the capacitance (C SGO ), and the potential at the interface between the dielectric layer 220 and the drift region 120 (V surf ), that is, Q d =C SGO ×V surf Moreover, the amount of capacitance (C SGO ) is inversely proportional to the thickness of the dielectric layer 220, that is, C SGO =ε ox A / t ox , where ε refers to the dielectric constant of the dielectric layer, A refers to the area of ​​the separation gate structure 240 and the drift region 120 facing each other, and tox Refers to the distance between the separation gate structure 240 and the drift region 120 (i.e., the width of the dielectric layer). When a voltage is applied to the drain 110, although the potential at the interface between the dielectric layer 220 and the drift region 120 gradually decreases from the bottom position of the separation gate structure 240 to the top position of the separation gate structure 240, the width of the top of the dielectric layer 220 is smaller than the width of the bottom of the dielectric layer 220, so that the capacitance near the bottom position of the separation gate structure 240 is smaller than the capacitance near the top position of the separation gate structure 240, and the difference between the charge amount near the bottom position of the separation gate structure 240 and the charge amount near the top position of the separation gate structure 240 is correspondingly reduced, and the uniformity of the charge amount distribution in the drift region 120 is improved, and the uniformity of the electric field strength in the drift region 120 is correspondingly improved, thereby improving the breakdown voltage of the dielectric layer 220, and then improving the breakdown voltage of the semiconductor structure.

[0051] in, Fig. 22 The ordinate represents the electric field strength of the semiconductor structure at the interface between the drift region and other film layers. Fig. 22 The abscissa represents the size of the semiconductor structure.

[0052] In this embodiment, the width of the dielectric layer 220 gradually decreases from the top to the bottom.

[0053] The width of the dielectric layer 220 gradually decreases from top to bottom, so that the capacitance also gradually decreases from top to bottom of the dielectric layer 220, thereby further improving the uniformity of charge distribution from the top position of the separation gate structure 240 to the bottom position of the separation gate structure 240.

[0054] It should be noted that the difference between the width w1 at the top of the dielectric layer 220 and the width w2 at the bottom of the dielectric layer 220 should not be too small or too large. If the difference between the width w1 at the top of the dielectric layer 220 and the width w2 at the bottom of the dielectric layer 220 is too small, it is easy to make the capacitance near the bottom of the separation gate structure 240 smaller than the capacitance near the top of the separation gate structure 240, which is not a good effect. Correspondingly, the effect of reducing the difference between the charge amount near the bottom of the separation gate structure 240 and the charge amount near the top of the separation gate structure 240 is not good, so that the effect of improving the uniformity of the charge distribution in the drift region 120 is not ideal. Therefore, in this embodiment, the difference between the width w1 at the top of the dielectric layer 220 and the width w2 at the bottom of the dielectric layer 220 ranges from 500 angstroms to 2000 angstroms.

[0055] It should also be noted that the width of the dielectric layer 220 should not be too small or too large along the direction perpendicular to the sidewall of the separation gate structure 240. If the width of the dielectric layer 220 is too small, it is easy to make the capacitance of the capacitor formed by the separation gate structure 240 and the drift region 120 too small, so that the difference between the amount of charge near the bottom of the separation gate structure 240 and the amount of charge near the top of the separation gate structure 240 is not ideal; if the width of the dielectric layer 220 is too large, it is easy to increase the difficulty of forming the separation gate structure 240 covering the dielectric layer 220. Therefore, in this embodiment, along the direction perpendicular to the sidewall of the separation gate structure 240, the width of the dielectric layer 220 ranges from 150 angstroms to 2000 angstroms.

[0056] In this embodiment, the material of the dielectric layer 220 is an insulating material. As an example, the material of the dielectric layer 220 includes silicon oxide.

[0057] Silicon oxide has good insulation properties and is also a common material in semiconductor manufacturing, which is easy to obtain and has low process cost. In other embodiments, the material of the dielectric layer may also include silicon nitride.

[0058] In this embodiment, the interface between the dielectric layer 220 and the separation gate structure 240 is in a stepped shape, and the number of steps is multiple.

[0059] The steps for forming the dielectric layer 220 generally include: forming an initial dielectric layer on the inner wall of the second groove (not shown); filling a sacrificial layer (not shown) in the remaining space of the second groove; performing multiple initial dielectric layer thinning processes, each initial dielectric layer thinning process includes: removing a portion of the height of the sacrificial layer to expose the side wall of the initial dielectric layer; removing a portion of the width of the initial dielectric layer through the exposed side wall of the initial dielectric layer; wherein, after completing the last initial dielectric layer thinning process, the remaining initial dielectric layer located on the inner wall of the second groove serves as the dielectric layer 220.

[0060] An initial dielectric layer is first formed, and then a sacrificial layer covering the initial dielectric layer is formed. The sacrificial layer protects the unexposed initial dielectric layer, so that during the thinning process of the initial dielectric layer, the unexposed initial dielectric layer is not easily damaged, thereby making it easier to make the width w1 of the top of the dielectric layer 220 smaller than the width w2 of the bottom of the dielectric layer 220.

[0061] Furthermore, multiple initial dielectric layer thinning processes are performed to gradually reduce the width of the dielectric layer 220 from top to bottom. Accordingly, in this embodiment, the interface between the dielectric layer 220 and the separation gate structure 240 is stepped, and the number of steps is multiple.

[0062] Specifically, the number of initial dielectric layer thinning treatments is greater than or equal to 5 times. The number of initial dielectric layer thinning treatments is greater than or equal to 5 times, which is conducive to making the width of the dielectric layer 220 gradually decrease from top to bottom. Accordingly, the number of steps is at least 5.

[0063] In this embodiment, the semiconductor structure further includes a body region 130 located in the drift region 120 on the side of the control gate structure 260 between the drift region 120 and the source 140 , and ions in the body region 130 have a second conductivity type, and the first conductivity type and the second conductivity type are different.

[0064] The body region 130 near the control gate structure 260 is used as a conductive channel. As an example, the body region 130 near the control gate structure 260 is used as a conductive channel of a VDMOS transistor.

[0065] Specifically, when the ions of the first conductivity type are N-type ions, correspondingly, the ions of the second conductivity type are P-type ions; when the ions of the first conductivity type are P-type ions, correspondingly, the ions of the second conductivity type are N-type ions.

[0066] As an example, correspondingly, the ions of the second conductive type are P-type ions.

[0067] The source 140 is used as a source terminal of a transistor. As an example, the source 140 is used as a source terminal of a VDMOS transistor.

[0068] The ions in the source 140 have the first conductivity type. It can be understood that the doping type of the source 140 is the same as the doping type of the drain 110 .

[0069] As an example, the doping ion concentration of the source 140 is the same as the doping ion concentration of the drain 110 .

[0070] In this embodiment, the source 140 and the separation gate structure 240 are electrically connected to the same potential.

[0071] The source 140 and the separation gate structure 240 are electrically connected to the same potential, shielding a portion of the gate-drain capacitance, thereby reducing the gate-drain capacitance.

[0072] Correspondingly, the present invention also provides a method for forming a semiconductor structure. Figures 3 to 20 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention; Fig. 22 It is a relationship diagram between a cross-sectional view and an electric field distribution of an embodiment of a semiconductor structure of the present invention.

[0073] refer to Figure 3 , providing a substrate 500, in which a drain 510 is formed, and ions in the drain 510 have a first conductivity type.

[0074] The substrate 500 is used to provide a process platform for the subsequent formation of a semiconductor structure. In this embodiment, the semiconductor structure is a VDMOS transistor, and the VDMOS transistor can be an N-type transistor or a P-type transistor.

[0075] In this embodiment, the substrate 500 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0076] The drain electrode 510 is used as the drain terminal of the transistor. In this embodiment, the drain electrode 510 is used as the drain terminal of the VDMOS transistor.

[0077] In this embodiment, the substrate 500 has a first surface 500 a located at the top, and a second surface 500 b disposed opposite to the first surface 500 a , and the drain 510 is located in the substrate 500 close to the second surface 500 b .

[0078] Specifically, the drain 510 is electrically led out from the second surface 500 b of the substrate 500 .

[0079] In this embodiment, the first conductive type of ions may be N-type ions or P-type ions. When the VDMOS transistor is an N-type transistor, the first conductive type of ions are N-type ions, and the N-type ions may be P, As, or Sb; when the VDMOS transistor is a P-type transistor, the first conductive type of ions are P-type ions, and the P-type ions may be B, Ga, or In.

[0080] As an example, the VDMOS transistor is an N-type transistor, and the ions of the first conductivity type are N-type ions.

[0081] refer to Figure 4 , a drift region 520 located above the drain 510 is formed in the substrate 500, and ions in the drift region 520 have a first conductivity type.

[0082] The drift region 520 is used to withstand a larger divided voltage. The existence of the drift region 520 is beneficial to improving the breakdown voltage between the source and the drain 510 .

[0083] The drift region 520 is a high resistance layer, and therefore the doping ion concentration in the drift region 520 is small, and the doping ion concentration in the drift region 520 is lower than the doping ion concentration in the drain 510 .

[0084] refer to Figure 5A groove 610 is formed in the substrate 500 , and the groove 610 includes a first groove 611 and a second groove 612 that penetrate each other. The first groove 611 is located in the drift region 520 of the first partial thickness H1 , and the second groove 612 is located in the drift region 520 of the second partial thickness H2 at the bottom of the first groove 611 .

[0085] The groove 610 is used to provide a process space for the subsequent formation of a separation gate structure and a control gate structure, wherein the first groove 611 provides a process space for the subsequent formation of the control gate structure, and the second groove 612 provides a process space for the subsequent formation of the separation gate structure.

[0086] refer to Figures 6 to 15 , a dielectric layer 620 (eg, Fig.15 As shown in FIG. 6 , the width W1 of the top of the dielectric layer 620 is smaller than the width W2 of the bottom of the dielectric layer 620 .

[0087] Here, the width of the dielectric layer 620 refers to the thickness along a direction perpendicular to the sidewall of the second groove 612 .

[0088] refer to Fig. 22 The subsequently formed separation gate structure, dielectric layer 620 and drift region 520 constitute a capacitor, the separation gate structure and drift region 520 serve as the field plate of the capacitor, and the dielectric layer 620 serves as the insulating layer of the capacitor. d ), and the capacitance (C SGO ), and the potential at the interface between the dielectric layer 620 and the drift region 520 (V surf ), that is, Q d =C SGO ×V surf Moreover, the amount of electricity (C SGO ) is inversely proportional to the thickness of the dielectric layer 620, that is, C SGO =ε ox A / t ox , where ε refers to the dielectric constant of the dielectric layer, A refers to the area of ​​the separation gate structure and the drift region 520, and t oxRefers to the distance between the separation gate structure and the drift region 520 (i.e., the width of the dielectric layer 620). When a voltage is applied to the drain 510, although the potential at the interface between the dielectric layer 620 and the drift region 520 gradually decreases from the bottom position of the separation gate structure to the top position of the separation gate structure, the width W1 of the top of the dielectric layer 620 is smaller than the width W2 of the bottom of the dielectric layer 620, so that the capacitance near the bottom position of the separation gate structure is smaller than the capacitance near the top position of the separation gate structure, and the difference between the charge amount near the bottom position of the separation gate structure and the charge amount near the top position of the separation gate structure is correspondingly reduced, and the uniformity of the charge amount distribution in the drift region 520 is improved, and the uniformity of the electric field strength in the drift region 520 is correspondingly improved, thereby improving the breakdown voltage of the dielectric layer 620, and then improving the breakdown voltage of the semiconductor structure.

[0089] in, Fig. 22 The ordinate represents the electric field strength of the semiconductor structure at the interface between the drift region and other film layers. Fig. 22 The abscissa represents the size of the semiconductor structure.

[0090] In this embodiment, in the step of forming the dielectric layer 620 on the inner wall of the second groove 612 , the width of the dielectric layer 620 gradually decreases from the top to the bottom.

[0091] The width of the dielectric layer 620 gradually decreases from top to bottom, so that the capacitance also gradually decreases from top to bottom of the dielectric layer 620, which facilitates further improving the uniformity of charge distribution from the top position of the separation gate structure to the bottom position of the separation gate structure.

[0092] like Fig.15 As shown, it should be noted that the difference between the width W1 at the top of the dielectric layer 620 and the width W2 at the bottom of the dielectric layer 620 should not be too small or too large. If the difference between the width W1 at the top of the dielectric layer 620 and the width W2 at the bottom of the dielectric layer 620 is too small, it is easy to make the capacitance near the bottom of the separation gate structure smaller than the capacitance near the top of the separation gate structure, which is not a good effect. Correspondingly, the effect of reducing the difference between the charge amount near the bottom of the separation gate structure and the charge amount near the top of the separation gate structure is not good, so that the effect of improving the uniformity of the charge amount distribution in the drift region 520 is not ideal. Therefore, in this embodiment, the difference between the width W1 at the top of the dielectric layer 620 and the width W2 at the bottom of the dielectric layer 620 ranges from 500 angstroms to 2000 angstroms.

[0093] It should also be noted that the width of the dielectric layer 620 should not be too small or too large along the direction perpendicular to the sidewall of the second groove 612. If the width of the dielectric layer 620 is too small, it is easy to make the electric charge of the capacitor formed by the separation gate structure and the drift region 520 too small, so that the difference between the electric charge near the bottom of the separation gate structure and the electric charge near the top of the separation gate structure is not ideal; if the width of the dielectric layer 620 is too large, it is easy to increase the difficulty of forming the separation gate structure covering the dielectric layer 620 in the remaining space of the second groove 612. Therefore, in this embodiment, along the direction perpendicular to the sidewall of the second groove 612, the width of the dielectric layer 620 ranges from 150 angstroms to 2000 angstroms.

[0094] In this embodiment, the material of the dielectric layer 620 is an insulating material. As an example, the material of the dielectric layer 620 includes silicon oxide.

[0095] Silicon oxide has good insulation properties and is also a common material in semiconductor manufacturing, which is easy to obtain and has low process cost. In other embodiments, the material of the dielectric layer may also include silicon nitride.

[0096] In this embodiment, the step of forming the dielectric layer 620 on the inner wall of the second groove 612 includes: forming an initial dielectric layer 625 on the inner wall of the second groove 612; filling the remaining space of the second groove 612 with a sacrificial layer 630; Figures 9 to 15 As shown, multiple thinning treatments of the initial dielectric layer 625 are performed, and each thinning treatment of the initial dielectric layer 625 includes: removing a portion of the height of the sacrificial layer 630 to expose the side wall of the initial dielectric layer 625; removing a portion of the width of the initial dielectric layer 625 through the exposed side wall of the initial dielectric layer 625; wherein, after the last thinning treatment of the initial dielectric layer 625 is completed, the remaining initial dielectric layer 625 located on the inner wall of the second groove 612 serves as the dielectric layer 620.

[0097] An initial dielectric layer 625 is first formed, and then a sacrificial layer 630 covering the initial dielectric layer 625 is formed. The sacrificial layer 630 protects the unexposed initial dielectric layer 625, so that during the thinning process of the initial dielectric layer 625, the unexposed initial dielectric layer 625 is not easily damaged, thereby making it easier to make the width W1 of the top of the dielectric layer 620 smaller than the width W2 of the bottom of the dielectric layer 620.

[0098] Furthermore, the initial dielectric layer 625 is thinned multiple times to gradually reduce the width of the dielectric layer 620 from the top to the bottom. Accordingly, in this embodiment, the sidewall of the dielectric layer 620 is stepped, and the number of steps is multiple.

[0099] Specifically, the number of times the initial dielectric layer 625 is thinned is greater than or equal to 5. The number of times the initial dielectric layer 625 is thinned is greater than or equal to 5, which is conducive to making the width of the dielectric layer 620 gradually decrease from the top to the bottom. Accordingly, the number of steps is at least 5.

[0100] It should be noted that the step of forming the initial dielectric layer 625 on the inner wall of the second groove 612 includes: forming a conformal dielectric material layer 626 on the inner wall of the groove 610 and on the substrate 500, and using the dielectric material layer 626 located in the second groove 612 as the initial dielectric layer 625 (such as Figure 6 After the sacrificial layer 630 is filled in the remaining space of the second groove 612, the forming method further includes: removing the dielectric material layer 626 (as shown in FIG. 6A ) on the inner wall of the first groove 611 and on the substrate 500 Figure 8 shown).

[0101] First, a conformal dielectric material layer 626 is formed on the inner wall of the groove 610 and on the substrate 500, and the dielectric material layer 626 located in the second groove 612 is used as the initial dielectric layer 625. After the sacrificial layer 630 is filled in the remaining space of the second groove 612, the dielectric material layer 626 on the inner wall of the first groove 611 and on the substrate 500 is removed. It can be understood that the dielectric material layer 626 located in the second groove 612, that is, the initial dielectric layer 625 is covered with the sacrificial layer 630, and the sacrificial layer 630 protects the initial dielectric layer 625, so that in the process of removing the dielectric material layer 626 on the inner wall of the first groove 611 and on the substrate 500, the initial dielectric layer 625 is not easily damaged, which is beneficial to improving the quality of the dielectric layer 620, and correspondingly, it is also beneficial to reduce the difficulty of removing the dielectric material layer 626 on the inner wall of the first groove 611 and on the substrate 500.

[0102] It should also be noted that the step of filling the remaining space of the second groove 612 with the sacrificial layer 630 includes: filling the remaining space of the groove 610 with a sacrificial material layer 635, the sacrificial material layer 635 also covering the substrate 500 outside the groove 610 (such as Figure 6 ); removing the sacrificial material layer 635 outside the groove 610 and the sacrificial material layer 635 in the first groove 611, and the remaining sacrificial material layer 635 is used as the sacrificial layer 630 (as shown); Figure 7 shown).

[0103] Firstly, a sacrificial material layer 635 is formed in the remaining space of the groove 610 and above the substrate 500 outside the groove 610 , and then the sacrificial material layer 635 outside the groove 610 and the sacrificial material layer 635 in the first groove 611 are removed, which helps to reduce the difficulty of forming the sacrificial layer 630 .

[0104] In this embodiment, the process of removing a portion of the height of the sacrificial layer 630 includes an anisotropic etching process.

[0105] The anisotropic etching process has anisotropic etching characteristics, so the etching accuracy is high and the controllability of the profile is better, which is beneficial to reduce the probability of the initial dielectric layer 625 being damaged during the process of removing a portion of the height of the sacrificial layer 630.

[0106] As an example, the anisotropic etching process includes an anisotropic dry etching process.

[0107] In this embodiment, the process of removing a portion of the width of the initial dielectric layer 625 includes an isotropic etching process.

[0108] The isotropic etching process has the characteristic of isotropic etching, which is conducive to achieving a higher etching selectivity ratio between the etched object (ie, the initial dielectric layer 625) and other film layers (eg, the substrate 500), thereby reducing damage to other film layers.

[0109] Specifically, the isotropic etching process includes an anisotropic wet etching process, and the etching solution of the wet etching process includes a hydrochloric acid solution.

[0110] The hydrochloric acid solution facilitates a higher etching selectivity ratio between the etching object and other film layers.

[0111] refer to Figure 16 to Figure 17 A separation gate structure 640 covering the dielectric layer 620 is formed in the remaining space of the second groove 612 .

[0112] The separation gate structure 640 serves as a field plate of the capacitor. When a voltage is applied to the drain 510, although the potential at the interface between the dielectric layer 620 and the drift region 520 gradually decreases from the bottom position of the separation gate structure 640 to the top position of the separation gate structure 640, the width of the top of the dielectric layer 620 is smaller than the width of the bottom of the dielectric layer 620, so that the capacitance near the bottom position of the separation gate structure 640 is smaller than the capacitance near the top position of the separation gate structure 640, and the difference between the charge amount near the bottom position of the separation gate structure 640 and the charge amount near the top position of the separation gate structure 640 is correspondingly reduced, and the uniformity of the charge amount distribution in the drift region 520 is improved, and the uniformity of the electric field strength in the drift region 520 is correspondingly improved, thereby improving the breakdown voltage of the dielectric layer 620, and then improving the breakdown voltage of the semiconductor structure.

[0113] Specifically, the step of forming a separation gate structure 640 covering the dielectric layer 620 in the remaining space of the second groove 612 includes: forming a separation gate structure material layer 641 (such as a dielectric layer 641) in the remaining space of the second groove 612, in the first groove 611, and on the substrate 500; Fig.16 ); removing the separation gate structure material layer 641 in the first groove 611 and on the substrate 500, and the remaining separation gate structure material layer 641 is used as the separation gate structure 640 (as shown); Fig.17 shown).

[0114] In this embodiment, the material of the separation gate structure 640 includes polysilicon. In other embodiments, the separation gate structure 640 may also include TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN or TiAlC. As an example, the separation gate structure 640 is polysilicon.

[0115] refer to Fig.18 In this embodiment, after forming the separation gate structure 640 and before forming the control gate structure, the forming method further includes: forming a gate dielectric layer 650 on the inner wall of the first groove 611 .

[0116] The gate dielectric layer 650 is used to isolate the control gate structure from the separation gate structure 640 .

[0117] Specifically, the material of the gate dielectric layer 650 includes one or more of HfO 2 , ZrO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al 2 O 3 , SiO 2 and La 2 O 3 .

[0118] refer to Figures 19 to 20 , a control gate structure 660 is formed in the first groove 611 .

[0119] The control gate structure 660 is used to control the opening and closing of the channel.

[0120] In this embodiment, the lateral width of the control gate structure 660 is greater than the lateral width of the separation gate structure 640 .

[0121] Here, the lateral width refers to the width in a direction perpendicular to the sidewall of the control gate structure 660 .

[0122] It can be understood that, compared with the lateral width of the control gate structure 660 , the lateral width of the separation gate structure 640 is smaller, which correspondingly reduces the contact area of ​​the separation gate structure 640 , thereby reducing the gate-drain capacitance and improving the frequency characteristics.

[0123] In this embodiment, the material of the control gate structure 660 includes polysilicon. In other embodiments, the control gate structure 660 may also include TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN or TiAlC. As an example, the control gate structure 660 is polysilicon.

[0124] Accordingly, in this embodiment, in the step of forming the control gate structure 660 , the control gate structure 660 covers the gate dielectric layer 650 .

[0125] refer to Fig. 20 In this embodiment, after forming the control gate structure 660 and before forming the source, the formation method further includes: forming a body region 530 in the drift region, wherein ions in the body region 530 have a second conductivity type, and the first conductivity type and the second conductivity type are different.

[0126] The body region 530 near the control gate structure 660 is used as a conductive channel. As an example, the body region 530 near the control gate structure 660 is used as a conductive channel of a VDMOS transistor.

[0127] Specifically, when the ions of the first conductivity type are N-type ions, correspondingly, the ions of the second conductivity type are P-type ions; when the ions of the first conductivity type are P-type ions, correspondingly, the ions of the second conductivity type are N-type ions.

[0128] As an example, correspondingly, the ions of the second conductive type are P-type ions.

[0129] Continue to refer Fig. 20 A source 540 is formed in the drift region 520 at the side of the control gate structure 660 and close to the top of the substrate 500 (ie, the first surface 500 a ), and ions in the source 540 have the first conductivity type.

[0130] The source electrode 540 is used as a source terminal of a transistor. As an example, the source electrode 540 is used as a source terminal of a VDMOS transistor.

[0131] A source 540 is formed in the drift region 520 at the side of the control gate structure 660 near the top of the substrate 500 (ie, the first surface 500 a ). It is understood that the body region 530 is located in the drift region at the bottom of the source 540 .

[0132] In this embodiment, the source 540 and the separation gate structure 640 are electrically connected to the same potential.

[0133] The source 540 and the separation gate structure 640 are electrically connected to the same potential, shielding a portion of the gate-drain capacitance.

[0134] The ions in the source 540 have the first conductivity type. It can be understood that the doping type of the source 540 is the same as the doping type of the drain 510 .

[0135] As an example, the doping ion concentration of the source 540 is the same as the doping ion concentration of the drain 510 .

[0136] It should be noted that the semiconductor structure can be formed by the formation method described in the above embodiment, or by other formation methods. For the specific description of the semiconductor structure described in this embodiment, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0137] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A drain electrode, located in the substrate, wherein ions in the drain electrode have a first conductivity type; A drift region, located in the substrate and above the drain, wherein ions in the drift region have a first conductivity type; a control gate structure located in the substrate and in the drift region of the first partial thickness; a split gate structure located in a second portion of the thickness of the drift region at the bottom of the control gate structure; A dielectric layer is located between the separation gate structure and the drift region, and the width of the top of the dielectric layer is smaller than the width of the bottom of the dielectric layer; The source is located in the drift region at the side of the control gate structure and close to the top of the substrate, and the ions in the source have a first conductivity type.

2. The semiconductor structure according to claim 1, wherein: The width of the dielectric layer gradually decreases from top to bottom.

3. The semiconductor structure according to claim 2, wherein: The interface between the dielectric layer and the separation gate structure is in a step shape, and the number of the steps is multiple.

4. The semiconductor structure according to claim 3, characterized in that The number of the steps is at least 5.

5. The semiconductor structure according to claim 1, wherein: The difference between the width of the top of the dielectric layer and the width of the bottom of the dielectric layer ranges from 500 angstroms to 2000 angstroms.

6. The semiconductor structure according to claim 1, wherein: Along a direction perpendicular to the sidewall of the separation gate structure, the width of the dielectric layer ranges from 150 angstroms to 2000 angstroms.

7. The semiconductor structure according to claim 1, wherein: The material of the dielectric layer includes one or both of silicon oxide and silicon nitride.

8. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes: a gate dielectric layer located between the control gate structure and the separation gate structure, and on the side wall of the control gate structure.

9. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes a body region located in a drift region at the bottom of the source, wherein ions in the body region have a second conductivity type, and the first conductivity type is different from the second conductivity type.

10. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, wherein a drain is formed in the substrate, and ions in the drain have a first conductivity type; forming a drift region located above the drain in the substrate, wherein ions in the drift region have a first conductivity type; Forming a groove in the substrate, the groove comprising a first groove and a second groove interpenetrating each other, the first groove being located in a drift region of a first partial thickness, and the second groove being located in a drift region of a second partial thickness at the bottom of the first groove; forming a dielectric layer on the inner wall of the second groove, wherein the width of the top of the dielectric layer is smaller than the width of the bottom of the dielectric layer; forming a separation gate structure covering the dielectric layer in a remaining space of the second groove; forming a control gate structure in the first groove; A source is formed in a drift region at a side of the control gate structure near a top position of the substrate, wherein ions in the source have a first conductivity type.

11. The method for forming a semiconductor structure according to claim 10, wherein: In the step of forming a dielectric layer on the inner wall of the second groove, the width of the dielectric layer gradually decreases from the top to the bottom.

12. The method for forming a semiconductor structure according to claim 11, wherein: The step of forming a dielectric layer on the inner wall of the second groove comprises: forming an initial dielectric layer on an inner wall of the second groove; Filling a sacrificial layer in the remaining space of the second groove; Performing multiple initial dielectric layer thinning processes, each of which includes: removing a portion of the height of the sacrificial layer to expose the sidewall of the initial dielectric layer; removing a portion of the width of the initial dielectric layer through the exposed sidewall of the initial dielectric layer; After the last thinning process of the initial dielectric layer is completed, the remaining initial dielectric layer on the inner wall of the second groove serves as the dielectric layer.

13. The method for forming a semiconductor structure according to claim 12, wherein: The process of removing a portion of the height of the sacrificial layer includes an anisotropic etching process.

14. The method for forming a semiconductor structure according to claim 12, wherein: The process of removing a portion of the width of the initial dielectric layer includes an isotropic etching process.

15. The method for forming a semiconductor structure according to claim 14, wherein: The isotropic etching process includes an anisotropic wet etching process, and the etching solution of the wet etching process includes a hydrochloric acid solution.

16. The method for forming a semiconductor structure according to claim 12, wherein: The number of times of the initial dielectric layer thinning process is greater than or equal to 5 times.

17. The method for forming a semiconductor structure according to claim 12, wherein: The step of forming an initial dielectric layer on the inner wall of the second groove comprises: forming a conformal dielectric material layer on the inner wall of the groove and on the substrate, and using the dielectric material layer in the second groove as an initial dielectric layer; After the sacrificial layer is filled in the remaining space of the second groove, the forming method further includes: removing the dielectric material layer on the inner wall of the first groove and on the substrate.

18. The method for forming a semiconductor structure according to claim 12 or 17, wherein: The step of filling the remaining space of the second groove with a sacrificial layer comprises: A sacrificial material layer is filled in the remaining space of the groove, and the sacrificial material layer also covers the substrate outside the groove; the sacrificial material layer outside the groove and the sacrificial material layer in the first groove are removed, and the remaining sacrificial material layer is used as a sacrificial layer.

19. The method for forming a semiconductor structure according to claim 10, wherein: After forming the separation gate structure and before forming the control gate structure, the forming method further includes: forming a gate dielectric layer on an inner wall of the first groove; In the step of forming the control gate structure, the control gate structure covers the gate dielectric layer.

Images