Integrated circuit device

Abstract

An integrated circuit device is disclosed. The integrated circuit device includes a first fin and a second fin extending in a first horizontal direction on a first region of a substrate; a third fin and a fourth fin extending in a first horizontal direction on the second region of the substrate; a connection gate line at least partially surrounding the first channel region and the second channel region; and a separation gate line including a first separation portion at least partially surrounding the third channel region and a second separation portion at least partially surrounding the fourth channel region, in which an uppermost portion of a top surface of the separation gate line is at a first vertical height and an uppermost portion of a top surface of the separation gate line is at a second vertical height. And an uppermost portion of a top surface connecting the gate line is at a second vertical height higher than the first vertical height.

Description

[0001] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0129570 filed on September 26, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to an integrated circuit device, and more particularly, to an integrated circuit device including a forksheet (or referred to as a forkboard). Background Art

[0003] Since electronic products are expected to be miniaturized, multifunctional, and high-performance, high capacity and high integration of integrated circuit devices are expected. Therefore, there is a desire to effectively design a circuit structure to achieve high integration while ensuring the desired functions and operating speed of the integrated circuit device. Summary of the invention

[0004] The present disclosure provides integrated circuit devices with improved performance and reliability.

[0005] According to one aspect of the present disclosure, an integrated circuit device is provided. The integrated circuit device may include: a substrate including a first region and a second region; a first fin and a second fin extending in a first horizontal direction, on the first region, and adjacent to each other in a second horizontal direction intersecting the first horizontal direction; a third fin and a fourth fin extending in the first horizontal direction, on the second region, and adjacent to each other in the second horizontal direction; a first channel region on the first fin; a second channel region on the second fin; a third channel region on the third fin; a fourth channel region on the fourth fin; a connecting gate line at least partially surrounding the first channel region and the second channel region, extending in the second horizontal direction, and on the first region; a separating gate line including a first separating portion and a second separating portion, the first separating portion at least partially surrounding the third channel region, the second separating portion at least partially surrounding a fourth channel region, wherein the third channel region and the fourth channel region extend in a second horizontal direction and are on the second region; a first vertical structure, between the first channel region and the second channel region; a second vertical structure, between the third channel region and the fourth channel region, and insulating a first separation portion and a second separation portion of a separation gate line from each other; and a plurality of source / drain regions, contacting each of the first channel region, the second channel region, the third channel region, and the fourth channel region, wherein a top surface of the first vertical structure and a top surface of the second vertical structure are at a first vertical height, wherein an uppermost portion of a top surface of the connection gate line is at a second vertical height that is higher than the first vertical height, and wherein an uppermost portion of a top surface of the separation gate line is at the first vertical height.

[0006] According to another aspect of the present disclosure, an integrated circuit device is provided. The integrated circuit device may include: a substrate including a first region; a first fin and a second fin extending in a first horizontal direction, on the first region, and adjacent to each other in a second horizontal direction intersecting the first horizontal direction; a first nanosheet stack including a plurality of first nanosheets and on the first fin; a second nanosheet stack including a plurality of second nanosheets and on the second fin; a connecting gate line at least partially surrounding the plurality of first nanosheets and the plurality of second nanosheets and extending in the second horizontal direction on the first region; a first vertical structure contacting the first nanosheet stack and the second nanosheet stack and between the first nanosheet stack and the second nanosheet stack; and a plurality of source / drain regions spaced apart from each other, wherein the connecting gate line is between the plurality of source / drain regions, wherein a top surface of the first vertical structure is at a first vertical height, wherein an uppermost portion of a top surface of the connecting gate line is at a second vertical height higher than the first vertical height, wherein a lowermost portion of a top surface of the connecting gate line is at the first vertical height, and wherein an uppermost portion of a top surface of the connecting gate line overlaps the first vertical structure in a vertical direction.

[0007] According to another aspect of the present disclosure, an integrated circuit device is provided. The integrated circuit device may include: a substrate, including a first region and a second region adjacent to each other in a second horizontal direction intersecting the first horizontal direction; a first fin and a second fin extending in the first horizontal direction, on the first region, and adjacent to each other in the second horizontal direction; a third fin and a fourth fin extending in the first horizontal direction, on the second region, and adjacent to each other in the second horizontal direction; a first nanosheet stack, including a plurality of first nanosheets, and on the first fin; a second nanosheet stack, including a plurality of second nanosheets, and on the second fin; a third nanosheet stack, including a plurality of third nanosheets, and on the third fin; a fourth nanosheet stack, including a plurality of fourth nanosheets, and on the fourth fin; a connecting gate line, at least partially surrounding the plurality of first nanosheets and the plurality of second nanosheets, extending in the second horizontal direction, and on the first region; a separating gate line, including a first separating portion and a second separating portion, the first separating portion at least partially surrounding the plurality of third nanosheets, and the second separating portion at least partially surrounding the plurality of fourth nanosheets, wherein, The separation gate line overlaps with the connecting gate line in a second horizontal direction, and wherein the separation gate line extends in the second horizontal direction and is on a second region; a first vertical structure, contacting the plurality of first nanosheets and the plurality of second nanosheets, and between the first fin and the second fin; a second vertical structure, contacting the plurality of third nanosheets and the plurality of fourth nanosheets, between the third fin and the fourth fin, and insulating the first separation portion and the second separation portion from each other; a cutting structure, between the connecting gate line and the separation gate line, and insulating the connecting gate line and the separation gate line from each other; a first gate contact, electrically connected to the connecting gate line; and a second gate contact, electrically connected to the separation gate line, wherein a top surface of each of the first vertical structures and a top surface of the second vertical structure are at a first vertical height, wherein an uppermost portion of a top surface of the connecting gate line is at a second vertical height higher than the first vertical height, wherein an uppermost portion of a top surface of the separation gate line is at the first vertical height, and wherein an uppermost portion of a top surface of the connecting gate line overlaps with the first vertical structure in a vertical direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0009] Figure 1 is a plan layout diagram of an integrated circuit device according to some embodiments.

[0010] Figure 2A , Figure 2B and Figure 2C is a cross-sectional view of an integrated circuit device according to some embodiments.

[0011] Figure 3 and Figure 4 is a cross-sectional view of an integrated circuit device according to some embodiments.

[0012] Figure 5 is a plan layout diagram of an integrated circuit device according to some embodiments.

[0013] Figure 6 is a cross-sectional view of an integrated circuit device according to some embodiments.

[0014] Figure 7 is a cross-sectional view of an integrated circuit device according to some embodiments.

[0015] Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11 , Fig. 12A , Fig. 12B , Fig.13A and Fig. 13B are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to some embodiments.

[0016] Fig.14 , Fig.15 and Fig.16 are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to some embodiments. DETAILED DESCRIPTION

[0017] In order to clarify the present disclosure, parts not related to the description will be omitted, and the same elements or equivalents are referenced by the same reference numerals throughout the specification. In addition, since the sizes and thicknesses of the constituent members shown in the drawings are arbitrarily given for better understanding and ease of description, the present disclosure is not limited to the sizes and thicknesses shown. In the drawings, the thicknesses of layers, films, plates, regions, etc. are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are excessively displayed for better understanding and ease of description.

[0018] It will be understood that when an element (such as a layer, film, region or substrate) is referred to as "on" another element, the element may be directly on the other element, or there may also be an intermediate element. In contrast, when an element is referred to as "directly on" another element, there is no intermediate element. In addition, for ease of description, spatial relative terms (such as "below", "below", "lower (lower part)", "above", "upper (lower part)", etc.) may be used to describe the relationship between an element or feature and another (one or more) elements or (one or more) features as shown in the figure. It will be understood that, in addition to the orientation depicted in the figure, spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the figure is turned over, the element described as "below" or "below" other elements or features will then be oriented to "above" other elements or features. Therefore, the term "below" can cover both the upper and lower orientations. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0019] In addition, unless explicitly described to the contrary, the word "include" and deformation will be understood to indicate that the elements stated are included, but any other elements are not excluded. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. It will also be understood that when the terms "include" and / or "comprising" are used here, the features, steps, operations, elements and / or components of the statements are explained, but the presence or addition of one or more other features, steps, operations, elements, components and / or their groups are not excluded. The term "and / or" includes any and all combinations of one or more of the related listed items. The term "connection" can be used to represent physical and / or electrical connections here, and can represent direct or indirect physical and / or electrical connections. When observed along a line extending in a specific direction or in a plane perpendicular to the specific direction, the components or layers described with reference to "overlapping" in the specific direction can be at least partially blocked from each other.

[0020] Hereinafter, embodiments are described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are used for the same components, and repeated descriptions thereof are omitted.

[0021] Figure 1 is a plan layout diagram of the integrated circuit device 100 according to some embodiments. FIG. 2A to FIG. 2C is a cross-sectional view of an integrated circuit device 100 according to some embodiments. Specifically, Figure 2A It is along Figure 1 A cross-sectional view taken along line X1-X1'. Figure 2B It is along Figure 1 A cross-sectional view taken along line Y1-Y1'. Figure 2CIt is along Figure 1 A cross-sectional view taken along line Y2-Y2'.

[0022] Reference Figure 1 and FIG. 2A to FIG. 2C , describes an integrated circuit device 100 including a field effect transistor having a gate-all-around structure, the gate-all-around structure including an active region in the shape of a nanowire or nanosheet and a gate surrounding the active region.

[0023] The integrated circuit device 100 may include a substrate 102 having a first surface 102_1, and a plurality of fin-type active regions FA protruding or extending from the first surface 102_1 of the substrate 102. The plurality of fin-type active regions FA may be elongated in a first horizontal direction (X direction) and may extend parallel to each other on the substrate 102.

[0024] The substrate 102 may include a semiconductor such as silicon (Si) or germanium (Ge) or a compound semiconductor such as silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium gallium arsenide (InGaAs), or indium phosphide (InP). The terms "SiGe", "SiC", "GaAs", "InAs", "InGaAs", and "InP" used herein represent materials composed of elements included in each term, and are not chemical formulas representing stoichiometric relationships. The substrate 102 may include a conductive region (e.g., a well doped with impurities or a structure doped with impurities). The substrate 102 may include a first region R1 and a second region R2 adjacent to each other in a second horizontal direction (Y direction).

[0025] The plurality of fin-type active regions FA may include a first fin F1, a second fin F2, a third fin F3, and a fourth fin F4, each of which extends in a first horizontal direction (X direction). In some embodiments, the first fin F1 may be adjacent to the second fin F2 in a second horizontal direction (Y direction). The third fin F3 may be adjacent to the fourth fin F4 in a second horizontal direction (Y direction).

[0026] In some embodiments, the first fin F1 and the second fin F2 may be arranged on the first region R1 of the substrate 102. The third fin F3 and the fourth fin F4 may be arranged on the second region R2 of the substrate 102. For example, the second fin F2 may be arranged adjacent to the second region R2. For example, the third fin F3 may be arranged adjacent to the first region R1. For example, the second fin F2 may be adjacent to the third fin F3 in the second horizontal direction (Y direction).

[0027] In some embodiments, the distance between the first fin F1 and the second fin F2 and the distance between the third fin F3 and the fourth fin F4 may be smaller than the distance between the second fin F2 and the third fin F3. For example, the first fin F1, the second fin F2, the third fin F3, and the fourth fin F4 may not be arranged at equal intervals in the second horizontal direction (Y direction). In some embodiments, the first fin F1, the second fin F2, the third fin F3, and the fourth fin F4 may be arranged at equal intervals in the second horizontal direction (Y direction).

[0028] The device isolation film 112 may be located in a trench defining a plurality of fin-type active regions FA. The device isolation film 112 may cover a portion of a sidewall of each of the plurality of fin-type active regions FA or overlap a portion of a sidewall of each of the plurality of fin-type active regions FA, and may overlap (or be on) the substrate 102 in a vertical direction (Z direction). The device isolation film 112 may include a silicon oxide film. The device isolation film 112 may include a material having an etching selectivity different from that of the substrate 102.

[0029] like Figure 1 , Figure 2A and Figure 2C As shown in , a plurality of gate lines 160 may be arranged on a plurality of fin-type active areas FA. Each of the plurality of gate lines 160 may extend in a second horizontal direction (Y direction) intersecting with a first horizontal direction (X direction). In the region where the plurality of fin-type active areas FA intersect with the plurality of gate lines 160, a plurality of nanosheet stacks NSS may be arranged above a fin top surface FT of each of the plurality of fin-type active areas FA. The plurality of nanosheet stacks NSS may each include at least one nanosheet facing the fin top surface FT at a position spaced apart from the fin top surface FT of the fin-type active area FA in the vertical direction (Z direction). The term "nanosheet" used herein refers to a conductive structure having a cross-section substantially perpendicular to the direction along which current flows. Nanosheets should be understood to include nanowires.

[0030] like Figure 2A and Figure 2C As shown in , the plurality of nanosheet stacks NSS may include a plurality of nanosheets stacked on each other in the vertical direction (Z direction) on the fin type active area FA. The plurality of nanosheets may have different vertical distances (Z direction distances) from the fin top surface FT of the fin type active area FA. Each of the plurality of gate lines 160 may at least partially surround the “plurality of nanosheets stacked on each other in the vertical direction (Z direction) included in the nanosheet stack NSS”.

[0031] Specifically, the first nanosheet stack NSS1 may include a plurality of first nanosheets N1 stacked on each other in a vertical direction (Z direction) on the first fin F1. The plurality of first nanosheets N1 may have different vertical distances (Z direction distances) from the fin top surface of the first fin F1.

[0032] Likewise, the second nanosheet stack NSS2 may include a plurality of second nanosheets N2 stacked one on another in the vertical direction (Z direction) on the second fin F2. The third nanosheet stack NSS3 may include a plurality of third nanosheets N3 stacked one on another in the vertical direction (Z direction) on the third fin F3. The fourth nanosheet stack NSS4 may include a plurality of fourth nanosheets N4 stacked one on another in the vertical direction (Z direction) on the fourth fin F4.

[0033] Each of the plurality of nanosheets included in the plurality of nanosheet stacks NSS may be used as a channel region. Each of the plurality of first nanosheets N1 included in the first nanosheet stack NSS1 placed on the first fin F1 may be referred to as a first channel region. Each of the plurality of second nanosheets N2 included in the second nanosheet stack NSS2 placed on the second fin F2 may be referred to as a second channel region. Each of the plurality of third nanosheets N3 included in the third nanosheet stack NSS3 placed on the third fin F3 may be referred to as a third channel region. Each of the plurality of fourth nanosheets N4 included in the fourth nanosheet stack NSS4 placed on the fourth fin F4 may be referred to as a fourth channel region.

[0034] exist Figure 1 , a case where the planar shape of the nanosheet stack NSS is approximately rectangular is shown, but the present disclosure is not limited thereto. The nanosheet stack NSS may have various planar shapes according to the planar shape of each of the fin-type active area FA and the gate line 160. A configuration is shown in which a plurality of nanosheet stacks NSS and a plurality of gate lines 160 are arranged on one fin-type active area FA, and a plurality of nanosheet stacks NSS are arranged in a row along a first horizontal direction (X direction) on one fin-type active area FA. However, the number of nanosheet stacks NSS and gate lines 160 placed on one fin-type active area FA is not particularly limited.

[0035] In some embodiments, each of the plurality of nanosheets may have a thickness in the range of about 4 nanometers (nm) to about 6 nm, but is not limited thereto. The thickness of each of the plurality of nanosheets represents a dimension in the vertical direction (Z direction). In some embodiments, the plurality of nanosheets may have substantially the same thickness in the vertical direction (Z direction). In some embodiments, at least some of the plurality of nanosheets may have different thicknesses in the vertical direction (Z direction). In some embodiments, the plurality of nanosheets each included in the plurality of nanosheet stacks NSS may include a Si layer, a SiGe layer, or a combination thereof.

[0036] like Figure 2A As shown in , a plurality of nanosheets included in one nanosheet stack (e.g., the first nanosheet stack NSS1) may have the same or similar size in the first horizontal direction (X direction). In a variation, at least some of the plurality of nanosheets included in one nanosheet stack (e.g., the first nanosheet stack NSS1) may have different sizes in the first horizontal direction (X direction). The case where the plurality of nanosheet stacks NSS are each composed of three nanosheets is shown here, but the present disclosure is not limited thereto. For example, the nanosheet stack NSS may include at least one nanosheet, and the number of nanosheets constituting the nanosheet stack NSS is not particularly limited.

[0037] like Figure 1 , Figure 2B and Figure 2C As shown in , the first vertical structure VS1 may be placed between the first fin F1 and the second fin F2 on the first region R1 of the substrate 102. The first vertical structure VS1 may be placed between the first nanosheet stack NSS1 and the second nanosheet stack NSS2. The first vertical structure VS1 may extend in a vertical direction (Z direction) on the substrate 102. The first vertical structure VS1 may be in contact with a plurality of first nanosheets N1 included in the first nanosheet stack NSS1. The first vertical structure VS1 may be in contact with a side surface of each of the plurality of first nanosheets N1 included in the first nanosheet stack NSS1. The first vertical structure VS1 may be in contact with a plurality of second nanosheets N2 included in the second nanosheet stack NSS2. The first vertical structure VS1 may be in contact with a side surface of each of the plurality of second nanosheets N2 included in the second nanosheet stack NSS2. For example, the first vertical structure VS1 may be in contact with the first channel region and the second channel region.

[0038] The second vertical structure VS2 may be placed between the third fin F3 and the fourth fin F4 on the second region R2 of the substrate 102. The second vertical structure VS2 may be placed between the third nanosheet stack NSS3 and the fourth nanosheet stack NSS4. The second vertical structure VS2 may extend in a vertical direction (Z direction) on the substrate 102. The second vertical structure VS2 may contact a plurality of third nanosheets N3 included in the third nanosheet stack NSS3. The second vertical structure VS2 may contact a side surface of each of the plurality of third nanosheets N3 included in the third nanosheet stack NSS3. The second vertical structure VS2 may contact a plurality of fourth nanosheets N4 included in the fourth nanosheet stack NSS4. The second vertical structure VS2 may contact a side surface of each of the plurality of fourth nanosheets N4 included in the fourth nanosheet stack NSS4. For example, the second vertical structure VS2 may contact the third channel region and the fourth channel region.

[0039] For example, the first vertical structure VS1 and the second vertical structure VS2 may include a dielectric material.

[0040] like Figure 2C As shown in , the top surface VS1_T of the first vertical structure VS1 and the top surface VS2_T of the second vertical structure VS2 may be located at the same vertical height (or referred to as level) (for example, the distance between the top surface VS1_T and the first surface 102_1 of the substrate 102 and the distance between the top surface VS2_T and the first surface 102_1 are the same). Specifically, the top surface VS1_T of the first vertical structure VS1 and the top surface VS2_T of the second vertical structure VS2 may both be located at a first vertical height LV1.

[0041] like Figure 2A As shown in , a plurality of connected gate lines 161 may each include a main gate portion 161M and a plurality of sub-gate portions 161S. The main gate portion 161M may cover or overlap the top surface of the first nanosheet stack NSS1, and may extend in a second horizontal direction (Y direction). The plurality of sub-gate portions 161S and the main gate portion 161M may be integrally formed (e.g., each of the connected gate lines 161 is provided by a single unitary object), and the plurality of sub-gate portions 161S may be respectively placed between two adjacent first nanosheets N1 among the plurality of first nanosheets N1 and between the lowest first nanosheet N1 among the plurality of first nanosheets N1 and the first fin F1. In the vertical direction (Z direction), the thickness of each of the plurality of sub-gate portions 161S may be smaller than the thickness of the main gate portion 161M.

[0042] Reference Figure 2CThe main gate portion 161M may extend in the second horizontal direction (Y direction) while covering or overlapping the top surface of the second nanosheet stack NSS2, and the plurality of sub-gate portions 161S may be respectively placed between two adjacent second nanosheets N2 among the plurality of second nanosheets N2 and between the bottommost second nanosheet N2 among the plurality of second nanosheets N2 and the second fin F2.

[0043] Similarly, refer to Figure 2C , each of the separated gate lines 162 may include a main gate portion and a plurality of sub-gate portions.

[0044] like Figure 1 and Figure 2C As shown in FIG. 1 , the connection gate line 161 and the separation gate line 162 overlapped in the second horizontal direction (Y direction) may be placed on the substrate 102 .

[0045] The connection gate line 161 may be placed on the first region R1 of the substrate 102. The connection gate line 161 may at least partially surround the plurality of first nanosheets N1 and the plurality of second nanosheets N2. For example, the connection gate line 161 may at least partially surround the first channel region and the second channel region.

[0046] Specifically, the connection gate line 161 may include a first connection portion 161_1, a second connection portion 161_2, and a common portion 161_C. The first connection portion 161_1 may at least partially surround a plurality of first nanosheets N1 on the first fin F1. For example, the first connection portion 161_1 may surround the first channel region. The second connection portion 161_2 may at least partially surround a plurality of second nanosheets N2 on the second fin F2. For example, the second connection portion 161_2 may surround the second channel region. The first connection portion 161_1 and the second connection portion 161_2 may each be placed on a side surface of the first vertical structure VS1. The common portion 161_C may connect the first connection portion 161_1 to the second connection portion 161_2. The common portion 161_C located at a vertical height higher than the first connection portion 161_1 and the second connection portion 161_2 may be placed on the top surface of each of the first connection portion 161_1 and the second connection portion 161_2. The common portion 161_C may be placed on the top surface VS1_T of the first vertical structure VS1 .

[0047] The first connection portion 161_1 may overlap with the first nanosheet stack NSS1 in the vertical direction (Z direction). The second connection portion 161_2 may overlap with the second nanosheet stack NSS2 in the vertical direction (Z direction). The common portion 161_C may overlap with the first vertical structure VS1 in the vertical direction (Z direction). The first vertical structure VS1 may be placed between the first connection portion 161_1 and the second connection portion 161_2. The first vertical structure VS1 may overlap with the first connection portion 161_1 and the second connection portion 161_2 in the second horizontal direction (Y direction).

[0048] The common portion 161_C may include a portion overlapping each of the first connection portion 161_1 and the second connection portion 161_2 in a vertical direction (Z direction). The first connection portion 161_1 , the second connection portion 161_2 , and the common portion 161_C connecting the gate line 161 may be integrally formed.

[0049] Therefore, since the connection gate line 161 of the integrated circuit device 100 according to some embodiments includes the first connection portion 161_1, the second connection portion 161_2, and the common portion 161_C formed integrally, the resistance of the connection gate line 161 can be reduced. Specifically, an interface may not be formed between the first connection portion 161_1, the second connection portion 161_2, and the common portion 161_C, thereby reducing the resistance of the connection gate line 161. That is, the integrated circuit device 100 with improved performance and reliability can be provided through some embodiments.

[0050] The separation gate line 162 may be placed on the second region R2 of the substrate 102. The separation gate line 162 may at least partially surround the plurality of third nanosheets N3 and the plurality of fourth nanosheets N4. For example, the separation gate line 162 may surround the third channel region and the fourth channel region.

[0051] Specifically, the separation gate line 162 may include a first separation portion 162_1 and a second separation portion 162_2. The first separation portion 162_1 may at least partially surround a plurality of third nanosheets N3 on the third fin F3. For example, the first separation portion 162_1 may surround the third channel region. The second separation portion 162_2 may at least partially surround a plurality of fourth nanosheets N4 on the fourth fin F4. For example, the second separation portion 162_2 may surround the fourth channel region. The first separation portion 162_1 may overlap with the third nanosheet stack NSS3 in the vertical direction (Z direction). The second separation portion 162_2 may overlap with the fourth nanosheet stack NSS4 in the vertical direction (Z direction). The first separation portion 162_1 and the second separation portion 162_2 may overlap with the second vertical structure VS2 in the second horizontal direction (Y direction).

[0052] In some embodiments, the first separation portion 162_1 and the second separation portion 162_2 may be spaced apart from each other in the second horizontal direction (Y direction), wherein the second vertical structure VS2 is located between the first separation portion 162_1 and the second separation portion 162_2. Specifically, the second vertical structure VS2 may insulate the first separation portion 162_1 and the second separation portion 162_2. The first separation portion 162_1 and the second separation portion 162_2 may each be placed on a side surface of the second vertical structure VS2. The separation gate line 162 may not be placed on the top surface VS2_T of the second vertical structure VS2.

[0053] In some embodiments, a top surface of the connection gate line 161 may be located at or above a first vertical height LV1 and at or below a second vertical height LV2 on the first region R1 .

[0054] The uppermost portion 161_Tt of the top surface of the connection gate line 161 may be located at a vertical height higher than the top surface VS1_T of the first vertical structure VS1. The uppermost portion of the top surface may refer to a portion of the top surface located at the highest vertical height. Specifically, the uppermost portion 161_Tt of the top surface of the connection gate line 161 may be located at a second vertical height LV2 higher than the first vertical height LV1.

[0055] In some embodiments, the common portion 161_C of the connection gate line 161 may be located at a higher vertical height than the first connection portion 161_1 and the second connection portion 161_2. For example, the uppermost portion 161_Tt of the top surface of the connection gate line 161 may include the uppermost portion of the top surface of the common portion 161_C. For example, the uppermost portion of the top surface of the common portion 161_C of the connection gate line 161 may be located at the second vertical height LV2. For example, the top surface of the common portion 161_C of the connection gate line 161 may include a portion located at the second vertical height LV2.

[0056] In some embodiments, a top surface of the first connection portion 161_1 and / or the second connection portion 161_2 connecting the gate line 161 may include a portion located at a first vertical height LV1 .

[0057] The lowest portion 161_Tb of the top surface of the connection gate line 161 may be located at the same vertical height as the top surface VS1_T of the first vertical structure VS1. The lowest portion of the top surface may refer to a portion of the top surface located at the lowest vertical height. Specifically, the lowest portion 161_Tb of the top surface of the connection gate line 161 may be located at a first vertical height LV1.

[0058] In some embodiments, the top surface 162_T of the separation gate line 162 may be located at the same vertical height as the top surface VS2_T of the second vertical structure VS2 on the second region R2. Specifically, the top surface 162_T of the separation gate line 162 may be located at the first vertical height LV1. For example, the uppermost portion of the top surface 162_T of the separation gate line 162 may be located at the first vertical height LV1.

[0059] In other words, the uppermost portion 161_Tt of the top surface of the connection gate line 161 on the first region R1 may be located at a vertical height higher than the top surface VS1_T of the first vertical structure VS1, the top surface VS2_T of the second vertical structure VS2, and the top surface 162_T of the separation gate line 162. The lowermost portion 161_Tb of the top surface of the connection gate line 161 may be located at the same vertical height as the top surface VS1_T of the first vertical structure VS1, the top surface VS2_T of the second vertical structure VS2, and the top surface 162_T of the separation gate line 162.

[0060] In some embodiments, an uppermost portion 161_Tt of a top surface of the connection gate line 161 on the first region R1 may overlap the first vertical structure VS1 in a vertical direction (Z direction).

[0061] In some embodiments, a portion of the top surface of the connection gate line 161 overlapping the first connection portion 161_1 and the second connection portion 161_2 may be located at a lower vertical height than an uppermost portion 161_Tt of the top surface of the connection gate line 161. For example, a portion of the top surface of the connection gate line 161 overlapping the first connection portion 161_1 and the second connection portion 161_2 may be located above the first vertical height LV1 and below the second vertical height LV2.

[0062] Therefore, a cross section of the connection gate line 161 of the integrated circuit device 100 perpendicular to the first horizontal direction (X direction) may have a smaller area than when the top surface of the connection gate line 161 is vertically located at the second vertical height LV2. That is, the integrated circuit device 100 in which the capacitance of the connection gate line 161 is reduced may be provided by some embodiments. That is, the integrated circuit device 100 with improved performance and reliability may be provided by some embodiments.

[0063] Each of the plurality of gate lines 160 may include a metal, a metal nitride, a metal carbide, or a combination thereof. The metal may be selected from titanium (Ti), tungsten (W), ruthenium (Ru), niobium (Nb), molybdenum (Mo), hafnium (Hf), nickel (Ni), cobalt (Co), platinum (Pt), ytterbium (Yb), terbium (Tb), dysprosium (Dy), erbium (Er), and palladium (Pd). The metal nitride may be selected from titanium nitride (TiN) and tantalum nitride (TaN). The metal carbide may be titanium aluminum carbide (TiAlC). However, the material constituting the plurality of gate lines 160 is not limited thereto.

[0064] like Figure 1 and Figure 2C As shown in , the first cutting structure CTS1 may be placed between the connecting gate line 161 and the separating gate line 162. The first cutting structure CTS1 may overlap the connecting gate line 161 and the separating gate line 162 in the second horizontal direction (Y direction). The first cutting structure CTS1 may contact the connecting gate line 161 and the separating gate line 162. The first cutting structure CTS1 may insulate the connecting gate line 161 and the separating gate line 162 from each other. The bottom surface of the first cutting structure CTS1 may be located at a vertical height lower than the lowest portion of the bottom surface of each of the connecting gate line 161 and the separating gate line 162. The first cutting structure CTS1 may include a silicon nitride film.

[0065] like Figure 2A and Figure 2B As shown in , a plurality of grooves R may be formed on the fin type active area FA. A vertical height of a lowermost surface of each of the plurality of grooves R may be lower than a vertical height of a fin top surface FT of the fin type active area FA.

[0066] like Figure 2A and Figure 2B As shown in , a plurality of source / drain regions 130 may be placed in a plurality of grooves R. The plurality of source / drain regions 130 may each be placed adjacent to at least one gate line 160 selected from among a plurality of gate lines 160. Each of the plurality of source / drain regions 130 may have a surface facing a plurality of nanosheets included in an adjacent nanosheet stack NSS. Each of the plurality of source / drain regions 130 may be in contact with a plurality of nanosheets included in an adjacent nanosheet stack NSS.

[0067] like Figure 2A and Figure 2C As shown in , the gate dielectric film 152 may be placed between the nanosheet stack NSS and the gate line 160. The gate dielectric film 152 may include a first gate dielectric film 152_1 on the first region R1 and a second gate dielectric film 152_2 on the second region R2.

[0068] The first gate dielectric film 152_1 on the first region R1 may be placed between each of the first nanosheet stack NSS1 and the second nanosheet stack NSS2 and the connection gate line 161. Specifically, the first gate dielectric film 152_1 may be placed between the plurality of first nanosheets N1 and the connection gate line 161, between the plurality of second nanosheets N2 and the connection gate line 161, and between the connection gate line 161 and the first vertical structure VS1. The first gate dielectric film 152_1 may extend on the side surface and the top surface of the first vertical structure VS1. As described above, when the connection gate line 161 is placed on the top surface of the first vertical structure VS1, the first gate dielectric film 152_1 may be placed on the top surface VS1_T of the first vertical structure VS1.

[0069] The second gate dielectric film 152_2 may be placed between each of the third nanosheet stack NSS3 and the fourth nanosheet stack NSS4 and the separation gate line 162 on the second region R2. Specifically, the second gate dielectric film 152_2 may be placed between the plurality of third nanosheets N3 and the separation gate line 162, between the plurality of fourth nanosheets N4 and the separation gate line 162, and between the separation gate line 162 and the second vertical structure VS2. The second gate dielectric film 152_2 may extend on the side surface of the second vertical structure VS2. The second gate dielectric film 152_2 may not be placed on the top surface VS2_T of the second vertical structure VS2.

[0070] In some embodiments, the gate dielectric film 152 may include a structure in which an interface dielectric film and a high dielectric film are stacked. The interface dielectric film may include a low dielectric material film having a dielectric constant of about 9 or less, for example, a silicon oxide film, a silicon oxynitride film, or a combination thereof. In some embodiments, the interface dielectric film may be omitted. The high dielectric film may include a material having a higher dielectric constant than the silicon oxide film. For example, the high dielectric film may have a dielectric constant of about 10 to about 25. The high dielectric film may include hafnium oxide, but is not limited thereto.

[0071] like Figure 2A and Figure 2C As shown in FIG. 1 , the top surface of each of the gate dielectric film 152 and the gate line 160 may be covered or overlapped by a capping insulating pattern 168. The capping insulating pattern 168 may include a silicon nitride film. The capping insulating pattern 168 may be integrated with the above-described first cutting structure CTS1.

[0072] Both sidewalls of each of the gate line 160 and the capping insulating pattern 168 may be covered or overlapped by the outer insulating spacer 118. The outer insulating spacer 118 may cover or overlap both sidewalls of the main gate portion on the top surface of the plurality of nanosheet stacks NSS. The outer insulating spacer 118 may be spaced apart from the gate line 160, with the gate dielectric film 152 located between the outer insulating spacer 118 and the gate line 160.

[0073] like Figure 2B As shown in FIG, a plurality of groove side insulating spacers 119 covering or overlapping the sidewalls of the source / drain region 130 may be disposed on the top surface of the device isolation film 112. In some embodiments, each of the plurality of groove side insulating spacers 119 may be connected to the outer insulating spacer 118 adjacent thereto.

[0074] The plurality of outer insulating spacers 118 and the plurality of groove side insulating spacers 119 may each include silicon nitride, silicon oxide, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or a combination thereof. The terms "SiCN", "SiBN", "SiON", "SiOCN", "SiBCN", and "SiOC" used herein represent materials composed of elements included in each term, and are not chemical formulas representing a stoichiometric relationship.

[0075] The first metal silicide film 172 may be formed on the top surface of each of the plurality of source / drain regions 130. The first metal silicide film 172 may include a metal silicide formed of Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or Pd. For example, the first metal silicide film 172 may include titanium silicide, but is not limited thereto.

[0076] The plurality of source / drain regions 130, the plurality of first metal silicide films 172, and the plurality of outer insulating spacers 118 may be covered or overlapped by an insulating liner 142 on the substrate 102. In some embodiments, the insulating liner 142 may be omitted. The inter-gate insulating film 144 may be disposed on the insulating liner 142. When the insulating liner 142 is omitted, the inter-gate insulating film 144 may contact the plurality of source / drain regions 130.

[0077] The insulating liner 142 and the inter-gate insulating film 144 may be sequentially arranged on the plurality of source / drain regions 130 and the plurality of first metal silicide films 172. The insulating liner 142 and the inter-gate insulating film 144 may form an insulating structure. In some embodiments, the insulating liner 142 may include silicon nitride, SiCN, SiBN, SiON, SiOCN, SiBCN, or a combination thereof, but is not limited thereto. The inter-gate insulating film 144 may include a silicon oxide film, but is not limited thereto.

[0078] Both sidewalls of each of the plurality of sub-gate portions 161S included in the connection gate line 161 may be spaced apart from the source / drain region 130, wherein the first gate dielectric film 152_1 is located between both sidewalls of each of the plurality of sub-gate portions 161S included in the connection gate line 161 and the source / drain region 130. The first gate dielectric film 152_1 may be located between the sub-gate portion 161S included in the connection gate line 161 and each of the plurality of first nanosheets N1, and between the sub-gate portion 161S included in the connection gate line 161 and the adjacent source / drain region 130.

[0079] The plurality of nanosheet stacks NSS may be placed on the fin top surface FT of each of the plurality of fin active regions FA in the region where the plurality of fin active regions FA intersect the plurality of gate lines 160, and may face the fin top surface FT of the fin active region FA at a position spaced apart from the fin active region FA. The plurality of nanosheet transistors may be formed in a portion where the plurality of fin active regions FA intersect the plurality of gate lines 160 on the substrate 102.

[0080] like Figure 2A As shown in , the active contact CA may be disposed on the source / drain region 130. The active contact CA may pass through or extend through the inter-gate insulating film 144 and the insulating liner 142 in the vertical direction (Z direction) to contact the first metal silicide film 172. The active contact CA may be configured to be electrically connected to the source / drain region 130 through the first metal silicide film 172.

[0081] The active contact CA may include a conductive barrier pattern 174 and a contact plug 176 sequentially stacked on the source / drain region 130. The conductive barrier pattern 174 may at least partially surround and contact the bottom surface and sidewall of the contact plug 176. The active contact CA may extend in the vertical direction (Z direction) through the inter-gate insulating film 144 and the insulating liner 142. The conductive barrier pattern 174 may be located between the first metal silicide film 172 and the contact plug 176. The conductive barrier pattern 174 may have a surface in contact with the first metal silicide film 172 and a surface in contact with the contact plug 176. In some embodiments, the conductive barrier pattern 174 may include a metal or a metal nitride. For example, the conductive barrier pattern 174 may include Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof, but is not limited thereto. The contact plug 176 may be composed of Mo, copper (Cu), W, Co, Ru, manganese (Mn), Ti, tantalum (Ta), aluminum (Al), a combination thereof, or an alloy thereof, but is not limited thereto.

[0082] like Figure 2A and Figure 2B As shown in , the top surface of each of the active contact CA, the capping insulating pattern 168 and the inter-gate insulating film 144 may be covered or overlapped by the upper insulating structure 180. The upper insulating structure 180 may include an etch stop film 182 and an interlayer insulating film 184 sequentially stacked on each of the active contact CA, the plurality of capping insulating patterns 168 and the inter-gate insulating film 144. The etch stop film 182 may include silicon carbide (SiC), silicon nitride (SiN), nitrogen-doped silicon carbide (SiC:N), SiOC, AlN, AlON, AlO, AlOC, or a combination thereof. The interlayer insulating film 184 may include an oxide film, a nitride film, an ultra-low-k (ULK) film having an ultra-low dielectric constant k of about 2.2 to about 2.4, or a combination thereof. For example, the interlayer insulating film 184 may include a tetraethyl orthosilicate (TEOS) film, a high density plasma (HDP) oxide film, a borophosphosilicate glass (BPSG) film, a flowable chemical vapor deposition (FCVD) oxide film, a SiON film, a SiN film, a SiOC film, a SiCOH film, or a combination thereof, but is not limited thereto.

[0083] like Figure 2A and Figure 2BAs shown in , a via contact VA may be disposed on the active contact CA. The via contact VA may pass through or extend through the upper insulating structure 180 to contact the active contact CA. Each source / drain region 130 may be configured to be electrically connected to the via contact VA through the first metal silicide film 172 and the active contact CA. The bottom surface of the via contact VA may contact the top surface of the active contact CA. The via contact VA may be composed of W, Mo and / or Ru, but is not limited thereto.

[0084] like Figure 2A and Figure 2B As shown in FIG. 1 , a first wiring line M1 may pass through or extend through the upper insulating film 192. The first wiring line M1 may be connected to a via contact VA located below the first wiring line M1. In some embodiments, the first wiring line M1 may extend in a first horizontal direction (X direction). The first wiring line M1 may include Mo, Cu, W, Co, Ru, Mn, Ti, Ta, Al, a combination thereof, or an alloy thereof, but is not limited thereto.

[0085] like Figure 2A and Figure 2B As shown in , the backside contact BC may pass through or extend through the substrate 102 to contact the source / drain region 130. The backside contact BC may pass through the substrate 102 and the fin type active region FA in the vertical direction (Z direction) to contact the second metal silicide film 171. The backside contact BC may be configured to be electrically connected to the source / drain region 130 through the second metal silicide film 171.

[0086] The backside contact BC may include a barrier pattern 173 and a conductive plug 175 sequentially stacked. The barrier pattern 173 may at least partially surround and contact a sidewall and a top surface of the conductive plug 175. The barrier pattern 173 may be located between the second metal silicide film 171 and the conductive plug 175. The barrier pattern 173 may have a surface in contact with the second metal silicide film 171 and a surface in contact with the conductive plug 175.

[0087] In some embodiments, the barrier pattern 173 may include a metal or a metal nitride. For example, the barrier pattern 173 may include Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof, but is not limited thereto. The conductive plug 175 may be composed of Mo, Cu, W, Co, Ru, Mn, Ti, Ta, Al, a combination thereof, or an alloy thereof, but is not limited thereto.

[0088] like Figure 2A and Figure 2CAs shown in , the first gate contact CB1 electrically connected to the connection gate line 161 may be placed on the first region R1. The first gate contact CB1 may pass through or extend through the upper insulating structure 180 and the capping insulating pattern 168 in the vertical direction (Z direction) to contact the connection gate line 161. The first gate contact CB1 may connect the connection gate line 161 to the first line line M1. In some embodiments, the first gate contact CB1 may be disposed on the top surface of the connection gate line 161. Specifically, the first gate contact CB1 may be disposed on the uppermost portion 161_Tt of the top surface of the connection gate line 161.

[0089] The second gate contact CB2 electrically connected to the separation gate line 162 may be placed on the second region R2. The second gate contact CB2 may pass through or extend through the upper insulating structure 180 and the capping insulating pattern 168 in the vertical direction (Z direction) to contact the separation gate line 162. The second gate contact CB2 may connect the separation gate line 162 to the second line line M2. In some embodiments, the second gate contact CB2 may be disposed on the top surface 162_T of the separation gate line 162.

[0090] Figure 3 and Figure 4 are cross-sectional views of an integrated circuit device 100A and an integrated circuit device 101 according to some embodiments. Figure 1 and FIG. 2A to FIG. 2C The differences in the integrated circuit device 100 are described.

[0091] Reference Figure 3 , an integrated circuit device 100A may be provided. The integrated circuit device 100A may include a connection gate line 161A, and the connection gate line 161A at least partially surrounds the plurality of first nanosheets N1 and the plurality of second nanosheets N2 on the first region R1.

[0092] Specifically, the connection gate line 161A may include a first connection portion 161A_1, a second connection portion 161A_2, and a common portion 161A_C. The first connection portion 161A_1 and the second connection portion 161A_2 may overlap the common portion 161A_C in the vertical direction (Z direction). The first connection portion 161A_1, the second connection portion 161A_2, and the common portion 161A_C may be integrally formed and may be similar to the reference Figure 1 and Figure 2C The first connection portion 161_1, the second connection portion 161_2 and the common portion 161_C are described.

[0093] In some embodiments, a top surface 161A_Tt of the connection gate line 161A may be located at a vertical height higher than a top surface VS1_T of the first vertical structure VS1 on the first region R1. A top surface 161A_Tt of the connection gate line 161A may be located at a vertical height higher than the first vertical height LV1. A top surface 161A_Tt of the connection gate line 161A may be located at a second vertical height LV2.

[0094] In some embodiments, a top surface of the common portion 161A_C connecting the gate lines 161A may be located at a vertical height higher than the first vertical height LV1. A top surface of the common portion 161A_C connecting the gate lines 161A may be located at a second vertical height LV2.

[0095] In other words, the top surface 161A_Tt of the connection gate line 161A on the first region R1 may be located at a higher vertical height than the top surfaces VS1_T of the first vertical structure VS1 , VS2_T of the second vertical structure VS2 , and 162_T of the separation gate line 162 .

[0096] Reference Figure 4 , an integrated circuit device 101 may be provided. The integrated circuit device 101 may include a connection gate line 161 on the first region R1 and a separation gate line 162 on the second region R2.

[0097] In some embodiments, the connection gate line 161 may include a first metal layer 161_M and a first filling metal layer 161_MF on the first metal layer 161_M. Specifically, each of the first connection portion 161_1 , the second connection portion 161_2 , and the common portion 161_C may include a first metal layer 161_M and a first filling metal layer 161_MF.

[0098] The first metal layer 161_M may be located between the first filling metal layer 161_MF and the first gate dielectric film 152_1. The first metal layer 161_M may include a portion between two adjacent first nanosheets N1 among the plurality of first nanosheets N1 and between two adjacent second nanosheets N2 among the plurality of second nanosheets N2. The first metal layer 161_M may be disposed on the top surface and the side surface of the first vertical structure VS1.

[0099] In some embodiments, the main gate portion 161M connected to the gate line 161 (see Figure 2A ) may include a first metal layer 161_M and a first filling metal layer 161_MF. A plurality of sub-gate portions 161S (see Figure 2A) may include a first metal layer 161_M. In some embodiments, each of the main gate portion 161M and the plurality of sub-gate portions 161S may include a first metal layer 161_M and a first filling metal layer 161_MF.

[0100] In some embodiments, the separation gate line 162 may include a second metal layer 162_M and a second filling metal layer 162_MF on the second metal layer 162_M. Specifically, the first separation portion 162_1 may include the second metal layer 162_M and the second filling metal layer 162_MF. The second separation portion 162_2 may include the second metal layer 162_M and the second filling metal layer 162_MF.

[0101] The second metal layer 162_M may be located between the second filling metal layer 162_MF and the second gate dielectric film 152_2. The second metal layer 162_M may include a portion between two adjacent third nanosheets N3 among the plurality of third nanosheets N3 and between two adjacent fourth nanosheets N4 among the plurality of fourth nanosheets N4. The second metal layer 162_M may be disposed on the side surface of the second vertical structure VS2. The second metal layer 162_M may not be disposed on the top surface of the second vertical structure VS2.

[0102] In some embodiments, the main gate portion of the separation gate line 162 may include a second metal layer 162_M and a second filling metal layer 162_MF. The plurality of sub-gate portions of the separation gate line 162 may include a second metal layer 162_M. In some embodiments, the main gate portion and each of the plurality of sub-gate portions of the separation gate line 162 may include a second metal layer 162_M and a second filling metal layer 162_MF.

[0103] In some embodiments, the first metal layer 161_M and the second metal layer 162_M may include Ti. For example, the first metal layer 161_M and the second metal layer 162_M may include TiN, TiC, and / or TiAlC.

[0104] For example, the first filling metal layer 161_MF and the second filling metal layer 162_MF may include W. The first filling metal layer 161_MF and the second filling metal layer 162_MF may include the same metal.

[0105] In some embodiments, the first fin F1 and the second fin F2 may have the same conductivity type. For example, both the first fin F1 and the second fin F2 may have a P-type conductivity type. For example, both the first fin F1 and the second fin F2 may have an N-type conductivity type.

[0106] In some embodiments, the third fin F3 and the fourth fin F4 may have the same conductivity type. For example, both the third fin F3 and the fourth fin F4 may have a P-type conductivity type. For example, both the third fin F3 and the fourth fin F4 may have an N-type conductivity type.

[0107] In some embodiments, the first and second fins F1 and F2 may have a first conductivity type, and the third and fourth fins F3 and F4 may have a second conductivity type. When the first and second fins F1 and F2 have a conductivity type different from that of the third and fourth fins F3 and F4, the first and second metal layers 161_M and 162_M may include different metal layers.

[0108] For example, the first and second fins F1 and F2 may have P-type conductivity, and the third and fourth fins F3 and F4 may have N-type conductivity. In this case, the first metal layer 161_M may include TiN, and the second metal layer 162_M may include TiC and / or TiAlC.

[0109] For example, the first and second fins F1 and F2 may have N-type conductivity, and the third and fourth fins F3 and F4 may have P-type conductivity. In this case, the first metal layer 161_M may include TiC and / or TiAlC, and the second metal layer 162_M may include TiN.

[0110] In some other embodiments, the first fin F1 and the fourth fin F4 may have a third conductivity type, and the second fin F2 and the third fin F3 may have a fourth conductivity type. For example, the first fin F1 and the fourth fin F4 may have a P-type conductivity type, and the second fin F2 and the third fin F3 may have an N-type conductivity type. For example, the first fin F1 and the fourth fin F4 may have an N-type conductivity type, and the second fin F2 and the third fin F3 may have a P-type conductivity type.

[0111] Figure 5 is a plan layout diagram of an integrated circuit device 200 according to some embodiments. Figure 6 is a cross-sectional view of an integrated circuit device 200 according to some embodiments. Specifically, Figure 6 It is along Figure 5 The sectional view taken along the line Y3-Y3' and the line Y4-Y4' is shown below. Figure 1 and FIG. 2A to FIG. 2C The differences in the integrated circuit device 100 are described.

[0112] Reference Figure 5 and Figure 6, an integrated circuit device 200 may be provided. The integrated circuit device 200 may include a plurality of fin-type active regions FA' extending along a first horizontal direction (X direction) on a substrate 202. The substrate 202 may include a third region R3 and a fourth region R4 adjacent to each other in the first horizontal direction (X direction).

[0113] In some embodiments, the integrated circuit device 200 may include a first wiring line M3, a second wiring line M4, a first gate contact CB3, a second gate contact CB4, a second cutting structure CTS2, an upper insulating film 292, an upper insulating structure 280 (etching stop film 282 and interlayer insulating film 284), a capping insulating pattern 268, a gate dielectric film 252 (a first gate dielectric film 252_1, a second gate dielectric film 252_2), a source / drain region 230, and a device isolation film 212. The description of each of the above components may refer to reference. Figure 1 , FIG. 2A to FIG. 2C Description of those components described.

[0114] The plurality of fin-type active regions FA' may extend in a first horizontal direction (X direction) and may include a fifth fin F5, a sixth fin F6, a seventh fin F7, and an eighth fin F8 arranged in a second horizontal direction (Y direction). In some embodiments, the fifth fin F5 may be adjacent to the sixth fin F6 in the second horizontal direction (Y direction). The seventh fin F7 may be adjacent to the eighth fin F8 in the second horizontal direction (Y direction).

[0115] In some embodiments, the fifth fin F5 , the sixth fin F6 , the seventh fin F7 , and the eighth fin F8 may extend across the third region R3 and the fourth region R4 in the first horizontal direction (X direction).

[0116] like Figure 5 and Figure 6 As shown in , a plurality of gate lines 260 extending in the second horizontal direction (Y direction) may be arranged on the plurality of fin type active regions FA'. A plurality of nanosheet stacks NSS' may be arranged on the fin top surface FT of each of the plurality of fin type active regions FA' in a region where the plurality of fin type active regions FA' intersects the plurality of gate lines 260.

[0117] Specifically, the fifth nanosheet stack NSS5 may include a plurality of fifth nanosheets N5 stacked on each other in the vertical direction (Z direction) on the fifth fin F5. Each of the plurality of fifth nanosheets N5 may be referred to as a fifth channel region. The sixth nanosheet stack NSS6 may include a plurality of sixth nanosheets N6 stacked on each other in the vertical direction (Z direction) on the sixth fin F6. Each of the plurality of sixth nanosheets N6 may be referred to as a sixth channel region. The seventh nanosheet stack NSS7 may include a plurality of seventh nanosheets N7 stacked on each other in the vertical direction (Z direction) on the seventh fin F7. Each of the plurality of seventh nanosheets N7 may be referred to as a seventh channel region. The eighth nanosheet stack NSS8 may include a plurality of eighth nanosheets N8 stacked on each other in the vertical direction (Z direction) on the eighth fin F8. Each of the plurality of eighth nanosheets N8 may be referred to as an eighth channel region.

[0118] like Figure 5 and Figure 6 As shown in , the third vertical structure VS3 may be placed between the fifth fin F5 and the sixth fin F6 on the third region R3 of the substrate 202. The third vertical structure VS3 may be placed between the fifth nanosheet stack NSS5 and the sixth nanosheet stack NSS6. The third vertical structure VS3 may be in contact with the plurality of fifth nanosheets N5 included in the fifth nanosheet stack NSS5. The third vertical structure VS3 may be in contact with the side surface of each of the plurality of fifth nanosheets N5 included in the fifth nanosheet stack NSS5. The third vertical structure VS3 may be in contact with the plurality of sixth nanosheets N6 included in the sixth nanosheet stack NSS6. The third vertical structure VS3 may be in contact with the side surface of each of the plurality of sixth nanosheets N6 included in the sixth nanosheet stack NSS6. For example, the third vertical structure VS3 may be in contact with the fifth channel region and the sixth channel region.

[0119] Likewise, the third vertical structure VS3 may be located between the seventh fin F7 and the eighth fin F8 on the third region R3 of the substrate 202. The third vertical structure VS3 may be located between the seventh nanosheet stack NSS7 and the eighth nanosheet stack NSS8. The third vertical structure VS3 may contact the plurality of seventh nanosheets N7 included in the seventh nanosheet stack NSS7. The third vertical structure VS3 may contact the plurality of eighth nanosheets N8 included in the eighth nanosheet stack NSS8. For example, the third vertical structure VS3 may contact the seventh channel region and the eighth channel region.

[0120] The fourth vertical structure VS4 may be located between the fifth fin F5 and the sixth fin F6 on the fourth region R4 of the substrate 202. The fourth vertical structure VS4 may be placed between the fifth nanosheet stack NSS5 and the sixth nanosheet stack NSS6. The fourth vertical structure VS4 may be in contact with a plurality of fifth nanosheets N5 included in the fifth nanosheet stack NSS5. The fourth vertical structure VS4 may be in contact with a side surface of each of the plurality of fifth nanosheets N5 included in the fifth nanosheet stack NSS5. The fourth vertical structure VS4 may be in contact with a plurality of sixth nanosheets N6 included in the sixth nanosheet stack NSS6. The fourth vertical structure VS4 may be in contact with a side surface of each of the plurality of sixth nanosheets N6 included in the sixth nanosheet stack NSS6. For example, the fourth vertical structure VS4 may be in contact with the fifth channel region and the sixth channel region.

[0121] Likewise, the fourth vertical structure VS4 may be located between the seventh fin F7 and the eighth fin F8 on the fourth region R4 of the substrate 202. The fourth vertical structure VS4 may be located between the seventh nanosheet stack NSS7 and the eighth nanosheet stack NSS8. The fourth vertical structure VS4 may contact the plurality of seventh nanosheets N7 included in the seventh nanosheet stack NSS7. The fourth vertical structure VS4 may contact the plurality of eighth nanosheets N8 included in the eighth nanosheet stack NSS8. For example, the fourth vertical structure VS4 may contact the seventh channel region and the eighth channel region.

[0122] like Figure 6 As shown in , the top surface VS3_T of the third vertical structure VS3 and the top surface VS4_T of the fourth vertical structure VS4 may be located at the same vertical height. Specifically, the top surface VS3_T of the third vertical structure VS3 and the top surface VS4_T of the fourth vertical structure VS4 may both be located at a third vertical height LV3.

[0123] like Figure 5 and Figure 6 As shown in the figure, the connection gate line 261 overlapped in the second horizontal direction (Y direction) and the separation gate line 262 overlapped in the second horizontal direction (Y direction) may be placed on the substrate 202. The connection gate line 261 and the separation gate line 262 may not overlap each other in the second horizontal direction (Y direction). Specifically, the connection gate line 261 and the separation gate line 262 may overlap in the first horizontal direction (X direction).

[0124] The connection gate line 261 may be placed on the third region R3 of the substrate 202. The connection gate line 261 may at least partially surround the plurality of fifth nanosheets N5 on the fifth fin F5 on the third region R3 and the plurality of sixth nanosheets N6 on the sixth fin F6 on the third region R3. For example, the connection gate line 261 may at least partially surround the fifth channel region on the fifth fin F5 and the sixth channel region on the sixth fin F6.

[0125] Specifically, the connection gate line 261 may include a first connection portion 261_1, a second connection portion 261_2, and a common portion 261_C. The first connection portion 261_1 may at least partially surround a plurality of fifth nanosheets N5 on the fifth fin F5. For example, the first connection portion 261_1 may surround a fifth channel region on the fifth fin F5. The second connection portion 261_2 may at least partially surround a plurality of sixth nanosheets N6 on the sixth fin F6. For example, the second connection portion 261_2 may surround a sixth channel region on the sixth fin F6. The first connection portion 261_1 and the second connection portion 261_2 may each be placed on a side surface of the third vertical structure VS3. The common portion 261_C may connect the first connection portion 261_1 to the second connection portion 261_2. The common portion 261_C may be placed on the top surface VS3_T of the third vertical structure VS3. The first connection portion 261_1 , the second connection portion 261_2 , and the common portion 261_C connecting the gate line 261 may be integrally formed.

[0126] The first connection portion 261_1 may overlap with the fifth nanosheet stack NSS5 in the vertical direction (Z direction). The second connection portion 261_2 may overlap with the sixth nanosheet stack NSS6 in the vertical direction (Z direction). The common portion 261_C may overlap with the third vertical structure VS3 in the vertical direction (Z direction). The common portion 261_C may be placed on the top surface of the third vertical structure VS3. The third vertical structure VS3 may be placed between the first connection portion 261_1 and the second connection portion 261_2. The third vertical structure VS3 may overlap with the first connection portion 261_1 and the second connection portion 261_2 in the second horizontal direction (Y direction).

[0127] Likewise, the connection gate line 261 may at least partially surround the plurality of seventh nanosheets N7 on the seventh fin F7 on the third region R3 and the plurality of eighth nanosheets N8 on the eighth fin F8 on the third region R3. For example, the connection gate line 261 may at least partially surround the seventh channel region on the seventh fin F7 and the eighth channel region on the eighth fin F8.

[0128] The separation gate line 262 may be placed on the fourth region R4 of the substrate 202. The separation gate line 262 may at least partially surround the plurality of fifth nanosheets N5 on the fifth fin F5 on the fourth region R4 and the plurality of sixth nanosheets N6 on the sixth fin F6 on the fourth region R4. For example, the separation gate line 262 may surround the fifth channel region on the fifth fin F5 on the fourth region R4 and the sixth channel region on the sixth fin F6 on the fourth region R4.

[0129] Specifically, the separation gate line 262 may include a first separation portion 262_1 and a second separation portion 262_2. The first separation portion 262_1 may at least partially surround a plurality of fifth nanosheets N5 on the fifth fin F5. For example, the first separation portion 262_1 may surround a fifth channel region on the fifth fin F5. The second separation portion 262_2 may at least partially surround a plurality of sixth nanosheets N6 on the sixth fin F6. The second separation portion 262_2 may surround a sixth channel region on the sixth fin F6. The first separation portion 262_1 may overlap with the fifth nanosheet stack NSS5 in the vertical direction (Z direction). The second separation portion 262_2 may overlap with the sixth nanosheet stack NSS6 in the vertical direction (Z direction). The first separation portion 262_1 and the second separation portion 262_2 may overlap with the fourth vertical structure VS4 in the second horizontal direction (Y direction).

[0130] In some embodiments, the first separation portion 262_1 and the second separation portion 262_2 may be spaced apart from each other in the second horizontal direction (Y direction), wherein the fourth vertical structure VS4 is located between the first separation portion 262_1 and the second separation portion 262_2. Specifically, the fourth vertical structure VS4 may insulate the first separation portion 262_1 and the second separation portion 262_2. The first separation portion 262_1 and the second separation portion 262_2 may each be placed on a side surface of the fourth vertical structure VS4. The separation gate line 262 may not be placed on the top surface VS4_T of the fourth vertical structure VS4.

[0131] In some embodiments, a top surface of the connection gate line 261 may be located at or above a third vertical height LV3 and at or below a fourth vertical height LV4 on the third region R3 .

[0132] The uppermost portion 261_Tt of the top surface of the connection gate line 261 may be located at a vertical height higher than the top surface VS3_T of the third vertical structure VS3. Specifically, the uppermost portion 261_Tt of the top surface of the connection gate line 261 may be located at a fourth vertical height LV4 higher than the third vertical height LV3.

[0133] The lowermost portion 261_Tb of the top surface of the connection gate line 261 may be located at the same vertical height as the top surface VS3_T of the third vertical structure VS3. Specifically, the lowermost portion 261_Tb of the top surface of the connection gate line 261 may be located at the third vertical height LV3.

[0134] In some embodiments, the top surface 262_T of the separation gate line 262 may be located at the same vertical height as the top surface VS4_T of the fourth vertical structure VS4 on the fourth region R4. Specifically, the top surface 262_T of the separation gate line 262 may be located at the third vertical height LV3. For example, the uppermost portion of the top surface 262_T of the separation gate line 262 may be located at the third vertical height LV3.

[0135] In other words, the uppermost portion 261_Tt of the top surface of the connection gate line 261 on the third region R3 may be located at a vertical height higher than the top surface VS3_T of the third vertical structure VS3, the top surface VS4_T of the fourth vertical structure VS4, and the top surface 262_T of the separation gate line 262. The lowermost portion 261_Tb of the top surface of the connection gate line 261 may be located at the same vertical height as the top surface VS3_T of the third vertical structure VS3, the top surface VS4_T of the fourth vertical structure VS4, and the top surface 262_T of the separation gate line 262.

[0136] In some embodiments, an uppermost portion 261_Tt of the top surface of the connection gate line 261 on the third region R3 may overlap the third vertical structure VS3 in the vertical direction (Z direction).

[0137] Figure 7 is a cross-sectional view of an integrated circuit device 200A according to some embodiments. Figure 5 and Figure 6 The differences in the integrated circuit device 200 are described.

[0138] Reference Figure 7 , an integrated circuit device 200A may be provided. The integrated circuit device 200A may include a connecting gate line 261A, and the connecting gate line 261A at least partially surrounds the plurality of fifth nanosheets N5 and the plurality of sixth nanosheets N6 on the third region R3.

[0139] Specifically, the connection gate line 261A may include a first connection portion 261A_1, a second connection portion 261A_2, and a common portion 261A_C, which may be integrally formed. The first connection portion 261A_1 and the second connection portion 261A_2 may overlap the common portion 261A_C in a vertical direction (Z direction).

[0140] In some embodiments, the top surface 261A_Tt of the connection gate line 261A may be located at a vertical height higher than the top surface VS3_T of the third vertical structure VS3 on the third region R3. The top surface 261A_Tt of the connection gate line 261A may be located at a vertical height higher than the third vertical height LV3. The top surface 261A_Tt of the connection gate line 261A may be located at a fourth vertical height LV4.

[0141] In some embodiments, a top surface of the common portion 261A_C of the connection gate lines 261A may be located at a vertical height higher than the third vertical height LV3. A top surface of the common portion 261A_C of the connection gate lines 261A may be located at a fourth vertical height LV4.

[0142] In other words, the top surface 261A_Tt of the connection gate line 261A on the third region R3 may be located at a vertical height higher than the top surfaces VS3_T of the third vertical structure VS3 , VS4_T of the fourth vertical structure VS4 , and 262_T of the separation gate line 262 .

[0143] Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11 , Fig. 12A , Fig. 12B , Fig.13A and Fig. 13B 1 is a cross-sectional view showing a method for manufacturing an integrated circuit device according to some embodiments according to a process sequence. Specifically, Fig. 8A , Fig.9A , Fig. 10A , Fig. 12A and Fig.13A is corresponding to Figure 2A sectional view of . Figure 8B , Fig. 9B , Fig. 10B , Fig.11 , Fig. 12B and Fig. 13B is corresponding to Figure 2C sectional view of .

[0144] Reference Fig. 8A and Figure 8B , a first fin F1, a second fin F2, a third fin F3, and a fourth fin F4 may be defined on the first surface 102_1 of the substrate 102 by etching a portion of the substrate 102. Then, a device isolation film 112 covering or overlapping a sidewall of each of the first fin F1, the second fin F2, the third fin F3, and the fourth fin F4 may be formed.

[0145] A plurality of nanosheet stacks NSS including a plurality of nanosheets N1 , N2 , N3 , and N4 may be formed on the fin top surface FT of each of the first fin F1 , the second fin F2 , the third fin F3 , and the fourth fin F4 .

[0146] A first vertical structure VS1 contacting the first nanosheet stack NSS1 and the second nanosheet stack NSS2 may be formed, and a second vertical structure VS2 contacting the third nanosheet stack NSS3 and the fourth nanosheet stack NSS4 may be formed. The first vertical structure VS1 and the second vertical structure VS2 may be formed by disposing a dielectric material between the first nanosheet stack NSS1 and the second nanosheet stack NSS2 and between the third nanosheet stack NSS3 and the fourth nanosheet stack NSS4.

[0147] A main gate space GSM may be formed on the plurality of nanosheet stacks NSS, and a plurality of sub gate spaces GSS may be formed between the plurality of nanosheets N1, N2, N3, and N4 and between the plurality of nanosheets N1, N2, N3, and N4 and the fin top surface FT.

[0148] Reference Fig.9A and Fig. 9B , gate dielectric films 152_1 and 152_2 are formed on the plurality of nanosheets N1, N2, N3, and N4, the first vertical structure VS1, and the second vertical structure VS2. Specifically, on the first region R1 of the substrate 102, the first gate dielectric film 152_1 may be formed on the top surface of the device isolation film 112, the top surface, the side surface, and the bottom surface of each of the plurality of first nanosheets N1 and the plurality of second nanosheets N2, and the side surface and the top surface of the first vertical structure VS1. On the second region R2 of the substrate 102, the second gate dielectric film 152_2 may be formed on the top surface of the device isolation film 112, the top surface, the side surface, and the bottom surface of each of the plurality of third nanosheets N3 and the plurality of fourth nanosheets N4, and the side surface and the top surface of the second vertical structure VS2.

[0149] Subsequently, a gate-forming conductive layer 160L may be formed on the gate dielectric films 152_1 and 152_2. The gate-forming conductive layer 160L may be formed on the top surface of the device isolation film 112, the top surface, the side surface, and the bottom surface of each of the plurality of nanosheets N1, N2, N3, and N4, the side surface and the top surface of the first vertical structure VS1, and the side surface and the top surface of the second vertical structure VS2. The top surface of the gate-forming conductive layer 160L may be located at the same vertical height as the top surface of each of the insulating liner 142 and the inter-gate insulating film 144.

[0150] Reference Fig. 10A and Fig. 10B, a portion of the gate-forming conductive layer 160L may be removed. As a result, a top surface of the gate-forming conductive layer 160L may be located at a fifth vertical height LV5.

[0151] Reference Fig.11 , a first hardmask film HM1 may be formed on the first region R1 of the substrate 102, and the gate-forming conductive layer 160L and the gate dielectric film may be etched using the first hardmask film HM1 as a mask. Through the above process, the gate-forming conductive layer 160L and the second gate dielectric film 152_2 on the top surface of the second vertical structure VS2 may be etched to expose the top surface of the second vertical structure VS2. Through the above process, the top surface of the gate-forming conductive layer 160L on the first region R1 may include a portion located at the first vertical height LV1. Through the above process, the top surface of the gate-forming conductive layer 160L on the second region R2 may be located at the first vertical height LV1.

[0152] Reference Fig. 12A and Fig. 12B After removing the first hard mask film HM1 and etching the gate-forming conductive layer 160L under the first hard mask film HM1, the uppermost portion of the top surface of the gate-forming conductive layer 160L may be positioned at the second vertical height LV2. Subsequently, a cutting trench CT_tr may be formed by etching the gate-forming conductive layer 160L and the device isolation film 112 between the second fin F2 and the third fin F3.

[0153] Through the above process, the connection gate line 161 may be formed on the first region R1, and the separation gate line 162 may be formed on the second region R2. The uppermost portion of the top surface of the connection gate line 161 may be located at the second vertical height LV2, and the lowermost portion of the top surface of the connection gate line 161 and the top surface of the separation gate line 162 may be located at the first vertical height LV1.

[0154] Reference Fig.13A and Fig. 13B , a first cutting structure CTS1 may be formed in the cutting trench CT_tr, and a capping insulating pattern 168 may be formed on top surfaces of the connection gate line 161 , the separation gate line 162 , and the second vertical structure VS2 .

[0155] Subsequently, subsequent processes may be performed to produce a reference Figure 1 and FIG. 2A to FIG. 2C An integrated circuit device 100 is described.

[0156] Fig.14 , Fig.15 and Fig.161 is a cross-sectional view shown according to a process sequence for explaining a method for manufacturing an integrated circuit device 100A according to some embodiments. Specifically, Fig.14 , Fig.15 and Fig.16 is corresponding to Figure 3 A cross-sectional view of Fig. 10A and Fig. 10B The stage that is executed after the stage.

[0157] Reference Fig.14 , a second hard mask film HM2 may be formed on the first region R1 of the substrate 102, and the gate-forming conductive layer 160AL and the gate dielectric film may be etched using the second hard mask film HM2 as a mask. Through the above process, the gate-forming conductive layer 160AL and the gate dielectric film 152 on the top surface of the second vertical structure VS2 may be etched to expose the top surface of the second vertical structure VS2. Through the above process, the top surface of the gate-forming conductive layer 160AL on the second region R2 may be located at the first vertical height LV1.

[0158] Reference Fig.15 After removing the second hard mask film HM2 and etching the gate-forming conductive layer 160AL under the second hard mask film HM2, the uppermost portion of the top surface of the gate-forming conductive layer 160AL may be positioned at the second vertical height LV2. Subsequently, a cutting trench CT_tr may be formed by etching the gate-forming conductive layer 160AL and the device isolation film 112 between the second fin F2 and the third fin F3.

[0159] Through the above process, the connection gate line 161A may be formed on the first region R1, and the separation gate line 162 may be formed on the second region R2. The top surface of the connection gate line 161A may be located at the second vertical height LV2, and the top surface of the separation gate line 162 may be located at the first vertical height LV1.

[0160] Reference Fig.16 , a first cutting structure CTS1 may be formed in the cutting trench CT_tr, and a capping insulating pattern 168 may be formed on top surfaces of the connection gate line 161A, the separation gate line 162, and the second vertical structure VS2.

[0161] Subsequently, subsequent processes may be performed to produce a reference Figure 3 An integrated circuit device 100A is described.

[0162] While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit device, comprising: a substrate comprising a first region and a second region; a first fin and a second fin extending in a first horizontal direction, on a first region, and adjacent to each other in a second horizontal direction intersecting the first horizontal direction; a third fin and a fourth fin extending in the first horizontal direction, on the second region, and adjacent to each other in the second horizontal direction; a first channel region on the first fin; a second channel region on the second fin; a third channel region, on a third fin; a fourth channel region on a fourth fin; a connecting gate line at least partially surrounding the first channel region and the second channel region, extending in the second horizontal direction, and on the first region; a separation gate line including a first separation portion and a second separation portion, the first separation portion at least partially surrounding the third channel region, the second separation portion at least partially surrounding the fourth channel region, wherein the third channel region and the fourth channel region extend in a second horizontal direction and on the second region; a first vertical structure between the first channel region and the second channel region; a second vertical structure between the third channel region and the fourth channel region and insulating the first separation portion and the second separation portion of the separation gate line from each other; and A plurality of source / drain regions respectively contact the first channel region, the second channel region, the third channel region and the fourth channel region, wherein the top surface of the first vertical structure and the top surface of the second vertical structure are at a first vertical height, wherein an uppermost portion of the top surface of the connection gate line is at a second vertical height higher than the first vertical height, and Wherein an uppermost portion of a top surface of the separation gate line is at a first vertical height.

2. The integrated circuit device according to claim 1, wherein: A lowermost portion of the top surface of the connection gate line is at a first vertical height.

3. The integrated circuit device according to claim 1, wherein: Connecting the gate lines includes: a first connection portion at least partially surrounding the first channel region and on the first fin; a second connection portion at least partially surrounding the second channel region and on the second fin; and The common portion electrically connects the first connection portion to the second connection portion and includes an uppermost portion connected to a top surface of the gate line.

4. The integrated circuit device according to claim 1, further comprising: a first gate contact electrically connected to a connecting gate line; as well as The second gate contact is electrically connected to the separation gate line.

5. The integrated circuit device according to claim 1, wherein: The first region is adjacent to the second region in a second horizontal direction, The connecting gate line overlaps the separating gate line in a second horizontal direction, and The integrated circuit device further includes a cutting structure between the connecting gate line and the separating gate line and insulating the connecting gate line and the separating gate line from each other.

6. The integrated circuit device according to claim 1, wherein: An uppermost portion of the top surface of the connection gate line overlaps the first vertical structure in a vertical direction.

7. An integrated circuit device comprising: a substrate including a first region; a first fin and a second fin extending in a first horizontal direction, on a first region, and adjacent to each other in a second horizontal direction intersecting the first horizontal direction; a first nanosheet stack including a plurality of first nanosheets and on the first fin; a second nanosheet stack including a plurality of second nanosheets and on the second fin; a connecting gate line at least partially surrounding the plurality of first nanosheets and the plurality of second nanosheets and extending in a second horizontal direction on the first region; a first vertical structure contacting the first nanosheet stack and the second nanosheet stack and between the first nanosheet stack and the second nanosheet stack; as well as A plurality of source / drain regions are spaced apart from each other, wherein a connecting gate line is connected between the plurality of source / drain regions, wherein the top surface of the first vertical structure is at a first vertical height, wherein the uppermost portion of the top surface of the connection gate line is at a second vertical height higher than the first vertical height, wherein the lowest portion of the top surface connected to the gate line is at a first vertical height, and Wherein, the uppermost portion of the top surface connected to the gate line overlaps with the first vertical structure in the vertical direction.

8. The integrated circuit device according to claim 7, wherein: The connecting gate line includes a first connecting portion, a second connecting portion, and a common portion, the first connecting portion at least partially surrounding the plurality of first nanosheets and on the first fin, the second connecting portion at least partially surrounding the plurality of second nanosheets and on the second fin, the common portion electrically connecting the first connecting portion to the second connecting portion, the common portion including an uppermost portion of a top surface of the connecting gate line, and A top surface of at least one of the first connection portion and the second connection portion includes a corresponding portion at a first vertical height.

9. The integrated circuit device according to claim 7, further comprising a first gate dielectric film between the plurality of first nanosheets and the connecting gate line, between the plurality of second nanosheets and the connecting gate line, and between the first vertical structure and the connecting gate line, wherein A portion of the first gate dielectric film is on a top surface of the first vertical structure.

10. The integrated circuit device according to claim 7, further comprising: a third fin and a fourth fin extending in the first horizontal direction, on the second region of the substrate, and adjacent to each other in the second horizontal direction, wherein the first region is adjacent to the second region in the second horizontal direction; a third nanosheet stack including a plurality of third nanosheets and on a third fin; a fourth nanosheet stack including a plurality of fourth nanosheets and on a fourth fin; a separation gate line comprising a first separation portion and a second separation portion, the first separation portion at least partially surrounding the plurality of third nanosheets, the second separation portion at least partially surrounding the plurality of fourth nanosheets, wherein the separation gate line extends in a second horizontal direction and is on a second region; a second vertical structure contacting the plurality of third nanosheets and the plurality of fourth nanosheets, between the third nanosheet stack and the fourth nanosheet stack, and insulating the first separation portion and the second separation portion from each other; and The cutting structure is between the connecting gate line and the separating gate line, and the connecting gate line and the separating gate line are insulated from each other, wherein the top surface of the second vertical structure is at a first vertical height, and Wherein an uppermost portion of a top surface of the separation gate line is at a first vertical height.

11. The integrated circuit device according to claim 10, wherein: The first fin and the second fin have a first conductivity type, and The third fin and the fourth fin have a second conductivity type different from the first conductivity type.

12. The integrated circuit device according to claim 10, further comprising: a first gate contact electrically connected to a connection gate line; and The second gate contact is electrically connected to the separation gate line.

13. The integrated circuit device according to claim 10, wherein: The connecting gate line overlaps the separating gate line in a second horizontal direction, and The cutting structure overlaps the connecting gate line and the separating gate line in a second horizontal direction.

14. The integrated circuit device according to claim 10, further comprising a second gate dielectric film between the plurality of third nanosheets and the first separation portion and between the plurality of fourth nanosheets and the second separation portion, wherein: The second gate dielectric film is not on the top surface of the second vertical structure.

15. The integrated circuit device according to claim 7, further comprising: a third fin and a fourth fin extending in the first horizontal direction, on the second region of the substrate, and adjacent to each other in the second horizontal direction, wherein the second region does not overlap the first region of the substrate in the second horizontal direction; a third nanosheet stack including a plurality of third nanosheets and on a third fin; a fourth nanosheet stack including a plurality of fourth nanosheets and on a fourth fin; a separation gate line, the separation gate line comprising a first separation portion at least partially surrounding the plurality of third nanosheets and a second separation portion at least partially surrounding the plurality of fourth nanosheets, wherein the separation gate line extends in a second horizontal direction and is on the second area; and a second vertical structure contacting the plurality of third nanosheets and the plurality of fourth nanosheets, between the third nanosheet stack and the fourth nanosheet stack, and insulating the first separation portion and the second separation portion from each other, wherein the top surface of the second vertical structure is at a first vertical height, and An uppermost portion of a top surface of the separation gate line is at a first vertical height.

16. The integrated circuit device according to claim 7, wherein: The first fin and the second fin extend on a second region of the substrate, the second region of the substrate being adjacent to the first region in a first horizontal direction, The integrated circuit device further includes a separation gate line and a second vertical structure, the separation gate line including a first separation portion and a second separation portion, the first separation portion being on the first fin and the second region, the second separation portion being on the second fin and the second region, the second vertical structure being between the first separation portion and the second separation portion and insulating the first separation portion and the second separation portion from each other, The first separation portion and the second separation portion extend in a second horizontal direction, The separation gate line overlaps the connection gate line in a first horizontal direction, The top surface of the second vertical structure is at a first vertical height, and An uppermost portion of a top surface of the separation gate line is at a first vertical height.

17. The integrated circuit device according to any one of claims 7 to 16, wherein: The first vertical structure includes a portion between the first fin and the second fin.

18. An integrated circuit device comprising: a substrate including a first region and a second region adjacent to each other in a second horizontal direction intersecting the first horizontal direction; a first fin and a second fin extending in a first horizontal direction, on a first region, and adjacent to each other in a second horizontal direction; a third fin and a fourth fin extending in the first horizontal direction, on the second region, and adjacent to each other in the second horizontal direction; a first nanosheet stack including a plurality of first nanosheets and on the first fin; a second nanosheet stack including a plurality of second nanosheets and on the second fin; a third nanosheet stack including a plurality of third nanosheets and on a third fin; a fourth nanosheet stack including a plurality of fourth nanosheets and on a fourth fin; a connecting gate line at least partially surrounding the plurality of first nanosheets and the plurality of second nanosheets, extending in a second horizontal direction, and on the first region; a separation gate line comprising a first separation portion and a second separation portion, the first separation portion at least partially surrounding the plurality of third nanosheets, the second separation portion at least partially surrounding the plurality of fourth nanosheets, wherein the separation gate line overlaps the connection gate line in a second horizontal direction, and wherein the separation gate line extends in the second horizontal direction and is on the second region; a first vertical structure contacting the plurality of first nanosheets and the plurality of second nanosheets and between the first fin and the second fin; a second vertical structure contacting the plurality of third nanosheets and the plurality of fourth nanosheets, between the third fin and the fourth fin, and insulating the first separation portion and the second separation portion from each other; A cutting structure is provided between the connecting gate line and the separating gate line, and the connecting gate line and the separating gate line are insulated from each other; a first gate contact electrically connected to a connection gate line; and a second gate contact electrically connected to the separation gate line, wherein each of the top surface of the first vertical structure and the top surface of the second vertical structure is at a first vertical height, wherein the uppermost portion of the top surface of the connection gate line is at a second vertical height higher than the first vertical height, wherein an uppermost portion of a top surface of the separation gate line is at a first vertical height, and Wherein, the uppermost portion of the top surface connected to the gate line overlaps with the first vertical structure in the vertical direction.

19. The integrated circuit device according to claim 18, wherein: A lowermost portion of the top surface of the connection gate line is at a first vertical height.

20. The integrated circuit device according to claim 18, wherein: The connecting gate line includes a first connecting portion, the first connecting portion at least partially surrounding the plurality of first nanosheets and on the first fin, The connecting gate line includes a second connecting portion at least partially surrounding the plurality of second nanosheets and on the second fin, The connection gate line includes a common portion electrically connecting the first connection portion to the second connection portion, the common portion including an uppermost portion of a top surface of the connection gate line, and A top surface of at least one of the first connection portion and the second connection portion includes a corresponding portion at a first vertical height.

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