Integrated circuit structure with stacked transistors employing backside access

Abstract

Structures having stacked transistors with backside access are described. In an example, an integrated circuit structure includes a front surface structure. The front surface structure comprises a first nanowire stack body, a second nanowire stack body, a third nanowire stack body, a fourth nanowire stack body, a first overlying gate line, a second overlying gate line, a third overlying gate line, a fourth overlying gate line and a device layer, wherein the first overlying gate line, the second overlying gate line, the third overlying gate line and the fourth overlying gate line correspond to the first nanowire stack body, the second nanowire stack body, the third nanowire stack body and the fourth nanowire stack body. And the device layer includes a first source or drain structure, a second source or drain structure, a third source or drain structure, a fourth source or drain structure, and a fifth source or drain structure and corresponding overlying trench contacts alternating with the nanowire stack and the overlying gate line; and one or more metallization layers over the device layer. The backside structure includes a backside via connection coupled to a bottom portion of the third source or drain structure, the bottom portion of the third source or drain structure being isolated from a top portion of the third source or drain structure.

Description

Background Art

[0001] For the past several decades, the scaling of features in integrated circuits has been the driving force behind the continued growth of the semiconductor industry. Scaling to smaller and smaller features allows for an increased density of functional units to be implemented on the limited chip area of ​​a semiconductor chip. For example, shrinking the size of transistors allows an increased number of memory or logic devices to be incorporated onto a chip, thereby creating a product with increased capacity. However, the constant pursuit of higher capacity is not without its problems. The necessity to optimize the performance of each device becomes increasingly greater.

[0002] In the manufacture of integrated circuit devices, as the size of devices continues to shrink, multi-gate transistors (e.g., tri-gate transistors) become more and more dominant. In conventional processes, tri-gate transistors are generally made on bulk silicon substrates or on silicon-on-insulator substrates. In some cases, bulk silicon substrates are preferred because of their lower cost and the ability to achieve a tri-gate manufacturing process with lower complexity. On the other hand, maintaining improved mobility and short channel control while shrinking the size of microelectronic devices to below the 10 nanometer (nm) node will bring challenges to device manufacturing. Nanowires used to make devices provide improved short channel control.

[0003] However, scaling of multi-gate and nanowire transistors is not without consequences. As the size of these basic building blocks of microelectronic circuitry decreases and the absolute number of basic building blocks that can be fabricated in a given area increases, limitations on the photolithographic processes used to pattern these building blocks become difficult to overcome. Specifically, there may be a trade-off between the minimum size (critical dimension) of a feature patterned in a semiconductor stack and the spacing between such features.

[0004] Another area driving innovation is the pursuit of high-bandwidth (HBW) computing. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 Cross-sectional views of an interconnect stack with front side power delivery and an interconnect stack with back side power delivery are shown according to embodiments of the present disclosure.

[0006] Figure 2 A cross-sectional view of a double-sided device according to an embodiment of the present disclosure is shown.

[0007] Figure 3A A plan view of an integrated circuit structure including a 4-poly pitch (4pp) based complementary field effect transistor (CFET) bit cell is shown according to an embodiment of the present disclosure.

[0008] Figure 3B yes Figure 3ASchematic diagram of one of the bit cells.

[0009] Figure 3C yes Figure 3A A cross-sectional view of one of the bit cells.

[0010] Figure 4A A plan view of an integrated circuit structure including a 4-poly pitch (4pp) based complementary field effect transistor (CFET) bit cell is shown according to an embodiment of the present disclosure.

[0011] Figure 4B yes Figure 4A Cross-sectional view of a bit cell.

[0012] Figure 4C A plan view of an integrated circuit structure including a 4-poly pitch (4pp) based complementary field effect transistor (CFET) bit cell is shown according to an embodiment of the present disclosure.

[0013] Figure 4D yes Figure 4C Cross-sectional view of a bit cell.

[0014] Figure 5A A plan view of a semiconductor device having a gate contact disposed over an inactive portion of a gate electrode is shown.

[0015] Figure 5B A cross-sectional view of a non-planar semiconductor device having a gate contact disposed over an inactive portion of a gate electrode is shown.

[0016] Fig. 6A A plan view of a semiconductor device having a gate contact via disposed over an active portion of a gate electrode according to an embodiment of the present disclosure is shown.

[0017] Figure 6B A cross-sectional view of a non-planar semiconductor device having a gate contact via disposed over an active portion of a gate electrode according to an embodiment of the present disclosure is shown.

[0018] Figures 7A-7J Cross-sectional views are illustrated of various operations in a method of fabricating a gate-all-around integrated circuit structure in accordance with an embodiment of the present disclosure.

[0019] Figure 8 A cross-sectional view of a non-planar integrated circuit structure taken along a gate line according to an embodiment of the present disclosure is shown.

[0020] Fig. 9 Cross-sectional views taken through nanowires and fins are shown for a non-endcap architecture (left side (a)) and a comparative self-aligned gate endcap (SAGE) architecture (right side (b)) according to an embodiment of the present disclosure.

[0021] Fig.10 Cross-sectional views representing various operations in a method of fabricating a self-aligned gate endcap (SAGE) structure with a gate-all-around device in accordance with an embodiment of the present disclosure are illustrated.

[0022] Fig.11A A three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to an embodiment of the present disclosure is shown.

[0023] Fig. 11B The diagram according to an embodiment of the present disclosure is taken along the a-a' axis. Fig.11A A cross-sectional source or drain view of a nanowire-based integrated circuit structure.

[0024] Fig. 11C FIG. 2 shows a cross-sectional view taken along the bb' axis according to an embodiment of the present disclosure. Fig.11A Cross-sectional channel diagram of a nanowire-based integrated circuit structure.

[0025] Fig.12 A computing device according to one implementation of an embodiment of the present disclosure is shown.

[0026] Fig.13 An interposer including one or more embodiments of the present disclosure is shown.

[0027] Fig.14A A computing device according to one implementation of an embodiment of the present disclosure is shown.

[0028] Fig. 14B A processing device according to one implementation of an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0029] An integrated circuit structure with stacked transistors using backside access is described. In the following description, many specific details are set forth, such as specific integration and material systems, in order to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that the embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail to avoid unnecessarily obscuring the embodiments of the present disclosure. In addition, it should be recognized that the various embodiments shown in the drawings are illustrative representations only and are not necessarily drawn to scale.

[0030] Certain terms are also used in the following description for reference purposes only, and therefore these terms are not intended to be limiting. For example, terms such as "upper," "lower," "above," and "below" refer to directions in the drawings to which reference is made. Terms such as "front," "back," "rear," and "side" describe the orientation and / or position of portions of a component within a consistent but arbitrary reference system, which orientation and / or position can be clearly understood by reference to the text describing the component in question and the associated drawings. Such terminology may include the words specifically mentioned above, their derivatives, and words of similar meaning.

[0031] Embodiments described herein may relate to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) fabrication, where individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or semiconductor layer. FEOL generally encompasses all processing up to (but not including) the deposition of metal interconnect layers. Following the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

[0032] Embodiments described herein may relate to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second part of IC fabrication where the various devices (e.g., transistors, capacitors, resistors, etc.) are interconnected using wires on the wafer (e.g., one or more metallization layers). BEOL includes contacts, insulating layers (dielectrics), metal levels, and joints for chip-to-package connections. In the BEOL portion of the fabrication phase, contacts (pads), interconnect wires, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in the BEOL.

[0033] The embodiments described below may be applicable to FEOL processes and structures, BEOL processes and structures, or both FEOL processes and structures and BEOL processes and structures. Specifically, although exemplary processing schemes may be illustrated using a FEOL processing context, such schemes may also be applicable to BEOL processing. Similarly, although exemplary processing schemes may be illustrated using a BEOL processing context, such schemes may also be applicable to FEOL processing.

[0034] One or more embodiments described herein relate to a wide stacked transistor (CFET) SRAM bit cell architecture, for example, for a double-sided device. In some embodiments, the device is a nanowire-based device. It should be appreciated that unless otherwise indicated, references to nanowires herein may indicate nanowires or nanoribbons or even nanosheets. In other embodiments, the device is a fin-based device or a fork-based device.

[0035] To provide context, in a standard cell design, the diffusion placement and metal routing layers are designed around the power delivery scheme. This can be done through front side bumps that reach the M0 and diffusion contacts, or in newer architectures, it can be done through wafer back side metal that is tapped through vias that make contact with the diffusion contacts on the front side. When doing this, there is a space allocation for delivering power, either on the front side metal or on the diffusion.

[0036] Traditionally, power is delivered from the front interconnect. At the standard cell level, power can be delivered just at the top of the transistor or from the top and bottom cell boundaries. The power delivered from the top and bottom cell boundaries allows a relatively short standard cell height to be achieved along with a slightly higher power network resistance. However, the front power network shares the interconnect stack with the signal wiring and reduces the signal wiring trace. In addition, for high-performance designs, the top and bottom cell boundary power metal wires must be wide enough to reduce the power network resistance and improve performance. This usually leads to an increase in cell height. According to one or more embodiments of the present disclosure, power can be delivered from the back of the wafer or substrate to solve area and performance issues. At the cell level, the wider metal 0 power at the top and bottom cell boundaries may no longer be needed, so that the cell height can be reduced. In addition, the power network resistance can be significantly reduced, thereby obtaining performance improvement. At the block and chip level, the front signal wiring trace is increased due to the removal of the power wiring, and the power network resistance is significantly reduced due to the very wide wires, large vias, and reduced interconnect layers.

[0037] In earlier technologies, the power delivery network from the bumps to the transistors required significant block resources. The use of such resources on the metal stack has manifested itself in some process nodes as a standard cell architecture with block-level layout version selection or cell placement restrictions. In an embodiment, eliminating the power delivery network from the front metal stack allows free sliding of cell placement in the block without causing power delivery complications and placement-related delay timing variations.

[0038] As a comparison, Figure 1 Cross-sectional views of an interconnect stack with front side power delivery and an interconnect stack with back side power delivery are shown according to embodiments of the present disclosure.

[0039] refer to Figure 1 , an interconnect stack 100 with front side power delivery includes a transistor 102 and a signal and power delivery metallization 104. The transistor 102 includes a bulk substrate 106, a semiconductor fin 108, a terminal 110, and a device contact 112. The signal and power delivery metallization 104 includes a conductive via 114, a conductive line 116, and a metal bump 118.

[0040] Reference again Figure 1 , an interconnect stack 150 with backside power delivery includes a transistor 152, a frontside signal metallization 154A, and a power delivery metallization 154B. The transistor 152 includes a semiconductor nanowire or nanoribbon 158, a terminal 160 and a device contact 162, and a boundary deep via 163. The frontside signal metallization 154A includes a conductive via 164A and a conductive line 166A. The power delivery metallization 154B includes a conductive via 164B, a conductive line 166B, and a metal bump 168. It should be appreciated that in other embodiments, a backside power delivery network (BS-PDN) for a gate all around (GAA) device is implemented from the backside using a direct contact to the epitaxy (source or drain) (as opposed to through a via to the TCN).

[0041] To provide further context, one of the ultimate goals in standard cell design is to minimize the impact of power delivery on signal routing in terms of area while maintaining a robust power delivery scheme that should have minimal voltage drop relative to the power supply. With front-side power delivery, commercial standard cell architectures must allocate routing tracks for power and ground from the top of the front-side stack to the first metal wiring layer M0. This scheme will use metal wiring tracks. This means that tighter metal spacing is required to deliver power while routing signals. Tighter metal spacing leads to higher capacitance and resistance, resulting in higher power consumption. In addition, due to resistance, a larger voltage drop occurs from the top of the stack to the transistor source.

[0042] As an exemplary (but not limiting) structure that can be the basis for the embodiments described herein, Figure 2 A cross-sectional view of a double-sided device according to an embodiment of the present disclosure is shown.

[0043] refer to Figure 2 , the integrated circuit structure 200 includes a front side structure 204 and a back side structure 202, which may be separated by a dielectric layer 205. The front side structure 204 includes a device layer 206 and a plurality of metallization layers 208 located on the device layer 206. The structure 200 is supported by a Si (100) carrier wafer 210 and an intervening approximately 400 nm SiOx layer 211 located on the front side structure 204. The back side structure 202 includes a stack of back side conductive structures 218.

[0044] about Figure 2 , it should be appreciated that while a gate-all-around based transistor is depicted, embodiments may be applied to channels having any shape or material (e.g., fins, nanowires, nanoribbons, nanocombs / forks, etc.). Figure 2It should be appreciated that although a single layer of transistors is shown, embodiments may be applied to multi-layer transistor architectures.

[0045] In accordance with one or more embodiments of the present disclosure, wide stacked transistors, such as complementary field effect transistors (CFETs), for use in a static random access memory (SRAM) bit cell architecture are described.

[0046] To provide context, three-dimensional (3D) stacked complementary field effect transistor (CFET) SRAMs utilizing standard 2pp wide devices require some version of split gate (for efficient routing) and gate contact (GCN) connections. Embodiments described herein may include 4pp wide designs that do not require any of these features.

[0047] Prior art CFET structures may include bit cells at 2 poly pitch (2pp) along with backside GCN to provide cross coupling. This 2pp wide solution requires a split gate process. The split gate process may involve several additional masks to define the cutouts in the upper and lower gates and masks to make the connections between the upper and lower gates. In general, the split gate process may involve a very complex process flow.

[0048] Embodiments described herein may include (as an alternative to using 2pp wide bit cells) the use of 4-poly pitch (4pp) in conjunction with cross-coupling implemented using standard metal 0 (M0) lines. This implementation can completely eliminate the need for GCNs, with the added benefit that the bit lines can be located on the back side of the cell.

[0049] Advantages of implementing the embodiments described herein may include providing large SRAM bit cell area improvements (approximately 6 times) with minimal complexity and minimal masks. Additionally, placing the bit lines on the back side of the structure may allow for larger wires and a reduction in bit line (BL) resistance. Additionally, swapping the n- and p-positions may allow for direct passgate connections to the back side bit lines, which reduces BL capacitance.

[0050] Detectability of implementing the embodiments described herein may include that the bit cells described herein may be detectable during reverse engineering. The bit cells may be seen from top-down reverse engineering or XSEM. The array will likely require some de-processing to view the bit cells from top-down.

[0051] As a first exemplary embodiment, Figure 3A A plan view of an integrated circuit structure 300 including a 4-poly pitch (4pp) based complementary field effect transistor (CFET) bit cell is shown according to an embodiment of the present disclosure. Figure 3B yes Figure 3A Schematic diagram of one of the bit cells 325. Figure 3C yes Figure 3A A cross-sectional view of one of the bit cells.

[0052] refer to Figure 3A , the integrated circuit structure 300 includes a layout 301 based on a first bit cell 302 and a second bit cell 304. A diffusion region 306 (e.g., a stack of nanowires (or alternatively, a fin structure)) is included in each bit cell 302 and 304. Gate lines 307 (polysilicon) and trench contact lines 308 alternate with each other and are along a direction orthogonal to the diffusion regions 306. The bit line 310 is along a direction parallel to the diffusion regions 306. A backside power connection via 320 is included for each bit cell 302 and 304.

[0053] refer to Figure 3C , features visible from the cross-sectional view include oxide or dielectric structures 330 located at the locations of depopulated nanowires 332. Backside via power connections couple the bottom source or drain (Bot SD) to the VCC power line 331 and may extend through bottom oxide or dielectric 335. Epitaxial source or drain structures 333 located below trench contact structures 308 are isolated in some cases by structures 338 (to provide Bot SD and top source or drain Top SD) or electrically coupled by epi-epitaxial connections 336.

[0054] Reference again Figures 3A-3C In an embodiment, two 4pp CFET bit cells are laid out so that each bit cell is 4 poly pitches wide, and the pass gate is on the edge of the cell, and the cross coupling (n0 / n1) is implemented with metal 0 instead of GCN. No split gate is required. In this embodiment, the bit line is raised to M2 (not shown). Figure 3C As can be seen from the cross-sectional view of FIG. 3 , cross-coupling 334 is achieved through M0. The n transmission gates do not have active p transistors located below them. The deleted devices can either be removed after the lower layer is fabricated or blocked during the lower layer fabrication. Vias are also shown for connecting directly to the power supply on the bottom device.

[0055] As a second exemplary embodiment, Figure 4A A plan view of an integrated circuit structure 400 including a 4-poly pitch (4pp) based complementary field effect transistor (CFET) bit cell is shown according to an embodiment of the present disclosure. Figure 4B yes Figure 4A Cross-sectional view of a bit cell.

[0056] refer to Figure 4A, the integrated circuit structure 400 includes a layout having a lower layer direction along the VCC power line 402. A diffusion region 406 (e.g., a stack of nanowires (or alternatively, fins or fork structures)) is included along a direction parallel to the VCC power line 402. Gate lines 407 and trench contact lines 408 are alternated with each other and along a direction orthogonal to the diffusion region 406. Bit lines 410 are along a direction parallel to the diffusion region 406. A back side via connection 422 for back side power supply is included. A feed-through hole 420 is also included.

[0057] refer to Figure 4B , features visible from the cross-sectional view include an oxide or dielectric structure 430 located at the location of a reduced number of nanowires 432. A backside via connection 420 couples the bottom source or drain (Bot SD) to a backside bitline 431. A feed-through hole 420 couples an upper source or drain structure 433 to the backside bitline 431 and may extend through a bottom oxide or dielectric 435. An epitaxial source or drain structure 433 located below the trench contact structure 408 is isolated in some cases by structure 438 (to provide a Bot SD and a top source or drain Top SD), or is electrically coupled in other cases by an epitaxial-epi connection 436. Cross coupling 434 is achieved through M0.

[0058] Reference again Figure 4A and Figure 4B In one embodiment, the bit line is from M2 ( Figures 3A-3C ) to the back side. This can reduce the bit line resistance because the wire can be made very wide and can be a different material, such as copper if M2 is a material such as W or Co or Ru. To make a connection to the bottom bit line, in an embodiment, a feed-through via 420 is implemented. In one embodiment, other additional features include a "back trench contact TCN" 499 and a back via connection 422 that enables the final connection to the wire. Figure 4B The cross-sectional view of FIG. 4 shows the feed-through via 420 , the backside TCN 499 , and the backside via connection 422 for power routing.

[0059] As a third exemplary embodiment, Figure 4C A plan view of an integrated circuit structure 450 including a 4-poly pitch (4pp) based complementary field effect transistor (CFET) bit cell is shown according to an embodiment of the present disclosure. Figure 4D yes Figure 4C Cross-sectional view of a bit cell.

[0060] refer to Figure 4C , the integrated circuit structure 450 includes Figure 4AA similar layout with a lower layer direction along the VCC power line, a diffusion region (e.g., including a stack of nanowires (or alternatively, fin structures) along a direction parallel to the VCC power line), alternating gate lines and trench contacts along a direction orthogonal to the diffusion region, and a bit line along a direction parallel to the diffusion region. Also includes a backside via connection 454 and a backside TCN 452.

[0061] refer to Figure 4D , backside via connections 454A and 454B each couple the bottom source or drain (Bot Sd) to the backside bit line 483 via corresponding backside trench contacts 452A and 452B, respectively. The epitaxial source or drain structures below the trench contact structures are isolated by structures in some cases (to provide Bot SD and top source or drain Top SD), or are electrically coupled by epi-epi connections in other cases.

[0062] refer to Figure 4C and Figure 4D In an embodiment, in addition to moving the bit lines to the back side, the n-device and p-device are flipped. When flipping the device, the use of back side TCN and back side via connections is implemented. This eliminates the need for feed-through holes (e.g., relative to Figure 4C and Figure 4D ), and the bit line capacitance can be reduced.

[0063] In another aspect, a contact over active gate (COAG) structure and process are described, which can further realize a compact structure of a cell architecture including stacked transistors with backside access, for example. One or more embodiments of the present disclosure relate to a semiconductor structure or device having one or more gate contact structures (e.g., as gate contact vias) disposed above an active portion of a gate electrode of the semiconductor structure or device. One or more embodiments of the present disclosure relate to a method for manufacturing a semiconductor structure or device having one or more gate contact structures formed above an active portion of a gate electrode of the semiconductor structure or device. The scheme described herein can be used to reduce the standard cell area by realizing gate contact formation above an active gate region. According to one or more embodiments, a tapered gate and trench contact is implemented to realize COAG fabrication. Patterning with tight spacing can be achieved by implementing the embodiments.

[0064] To provide further context regarding the importance of the COAG processing scheme, in a technique where space and layout constraints are somewhat relaxed compared to current generation space and layout constraints, a contact to a gate structure may be made by making contact with a portion of a gate electrode disposed over an isolation region. As an example, Figure 5AA plan view of a semiconductor device having a gate contact disposed over an inactive portion of a gate electrode is shown.

[0065] refer to Figure 5A , semiconductor structure or device 500A includes a diffusion or active region 504 disposed in substrate 502 and within isolation region 506. One or more gate lines (also known as polysilicon lines) (e.g., gate lines 508A, 508B, and 508C) are disposed over the diffusion or active region 504 and over a portion of isolation region 506. Source or drain contacts (also known as trench contacts) (e.g., contacts 510A and 510B) are disposed over source and drain regions of semiconductor structure or device 500A. Trench contact vias 512A and 512B provide contact with trench contacts 510A and 510B, respectively. A separate gate contact 514 and an overlying gate contact via 516 provide contact with gate line 508B. Compared to source or drain trench contacts 510A or 510B, from a plan view, gate contact 514 is disposed over isolation region 506 rather than over diffusion or active region 504. In addition, gate contact 514 and gate contact via 516 are both not disposed between source or drain trench contacts 510A and 510B.

[0066] Figure 5B A cross-sectional view of a non-planar semiconductor device having a gate contact disposed over an inactive portion of a gate electrode is shown. Figure 5B , semiconductor structure or device 500B (eg, Figure 5A A non-planar version of device 500A) includes a non-planar diffusion or active region 504B (e.g., a fin structure) formed by substrate 502 and located within isolation region 506. Gate line 508B is disposed over non-planar diffusion or active region 504B and over a portion of isolation region 506. As shown, gate line 508B includes gate electrode 550 and gate dielectric 552 along with dielectric cap layer 554. Also visible from this angle are gate contact 514 and overlying gate contact via 516 along with overlying metal interconnect 560, all disposed in an interlayer dielectric stack or layer 570. Also, from the perspective of FIG. Figure 5B It can be seen from the perspective of FIG. 5 that the gate contact 514 is disposed on the isolation region 506 but not on the non-planar diffusion or active region 504B.

[0067] Reference again Figure 5A and Figure 5B, the arrangement of semiconductor structures or devices 500A and 500B respectively places the gate contact above the isolation region. Such an arrangement wastes layout space. However, placing the gate contact above the active area will require an extremely strict alignment budget or the gate size will have to be increased to provide sufficient space to land the gate contact. In addition, historically, contact with the gate above the diffusion region has been avoided because there is a risk of drilling through other gate materials (e.g., polysilicon) and contacting the underlying active area. One or more embodiments described herein solve the above-mentioned problems by providing a feasible solution and the resulting structure, thereby making a contact structure that contacts the portion of the gate electrode formed above the diffusion or active region.

[0068] As an example, Fig. 6A FIG. 1 is a plan view of a semiconductor device having a gate contact via disposed above an active portion of a gate electrode according to an embodiment of the present disclosure. Fig. 6A , semiconductor structure or device 600A includes a diffusion or active region 604 disposed in a substrate 602 and within an isolation region 606. One or more gate lines such as gate lines 608A, 608B, and 608C are disposed over the diffusion or active region 604 and over portions of the isolation region 606. Source or drain trench contacts such as trench contacts 610A and 610B are disposed over source and drain regions of the semiconductor structure or device 600A. Trench contact vias 612A and 612B provide contact to trench contacts 610A and 610B, respectively. A gate contact via 616 without any intervening separate gate contact layer provides contact to gate line 608B. Figure 5A In contrast, from a plan view perspective, gate contact 616 is disposed over diffusion or active region 604 and between source or drain contacts 610A and 610B.

[0069] Figure 6B A cross-sectional view of a non-planar semiconductor device having a gate contact via disposed above an active portion of a gate electrode according to an embodiment of the present disclosure is shown. Figure 6B , semiconductor structure or device 600B (eg, Fig. 6A A non-planar version of device 600A (see FIG. 6A ) includes a non-planar diffusion or active region 604B (e.g., a fin structure) formed from substrate 602 and located within isolation region 606. Gate line 608B is disposed over non-planar diffusion or active region 604B and over a portion of isolation region 606. As shown, gate line 608B includes gate electrode 650 and gate dielectric 652 along with dielectric cap layer 654. Also visible from this angle are gate contact vias 616 along with overlying metal interconnects 660, both of which are disposed in an interlayer dielectric stack or layer 670. Also, from FIG. Figure 6B It can be seen from the perspective of FIG. 6 that the gate contact via 616 is disposed above the non-planar diffusion or active region 604B.

[0070] Therefore, refer again to Fig. 6A and Figure 6B In an embodiment, the trench contact vias 612A, 612B and the gate contact via 616 are formed in the same layer and are substantially coplanar. Figure 5A and Figure 5B , the contact with the gate line would otherwise include an additional gate contact layer, which could, for example, extend perpendicularly to the corresponding gate line. Fig. 6A and Figure 6B In the described (one or more) structures, the fabrication of structures 600A and 600B, respectively, enables the contact to land directly from the metal interconnect layer on the active gate portion without shorting to the adjacent source and drain regions. In an embodiment, such an arrangement provides a large area reduction of the circuit layout by eliminating the need to extend the transistor gate over the isolation portion to form a reliable contact. As used throughout this document, in an embodiment, reference to the active portion of the gate refers to the portion of the gate line or structure disposed above the active or diffusion region of the underlying substrate (from a plan view). In an embodiment, reference to the inactive portion of the gate refers to the portion of the gate line or structure disposed above the isolation region of the underlying substrate (from a plan view).

[0071] In an embodiment, the semiconductor structure or device 600 is a non-planar device, such as, but not limited to, a fin FET or a tri-gate device. In such an embodiment, the corresponding semiconductive channel region is composed of or formed in a three-dimensional body. In one such embodiment, the gate electrode stack of gate lines 608A and 608B surrounds at least the top surface and a pair of sidewalls of the three-dimensional body. In another embodiment, for example, in a gate-all-around device, at least the channel region is a discrete three-dimensional body. In one such embodiment, the gate electrode stack of gate lines 608A and 608B completely surrounds the channel region.

[0072] Generally, one or more embodiments relate to schemes for landing gate contact vias directly on the gate of an active transistor and structures formed thereby. Such schemes can eliminate the need to extend the gate line over an isolation portion for contact purposes. Such schemes can also eliminate the need for a separate gate contact (GCN) layer for conducting signals from a gate line or structure. In an embodiment, the elimination of the above features is achieved by recessing the contact metal in the trench contact (TCN) and introducing additional dielectric material (e.g., a trench insulation layer (TILA)) in the process flow. The additional dielectric material is included as a trench contact dielectric cap layer having etching characteristics different from the gate dielectric material cap layer used for trench contact alignment in a gate aligned contact process (GAP) processing scheme (e.g., the use of a gate insulation layer (GILA)).

[0073] As an exemplary manufacturing scheme, the starting structure includes one or more gate stack structures disposed above the substrate. The gate stack structure may include a gate dielectric layer and a gate electrode. A trench contact (e.g., a diffusion region leading to the substrate or a contact with an epitaxial region formed in the substrate) is separated from the gate stack structure by a dielectric spacer. An insulating cap layer may be disposed on the gate stack structure (e.g., GILA). In one embodiment, a contact barrier region or "contact plug" that may be made of an interlayer dielectric material is included in an area that will prevent the contact from being formed.

[0074] In an embodiment, the contact pattern is substantially ideally aligned with an existing gate pattern while eliminating the use of lithography operations that employ extremely tight registration budgets. In one such embodiment, this approach enables the use of inherently highly selective wet etching (or anisotropic dry etching processes, some of which are non-plasma gas phase isotropic etching (e.g., in contrast to classical dry or plasma etching)) to generate contact openings. In an embodiment, the contact pattern is formed by utilizing an existing gate pattern and a contact plug lithography operation in combination therewith. In one such embodiment, the approach can eliminate the need for otherwise rigorous lithography operations (such as those used in other approaches) to generate the contact pattern. Doing so also allows for ideal or near-ideal self-alignment with greater margins for edge placement errors. In an embodiment, the trench contact grid is not patterned separately, but is formed between polysilicon (gate) lines. For example, in one such embodiment, the trench contact grid is formed after the gate grid is patterned but before the gate grid is cut.

[0075] In addition, the gate stack structure can be made by replacing the gate process. In this scheme, the dummy gate material such as polysilicon or silicon nitride columnar material can be removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in the process, rather than performing the formation of the layer by an earlier process. In an embodiment, the dummy gate is removed by a dry etching or wet etching process. In one embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed by a dry etching process (including SF6). In another embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed by a wet etching process (including water-soluble NH4OH or tetramethylammonium hydroxide). In one embodiment, the dummy gate is composed of silicon nitride and is removed by a wet etching process including water-soluble phosphoric acid.

[0076] In an embodiment, one or more of the schemes described herein primarily contemplate combining a dummy gate and replacement gate process with a dummy contact and replacement contact process. In one such embodiment, the replacement contact process is performed after the replacement gate process to allow for high temperature annealing of at least a portion of the permanent gate stack. For example, in a specific such embodiment, annealing of at least a portion of the permanent gate structure is performed at a temperature greater than about 600 degrees Celsius (e.g., after forming a gate dielectric layer). The annealing is performed before forming the permanent contact.

[0077] Next, the trench contact can be recessed to provide a recessed trench contact having a height lower than the top surface of the adjacent spacer. Afterwards, an insulating capping layer is formed on the recessed trench contact (e.g., TILA). According to an embodiment of the present disclosure, the insulating capping layer located on the recessed trench contact is composed of a material having different etching characteristics than the insulating capping layer on the gate stack structure.

[0078] The trench contact may be recessed by a process that is selective with respect to the materials of the spacer and the gate insulating capping layer. For example, in one embodiment, the trench contact is recessed by an etching process such as a wet etching process or a dry etching process. The trench contact insulating capping layer may be formed by a process suitable for providing a conformal and sealed layer over the exposed portion of the trench contact. For example, in one embodiment, the trench contact insulating capping layer is formed as a conformal layer over the entire structure by a chemical vapor deposition (CVD) process. Thereafter, the conformal layer is planarized by, for example, chemical mechanical polishing (CMP) to provide a trench contact insulating capping layer material that is only located over the recessed trench contact.

[0079] Regarding suitable material combinations for the gate or trench contact insulating capping layer, in one embodiment, one of the pair of gate insulating capping materials and the trench contact insulating capping material opposite thereto is composed of silicon oxide, and the other is composed of silicon nitride. In another embodiment, one of the pair of gate insulating capping materials and the trench contact insulating capping material opposite thereto is composed of silicon oxide, and the other is composed of carbon-doped silicon nitride. In another embodiment, one of the pair of gate insulating capping materials and the trench contact insulating capping material opposite thereto is composed of silicon oxide, and the other is composed of silicon carbide. In another embodiment, one of the pair of gate insulating capping materials and the trench contact insulating capping materials opposite thereto is composed of silicon nitride, and the other is composed of carbon-doped silicon nitride. In another embodiment, one of the pair of gate insulating capping materials and the trench contact insulating capping materials opposite thereto is composed of silicon nitride, and the other is composed of silicon carbide. In another embodiment, one of the pair of the gate insulating capping material and the trench contact insulating capping material opposite thereto is composed of carbon-doped silicon nitride, and the other is composed of silicon carbide.

[0080] In another aspect, a nanowire or nanoribbon structure is described. A nanowire or nanoribbon release process can be performed by replacing the gate trench. An example of such a release process will be described below. In addition, in yet another aspect, back-end (BE) interconnect scaling may result in lower performance and higher manufacturing costs due to the complexity of patterning. The embodiments described herein may be implemented to achieve front and back interconnect integration for nanowire transistors. The embodiments described herein may provide a solution to achieve a relatively wide interconnect spacing. The result may be improved product performance and lower patterning costs. Robust functionality of scaled nanowire or nanoribbon transistors with low power and high performance may be achieved by implementation of the embodiments.

[0081] In another aspect, it should be appreciated that the embodiments described herein may also include other implementations, such as nanowires and / or nanoribbons having various widths, thicknesses, and / or materials (including but not limited to Si and SiGe). For example, III-V materials may be used.

[0082] It should be appreciated that in certain embodiments, the nanowires or nanobelts or sacrificial intervening layers may be composed of silicon. As used throughout, a silicon layer may be used to describe a silicon material composed of a relatively high amount (if not all) of silicon. However, it should be appreciated that in practice it may be difficult to form 100% pure Si, and thus may include a small percentage of carbon, germanium, or tin. Such impurities may be included as unavoidable impurities or components during the deposition of Si, or may be "contamination" caused to Si during diffusion during post-deposition processing. As such, embodiments described herein involving silicon layers may include silicon layers containing relatively small amounts (e.g., "impurity" levels) of non-Si atoms or species (e.g., Ge, C, or Sn). It should be appreciated that the silicon layer as described herein may be undoped, or may be doped with dopant atoms such as boron, phosphorus, or arsenic.

[0083] It should be appreciated that in certain embodiments, the nanowires or nanoribbons or sacrificial intervening layers may be comprised of silicon germanium. As used throughout, a silicon germanium layer may be used to describe a silicon germanium material comprised of a substantial portion of both silicon and germanium (e.g., at least 5% each). In some embodiments, the amount of germanium is greater than the amount of silicon. In certain embodiments, the silicon germanium layer includes approximately 60% germanium and approximately 40% silicon (Si 40 Ge 60 In other embodiments, the amount of silicon is greater than the amount of germanium. In a particular embodiment, the silicon germanium layer includes about 30% germanium and about 70% silicon (Si 70 Ge 30 ). It should be appreciated that 100% pure silicon germanium (generally referred to as SiGe) may be difficult to form in practice, and may therefore include small percentages of carbon or tin. Such impurities may be included as unavoidable impurities or components during deposition of SiGe, or may be "contaminated" by diffusion of SiGe during post-deposition processing. As such, embodiments described herein involving silicon germanium layers may include silicon germanium layers containing relatively small amounts (e.g., "impurity" levels) of non-Ge and non-Si atoms or species (e.g., carbon or tin). It should be appreciated that the silicon germanium layers described herein may be undoped, or may be doped with dopant atoms such as boron, phosphorus, or arsenic.

[0084] Various apparatus and processing schemes that can be used to make devices that can be integrated with structures having stacked transistors with backside access are described below. It should be appreciated that exemplary embodiments do not necessarily require all of the described features, or may include more features than described. For example, a nanowire release process can be performed by replacing the gate trench. An example of such a release process is described below. In addition, in another aspect, due to the complexity of patterning, back-end (BE) interconnect scaling may result in lower performance and higher manufacturing costs. The embodiments described herein can be implemented to achieve front and backside interconnect integration for nanowire transistors. The embodiments described herein can provide a scheme for achieving relatively wide interconnect spacing. The result can be improved product performance and lower patterning costs. Robust functionality of scaled nanowire or nanoribbon transistors with low power and high performance can be achieved through implementation of the embodiments.

[0085] One or more embodiments described herein relate to directional dual epitaxial (EPI) connections for nanowire or nanoribbon transistors using partial source or drain (SD) and asymmetric trench contact (TCN) depth. In an embodiment, an integrated circuit structure is made by forming a source-drain opening of a nanowire / nanoribbon transistor partially filled with SD epitaxy. The remainder of the opening is filled with a conductive material. Deep trench formation on one of the source or drain sides enables direct contact to a backside interconnect level.

[0086] As an exemplary process flow for manufacturing a gate-all-around device of a gate-all-around integrated circuit structure, Figure 7A-7J Cross-sectional views are illustrated of various operations in a method of fabricating a gate-all-around integrated circuit structure in accordance with an embodiment of the present disclosure.

[0087] refer to Fig. 7A , a method of manufacturing an integrated circuit structure includes forming a starting stack including alternating sacrificial layers 704 and nanowires 706 located above a fin 702 (e.g., a silicon fin). The nanowires 706 may be referred to as a vertical arrangement of nanowires. A protective cap 708 may be formed above the alternating sacrificial layers 704 and nanowires 706, as shown. A relaxed buffer layer 752 and a defect modification layer 750 may be formed below the alternating sacrificial layers 704 and nanowires 706, also as shown.

[0088] refer to Figure 7B , a gate stack 710 is formed on the vertical arrangement of the horizontal nanowires 706. Thereafter, by removing a portion of the sacrificial layer 704 to provide a recessed sacrificial layer 704' and a cavity 712, a portion of the vertical arrangement of the horizontal nanowires 706 is released, such as Figure 7C as shown in .

[0089] It should be recognized that it is possible to make Figure 7C The structure is completed without first performing the deep etch and asymmetric contact processing described below. In either case (e.g., with or without the asymmetric contact processing), in an embodiment, the fabrication process involves the use of a process scheme that provides a gate-all-around integrated circuit structure with an epitaxial mass that may be a vertically discrete source or drain structure.

[0090] refer to Fig.7D , an upper gate spacer 714 is formed at the sidewalls of the gate structure 710. A cavity spacer 716 is formed in the cavity 712 below the upper gate spacer 714. A deep trench contact etch is then optionally performed to form a trench 718 and form a recessed nanowire 706'. There may also be a patterned relaxed buffer layer 752' and a patterned defect modification layer 750', as shown.

[0091] Then, a sacrificial material 720 is formed in the trench 718, such as Fig. 7E In other process schemes, an isolated trench bottom or a silicon trench bottom may be used.

[0092] refer to Figure 7F , a first epitaxial source or drain structure (e.g., left feature 722) is formed at a first end of the vertical arrangement of horizontal nanowire 706'. A second epitaxial source or drain structure (e.g., right feature 722) is formed at a second end of the vertical arrangement of horizontal nanowire 706'. In an embodiment, as shown, the epitaxial source or drain structure 722 is a vertically discrete source or drain structure and can be referred to as an epitaxial cluster.

[0093] Thereafter, an interlayer dielectric (ILD) material 724 is formed on the side of the gate electrode 710 and adjacent to the source or drain structure 722, such as Figure 7G Reference Figure 7H , a permanent gate dielectric 728 and a permanent gate electrode 726 are formed using a replacement gate process. Thereafter, the ILD material 724 is removed, such as Fig.7I Thereafter, the sacrificial material 720 is removed from one of the source-drain locations (eg, the right side) to form a trench 732 , but the sacrificial material 720 is not removed from the other of the source-drain locations, thereby forming a trench 730 .

[0094] refer to Figure 7J , forming a first conductive contact structure 734 coupled to the first epitaxial source or drain structure (e.g., left feature 722). Forming a second conductive contact structure 736 coupled to the second epitaxial source or drain structure (e.g., right feature 722). The second conductive contact structure 736 is formed deeper along the fin 702 than the first conductive contact structure 734. In an embodiment, although Figure 7JNot shown, but the method also includes forming an exposed surface of a second conductive contact structure 736 at the bottom of the fin 702. The conductive contact may include a contact resistance reducing layer and a main contact electrode layer, where examples may include Ti, Ni, Co (for the former, and W, Ru, Co for the latter).

[0095] In an embodiment, the second conductive contact structure 736 is deeper along the fin 702 than the first conductive contact structure 734, as shown. In one such embodiment, the first conductive contact structure 734 is not along the fin 702, as shown. In another such embodiment not shown, the first conductive contact structure 734 is partially along the fin 702.

[0096] In an embodiment, the second conductive contact structure 736 is along the entire fin 702. In an embodiment, although not shown, the second conductive contact structure 736 has an exposed surface at the bottom of the fin 702 if the bottom of the fin 702 is exposed by a backside substrate removal process.

[0097] In an embodiment, Figure 7J structure or Figures 7A-7J Related structures may be included in structures such as those described above that include stacked transistors with backside access.

[0098] In another aspect, in order to access two conductive contact structures of a pair of asymmetric source and drain contact structures, the integrated circuit structure described herein can be fabricated using a backside exposure fabrication scheme for the front side structure. In some exemplary embodiments, the backside exposure of transistors or other device structures requires wafer-level backside processing. In contrast to conventional TSV-type technologies, the exposure of the backside of transistors described herein can be performed at the density of device cells, or even in sub-regions of the device. In addition, such exposure of the backside of transistors can be performed to substantially remove all of the donor substrate on which the device layer was disposed during front side device processing. As such, since the thickness of the semiconductor in the device cell after the backside exposure of the transistor is likely to become only tens or hundreds of nanometers, a TSV several microns deep becomes unnecessary.

[0099] The revealing techniques described herein can enable a paradigm shift from "bottom-up" device fabrication to "center-out" fabrication, where the "center" is any layer employed in front-side fabrication, exposed from the backside, and then employed again in back-side fabrication. Processing of both the front side and the exposed backside of the device structure can address many of the challenges associated with fabricating 3DICs when relying primarily on front-side processing.

[0100] For example, a transistor backside exposure scheme can be used to remove at least a portion of the carrier layer and the intervening layer of the donor-acceptor substrate assembly. The process flow begins with the input of the donor-acceptor substrate assembly. The thickness of the carrier layer in the donor-acceptor substrate is polished (e.g., CMP), and / or etched using a wet or dry (e.g., plasma) etching process. Any grinding, polishing and / or wet / dry etching process known to be suitable for the composition of the carrier layer can be used. For example, in the case where the carrier layer is a Group IV semiconductor (e.g., silicon), a CMP slurry known to be suitable for thinning semiconductors can be used. Similarly, any wet etchant or plasma etching process known to be suitable for thinning Group IV semiconductors can also be used.

[0101] In some embodiments, the carrier layer is cleaved along a fracture plane substantially parallel to the intervening layer prior to the above operations. The cleaving or fracturing process can be used to remove a substantial portion of the carrier layer as a bulk, thereby shortening the polishing or etching time required to remove the carrier layer. For example, in the case where the carrier layer has a thickness of 400-900 μm, 100-700 μm can be cleaved off by practicing any uniform thickness implant known to promote wafer-level fracturing. In some exemplary embodiments, light elements (e.g., H, He, or Li) are implanted into the carrier layer to obtain a uniform target depth of fracture plane. Immediately following such a cleaving process, the remaining carrier layer thickness in the donor-acceptor substrate assembly can be polished or etched to completely remove it. Alternatively, a greater thickness of the carrier layer can be removed by grinding, polishing, and / or etching operations without fracturing the carrier layer.

[0102] Next, the exposure of the intervening layer is detected. This detection is used to identify the point when the back surface of the donor substrate has been advanced to the point close to the device layer. Any endpoint detection technology known to be suitable for detecting the transition between the materials used in the carrier layer and the intervening layer can be practiced. In some embodiments, one or more endpoint criteria are based on detecting the change in light absorption or emission of the back surface of the donor substrate during the polishing or etching execution. In some other embodiments, the endpoint criteria are associated with the change in optical absorption or emission of the byproducts during the polishing or etching of the back surface of the donor substrate. For example, the absorption or emission wavelength associated with the carrier layer etching byproduct can be changed as a function of the different components of the carrier layer and the intervening layer. In other embodiments, the endpoint criteria are associated with the mass change of the species in the byproducts of polishing or etching the back surface of the donor substrate. For example, the byproducts of the treatment can be sampled by a quadrupole mass spectrometer, and the change in the mass of the species can be related to the different components of the carrier layer and the intervening layer. In another exemplary embodiment, the endpoint criteria are associated with the change in friction between the back surface of the donor substrate and the polishing surface in contact with the back surface of the donor substrate.

[0103] Detection of the intervening layer can be enhanced in cases where the removal process is selective for the carrier layer relative to the intervening layer, because non-uniformities in the carrier removal process can be mitigated by the difference in etch rates between the carrier layer and the intervening layer. If the grinding, polishing and / or etching operation removes the intervening layer at a rate that is sufficiently lower than the rate at which the carrier layer is removed, then the detection can even be skipped. If no endpoint criteria are used, then the grinding, polishing and / or etching operation of a predetermined fixed duration can be stopped on the intervening layer material if the thickness of the intervening layer is sufficient for etching selectivity. In some examples, the carrier etch rate:intervening layer etch rate is 3:1-10:1 or higher.

[0104] Once the intervening layer is exposed, at least a portion of the intervening layer can be removed. For example, one or more component layers of the intervening layer can be removed. For example, the thickness of the intervening layer can be uniformly removed by polishing. Alternatively, the thickness of the intervening layer can be removed using a mask or a blanket etching process. The process can employ the same polishing or etching process used to thin the carrier, or can be a completely different process with completely different process parameters. For example, when the intervening layer provides an etch stop for the carrier removal process, the latter operation can employ a different polishing or etching process that facilitates the removal of the intervening layer relative to the removal of the device layers. In the case of an intervening layer thickness of less than a few hundred nanometers to be removed, the removal process can be relatively slow, can be optimized to achieve uniformity across the wafer, and can be more precisely controlled than the process used to remove the carrier layer. The CMP process employed may, for example, employ a slurry that provides very high selectivity (e.g., 100:1-300:1 or higher) between semiconductors (e.g., silicon) and dielectric materials (e.g., SiO) that surround the device layers and are embedded within intervening layers to serve as electrical isolation, for example, between adjacent device regions.

[0105] For embodiments where the device layer is exposed by completely removing the intervening layer, backside processing may begin with the exposed backside of the device layer or a specific device region therein. In some embodiments, backside device layer processing includes further polishing or wet / dry etching through the thickness of the device layer disposed between the intervening layer and a device region (e.g., a source or drain region) previously fabricated in the device layer.

[0106] In some embodiments where wet / plasma etching is used to recess the back side of a carrier layer, an intervening layer, or a device layer, such etching may be a patterned etch or a material selective etch that imparts significant non-planarity or topography to the back side surface of the device layer. As further described below, patterning may be within a device cell (i.e., "intra-cell" patterning) or may be across device cells (i.e., "inter-cell" patterning). In some patterned etching embodiments, at least a portion of the thickness of the intervening layer is used as a hard mask for patterning the back side device layer. Thus, the masked etching process may serve as the start of a corresponding masked device layer etch.

[0107] The processing scheme described above can result in a donor-acceptor substrate assembly including an IC device having a back side of an intervening layer, a back side of a device layer, and / or a back side of one or more semiconductor regions within a device layer, and / or an exposed front side metallization. Additional back side processing of any of these exposed regions can then be performed during downstream processing.

[0108] It should be appreciated that the structure obtained by the above exemplary processing scheme can be used in the same or similar form for subsequent processing operations to complete device manufacturing, such as PMOS and / or NMOS device manufacturing. As an example of a completed device, Figure 8 A cross-sectional view of a non-planar integrated circuit structure taken along a gate line according to an embodiment of the present disclosure is shown.

[0109] refer to Figure 8 , the semiconductor structure or device 800 includes a non-planar active region (e.g., a fin structure including a protruding fin portion 804 and a sub-fin region 805) located within a trench isolation region 806. In an embodiment, instead of a solid fin, the non-planar active region is divided into nanowires (e.g., nanowires 804A and 804B) located above the sub-fin region 805, as indicated by the dotted lines. In either case, for ease of describing the non-planar integrated circuit structure 800, the non-planar active region 804 is referred to below as the protruding fin portion. In an embodiment, the sub-fin region 805 also includes a relaxation buffer layer 842 and a defect modification layer 840, as shown.

[0110] The gate line 808 is disposed over the protruding portion 804 of the non-planar active area (including surrounding nanowires 804A and 804B, where applicable) and over a portion of the trench isolation region 806. As shown, the gate line 808 includes a gate electrode 850 and a gate dielectric layer 852. In one embodiment, the gate line 808 may also include a dielectric cap layer 854. Also visible from this angle are the gate contact 814 and the overlying gate contact via 816, along with the overlying metal interconnect 860, all of which are disposed in an interlayer dielectric stack or layer 870. From the top of the figure, the gate line 808 includes a gate electrode 850 and a gate dielectric layer 852. In one embodiment, the gate line 808 may also include a dielectric cap layer 854. Also visible from this angle are the gate contact 814 and the overlying gate contact via 816, along with the overlying metal interconnect 860, all of which are disposed in an interlayer dielectric stack or layer 870. Figure 8 It can also be seen from the perspective that in one embodiment, the gate contact 814 is disposed on the trench isolation region 806, but not on the non-planar active region. In another embodiment, the gate contact 814 is located on the non-planar active region.

[0111] In an embodiment, the semiconductor structure or device 800 is a non-planar device, such as, but not limited to, a fin-FET device, a tri-gate device, a nanoribbon device, or a nanowire device. In such an embodiment, the corresponding semiconductive channel region is formed by or in a three-dimensional body. In one such embodiment, the gate electrode stack of the gate line 808 surrounds at least the top surface and a pair of sidewalls of the three-dimensional body.

[0112] Likewise Figure 8 As shown, in an embodiment, an interface 880 exists between the protruding fin portion 804 and the sub-fin region 805. The interface 880 can be a transition region between the doped sub-fin region 805 and the lightly doped or undoped upper fin portion 804. In one such embodiment, each fin is approximately 10 nanometers wide or less, and the sub-fin dopant is optionally supplied from an adjacent solid-state doping layer at the sub-fin location. In a specific such embodiment, each fin is less than 10 nanometers wide.

[0113] although Figure 8 808, i.e., inside or outside the page. In another embodiment, the material of the protruding fin portion 804 located in the source or drain position is removed and replaced with another semiconductor material, for example by epitaxial deposition, to form an epitaxial source or drain structure. The source or drain region may extend below the height of the dielectric layer of the trench isolation region 806, i.e., into the sub-fin region 805. According to an embodiment of the present disclosure, the more heavily doped sub-fin region (i.e., the doped portion of the fin located below the interface 880) suppresses source-to-drain leakage through that portion of the bulk semiconductor fin. According to an embodiment, the source and drain regions have associated asymmetric source and drain contact structures, as described above in connection with the embodiment of the present disclosure. Figure 7J described.

[0114] Reference again Figure 8 In an embodiment, fins 804 / 805 (and possibly nanowires 804A and 804B) are composed of a crystalline silicon germanium layer, which may be doped with charge carriers such as, but not limited to, phosphorus, arsenic, boron, gallium, or combinations thereof.

[0115] In an embodiment, the trench isolation region 806 and the trench isolation regions (trench isolation structures or trench isolation layers) described herein may be composed of a material suitable for ultimately electrically isolating a portion of a permanent gate structure from an underlying bulk substrate, or contributing to the isolation of a portion of a permanent gate structure from an underlying bulk substrate, or suitable for isolating an active region formed in an underlying bulk substrate (e.g., isolating a fin active region). For example, in one embodiment, the trench isolation region 806 is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0116] The gate line 808 may be composed of a gate electrode stack including a gate dielectric layer 852 and a gate electrode layer 850. In an embodiment, the gate electrode of the gate electrode stack is composed of a metal gate, and the gate dielectric layer is composed of a high-k material. For example, in one embodiment, the gate dielectric layer 852 is composed of materials such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, tantalum scandium lead oxide, lead zinc niobate, or a combination thereof. In addition, a portion of the gate dielectric layer 852 may include a native oxide layer formed by the top layers of the substrate fin 804. In an embodiment, the gate dielectric layer 852 is composed of a top high-k portion and a lower portion composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer 852 is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride. In some embodiments, a portion of the gate dielectric is a "U" shaped structure including a bottom portion substantially parallel to a substrate surface and two sidewall portions substantially perpendicular to a top surface of the substrate.

[0117] In one embodiment, the gate electrode layer 850 is composed of a metal layer, such as but not limited to metal nitride, metal carbide, metal silicide, metal aluminide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel or conductive metal oxide. In a specific embodiment, the gate electrode layer 850 is composed of a non-work function setting filling material formed above the metal work function setting layer. The gate electrode layer 850 can be composed of a P-type work function metal or an N-type work function metal, depending on whether the transistor is a PMOS transistor or an NMOS transistor. In some embodiments, the gate electrode layer 850 can be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a conductive filling layer. For PMOS transistors, metals that can be used for gate electrodes include but are not limited to ruthenium, palladium, platinum, cobalt, nickel, tungsten and conductive metal oxides (e.g., ruthenium oxide). The P-type metal layer will enable the formation of a PMOS gate electrode with a work function between about 4.9eV and about 5.2eV. For NMOS transistors, metals that can be used for gate electrodes include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. The N-type metal layer will enable the formation of an NMOS gate electrode with a work function between about 3.9 eV and about 4.2 eV. In some embodiments, the gate electrode may be composed of a "U"-shaped structure comprising a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In another embodiment, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the substrate, and does not include a sidewall portion substantially perpendicular to the top surface of the substrate. In other embodiments of the present disclosure, the gate electrode may be composed of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be composed of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0118] The spacer associated with the gate electrode stack may be composed of a material suitable for ultimately electrically isolating the permanent gate structure from an adjacent conductive contact (e.g., a self-aligned contact), or contributing to the isolation of the permanent gate structure from an adjacent conductive contact (e.g., a self-aligned contact). For example, in one embodiment, the spacer is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0119] The gate contact 814 and the overlying gate contact via 816 may be made of a conductive material. In an embodiment, one or more of the contact or via is made of a metal species. The metal species may be a pure metal such as tungsten, nickel, or cobalt, or may be an alloy such as a metal-metal alloy or a metal-semiconductor alloy (e.g., a silicide material).

[0120] In an embodiment (although not shown), a contact pattern is formed that is substantially perfectly aligned with the existing gate pattern 808, while eliminating the use of a photolithography step with an extremely tight registration budget. In an embodiment, the contact pattern is a vertically symmetrical contact pattern, or an asymmetrical contact pattern, such as a contact pattern. Figure 7J as described. In other embodiments, all contacts are frontally connected and are not asymmetric. In one such embodiment, this self-aligned scheme enables the use of inherently highly selective wet etching (e.g., compared to conventional dry or plasma etching). In an embodiment, the contact pattern is formed by utilizing an existing gate pattern in conjunction with a contact plug lithography operation. In one such embodiment, the scheme enables the elimination of the need for otherwise rigorous lithography operations (such as those used in conventional schemes) to generate the contact pattern. In an embodiment, the trench contact grid is not patterned separately, but is formed between the polysilicon (gate) lines. For example, in one such embodiment, the trench contact grid is formed after the gate grid is patterned but before the gate grid is cut.

[0121] In an embodiment, providing structure 800 involves making a gate stack structure 808 by a replacement gate process. In this scheme, a dummy gate material such as a polysilicon or silicon nitride columnar material can be removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in the process, rather than performing the formation of the layer by an earlier process. In an embodiment, the dummy gate is removed by a dry etching or wet etching process. In one embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed by a dry etching process (including the use of SF6). In another embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed by a wet etching process (including the use of aqueous NH4OH or tetramethylammonium hydroxide). In one embodiment, the dummy gate is composed of silicon nitride and is removed by a wet etching process including aqueous phosphoric acid.

[0122] Reference again Figure 8, the arrangement of the semiconductor structure or device 800 places the gate contact above the isolation region. Such an arrangement may be viewed as an inefficient use of layout space. However, in another embodiment, the semiconductor device has a contact structure that contacts a portion of the gate electrode formed above the active region (e.g., formed above the fin 805) and in contact with a portion of the trench contact via formed in the same layer.

[0123] In an embodiment, Figure 8 The structure may be included in the structure with stacked transistors using backside access as described above.

[0124] It should be appreciated that not all aspects of the above-described processes need to be practiced to fall within the spirit and scope of the embodiments of the present disclosure. Moreover, the processes described herein can be used to fabricate one or more semiconductor devices. The semiconductor device can be a transistor or a similar device. For example, in an embodiment, the semiconductor device is a metal oxide semiconductor (MOS) transistor for logic or memory, or a bipolar transistor. Moreover, in an embodiment, the semiconductor device has a three-dimensional architecture, for example, a nanowire device, a nanobelt device, a tri-gate device, an independently accessed dual-gate device, or a FIN-FET. One or more embodiments can be particularly used to fabricate semiconductor devices at a sub-10 nanometer (10nm) technology node.

[0125] In an embodiment, as used throughout this specification, an interlayer dielectric (ILD) material includes or consists of a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, silicon oxides (e.g., silicon dioxide (SiO2)), doped silicon oxides, fluorinated silicon oxides, carbon-doped silicon oxides, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material can be formed by conventional techniques, such as chemical vapor deposition (CVD), physical vapor deposition (PDV), or by other deposition methods.

[0126] In an embodiment, as used throughout this specification, metal lines or interconnect materials (and via materials) are composed of one or more metals or other conductive structures. Common examples are the use of copper lines and structures, which may or may not include a barrier layer between copper and the surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, a metal interconnect may include a barrier layer (e.g., a layer including one or more of Ta, TaN, Ti, or TiN), a stack of different metals or alloys, and the like. Thus, the interconnect may be a single material layer or may be formed by several layers (including a conductive liner and a filling layer). Any suitable deposition process such as electroplating, chemical vapor deposition, or physical vapor deposition may be used to form the interconnect. In an embodiment, the interconnect is composed of conductive materials such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or its alloys. Interconnects are sometimes referred to as traces, wires, lines, metals, or simply interconnects in the art.

[0127] In an embodiment, as also used throughout this specification, the hard mask material, cap layer or plug is composed of a dielectric material different from the interlayer dielectric material. In one embodiment, different hard mask, cap or plug materials can be used in different regions to provide different growth or etching selectivities relative to each other and relative to the underlying dielectric layer and metal layer. In some embodiments, the hard mask layer, cap layer or plug layer includes a silicon nitride (e.g., silicon nitride) layer or a silicon oxide layer, or both, or a combination thereof. Other suitable materials may include carbon-based materials. Other hard mask layers, cap layers or plug layers known in the art may be used according to specific embodiments. The hard mask layer, cap layer or plug layer may be formed by CVD, PVD or by other deposition methods.

[0128] In an embodiment, as still used throughout this specification, lithography operations are performed using 193nm immersion lithography (i193) or EUV and / or EBDW lithography, etc. Positive or negative resists can be used. In one embodiment, the lithography mask is a three-layer mask consisting of a topography masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a specific embodiment of this type, the topography masking portion is a carbon hard mask (CHM) layer, and the anti-reflective coating layer is a silicon ARC layer.

[0129] In another aspect, one or more embodiments relate to adjacent semiconductor structures or devices separated by a self-aligned gate end cap (SAGE) structure. Specific embodiments may relate to the integration of multi-width (multi-Wsi) nanowires and nanoribbons in a SAGE architecture and separated by SAGE walls. In an embodiment, nanowires / nanoribbons are integrated with multi-Wsi in the SAGE architecture portion of the front-end process flow. Such a process flow may involve integrating nanowires and nanoribbons with different Wsi to provide robust functionality of next-generation transistors with low power and high performance. Associated epitaxial source or drain regions may be embedded (e.g., removing portions of the nanowires and then performing source or drain (S / D) growth).

[0130] To provide further context, the advantages of the self-aligned gate endcap (SAGE) architecture can include enabling higher layout density and, in particular, scaling of diffusion to diffusion spacing. To provide an illustrative comparison, Fig. 9 Cross-sectional views taken through nanowires and fins are shown for a non-endcap architecture (left side (a)) and a comparative self-aligned gate endcap (SAGE) architecture (right side (b)) according to an embodiment of the present disclosure.

[0131] refer to Fig. 9 On the left side (a), the integrated circuit structure 900 includes a substrate 902 with a fin 904, which protrudes from the substrate 902 to a certain amount 906 above the isolation structure 908 that laterally surrounds the lower portion of the fin 904. As shown, the upper portion of the fin can include a relaxed buffer layer 922 and a defect modification layer 920. The corresponding nanowire 905 is located above the fin 904. A gate structure can be formed on the integrated circuit structure 900 to make a device. However, the interruption in such a gate structure can be accommodated by increasing the spacing between the fin 904 / nanowire 905 pairs.

[0132] As a comparison, reference Fig. 9On the right side (b), the integrated circuit structure 950 includes a substrate 952 having a fin 954, which protrudes from the substrate 952 to a certain amount 956 above the isolation structure 958 that laterally surrounds the lower portion of the fin 954. The upper portion of the fin may include a relaxed buffer layer 972 and a defect modification layer 970, as shown. The corresponding nanowire 955 is located above the fin 954. An isolation SAGE wall 960 (which may include a hard mask located thereon, as shown) is included in the isolation structure 952 and is located between adjacent fin 954 / nanowire 955 pairs. The distance between the isolation SAGE wall 960 and the nearest fin 954 / nanowire 955 pair defines a gate end cap spacing 962. A gate structure can be formed above the integrated circuit structure 900 and between the isolation SAGE walls to make a device. This interruption in the gate structure is imposed by the isolation SAGE wall. Since the isolation SAGE wall 960 is self-aligned, it is possible to minimize the limitations from conventional schemes to achieve more aggressive diffusion to diffusion spacing. In addition, since the gate structure includes interrupts at all locations, the various gate structure portions can be layered through local interconnects formed on the isolation SAGE wall 960. In an embodiment, as shown in the figure, the SAGE wall 960 includes a lower dielectric portion and a dielectric cap located on the lower dielectric portion. According to an embodiment of the present disclosure, Fig. 9 The fabrication process of the associated structure involves the use of a process scheme that provides a gate-all-around integrated circuit structure with an epitaxial source or drain structure.

[0133] In an embodiment, Fig. 9 The structure of part (a) may be included in the structure of stacked transistors including backside access as described above. In an embodiment, Fig. 9 The structure of part (b) may be included in the structure having stacked transistors with backside access as described above.

[0134] A self-aligned gate end cap (SAGE) processing scheme involves forming a gate / trench contact end cap that is self-aligned with the fin, without requiring additional length to account for mask misalignment. Thus, embodiments may be implemented to achieve a reduction in transistor layout area. Embodiments described herein may involve making a gate end cap isolation structure, which may also be referred to as a gate wall, an isolation gate wall, or a self-aligned gate end cap (SAGE) wall.

[0135] In an exemplary processing scheme for a structure having SAGE walls separating adjacent devices, Fig.10 Cross-sectional views representing various operations in a method of fabricating a self-aligned gate endcap (SAGE) structure with a gate-all-around device in accordance with an embodiment of the present disclosure are illustrated.

[0136] refer to Fig.10 , the starting structure includes a nanowire patterned stack 1004 located above a substrate 1002. A lithographic patterned stack 1006 is formed above the nanowire patterned stack 1004. The nanowire patterned stack 1004 includes alternating sacrificial layers 1010 and nanowire layers 1012, which may be located above a relaxed buffer layer 1082 and a defect modification layer 1080, as shown. A protective mask 1014 is located between the nanowire patterned stack 1004 and the lithographic patterned stack 1006. In one embodiment, the lithographic patterned stack 1006 is a three-layer mask consisting of a topography masking portion 1020, an anti-reflective coating (ARC) layer 1022, and a photoresist layer 1024. In a specific such embodiment, the topography masking portion 1020 is a carbon hard mask (CHM) layer, and the anti-reflective coating layer 1022 is a silicon ARC layer.

[0137] refer to Fig.10 The stack of portion (b), portion (a) is photolithographically patterned and then etched to provide an etched structure including a patterned substrate 1002 and trenches 1030.

[0138] refer to Fig.10 1. In part (c), the structure of part (b) has an isolation layer 1040 and a SAGE material 1042 formed in the trench 1030. Thereafter, the structure is planarized to leave the patterned topographic masking layer 1020' as an exposed upper layer.

[0139] refer to Fig.10 In portion (d), the isolation layer 1040 is recessed below the upper surface of the patterned substrate 1002, for example, to define a protruding fin portion, and to provide a trench isolation structure 1041 located below the SAGE wall 1042.

[0140] refer to Fig.10 In the portion (e), at least the sacrificial layer 1010 in the channel region is removed to release the nanowires 1012A and 1012B. Fig.10 After the structure of portion (e) of FIG. 1 , a gate stack can be formed around nanowire 1012B or 1012A, over the protruding fins of substrate 1002, and between SAGE walls 1042. In one embodiment, the remaining portion of protective mask 1014 is removed before forming the gate stack. In another embodiment, the remaining portion of protective mask 1014 is retained as an insulating fin cap, which becomes an artifact of the processing scheme.

[0141] Reference again Fig.10, it should be recognized that it depicts a channel diagram in which the source region or the drain region is located inside or outside the page. In an embodiment, the channel region including nanowire 1012B has a width that is less than the channel region including nanowire 1012A. Thus, in an embodiment, the integrated circuit structure includes multi-width (multi-Wsi) nanowires. Although the structures of 1012B and 1012A can be divided into nanowires and nanoribbons, such structures are generally referred to as nanowires in this document. It is also recognized that references or depictions of fin / nanowire pairs throughout the text may refer to a fin and one or more overlying nanowires (e.g., Fig.10 According to an embodiment of the present disclosure, the structure of the nanowires is shown in FIG. Fig.10 The fabrication process of the associated structure involves the use of a process scheme that provides a gate-all-around integrated circuit structure with an epitaxial source or drain structure.

[0142] In an embodiment, Fig.10 The structure of part (e) may be included in the structure having stacked transistors with backside access as described above.

[0143] In an embodiment, as described throughout this document, the self-aligned gate end cap (SAGE) isolation structure can be composed of one or more materials suitable for ultimately electrically isolating portions of the permanent gate structure from each other, or contributing to the isolation of portions of the permanent gate structure from each other. Exemplary materials or material combinations include single material structures, such as silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride. Other exemplary materials or material combinations include a multilayer stack having a lower silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride and an upper higher dielectric constant material (e.g., hafnium oxide).

[0144] To highlight an exemplary integrated circuit structure with three vertically arranged nanowires, Fig.11A A three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to an embodiment of the present disclosure is shown. Fig. 11B The image taken along the a-a' axis is shown. Fig.11A A cross-sectional source or drain view of a nanowire-based integrated circuit structure. Fig. 11C The image taken along the b-b' axis is shown. Fig.11A Cross-sectional channel diagram of a nanowire-based integrated circuit structure.

[0145] refer to Fig.11A, the integrated circuit structure 1100 includes one or more vertically stacked nanowires (1104 groups) located above a substrate 1102. In an embodiment, a relaxation buffer layer 1102C, a defect modification layer 1102B, and a lower substrate portion 1102A are included in the substrate 1102, as shown. For illustrative purposes, in order to emphasize the reasons for the nanowire portion, the optional fins located below the bottommost nanowire and formed by the substrate 1102 are not shown. The embodiments herein target both single-wire devices and multi-wire devices. As an example, for illustrative purposes, a device based on three nanowires with nanowires 1104A, 1104B, and 1104C is shown. For ease of description, nanowire 1104A is used as an example, wherein the description focuses on one of the nanowires. It should be recognized that in the case of describing the properties of a nanowire, embodiments based on multiple nanowires may have the same or substantially the same properties for each of the nanowires.

[0146] Each of the nanowires 1104 includes a channel region 1106 located in the nanowire. The channel region 1106 has a length (L). Fig. 11C , the channel region also has a perimeter (Pc) orthogonal to the length (L). Fig.11A and Fig. 11C In both, the gate electrode stack 1108 surrounds the entire perimeter (Pc) of each of the channel regions 1106. The gate electrode stack 1108 includes a gate electrode together with a gate dielectric (not shown) located between the channel region 1106 and the gate electrode. In an embodiment, the channel region is discrete because it is completely surrounded by the gate electrode stack 1108 without any intervening materials such as underlying substrate materials or overlying channel fabrication materials. Accordingly, in an embodiment with multiple nanowires 1104, the channel regions 1106 of the nanowires are also discrete relative to each other.

[0147] refer to Fig.11A and Fig. 11B In both cases, the integrated circuit structure 1100 includes a pair of non-discrete source or drain regions 1110 / 1112. The pair of non-discrete source or drain regions 1110 / 1112 are located on both sides of a channel region 1106 of a plurality of vertically stacked nanowires 1104. In addition, the pair of non-discrete source or drain regions 1110 / 1112 are adjacent to the channel region 1106 of the plurality of vertically stacked nanowires 1104. In one such embodiment (not shown), the pair of non-discrete source or drain regions 1110 / 1112 for the channel region 1106 are directly vertically adjacent because epitaxial growth is performed on and between the portions of the nanowires extending beyond the channel region 1106, wherein the nanowire ends are shown as being located within the source or drain structure. In another embodiment, as shown in FIG. Fig.11AAs shown in FIG. 1 , the pair of non-discrete source or drain regions 1110 / 1112 for the channel region 1106 are indirectly vertically adjacent because they are formed at the ends of the nanowires and not between the nanowires.

[0148] In an embodiment, as shown, the source or drain regions 1110 / 1112 are non-discrete in that there is no independent and discrete source or drain region for each channel region 1106 of the nanowire 1104. Accordingly, in an embodiment with multiple nanowires 1104, the source or drain regions 1110 / 1112 of the nanowires are global or integrated source or drain regions, rather than being discrete for each nanowire. That is, the non-discrete source or drain regions 1110 / 1112 are global in the sense that a single integrated feature serves as the source or drain region for multiple (in this case, 3) nanowires 1104 and, more specifically, for more than one discrete channel region 1106. In one embodiment, each of the pair of non-discrete source or drain regions 1110 / 1112 has a generally rectangular shape having a bottom tapered portion and a top angular portion, as viewed from a cross-sectional perspective orthogonal to the length of the discrete channel region 1106. Fig. 11B However, in other embodiments, the source or drain region 1110 / 1112 of the nanowire is a relatively large but still discrete non-vertically fused epitaxial structure, for example, Figures 7A-7J Described clumps.

[0149] According to the embodiments of the present disclosure, Fig.11A and Fig. 11B As shown, the integrated circuit structure 1100 also includes a pair of contacts 1114, each contact 1114 being located on one of the pair of non-discrete source or drain regions 1110 / 1112. In one such embodiment, each contact 1114 completely surrounds the corresponding non-discrete source or drain region 1110 / 1112 in a vertical sense. In another aspect, the non-discrete source or drain region 1110 / 1112 is not accessible over its entire perimeter for contact with the contact 1114, and the contact 1114 only partially surrounds the non-discrete source or drain region 1110 / 1112, as shown in FIG. Fig. 11B In a comparative embodiment not shown, the entire perimeter of the non-discrete source or drain region 1110 / 1112 (taken along the aa′ axis) is surrounded by the contact 1114 .

[0150] Reference again Fig.11AIn an embodiment, the integrated circuit structure 1100 further includes a pair of spacers 1116. As shown, outer portions of the pair of spacers 1116 may overlap portions of the non-discrete source or drain regions 1110 / 1112, thereby providing "embedded" portions of the non-discrete source or drain regions 1110 / 1112 that are located below the pair of spacers 1116. As also shown, the embedded portions of the non-discrete source or drain regions 1110 / 1112 may not extend below the entire pair of spacers 1116.

[0151] Substrate 1102 may be made of a material suitable for integrated circuit structure fabrication. In one embodiment, substrate 1102 includes a lower bulk substrate made of a single crystal of a material, which may include but is not limited to silicon, germanium, silicon germanium, germanium tin, silicon germanium tin, or a III-V compound semiconductor material. An upper insulator layer made of a material that may include but is not limited to silicon dioxide, silicon nitride, or silicon oxynitride is located on the lower bulk substrate. Thus, structure 1100 may be made from a starting semiconductor-on-insulator substrate. Alternatively, structure 1100 is formed directly from a bulk substrate, and local oxidation is used to form an electrically insulating portion to replace the upper insulator layer described above. In another alternative embodiment, structure 1100 is formed directly from a bulk substrate, and doping is used to form an electrically isolated active region (e.g., a nanowire) thereon. In one such embodiment, the first nanowire (i.e., close to the substrate) has the form of an Ω-FET type structure.

[0152] In an embodiment, the nanowires 1104 may be sized as wires or ribbons, as described below, and may have square corners or rounded corners. In an embodiment, the nanowires 1104 are composed of a material such as, but not limited to, silicon, germanium, or a combination thereof. In one such embodiment, the nanowires are single crystalline. For example, for silicon nanowires 1104, the single crystalline nanowires may be based on a (100) global orientation, for example, with a z-direction having a <100> Plane. Other orientations are also contemplated as described below. In an embodiment, the dimensions of the nanowires 1104 are on the nanometer scale from a cross-sectional perspective. For example, in a specific embodiment, the smallest dimension of the nanowires 1104 is less than about 20 nanometers. In an embodiment, and particularly in the channel region 1106, the nanowires 1104 are composed of a strained material.

[0153] refer to Fig. 11C, in an embodiment, each of the channel regions 1106 has a width (Wc) and a height (Hc), the width (Wc) being approximately the same as the height (Hc). That is, in both cases, the cross-sectional profile of the channel regions 1106 resembles a square, or if the corners are rounded, the cross-sectional profile resembles a circle. In another aspect, the width and height of the channel regions are not necessarily the same, for example, as in the case of nanoribbons described throughout this document.

[0154] In an embodiment, as described throughout, an integrated circuit structure includes a non-planar device, such as, but not limited to, a FinFET or a tri-gate device having a corresponding one or more overlying nanowire structures. In such an embodiment, the corresponding semiconductive channel region is comprised of or formed in a three-dimensional body, wherein one or more discrete nanowire channel portions overlie the three-dimensional body. In one such embodiment, the gate structure surrounds at least a top surface and a pair of sidewalls of the three-dimensional body, and further surrounds each of the one or more discrete nanowire channel portions.

[0155] In an embodiment, Figures 11A-11C The structure may be included in the structure with stacked transistors using backside access as described above.

[0156] In an embodiment, as described throughout, the lower substrate may be composed of a semiconductor material that can withstand the manufacturing process and in which charge can migrate. In an embodiment, the substrate is a bulk substrate composed of a crystalline silicon, silicon / germanium or germanium layer, which is doped with charge carriers such as but not limited to phosphorus, arsenic, boron, gallium or a combination thereof to form an active region. In one embodiment, the concentration of silicon atoms in the bulk substrate is greater than 97%. In another embodiment, the bulk substrate is composed of an epitaxial layer grown on top of a distinct crystalline substrate, for example, a silicon epitaxial layer grown on top of a boron-doped bulk silicon single crystal substrate. The bulk substrate may alternatively be composed of a III-V group material. In an embodiment, the bulk substrate is composed of a III-V group material such as but not limited to gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, gallium indium arsenide, gallium aluminum arsenide, gallium indium phosphide or a combination thereof. In one embodiment, the bulk substrate is composed of a III-V group material, and the charge carrier dopant impurity atoms are impurity atoms such as but not limited to carbon, silicon, germanium, oxygen, sulfur, selenium or tellurium.

[0157] The embodiments disclosed herein can be used to manufacture a wide variety of different types of integrated circuits and / or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, etc. In other embodiments, semiconductor memories can be manufactured. In addition, integrated circuits or other microelectronic devices can be used in a wide variety of electronic devices known in the art. For example, in computer systems (e.g., desktops, laptops, servers), cellular phones, personal electronic products, etc. The integrated circuit can be coupled to buses and other components in the system. For example, a processor can be coupled to a memory, a chipset, etc. by one or more buses. Each of the processor, memory, and chipset can potentially be manufactured using the solutions disclosed herein.

[0158] Fig.12 A computing device 1200 is shown in accordance with one implementation of an embodiment of the present disclosure. The computing device 1200 houses a board 1202. The board 1202 may include several components including, but not limited to, a processor 1204 and at least one communication chip 1206. The processor 1204 is physically and electrically coupled to the board 1202. In some implementations, the at least one communication chip 1206 is also physically and electrically coupled to the board 1202. In other implementations, the communication chip 1206 is part of the processor 1204.

[0159] Depending on its application, the computing device 1200 may include other components that may or may not be physically and electrically coupled to the board 1202. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a cryptographic processor, a chipset, an antenna, a display, a touch screen display, a touch screen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (e.g., a hard drive, a compact disk (CD), a digital versatile disk (DVD), etc.).

[0160] The communication chip 1206 can implement wireless communication for transmitting data to and from the computing device 1200. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that transmit data through non-solid media using modulated electromagnetic radiation. The term does not imply that the associated device does not contain any wires, although in some embodiments they may not. The communication chip 1206 can implement any of many wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, their derivatives, and any other wireless protocols known as 3G, 4G, 5G and higher generations. The computing device 1200 may include multiple communication chips 1206. For example, the first communication chip 1206 may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and the second communication chip 1206 may be dedicated to longer-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0161] The processor 1204 of the computing device 1200 includes an integrated circuit die packaged within the processor 1204. The integrated circuit die of the processor 1204 may include one or more structures constructed according to implementations of embodiments of the present disclosure, for example, a gate-all-around integrated circuit structure with stacked transistors using backside access. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory.

[0162] The communication chip 1206 also includes an integrated circuit die packaged within the semiconductor chip 1206. The integrated circuit die of the communication chip 1206 may include one or more structures constructed according to implementations of embodiments of the present disclosure, such as a gate-all-around integrated circuit structure with stacked transistors using backside access.

[0163] In other implementations, another component housed within computing device 1200 may include an integrated circuit die having one or more structures constructed according to implementations of embodiments of the present disclosure (e.g., a gate-all-around integrated circuit structure having stacked transistors with backside access).

[0164] In various embodiments, computing device 1200 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a cell phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In other embodiments, computing device 1200 may be any other electronic device that processes data.

[0165] Fig.13 An interposer 1300 including one or more embodiments of the present disclosure is shown. Interposer 1300 is an intermediate substrate for bridging a first substrate 1302 to a second substrate 1304. First substrate 1302 may be, for example, an integrated circuit die. Second substrate 1304 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. In general, the purpose of interposer 1300 is to extend connections to a wider spacing or to rewire connections to different connections. For example, interposer 1300 may couple an integrated circuit die to a ball grid array (BGA) 1306, which in turn may be coupled to a second substrate 1304. In some embodiments, first and second substrates 1302 / 1304 are attached to opposite sides of interposer 1300. In other embodiments, first and second substrates 1302 / 1304 are attached to the same side of interposer 1300. In other embodiments, three or more substrates are interconnected by interposer 1300.

[0166] Interposer 1300 may be formed of epoxy, glass fiber reinforced epoxy, ceramic material, or polymer material such as polyimide. In other embodiments, interposer 1300 may be formed of alternating rigid or flexible materials, which may include the same materials used in semiconductor substrates described above, such as silicon, germanium, and other III-V and IV materials.

[0167] The interposer 1300 may include metal interconnects 1308 and vias 1310, including but not limited to through-silicon vias (TSVs) 1312. The interposer 1300 may also include embedded devices 1314, which include both passive devices and active devices. Such devices include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 1300. According to an embodiment of the present disclosure, the apparatus or process disclosed herein may be used for the manufacture of the interposer 1300 or the manufacture of components included in the interposer 1300.

[0168] In another aspect, in an embodiment, the structures described herein are adapted to be used as high bandwidth (HBW) devices that can operate at cryogenic temperatures (e.g., in the range of -77 degrees Celsius to 0 degrees Celsius). In an embodiment, a thermal regulator / refrigeration device is coupled to a common board having a device having structures such as those described herein coupled thereto. In an embodiment, the thermal regulator device and / or the refrigeration device are included on a processing device having structures such as those described herein. In an embodiment, the structures described herein enable calculations of zetta units (Zuoc) to, for example, enable operation at cryogenic temperatures, etc.

[0169] It should be appreciated that the structures described herein can operate at low temperatures, for example, in the range of -77 degrees Celsius to 0 degrees Celsius. In one embodiment, the thermal regulator / refrigeration device is coupled to a common board having a device having structures such as those described herein coupled thereto, for example, as described below in connection with Fig.14A In one embodiment, the heat regulator device and / or the refrigeration device are included on a processing device having a structure such as those described herein, for example, as described below in connection with Fig. 14B described.

[0170] Fig.14A A computing device 1400 is shown in accordance with one implementation of an embodiment of the present disclosure. The computing device 1400 houses a board. The board may include several components, including, but not limited to, a processing device 1402. The computing device 1400 may also include a communication chip 1412. In one embodiment, the processing device 1402 is physically and electrically coupled to the board. In some implementations, the communication chip 1412 is also physically and electrically coupled to the board. In other implementations, the communication chip 1412 is part of the processing device 1402.

[0171] Depending on its application, the computing device 1400 may include other components that may or may not be physically and electrically coupled to the board. These other components may include, but are not limited to, memory 1404 (e.g., volatile memory (DRAM), non-volatile memory (e.g., ROM), or flash memory), antenna 1422, display device 1406, battery / power supply 1414, audio output device 1408, audio input device 1418, global positioning system (GPS) device 1416, other output devices 1410 (e.g., video output) and other input devices 1420 (e.g., video input), security interface device 1421, and / or testing devices. In one embodiment, a thermal regulation / cooling device 1411 is included and coupled to the board, such as a device including actively cooled copper channels.

[0172] The communication chip 1412 is capable of wireless communication for transmitting data to and from the computing device 1400. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that transmit data through non-solid media using modulated electromagnetic radiation. The term does not imply that the associated device does not contain any wires, although in some embodiments they may not. The communication chip 1412 can implement any of many wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, their derivatives, and any other wireless protocols known as 3G, 4G, 5G and higher generations. The computing device 1400 may include multiple communication chips 1412. For example, the first communication chip 1412 may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and the second communication chip 1412 may be dedicated to longer-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0173] The processing device 1402 of the computing device 1400 may include an integrated circuit die in a package. The processing device 1402 may include one or more structures constructed according to embodiments of the present disclosure, for example, a gate-all-around integrated circuit structure with stacked transistors using backside access. The term "processing device" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory.

[0174] Fig. 14B A processing device according to an implementation of an embodiment of the present disclosure is shown. Fig. 14B , the exemplary processing device 1402 includes a memory region, a logic region, a communication device region, an interconnect and redistribution layer (RDL) and a metal-insulator-metal (MIM) region, a cooling device region, a thermal regulation device region, a battery / power regulation device region, and a hardware security device region. In one embodiment, the cooling device region and / or the thermal regulation device region are regions including actively cooled copper channels.

[0175] Thus, embodiments of the present disclosure include integrated circuit structures having stacked transistors with backside access and methods of fabricating integrated circuit structures having stacked transistors with backside access.

[0176] The above description of the implementation of the embodiment of the present disclosure illustrated (including the content described in the abstract) is not intended to be exhaustive or limit the present disclosure to the exact form disclosed. Although specific implementations and examples of the present disclosure are described herein for illustrative purposes, various equivalent modifications may exist within the scope of the present disclosure, as will be recognized by those skilled in the art.

[0177] These modifications may be made to the present disclosure in light of the detailed description above. The terms used in the following claims should not be interpreted to limit the present disclosure to the specific embodiments disclosed in the specification and claims. Instead, the scope of the present disclosure will be determined entirely by the following claims, which should be interpreted in accordance with established principles of claim interpretation.

[0178] Example embodiment 1: An integrated circuit structure includes a front structure. The front structure includes: a device layer including a first nanowire stack, a second nanowire stack, a third nanowire stack, and a fourth nanowire stack and corresponding first overlying gate lines, second overlying gate lines, third overlying gate lines, and fourth overlying gate lines, and the device layer includes a first source or drain structure, a second source or drain structure, a third source or drain structure, a fourth source or drain structure, and a fifth source or drain structure alternating with the nanowire stacks and the overlying gate lines, and corresponding overlying trench contacts; and one or more metallization layers located above the device layer. The back structure includes a back via connection coupled to a bottom portion of the third source or drain structure, and the bottom portion of the third source or drain structure is isolated from the top portion of the third source or drain structure.

[0179] Example Embodiment 2: The integrated circuit structure of Example Embodiment 1, wherein the back side structure further comprises a power line, wherein the direct back side via connection couples the power line to a bottom portion of a third source or drain structure.

[0180] Example embodiment 3: The integrated circuit structure of example embodiment 1 or 2, wherein the back side structure further comprises a second back side via connection coupled to a bottom portion of the first source or drain structure, the bottom portion of the first source or drain structure being isolated from a top portion of the first source or drain structure.

[0181] Example Embodiment 4: The integrated circuit structure of Example Embodiment 3, wherein the back side structure further comprises a back side bit line, wherein the second back side via connection is coupled to the back side bit line.

[0182] Example Embodiment 5: The integrated circuit structure of Example Embodiment 1, 2, 3, or 4, wherein the first nanowire stack and the fourth nanowire stack each have fewer nanowires than each of the second nanowire stack and the third nanowire stack.

[0183] Example embodiment 6: An integrated circuit structure includes a front structure. The front structure includes: a device layer including a first nanowire stack, a second nanowire stack, a third nanowire stack, and a fourth nanowire stack and corresponding first overlying gate lines, second overlying gate lines, third overlying gate lines, and fourth overlying gate lines, and the device layer includes a first source or drain structure, a second source or drain structure, a third source or drain structure, a fourth source or drain structure, and a fifth source or drain structure alternating with the nanowire stacks and the overlying gate lines and corresponding overlying trench contacts; and one or more metallization layers located above the device layer. The back structure includes a feed-through hole coupled to the first source or drain structure.

[0184] Example Embodiment 7: The integrated circuit structure of Example Embodiment 6, wherein the back side structure further comprises a back side bit line, and wherein the feed-through via is coupled to the back side bit line.

[0185] Example embodiment 8: The integrated circuit structure of example embodiment 6 or 7, wherein the back structure also includes a back via connection portion coupled to a bottom portion of a third source or drain structure, and the bottom portion of the third source or drain structure is isolated from a top portion of the third source or drain structure.

[0186] Example Embodiment 9: The integrated circuit structure of Example Embodiment 8, wherein the back side structure further comprises a power line, and wherein the back side via connection is coupled to the power line.

[0187] Example Embodiment 10: The integrated circuit structure of Example Embodiment 6, 7, 8, or 9, wherein the first nanowire stack and the fourth nanowire stack each have fewer nanowires than each of the second nanowire stack and the third nanowire stack.

[0188] Example embodiment 11: A computing device includes a board and a component coupled to the board. The component includes an integrated circuit structure having a front structure. The front structure includes: a device layer including a first nanowire stack, a second nanowire stack, a third nanowire stack, and a fourth nanowire stack and corresponding first overlying gate lines, second overlying gate lines, third overlying gate lines, and fourth overlying gate lines, and the device layer includes a first source or drain structure, a second source or drain structure, a third source or drain structure, a fourth source or drain structure, and a fifth source or drain structure alternating with the nanowire stacks and the overlying gate lines and corresponding overlying trench contacts; and one or more metallization layers located above the device layer. The back structure includes a back via connection coupled to a bottom portion of the third source or drain structure, the bottom portion of the third source or drain structure is isolated from a top portion of the third source or drain structure, or the back structure includes a feedthrough coupled to the first source or drain structure.

[0189] Example Embodiment 12: The computing device of Example Embodiment 11, wherein the back side structure includes a back side via connection coupled to a bottom portion of the third source or drain structure.

[0190] Example Embodiment 13: The computing device of Example Embodiment 11, wherein the backside structure comprises a feed-through via coupled to the first source or drain structure.

[0191] Example Embodiment 14: The computing device of Example Embodiment 11, 12, or 13, further comprising a memory coupled to the board.

[0192] Example Embodiment 15: The computing device of Example Embodiment 11, 12, 13 or 14, further comprising a communication chip coupled to the board.

[0193] Example Embodiment 16: The computing device of Example Embodiment 11, 12, 13, 14, or 15, wherein the component is a packaged integrated circuit die.

[0194] Example Embodiment 17: The computing device of Example Embodiment 11, 12, 13, 14, 15, or 16, further comprising a battery coupled to the board.

[0195] Example Embodiment 18: The computing device of Example Embodiment 11, 12, 13, 14, 15, 16, or 17, further comprising a display coupled to the board.

[0196] Example Embodiment 19: The computing device of Example Embodiment 11, 12, 13, 14, 15, 16, 17, or 18, further comprising a camera coupled to the board.

[0197] Example Embodiment 20: The computing device of Example Embodiment 11, 12, 13, 14, 15, 16, 17, 18 or 19, wherein the component is selected from the group consisting of a processor, a communication chip, and a digital signal processor.

Claims

1. An integrated circuit structure, comprising: A front structure, the front structure comprising: A device layer comprising a first nanowire stack, a second nanowire stack, a third nanowire stack, and a fourth nanowire stack and corresponding first overlying gate lines, second overlying gate lines, third overlying gate lines, and fourth overlying gate lines, and The device layer includes first, second, third, fourth, and fifth source or drain structures alternating with the nanowire stacks and the overlying gate lines and corresponding overlying trench contacts; and one or more metallization layers overlying the device layer; and A backside structure includes a backside via connection coupled to a bottom portion of the third source or drain structure, the bottom portion of the third source or drain structure being isolated from a top portion of the third source or drain structure.

2. The integrated circuit structure according to claim 1, wherein: The back side structures further include a power line, wherein the direct back side via connection couples the power line to the bottom portion of the third source or drain structure.

3. The integrated circuit structure according to claim 1 or 2, wherein: The back side structure also includes a second back side via connection coupled to a bottom portion of the first source or drain structure, the bottom portion of the first source or drain structure being isolated from a top portion of the first source or drain structure.

4. The integrated circuit structure according to claim 3, wherein: The back side structure further includes a back side bit line, wherein the second back side via connection is coupled to the back side bit line.

5. The integrated circuit structure according to claim 1 or 2, wherein: The first nanowire stack and the fourth nanowire stack each have fewer nanowires than each of the second nanowire stack and the third nanowire stack.

6. An integrated circuit structure comprising: A front structure, the front structure comprising: A device layer comprising a first nanowire stack, a second nanowire stack, a third nanowire stack, and a fourth nanowire stack and corresponding first overlying gate lines, second overlying gate lines, third overlying gate lines, and fourth overlying gate lines, and The device layer includes first, second, third, fourth, and fifth source or drain structures alternating with the nanowire stacks and the overlying gate lines and corresponding overlying trench contacts; and one or more metallization layers overlying the device layer; and A backside structure includes a feedthrough coupled to the first source or drain structure.

7. The integrated circuit structure according to claim 6, wherein: The back side structure further includes a back side bit line, and wherein the feed-through via is coupled to the back side bit line.

8. The integrated circuit structure according to claim 6 or 7, wherein: The backside structure also includes a backside via connection coupled to a bottom portion of the third source or drain structure, the bottom portion of the third source or drain structure being isolated from a top portion of the third source or drain structure.

9. The integrated circuit structure according to claim 8, wherein: The back side structure further includes a power line, and wherein the back side via connection is coupled to the power line.

10. The integrated circuit structure according to claim 6 or 7, wherein: The first nanowire stack and the fourth nanowire stack each have fewer nanowires than each of the second nanowire stack and the third nanowire stack.

11. A computing device comprising: plate; as well as a component coupled to the board, the component comprising an integrated circuit structure, the integrated circuit structure comprising: A front structure, the front structure comprising: a device layer comprising first, second, third and fourth nanowire stacks and corresponding first, second, third and fourth overlying gate lines, and the device layer comprising first, second, third, fourth and fifth source or drain structures alternating with the nanowire stacks and the overlying gate lines and corresponding overlying trench contacts; and one or more metallization layers overlying the device layer; and A back side structure comprising a back side via connection coupled to a bottom portion of the third source or drain structure, wherein the bottom portion of the third source or drain structure is isolated from a top portion of the third source or drain structure, or the back side structure comprises a feed-through via coupled to the first source or drain structure.

12. The computing device of claim 11, wherein: The backside structure includes a backside via connection coupled to the bottom portion of the third source or drain structure.

13. The computing device of claim 11, wherein: The backside structure includes a feed-through coupled to the first source or drain structure.

14. The computing device of claim 11, 12 or 13, further comprising: A memory is coupled to the board.

15. The computing device of claim 11, 12 or 13, further comprising: A communication chip is coupled to the board.

16. The computing device of claim 11, 12 or 13, wherein: The component is a packaged integrated circuit die.

17. The computing device of claim 11, 12 or 13, further comprising: A battery is coupled to the board.

18. The computing device of claim 11, 12 or 13, further comprising: A display is coupled to the panel.

19. The computing device of claim 11, 12 or 13, further comprising: A camera is coupled to the board.

20. The computing device of claim 11, 12 or 13, wherein: The component is selected from the group consisting of a processor, a communication chip and a digital signal processor.

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