Selective and self-aligned SOI thinning for RF switch applications

Abstract

Embodiments of the present disclosure relate to selective and self-aligned SOI thinning for RF switching applications. A transistor device includes a silicon-on-insulator (SOI) substrate having a plurality of polysilicon gates including a plurality of recessed gates and a plurality of non-recessed gates. A plurality of recessed gates are recessed in a top silicon layer of the SOI substrate, and a plurality of non-recessed gates are on the top silicon layer. The plurality of recessed gates includes an upper cap portion on a bottom buried portion in the recess of the SOI substrate. A method of manufacturing the device is provided.

Description

Technical Field

[0001] The present disclosure relates to devices having recessed gates in silicon-on-insulator (SOI) substrates and methods of fabricating the same. Background Art

[0002] Transistor devices, such as complementary metal oxide semiconductor (CMOS) transistors, are used in a range of products, such as 5G devices, mobile phones, antenna switches, and base station radio frequency (RF) switches. To improve the performance of such devices while reducing their size, some trade-offs need to be considered. For example, in an RF switch, R on With C off (RFV max ) must exist between on Determine the insertion or signal loss, C off Determines off-state isolation, and RFV max Determine the isolation breakdown. The goal is to optimize these values ​​to improve the performance of the device.

[0003] Lower C off One trend in increasing the value of the device is to use thin substrates. However, this approach increases the cost and complexity of the device. In addition, too thin a substrate can cause other problems, such as higher R due to increased signal loss during device performance. on Another example is when the substrate becomes too thin, in order to maintain the high dopant concentration areas required for low resistance, it is necessary to regrow the substrate in selected areas. While it is beneficial to have a thin substrate under the gate, it may be disadvantageous in other areas of the device. One remedy is to regrow in areas where a thin substrate is disadvantageous, however, this growth process complicates the manufacturing process and increases costs. Currently, reducing the thickness of the substrate is associated with complex and expensive manufacturing costs.

[0004] Therefore, it would be advantageous to have a substrate with a selective thickness throughout the substrate. Summary of the invention

[0005] The present disclosure relates to a device, which includes a silicon-on-insulator (SOI) substrate, the SOI substrate having: a first silicon layer and a second silicon layer; a first insulating layer between the first silicon layer and the second silicon layer, the first silicon layer having a first surface; and a recess in the first surface of the first silicon layer. The device also includes a second insulating layer and a first gate, the second insulating layer is on the first surface of the first silicon layer and in the recess, the first gate is on the second insulating layer, the first gate has a first portion in the recess and a second portion on the first portion, and the second portion has a size different from the first portion in a first direction. A method for manufacturing the device is also disclosed.

[0006] The present disclosure relates to optimizing Ron C off (RFV max ) value without compromising other features and utilizing deliberate cost control methods for manufacturing to improve performance. Some advantages of the present disclosure are self-alignment of the gate on the substrate and selective thinning of the substrate below the gate footprint rather than the entire substrate. In addition, the manufacturing method and device can be applied to areas other than RF switches, such as SOI technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In the drawings, the same reference numerals identify similar features or elements. The sizes and relative positions of features in the drawings are not necessarily drawn to scale, but the relationships between the features are representative of the relationships in the final product.

[0008] Figure 1 A plurality of recessed gates in a silicon-on-insulator (SOI) substrate and a plurality of gates on the SOI substrate according to some embodiments.

[0009] Figure 2 yes Figure 3 Cross-sectional view of the recessed gate in FIG.

[0010] Figure 3 Is a multiple Figure 2 A top view of a recessed gate transistor device.

[0011] Figure 4A and Figure 4B are steps of a method for manufacturing a plurality of recessed gates.

[0012] FIG. 5A to FIG. 5E are steps of a method for manufacturing a plurality of recessed gates according to another embodiment.

[0013] Figure 6 yes 7A to 7J Flowchart of the steps.

[0014] 7A to 7J are steps of a method for manufacturing a plurality of gates according to another embodiment.

[0015] Figure 8 yes 9A to 9H Flowchart of the steps.

[0016] 9A to 9H are steps of a method for manufacturing a plurality of gates according to another embodiment. DETAILED DESCRIPTION

[0017] The present disclosure relates to transistor structures in RF or radio frequency devices, such as cell phones or antenna circuits. The transistor structures include controlled thinning of a silicon-on-insulator (SOI) substrate on which the RF transistors are formed. Another component of the same device may include other transistors that are not on the thinned SOI. The goal is to improve R on and C off , with a stable or consistent RFV max , or even better RFV max This can be implemented in a small chip such as 0.05 square millimeters or 220 μm x 220 μm.

[0018] The present disclosure is directed to local SOI thinning at the transistor level. In some embodiments, these are self-aligned gates. The present disclosure reduces or eliminates the re-epitaxial growth step in the current technology of thinning the entire epitaxial layer. The present disclosure is directed to thinning the SOI only at the gate location or only within a small radius of the gate location.

[0019] Figure 1 The present invention is a transistor device 101 formed on and in a silicon-on-insulator (SOI) substrate 110. The device 101 includes a plurality of recessed gates 230, the plurality of recessed gates 230 are in the SOI substrate 110, and are spaced apart from a plurality of non-recessed gates 250 on or on top of the SOI substrate 110. An oxide or insulating layer 123 is between the plurality of gates 230, 250 and the SOI substrate 110. The plurality of recessed gates 230 are located in a first region 102 of the device 101. The plurality of non-recessed gates 250 are located in a second region 104 of the device 101. Shallow trench isolation 260 separates the first region 102 from the second region 104. In the final chip, these first and second regions may be spaced apart by other parts or circuits on the chip. For simplicity, they are illustrated as being separated only by shallow trench isolation.

[0020] Bottom and top are used for orientation and simplification in understanding the drawings. Bottom and top are relative to the drawings shown, but the positions in the final product may be reversed.

[0021] The SOI substrate 110 has a first silicon layer 112 having a bottom surface 114 opposite to a top surface 119. The first silicon layer 112 is the bottommost layer of the SOI substrate 110 and has a bottom surface 114 that is exposed and can be coupled to another device or surface. The first silicon layer 112 can be bulk silicon or other suitable substrate materials.

[0022] The SOI substrate 110 also has a buried oxide layer or region 200 on the first silicon layer 112. The buried oxide layer 200 has a bottom surface 202 that contacts the top surface 119 of the first silicon layer 112. The top surface 119 of the first silicon layer 112 is substantially covered by the bottom surface 202 of the buried oxide layer 200. A top surface 207 of the buried oxide layer 200, opposite the bottom surface 202, is substantially covered by a second silicon layer 208. The buried oxide layer 200 may be silicon dioxide.

[0023] The second silicon layer 208 is part of the SOI substrate 110 and is the uppermost layer of the SOI substrate 110. The top surface 214 of the second silicon layer 208 is the top surface of the SOI substrate 110. The bottom surface 210 of the second silicon layer 208 contacts the top surface 207 of the buried oxide layer 200.

[0024] In some embodiments, the second silicon layer 208 has a thickness greater than 10 nm in the first direction. Figure 1 In some embodiments, the thickness of the second silicon layer 208 is between 60 and 300 nm. In a specific embodiment, the thickness of the second silicon layer 208 is between 60 and 70 nm.

[0025] An oxide or insulating layer 123 covers or is otherwise on a top surface 214 of the second silicon layer 208. The insulating layer 123 contacts the top surface 214 of the second silicon layer 208. The insulating layer 123 extends between the recessed gate 230 and the substrate 110. More specifically, the insulating layer 123 covers a bottom surface 124 of the recess 120 in the substrate 110, including the sidewalls 122 of the recess 120. The insulating layer 123 is also between portions of the cap portion 240 that are on the top surface 214 of the second silicon layer 208. In some embodiments, the insulating layer 123 is not present.

[0026] The first recessed gate 230 is in the recess 120 of the first region 102 of the device. The recessed gate 230 has a buried portion 232 in the recess 120 and a second cap or upper portion 240 on the buried portion 232, wherein the upper portion 240 is above the SOI substrate 110. Although only RF devices are noted, the first region 102 may be an RF transistor and the second region 104 may be other types of transistors.

[0027] The insulating layer 123 extends along the second direction between the bottom surface 254 of the second gate 250 and the substrate 110 . In some embodiments, the insulating layer 123 is on the corner 216 of the second silicon layer 208 .

[0028] The buried portion 232 includes a bottom surface 234, which is between the surfaces 214, 210 or in an intermediate position between the surfaces 214, 210. The buried portion 232 extends in the second silicon layer 208 to a first dimension in the first direction. In some embodiments, the first dimension of the buried portion 232 is less than half of the entire second silicon layer 208. The buried portion 232 includes a side surface 235 adjacent to the sidewall 122 of the recess 120. In some embodiments, the bottom surface 234 of the buried portion 232 is curved. The second dimension of the buried portion 232 is between the side surfaces 235 in the second direction. The first dimension of the buried portion 232 is less than the second dimension of the buried portion 232. In some embodiments, the second dimension of the buried portion 232 is between 0.12 and 0.24 μm.

[0029] The upper cap portion 240 is wider and taller than the buried portion 232 of the recessed gate 230. The upper cap portion 240 has a top surface 242 opposite to the bottom surface 124 of the buried portion 232. The cap portion 240 extends outwardly away from the center in the second direction on the first surface 214 of the second silicon layer 208. The cap portion 240 overlaps the second silicon layer 208. In some embodiments, the gate 230 is T-shaped.

[0030] The cap portion 240 has a first dimension in the first direction that is greater than a first dimension of the buried portion 232. The cap portion 240 has a second dimension in the second direction that is greater than a second dimension of the buried portion 232.

[0031] The recessed gate 230 has an indentation defined or defined by a side surface 235 of the buried portion 232 and an outer edge of the cap portion 240. The recessed gate 230 has at least two indentations that are opposite to each other.

[0032] The insulating layer 123 may have a constant thickness in the first direction. In some embodiments, the thickness of the insulating layer 123 is from 1 to 15 nm. In a specific embodiment, the thickness of the insulating layer 123 may be about 5 nm. The insulating layer 123 may be an oxide layer of silicon dioxide or silicon oxynitride (SiON). The top surface 264 of the shallow trench isolation 260 may start from the insulating layer 123. In some embodiments, the top surface 264 of the shallow trench isolation 260 is covered by the insulating layer 123. The first silicon layer 112 has a first dimension extending from the bottom surface 114 to the top surface 119 along the first direction. The buried oxide layer 200 has a second dimension from the bottom surface 202 to the top surface 207 along the first direction. The second silicon layer 208 has a third dimension from the bottom surface 210 to the top surface 214. The third dimension of the second silicon layer 208 may be smaller than the first dimension. The third dimension of the second silicon layer 208 may be smaller than the second dimension.

[0033] The three layers of the SOI substrate 110 include a first silicon layer 112, a buried oxide layer 200, and a second silicon layer 208, each of which has substantially similar dimensions between corresponding side surfaces. The side surfaces of the three layers are substantially coplanar with each other.

[0034] The shallow trench isolation 260 extends from the buried oxide layer 200 through the second silicon layer 208. In some embodiments, the shallow trench isolation 260 extends beyond the top surface 214 of the second silicon layer 208. The shallow trench isolation 260 may have tapered sidewalls 262 and a first dimension between the tapered sidewalls 262 in a second direction transverse to the first direction. The first dimension may be closer to the top surface 207 of the buried oxide layer 200 than the top surface 214 of the second silicon layer 208. The shallow trench isolation 260 has a second dimension in the second direction between the tapered sidewalls 262. The second dimension of the shallow trench isolation 260 is greater than the first dimension. In some embodiments, the second dimension is at the top surface 264 of the shallow trench isolation 260 and extends above the top surface 214 of the second silicon layer 208.

[0035] A shallow trench isolation 260 may separate the first region 102 and the second region 104 of the device 100. The first region 102 has a recess 120 in the second silicon layer 208. The shallow trench isolation 260 may be adjacent to the recess 120. The SOI substrate 110 may include a plurality of recesses 120 spaced apart from each other and located in the first region 102. In some embodiments, there is no shallow trench isolation 260. In other embodiments, there are multiple shallow trench isolations.

[0036] The recess 120 has sidewalls 122 and an inner bottom surface 124 between the top surface 214 of the second silicon layer 208 and the top surface 207 of the buried oxide layer 200. In some embodiments, the bottom surface 124 is closer to the top surface 214 of the second silicon layer 208 than to the top surface 207 of the buried oxide layer 200. The sidewalls 122 are opposite to each other and extend from the bottom surface 124 of the recess 120 to the top surface 214 of the second silicon layer 208. In some embodiments, the recess 120 is curved.

[0037] In some embodiments, the recess sidewall 122 defines a corner 216 of the second silicon layer 208. The recess 120 has a first dimension in the first direction from the bottom surface 124 of the recess 120 to the top surface 214 of the second silicon layer 208. The recess 120 has a second dimension in the second direction of the bottom surface 124 between the sidewalls 122. In some embodiments, the first dimension is smaller than the second dimension. The first dimension of the recess 120 can be between 5 and 50 nm. In some embodiments, the first dimension of the recess 120 is between 10 and 30 nm. The second silicon layer 208 can have a thickness in the first direction below the recess 120, which is between 50 and 130 nm. In some embodiments, the thickness of the second silicon layer 208 is 60 nm.

[0038] In some embodiments, corner 216 of second silicon layer 208 is positioned below cap portion 240 and above bottom surface 234 of buried portion 232 .

[0039] The recessed gate 230 may be a polysilicon gate or other suitable conductive material. In some embodiments, the recessed gate 230 may be T-shaped. The device 101 may include a plurality of recessed gates 230, and the recessed gates 230 are spaced apart from each other. One end of the cap portion 240 of the recessed gate 230 may face one end of the cap portion of another recessed gate arranged in an array, such as Figure 3 shown.

[0040] A plurality of second gates 250 are located in the second region 104 of the device 100, spaced apart from the plurality of first gates 230. The second gates 250 are on the top surface 214 of the second silicon layer 208. The second gates 250 have a top surface 252, a bottom surface 254, and a side surface 256 between the top surface 252 and the bottom surface 254. The bottom surface 254 is on the top surface 214 of the second silicon layer 208. A first dimension of the second gates 250 is between the top surface 252 and the bottom surface 254 in a first direction. A second dimension of the second gates 250 is between the side surfaces 256 in a second direction. In some embodiments, the first dimension of the second gates 250 is substantially similar to a second dimension of the cap portion 240 of the recessed gates 230, and the second dimension of the second gates 250 is substantially similar to the first dimension of the cap portion 240.

[0041] The second gate 250 may also be a polysilicon gate. The second gate 250 may be the same material as the first gate 230. In some embodiments, the second gate 250 is substantially rectangular. The second gate 250 may be adjacent to and spaced apart from the shallow trench isolation 260. The side surface 256 of the second gate 250 may face the side surface of another second gate.

[0042] Figure 2 It is along Figure 3This is a cross-sectional view of the transistor array along line II. Figure 1 The transistor includes a plurality of recessed gates 230 in the SOI substrate 110, the recessed gates 230 extending in a first direction ( Figure 3 The gate contacts 130 are spaced apart from each other in the horizontal direction in the first direction. The gate contacts 130 are coupled to each first end of each of the recessed gates 230 along the first direction. The gate contacts 130 extend transversely to the extension of each recessed gate 230. The second end of the recessed gate 230 opposite to the first end is coupled to the contact 180. Figure 3 , additional contacts 180 are on the SOI substrate 110 and between adjacent recessed gates 230. In particular, the contacts 180 are spaced apart from each other on the active region 160 of the SOI substrate 110.

[0043] The doped regions in the second silicon layer 208 of the SOI substrate 110 include the active region 160. The doped regions are formed in and around each recess 120 in the second silicon layer 208, and in and around the top surface 214 of the second silicon layer 208. In some embodiments, the doped regions do not reach the bottom surface 210 of the second silicon layer 208. In other embodiments, the doped regions reach the bottom surface 210 of the second silicon layer 208. These doped regions form the source and drain of the transistor, and form or otherwise create the boundary of the channel region below the gate 230.

[0044] The doped region includes an N-doped region and an N+ doped region, wherein the N-doped region is closer to the recess 120 than the N+ doped region. The N+ doped region is closer to the bottom surface 210 than to the top surface 214 of the second silicon layer 208. Compared with the N-doped region below the recess 120, the N+ doped region extends further into the second silicon layer 208 toward the bottom surface 210 in the first direction.

[0045] The doped region extends upward to a corner 216 of the second silicon layer 208, wherein the sidewall 122 of the recess 120 intersects the top surface 214 including the corner 216. The doped region extends in the first direction adjacent to the sidewall 122. The N-doped region extends to the top surface 214.

[0046] Portions of the opposing N-doped regions extend toward each other under the recess 120, but do not contact each other. A channel 170 is formed under the recess 120, between the opposing N-doped regions and a portion of the second silicon layer 208 that does not have any doped regions under the recess 120. The channel 170 is under the recessed gate 230 in the recess 120, and in particular, under the buried portion 232 of the recessed gate 230. In some embodiments, the N-doped region under the recess 120 and the recessed gate 230 extends about 10-20 nm in the second direction.

[0047] An insulating layer or oxide layer 223 extends over the active region 160 and in the recess 120. The insulating layer 223 covers the top surface 214 of the second silicon layer 208, including the sidewalls 122 and the bottom surface 124 of the recess 120. The insulating layer 223 covers the corners 216 of the second silicon layer 208. Another insulating layer 225, which may be an oxide, extends laterally to the top surface 214 along the side surfaces 246 of the recessed gate 230. The top surface of the insulating layer 225 is coplanar with the top surface 242 of the recessed gate 230. The insulating layer 223 is between the recessed gate 230 and a plurality of spacers 280. For simplicity, the insulating layer 223 is disposed between the recessed gate 230 and the plurality of spacers 280. Figure 3 The spacer 280 is not shown in the top view of FIG.

[0048] A plurality of spacers 280 are adjacent to the side surface 246 of the cap portion 240 of the recessed gate 230. The insulating layer 223 extends between each spacer 280 and the cap portion 240 of the recessed gate 230. The insulating layer 223 also extends between the bottom surface of the spacer and the top surface 214 of the second silicon layer 208. The entire insulating layer 223 has a substantially similar thickness. In some embodiments, the insulating layer 223 substantially surrounds the recessed gate 230 except for the top surface 242.

[0049] The spacer 280 has an outer curved surface extending downward to the insulating layer 223 on the second silicon layer 208. The spacer 280 tapers toward the top surface 242 of the cap portion 240. The spacer 280 has a first end on the second silicon layer 208 and a first dimension in the second direction. The spacer 280 has a second end opposite to the first end and a second dimension in the second direction. The second dimension of the spacer 280 is smaller than the first dimension of the spacer. The second end of the spacer 280 is closer to the top surface 242 of the cap portion 240 than the first end. In some embodiments, the first dimension of the spacer is between 20 and 40 nm.

[0050] A plurality of contacts 180 are spaced apart from the spacers 280. In particular, the contacts are adjacent to and spaced apart from the spacers 280. The contacts 180 are illustrated on the insulating layer 223 on the top surface 214 of the second silicon layer 208, however, in the final product, the contacts may be in direct contact with the doped regions or in electrical contact through a conductive layer. The contacts 180 extend beyond the top surface 242 of the recessed gate 230 in the first direction.

[0051] Figure 4A and Figure 4B 4 is a method of manufacturing a plurality of recessed gates 430 according to another embodiment. An SOI substrate having a top silicon layer 408 is provided. For simplicity, other layers of the SOI substrate are not shown, including a buried oxide region below the top silicon layer 408 and a bottom silicon layer below the buried oxide region. In some embodiments, the second silicon layer 408 has a thickness of about 70 nm in the first direction.

[0052] A nitride layer or masking region 471 substantially covers the top surface 414 of the top silicon layer 408. The nitride layer 471 is silicon nitride or other suitable material. A photoresist layer or patterned region 472 patterns the top surface of the nitride layer 471. Then, a plurality of recesses 420 are formed by etching the second silicon layer 408 through the nitride layer 471. Each of the recesses 420 formed is spaced apart from each other. The recesses are formed in the top surface 414 of the second silicon layer 408. Etching exposes the top surface 414 of the second silicon layer 408. Only the gate recess region 420 is etched in the SOI.

[0053] Each recess 420 has a bottom surface 424 in the second silicon layer 408 and lateral sidewalls 422 extending from the bottom surface 424 of the second silicon layer 408 to the top surface 414. The sidewalls 422 are lateral to the top surface 414 and the bottom surface 424.

[0054] Then, an insulating layer 423 is formed in the recess 420, covering the bottom surface 424 and the sidewalls 422. The insulating layer 423 is continuous along the sidewalls 422 of the recess 420 and the exposed top surface 414 of the second silicon layer 408 (e.g., the bottom surface 424 of the recess 420). The insulating layer 423 has a top surface coplanar with the top surface 414 of the second silicon layer 408. The top surface of the insulating layer 423 is adjacent to the sidewalls 422 of the recess 420. In other embodiments, the insulating layer 423 extends beyond the top surface 414 of the second silicon layer 408 and extends along the side surface of the nitride layer 471. In other embodiments, the insulating layer 423 may be omitted.

[0055] Then, a recessed gate 430 is formed. In this embodiment, the recessed gate 430 is formed on the insulating layer 423. Forming the recessed gate 430 includes forming a conductive gate material in the recess 420. The conductive gate material is formed using an inversion of the recessed gate 430.

[0056] The formed recessed gate 430 includes an upper portion 440 integral with a buried portion 432. The upper portion 440 is centrally aligned with the buried portion 432. The upper portion 440 extends beyond the top surface 414 of the second silicon layer 208, while the buried portion 432 extends below the top surface 414. The buried portion 432 is in the recess 420.

[0057] In this embodiment, the buried portion 432 does not extend onto the top surface 414 of the second silicon layer 408. In this embodiment, the side surface 446 of the upper portion 440 and the side surface 435 of the buried portion 432 are coplanar. In this embodiment, the first dimension and the second dimension of the recessed gate 430 are substantially similar, and the upper portion 440 does not extend onto the top surface 414 of the second silicon layer 408. In particular, the first dimension and the second dimension are between 0.065 μm and 0.24 μm, inclusive.

[0058] In some embodiments, the first dimension of recessed gate 430 is smaller than the second dimension of recessed gate 430 and side surfaces 446, 435 of upper portion 440 and buried portion 432 are not coplanar. In some embodiments, portions of insulating layer 423 exist along side surface 446 of upper portion 440 of recessed gate 430.

[0059] After forming the insulating layer 423, the photoresist layer 472 and the nitride layer 471 are removed. Figure 4A and Figure 4B This is a good solution, but there is a risk that there may be a gap between the sidewalls of the recess and the conductive material of the gate.

[0060] FIG. 5A to FIG. 5E 5 is a step of a method for manufacturing a plurality of recessed gates 530 according to another embodiment, wherein each recessed gate 530 has a cap portion 540 extending onto the surface of the substrate and reducing the risk of gaps in the recesses. An SOI substrate is provided, which has a top silicon layer 508 on a buried oxide layer. Below the buried oxide layer is a bottom silicon layer, and for simplicity, both layers are not shown. The top surface 514 of the top silicon layer 508 is the top surface of the SOI substrate. For simplicity, not shown, at least one or more shallow trench isolations extending from the buried oxide layer through the top surface 514 are formed in the SOI substrate. The shallow trench isolation separates these transistors (which may be RF transistors) from other types of transistors in the final integrated circuit or chip.

[0061] The first insulating layer 501 is on the top surface 514 and substantially covers the top surface 514. The first insulating layer 501 includes silicon dioxide or other suitable insulating materials. The first insulating layer 501 has a substantially uniform thickness throughout.

[0062] On the first insulating layer 501 is a nitride layer 571, which substantially covers the first insulating layer 501, so that the first insulating layer 501 is sandwiched between the top surface 514 and the nitride layer 571. The nitride layer 571 includes silicon nitride or other suitable materials. The nitride layer 571 has a substantially uniform thickness as a whole. The nitride layer 571 has a thickness in the first direction that is significantly greater than the thickness of the first insulating layer 501 in the first direction. In some embodiments, the first insulating layer 501 is not present.

[0063] The nitride layer 571 is patterned using a mask that is an inverse of the recessed gate 530 .

[0064] Then, in Figure 5A In the embodiment of the present invention, a plurality of recesses 520 are formed in the top surface 514, and each recess 520 is spaced apart from each other. Forming the recesses 520 includes etching through the nitride layer 571 and the first insulating layer 501 using a mask. Portions of the top silicon layer 508 are also etched, but the etching stops at an intermediate position in the top silicon layer 508. In some embodiments, the etching in the first direction stops at or before the middle of the top silicon layer 508.

[0065] The etching exposes a portion of the top silicon layer 508 and the side surfaces of the nitride layer 571 and the first insulating layer 501. The exposed side surfaces of the nitride layer 571 and the first insulating layer 501 are lateral to the top surface 514 of the second silicon layer 208 and are coplanar with the side exposed surfaces of the top silicon layer 508. The side exposed surfaces of the top silicon layer 508 define the sidewalls 522 of the recess 520.

[0066] Each of the recesses 520 formed has a bottom surface 524 defined by the top silicon layer 508. The bottom surface 524 is transverse to the sidewalls 522. The bottom surface 524 is located in the top silicon layer 508 closer to the top surface 514 than to the opposite bottom surface near the top silicon layer 508. Each recess 520 has a first dimension between the sidewalls 522. A second dimension of each recess 520 is greater than the first dimension of the recess 520. In other embodiments, the second dimension is substantially similar to or less than the first dimension.

[0067] After etching, the top silicon layer 508 has a first thickness from the top surface 514 to the bottom surface and a second thickness from the bottom surface 524 of the recess to the bottom surface of the top silicon layer 508. The first thickness is greater than the second thickness. A column or stack is formed between adjacent recesses 520, the column or stack including a portion of the nitride layer 571, the first insulating layer 501, and the top silicon layer 508.

[0068] Then, in Figure 5B In the embodiment, nitride layer 571 is etched at the side surfaces. The etching reduces the thickness of nitride layer 571 between the side surfaces. In some embodiments, the etching is performed via nitride pull-back.

[0069] Etching the nitride layer 571 exposes a portion of the top surface of the first insulating layer 501. The side surface of the first insulating layer 501 is no longer coplanar with the side surface of the nitride layer 571. Instead, the side surface of the first insulating layer 501 remains coplanar with the sidewall 522 of the recess 520. The exposed portion of the first insulating layer 501 forms a step feature or corner between the nitride layer 571 and the sidewall 522. In some embodiments, etching the nitride layer 571 is optional.

[0070] exist Figure 5C , a second insulating layer 502 is formed on the top silicon layer 508. The second insulating layer 502 continuously covers the nitride layer 571, including the top surface and the side surface of the nitride layer 571. The exposed portion of the top silicon layer 508 (including the sidewall 522 and the bottom surface 524 of the recess 520) is coated with the second insulating layer 502. The second insulating layer 502 contacts the first insulating layer 501 and has a uniform thickness as a whole. The second insulating layer 502 is made of the same material as the first insulating layer 501 or other suitable insulating materials.

[0071] Then, in Figure 5D In the embodiment, the gate polysilicon material 503 is deposited in the recess 520. The second insulating layer 502 is between the gate polysilicon material 503 and the nitride layer 571. In some embodiments, the gate polysilicon material 503 completely fills the recess 520. In some embodiments, the gate polysilicon material 503 overfills the recess 520 and covers the second insulating layer 502 on the top surface of the nitride layer 571.

[0072] The recessed gate 530 in the recessed portion 520 is Figure 5E Chemical mechanical polishing or another suitable method is performed to remove the top portion of the gate polysilicon material 503. Then, phosphoric acid (H 3 PO 4), hydrofluoric acid (HF), or a combination thereof may be used to remove a portion of the second insulating layer 502. The removal exposes a top surface of the nitride layer 571 that is coplanar with the exposed top surface 542 of the recessed gate 530. The removal also exposes a top surface of the second insulating layer 502 that is coplanar with the top surface 542 of the recessed gate 530.

[0073] The formed recessed gate 530 includes a cap portion 540 on the buried portion 532 in the recess 520. The second insulating layer 502 is continuous and integral with the first insulating layer 501. The second insulating layer 502 is between the recessed gate 530 and the top silicon layer 508. The first insulating layer 501 and the second insulating layer 502 are between the recessed gate 530 and the nitride layer 571.

[0074] Thereafter, the nitride layer 571 is removed, which is not shown for simplicity. Subsequent steps may be performed to produce Figure 2 The recessed gate 230 is formed. In some embodiments, the steps of forming a lightly doped drain region and forming a spacer 280 are performed.

[0075] Figure 6 and 7A to 7J is a flow chart of steps of a method for manufacturing a device including multiple gates according to another embodiment of the present disclosure. Figure 7H , the plurality of gates include a plurality of recessed gates 730 and a plurality of non-recessed gates 750. The plurality of gates are formed on a silicon-on-insulator (SOI) substrate, the SOI substrate including a top silicon layer 708 on a buried oxide layer. The buried oxide layer is on the bottom silicon layer. For simplicity, the buried oxide layer and the bottom silicon layer are not shown. The first insulating layer 705 is formed on the top surface 714 of the top silicon layer 708. The first insulating layer 705 substantially covers the top surface 714 and is made of silicon dioxide or other suitable materials. The first insulating layer 705 has a uniform thickness as a whole. The top silicon layer 708 can have a thickness from 60 to 300 nm from the bottom surface to the first insulating layer 705.

[0076] In step 602 of the method, a shallow trench isolation structure is formed in the SOI substrate. For simplicity, this is 7A to 7J Shallow trench isolation can have Figure 1 Shallow trench isolation structures are formed to separate the plurality of recessed gates 730 from other gates and circuit structures in the final device.

[0077] Then, in step 604, a well is etched according to the final transistor design, the well including the doped region in the SOI substrate. For the sake of clarity, this step is not shown in the figure. 7A to 7J is shown in .

[0078] Next, in step 606, nitride layers 771, 773 and insulating layers 705, 706 are formed on the SOI substrate, see Fig. 7A In some embodiments, the first insulating layer 705 completely covers the top surface 714. In other embodiments, the insulating layer 705 partially covers the top surface 714. In some embodiments, the first insulating layer 705 is not present. Covering the first insulating layer 705 is a first nitride layer 771. The first nitride layer 771 is silicon nitride or other suitable materials. The first nitride layer 771 has a uniform thickness throughout.

[0079] In some embodiments, the first nitride layer 771 completely or partially covers the top surface of the first insulating layer 705. In the absence of the insulating layer 705, the first nitride layer 771 is on the top surface 714 of the top silicon layer 708 and partially or completely covers the top surface 714 of the top silicon layer 708.

[0080] The second insulating layer 706 is on the first nitride layer 771. The second insulating layer 706 may be made of the same material as the first insulating layer 705, or other suitable insulating materials. The second insulating layer 706 completely covers the top surface of the first nitride layer 771. The second insulating layer 706 has a uniform thickness as a whole. The second insulating layer 706 is thinner than the nitride layer 771. The first nitride layer 771 may have a thickness of 120 nm from the first insulating layer 705 to the second insulating layer 706.

[0081] A second nitride layer 773 is formed or deposited on the second insulating layer 706. The second nitride layer 773 is patterned and shaped using the photoresist layer 772 so as not to completely cover the top surface of the second insulating layer 706. Instead, only a portion of the second insulating layer 706 is covered by the second nitride layer 773, so that an area of ​​the second insulating layer 706 is exposed, see Fig. 7A The second nitride layer 773 may have the same material as the first nitride layer 771, or other suitable materials. The second nitride layer 773 has a thickness from the top surface to the second insulating layer 706 that is less than the thickness of the first nitride layer 771 between the first insulating layer 705 and the second insulating layer 706. In some embodiments, the thickness of the second nitride layer 773 is greater than or equal to the thickness of the first nitride layer 771. The second nitride layer 773 may have a thickness from the second insulating layer 706 to the first photoresist layer 772 between 20-50 nm.

[0082] The dotted line is for illustration purposes only and divides the device into the RF switch area on the left and the digital area on the right.

[0083] Then, at step 608, the nitride layers 771, 773 are patterned and etched using a second photoresist layer 774 and a mask to form a plurality of openings 726. The first photoresist layer 728 is used to create a plurality of openings 728 on the digital side of the device. This corresponds to Figure 7B , wherein etching of the first photoresist layer 772 and etching of the second photoresist layer 774 are performed simultaneously so that the depth or time of etching for forming the plurality of openings 726 and 728 is the same.

[0084] Then, the plurality of openings 726, 728 includes a plurality of first openings 726 and a plurality of second openings 728. The plurality of first openings 726 are formed by etching through the second insulating layer 706 and the first nitride layer 771 to expose the first insulating layer 705. Each first opening 726 has a bottom surface 727 defined by the first insulating layer 705 now exposed by the etching step, and sidewalls of the nitride layer 771 and the second insulating layer 706.

[0085] A plurality of second openings 728 are formed by etching through the second nitride layer 773, the second insulating layer 706, and into the first nitride layer 771. However, etching the second openings 728 stops at an intermediate surface 729 in the first nitride layer 771. The surface 729 is spaced apart from the first insulating layer 705 by a distance greater than zero. Each second recess 728 has a bottom surface 729 defined by the first nitride layer 771.

[0086] Etching the plurality of first openings 726 and the plurality of second openings 728 exposes the side surfaces of the photoresist layers 772, 774, the first and second insulating layers 705, 706, and the first and second nitride layers 771, 773. At least one of the first openings 726 is adjacent to and spaced apart from one of the second openings 728. The first openings 726 and the second openings 728 separate portions of the photoresist layers 772, 774, the second insulating layer 706, and the first and second nitride layers 771, 773, so that each is no longer continuous.

[0087] exist Figure 7C , the photoresist layers 772, 774 are removed, exposing the second nitride layer 773 and the top surface 775. Portions of the second insulating layer 706 are now also exposed where the second nitride layer 773 is not present. The exposed portion of the bottom surface 727 of the first insulating layer 705 that defines the first opening 726 is removed, for example, by etching or other suitable methods. Thereafter, the bottom surface 737 of the opening 726 is the top surface of the silicon layer 708.

[0088] In embodiments where the second insulating layer 706 is not present, the entire top surface of the first nitride layer 771 is now exposed.

[0089] In step 610, a third insulating layer 707 is formed on the SOI substrate and in the openings 726 and 728, see Fig.7D The third insulating layer 707 covers the second insulating layer 706 and coats the sidewalls of the first opening 726 and the sidewalls of the second opening 728, and the sidewalls of the first opening 726 and the sidewalls of the second opening 728 include the side surface of the first nitride layer 771, and the side surface of the first insulating layer 705 and the side surface of the second insulating layer 706. The bottom surface 737 of the first opening 726 and the bottom surface 729 of the second opening 728 also include the third insulating layer 707. However, because the first nitride layer 771 protects the second opening 728, the third insulating layer 707 is on the first nitride layer 771 at the bottom surface 729 of the second opening 728. The third insulating layer 707 can be made of the same material as the first insulating layer 705 or the second insulating layer 706, or other suitable insulating materials.

[0090] Forming the third insulating layer 707 includes growing the third insulating layer 707. In particular, the third insulating layer 707 is grown in the SOI substrate at the top surface 714 of the top silicon layer 708. The third insulating layer 707 is grown to form a convex edge at the bottom surface 737 of the opening 726. The third insulating layer 707 is grown and extends in all directions at the bottom surface 737 of the opening 726. The third insulating layer 707 protrudes into the top silicon layer 708, forming a convex edge below the top surface 714. The third insulating layer 707 located on the bottom surface 729 of the second opening 728 is not grown in this manner because the bottom surface is in the nitride layer 771.

[0091] A bending proof mass 776 is formed at the boundary between the third insulating layer and the silicon layer.The first opening and the second opening now have different shapes from each other.

[0092] In step 612, the third insulating layer 707 is removed. Fig. 7E As shown. This step includes forming or otherwise exposing a plurality of first openings 720 and a plurality of second openings 729. Removing the second insulating layer 706 and the third insulating layer 707 forms the shape and size of the plurality of first openings 720 and the plurality of second openings 729. In particular, removing the third insulating layer 707 removes a portion of the top silicon layer 708, wherein the third insulating layer 707 is grown at the bottom surface 737 of the opening 726. The curved proof mass 776 is removed, leaving a curved bottom 778. The edges 779a, 779b of the curved bottom 778, the outermost aspects of the opening 720 are wider than the sidewalls 780a, 780b. The sidewalls are substantially vertical or linear, while the bottom has a curved or rounded shape.

[0093] In other words, the first opening 720 has a rounded bottom or a lowered surface defined by the top silicon layer 708, wherein the rounded bottom surface is in the top silicon layer 708. Whereas the second opening 729 has a flat bottom surface defined by the top silicon layer 708. The second opening 729 does not substantially extend into the top silicon layer 708, whereas the first opening 720 extends into the top silicon layer 708.

[0094] Both the first opening 720 and the second opening 729 have substantially straight sidewalls defined by the first nitride layer 771. The side surfaces of the first insulating layer 705 define the substantially straight sidewalls of the second opening 729. The side surfaces of the first insulating layer 705 define the curved sidewalls of the first opening 730, wherein the curved sidewalls are below or under the substantially straight sidewalls. The bottom surface of the first nitride layer 771 also defines the curved sidewalls of the first opening 730.

[0095] Removing the second insulating layer 706 and the third insulating layer 707 exposes the first nitride layer 771. However, removing the second insulating layer 706 and the third insulating layer 707 does not remove part of the first nitride layer 771. In particular, the top surface and the side surface of the first nitride layer 771 are exposed. In addition, in the first opening 720, the bottom surface of the first nitride layer 771 is also exposed. The side surface of the first insulating layer 705 is also exposed in both the first opening 720 and the second opening 729.

[0096] Then, in Figure 7F In the embodiment, a fourth insulating layer 709 is formed on the SOI substrate. The fourth insulating layer 709 is on the first nitride layer 771, including the side surface of the first nitride layer 771. The openings 720 and 729 including the sidewalls and the bottom surface are coated and covered by the fourth insulating layer 709. The fourth insulating layer 709 has a uniform thickness as a whole and is made of the same material as the first insulating layer 705 or other suitable insulating materials. The first insulating layer 705 and the fourth insulating layer 709 are integrated.

[0097] Then, at step 614, a plurality of gates 730, 750 are formed in the openings 720, 729 by forming a conductive layer 703 in each of the openings and on the fourth insulating layer 709. This includes chemical mechanical polishing to remove excess portions of the conductive layer 703 so that the top surface of each gate 730, 750 is substantially coplanar. Then, phosphoric acid (H 3 PO 4 ), hydrofluoric acid (HF), or a combination thereof may be used to remove portions of the second insulating layer.

[0098] In some embodiments, silicon dioxide or silicon nitride deposition is followed by silicon dioxide or silicon nitride etching. The silicon dioxide or silicon nitride etching is followed by a gate reverse mask (gate last) step. The silicon dioxide or silicon nitride is then further removed. Gate oxide and polysilicon are then formed. CMP and phosphoric acid (HPO) may then be performed. 3 PO 4 ) step. Figure 7G In the embodiment, the conductive layer 703 may be a gate polysilicon material 703 deposited on the SOI substrate. The gate polysilicon material 703 overfills the first opening 720 and the second opening 729. The fourth insulating layer 709 including the top surface is covered by the gate polysilicon material 703. In particular, the gate polysilicon material 703 extends to cover the bottom surfaces of the openings 720, 729.

[0099] The CMP step removes excess gate polysilicon material 703. The CMP step exposes the top surface of the fourth insulating layer 709 and the top surface of the first nitride layer 771. The top surface of the first nitride layer 771 and the top surface of the fourth insulating layer 709 are coplanar with the top surface of the gates 730, 750.

[0100] In some embodiments, a portion of the first nitride layer 771 is not removed during the step of forming the gates 730, 750. In some embodiments, a portion of the fourth insulating layer 709 is not removed during the step of forming the gates 730, 750.

[0101] In other embodiments, the non-recessed gate 750 is not formed. In some embodiments, one or at least one recessed gate 730 is formed. In some embodiments, one or at least one non-recessed gate 750 is formed. The first insulating layer 705 and the fourth insulating layer 709 are integral with each other. The fourth insulating layer 709 protrudes laterally to the first insulating layer 705 along the sidewalls of the gates 730, 750.

[0102] The recessed gate 730 is formed to have a bottom buried portion 732 in the top silicon layer 708, which is integrated with an upper cap portion 740 on the buried portion 732. The recessed gate 730 has a bottom surface 734 of the buried portion 732, which is in the top silicon layer 708. The upper portion 740 has a substantially straight sidewall extending from the buried portion 732. The buried portion 732 protrudes laterally in the top surface 714 and protrudes longitudinally in and on the top surface 714. The buried portion 732 has a rounded rectangular shape with curved edges. The protrusion of the buried portion 732 has curved edges and has no straight edges. The top surface 742 of the recessed gate 730 belongs to the upper portion 740 and is substantially flat.

[0103] The first dimension of the recessed gate is the diameter in the second direction of the buried portion 732. The second dimension of the recessed gate is between the sidewalls of the upper portion 740. In this embodiment, the second dimension is greater than the first dimension.

[0104] In addition, the cap portion 740 extends in the first direction to a first distance, while the buried portion 732 extends in the first direction to a second distance. In this embodiment, the first distance is greater than the second distance. The cap portion 740 extends from the top of the gate to the top of the insulating layer 705. The buried portion 732 extends from the insulating layer to the bottom surface of the curved recess.

[0105] The non-recessed gate 750 is formed on the top silicon layer 708 and is not in the top silicon layer 708, unlike the recessed gate 730. In this embodiment, the non-recessed gate 750 is formed on the fourth insulating layer 709 on the top silicon layer 708. In addition, the non-recessed gate 750 has a square or rectangular shape, with a top surface 752 opposite to a bottom surface 754. A sidewall 756 of the non-recessed gate 750 extends between the top surface 752 and the bottom surface 754.

[0106] Non-recessed gate 750 extends in the first direction to a third dimension between top surface 752 and bottom surface 754. Recessed gate 730 extends in the first direction to a fourth dimension between top surface 742 and bottom surface 732. In this embodiment, the third dimension is less than the fourth dimension.

[0107] In this embodiment, the top surface 742 of the gate 730 is coplanar with the top surface 752 of the gate 750 .

[0108] To keep it simple, 7A to 7J Step 616, not shown in FIG. 6 , includes forming a lightly doped drain region. The lightly doped drain region may be formed before the conductive layer is formed.

[0109] exist Fig.7I In the step 618, a plurality of spacers 780 are formed on the SOI substrate adjacent to the gates 730 and 750. For simplicity, this is not shown in the figure. In step 620, contacts are formed on the SOI substrate adjacent to the gates 730 and 750.

[0110] exist Fig.7I, the first nitride layer 771 is removed, thereby exposing more surfaces of the first insulating layer 705 and the fourth insulating layer 709. In particular, the top surface of the first insulating layer 705 is now completely exposed. In addition, the side surfaces, and the additional top surface of the fourth insulating layer 709 are now exposed. The exposed top surface of the fourth insulating layer 709 is adjacent to and located on the buried portion 732 of the recessed gate 730. The exposed side surfaces of the fourth insulating layer 709 are adjacent to the sidewalls 746, 756 of the gates 730, 750.

[0111] In embodiments where the first insulating layer 705 and the fourth insulating layer 709 are not present, the top surface 714 of the top silicon layer 708 will be exposed.

[0112] In step 618, the adjacent Figure 7J A plurality of spacers 780 are formed on the gates 730, 750 in the top silicon layer 708. Each gate 730, 750 has a set of spacers 780 including two spacers 780. Each of the two spacers 780 is adjacent to the opposite sidewalls 746, 756 of the gates 730, 750. In addition, the corresponding spacers 780 are adjacent to and contact the sidewalls 746, 756. The spacers 780 are formed on the first insulating layer 705 and the fourth insulating layer 709 on the top silicon layer 708. The spacers 780 have edges that taper toward the top silicon layer 708. The top of the spacer 780 has a width in the second direction that is smaller than the bottom of the spacer 780. The spacers 780 are spaced apart from each other.

[0113] Figure 8 is a flowchart of the steps of a method for manufacturing a plurality of recessed and non-recessed gates 930, 950 according to another embodiment. 9A to 9H Detailed description in . First, in step 802, a first insulating layer 905 and a second insulating layer 906 and a first nitride layer 971 and a second nitride layer 973 are formed on a top silicon layer 908 of an SOI substrate. Next, in step 804, the second nitride layer 973 is patterned and etched using a first photoresist or resist layer 974, thereby forming a plurality of first recesses 929. Then, in step 806, the first nitride layer 971 is patterned and etched using a second photoresist or resist layer 972, thereby forming a plurality of second recesses 920. In step 808, a nitride pullback is performed on the first nitride layer 971, thereby changing the shape of the second recess 920. Then, in step 810, a plurality of recessed gates 930 and a plurality of non-recessed gates 950 are formed, wherein the recessed gates 930 are in the second recesses 920, and the non-recessed gates 950 are in the first recesses 929. Finally, in step 812 , a plurality of spacers 980 are formed adjacent to the gates 930 , 950 .

[0114] The SOI substrate includes a top silicon layer 908 on a buried oxide layer. The buried oxide layer is on a bottom silicon layer, neither of which is shown for simplicity. The top silicon layer 908 has a top surface 914 and opposite to the top surface 914 is a bottom surface contacting the buried oxide layer.

[0115] The top silicon layer 908 may have a thickness of about 60 nm from the bottom surface to the top surface 914. The buried oxide layer may be silicon dioxide. In some embodiments, the top silicon layer 908 and the bottom silicon layer may be made of the same material. In other embodiments, the top silicon layer 908 and the bottom silicon layer may be different materials. In this embodiment, the bottom silicon layer is bulk silicon.

[0116] In step 802, a first insulating layer or oxide layer 905 is formed on the SOI substrate. The first insulating layer 905 is continuous on the top surface 914 of the top silicon layer 908. The first insulating layer 905 includes silicon dioxide or other suitable insulating materials. The first insulating layer 905 has a uniform thickness throughout.

[0117] A first nitride layer 971 made of silicon nitride or other suitable material is formed on the first insulating layer 905. The first nitride layer 971 is continuous and substantially covers the top surface of the first insulating layer 905. The first nitride layer 971 has a uniform thickness throughout.

[0118] The second insulating layer 906 is formed on the first nitride layer 971. The second insulating layer 906 is continuous on the top surface of the first nitride layer 971. The second insulating layer 906 can be made of the same material as the first insulating layer 905, or made of another suitable insulating material. The second insulating layer 906 has a uniform thickness as a whole.

[0119] The second nitride layer 973 is formed on the first portion of the second insulating layer 906 and does not completely cover the top surface of the second insulating layer 906. The second portion of the second insulating layer 906 is not covered by the second nitride layer 973. The second nitride layer 973 can be made of the same material as the first nitride layer 971, or other suitable materials. The second nitride layer 973 has a uniform thickness as a whole.

[0120] At step 804, a first photoresist layer 974 is formed on the second nitride layer 973. Using a mask, the first photoresist layer 974 is used to pattern the second nitride layer 973. The second nitride layer 973 is etched to form Fig. 9AThe plurality of first recesses 929 are formed in the silicon layer 908. The plurality of first recesses 929 are formed by etching through the first photoresist layer 974, the second insulating layer 906, and the first nitride layer 971 and the second nitride layer 973. The etching stops at the first insulating layer 905. The plurality of first recesses 929 are formed by etching the top silicon layer 908. Each of the first recesses 929 is spaced apart from each other.

[0121] The formed first recess 929 includes a bottom surface 931 defined by the first insulating layer 905. The bottom surface 931 is not in the top silicon layer 908. In embodiments where the first insulating layer 905 is not present, the bottom surface 931 is defined by the top surface 914 of the top silicon layer 908.

[0122] The etching exposes the side surfaces of the first nitride layer 971 and the side surfaces of the second nitride layer 973, and the side surfaces of the first nitride layer 971 and the side surfaces of the second nitride layer 973 define the side walls of the first recess 929. The side surfaces of the second insulating layer 906 are also exposed due to the etching, and also define the side walls of the first recess 929. The exposed side surfaces of the first nitride layer 971 and the second nitride layer 973 are coplanar with the exposed side surfaces of the second insulating layer 906.

[0123] Due to etching, the first nitride layer 971 and the second nitride layer 973 and the first insulating layer 905 and the second insulating layer 906 are now discontinuous. Instead, recesses 920, 929 separate portions of the first nitride layer 971 and portions of the second insulating layer 906. The first recess 929 separates portions of the second nitride layer 973. The second recess 920 separates portions of the first insulating layer 905.

[0124] At step 806, a second photoresist layer 972 is formed on the first nitride layer 971. Using a mask, the second photoresist layer 972 is used to pattern the first nitride layer 971. The first nitride layer 971 is etched to form Fig. 9A The plurality of second recesses 920 are formed in the top silicon layer 908. Forming the plurality of second recesses 920 includes etching through the second photoresist layer 972, the first insulating layer 905 and the second insulating layer 906, the first nitride layer 971, and a portion of the top silicon layer 908. The etching is performed in the top surface 914 of the top silicon layer 908, and the etching stops in the top silicon layer 908. In particular, the etching stops before reaching the center of the top silicon layer 908.

[0125] In some embodiments, etching continues deeper into the top silicon layer 908. In other embodiments, etching stops closer to the top surface 914 of the top silicon layer 908.

[0126] The formed second recess 920 includes a bottom surface 924 defined by the top silicon layer 908. The second recess 920 does not extend beyond the top silicon layer 908. Furthermore, the second recess 920 does not extend to reach the buried oxide layer below the top silicon layer 908. The bottom surface 924 of the second recess 920 is in the top silicon layer 908.

[0127] The sidewalls of the second recesses include portions of the top silicon layer 908. Each of the second recesses 920 is spaced apart from each other.

[0128] The etching exposes the side surface of the first nitride layer 971, and the side surface of the first nitride layer 971 defines the side wall of the second recess 920. The side surface of the first insulating layer 905 and the side surface of the second insulating layer 906 are also exposed due to the etching, and also define the side wall of the second recess 920. The exposed side surface of the first nitride layer 971, the exposed side surface of the first insulating layer 905, the exposed side surface of the second insulating layer 906, and the exposed side surface of the exposed portion of the top silicon layer 908 are coplanar.

[0129] exist Fig. 9B , the first photoresist layer 974 and the second photoresist layer 972 are removed, thereby exposing a portion of the second insulating layer 906 and a portion of the second nitride layer 973. The top surface of the second insulating layer 906 is exposed where the second nitride layer 973 does not exist. In particular, the exposed top surface of the second insulating layer 906 is adjacent to the second recess 920. The top surface of the second nitride layer 973 is also exposed.

[0130] exist Fig. 9C In the embodiment, the exposed portion of the second insulating layer 906 and the exposed portion of the second nitride layer 973 are removed. The unexposed portion of the second insulating layer 906 covered by the second nitride layer 973 remains. The exposed portion of the second insulating layer 906 adjacent to the second recess 920 is removed.

[0131] In step 808, Fig. 9C In the embodiment of the present invention, a nitride pull-back is performed on the first nitride layer 971. In particular, lateral portions of the first nitride layer 971 in the recesses 920, 929 are removed. The width between the sidewalls of the first nitride layer 971 is thereby reduced.

[0132] For the second recesses 920, the bottom surface 924 is now below or under a larger or wider opening between the side surfaces of the first nitride layer 971. Between the bottom surface 924 and the larger opening are corners that have been formed by the top silicon layer 908 and portions of the first insulating layer 905. There are two opposing corners in each second recess 920. Furthermore, the corners protrude toward each other and face each other in the second recesses 920. These corners do not exist in the first recesses 929 because they do not include a recessed portion of the top silicon layer 908.

[0133] Sidewalls 922 defined by the top silicon layer 908 extend from a bottom surface 924 of the second recess to a top surface 914 of the top silicon layer 908. The sidewalls 922 are below or under the larger upper opening of the second recess 920. Between the sidewalls 922 is a first dimension, and between the side surfaces of the first nitride layer 971 in the second recess 920 is a second dimension. The first dimension is smaller than the second dimension.

[0134] In other embodiments, the first dimension is substantially similar to the second dimension. In other embodiments, the first dimension is greater than the second dimension.

[0135] Portions of the top surface of the first insulating layer 905 are now exposed. The exposed portions of the first insulating layer 905 are no longer covered by the first nitride layer 971. The exposed portions of the first insulating layer 908 extend outwardly into the first recess 929 and the second recess 920.

[0136] The second insulating layer 906 on the first nitride layer 971 is now exposed. In particular, the top surface of the second insulating layer 906 is exposed.

[0137] Then, in Fig.9D In the embodiment, the exposed portions of the second insulating layer 906 and the first insulating layer 905 in the recesses 929 and 920 are removed. The side surface of the first nitride layer 971 is coplanar with the side surface of the first insulating layer 905.

[0138] Portions of the top surface 914 of the top silicon layer 908 are no longer covered by the first insulating layer 905, thereby exposing portions of the top surface 914 in the second recess 920. The top surface of the corner 916 in the second recess 920 is now exposed, wherein the corner 916 is between the exposed top surface 914 and the sidewall 922.

[0139] The first recess 929 has a square or rectangular shape. The top surface 914 of the second silicon layer 908 defines the bottom of the second recess 929. The bottom surface 931 of the second recess 929 is the top surface 914 of the top silicon layer 908.

[0140] Then, in Fig.9E , a third insulating layer 907 is formed on the SOI substrate. The third insulating layer 907 is on the first nitride layer 971 and the top silicon layer 908. In particular, the third insulating layer 907 covers the exposed areas of the top silicon layer 908, including in the recesses 920, 929. The bottom surfaces 924, 931 of the recesses 920, 929 are covered by the third insulating layer 907. In the second recess 920, the sidewalls 922 and the corners 916 are also covered by the third insulating layer 907. In the first recess 929, the side surfaces of the first nitride layer 971 are coated with the third insulating layer 907. The top surface of the first nitride layer 971 is covered by the third insulating layer 907.

[0141] The third insulating layer 907 has a uniform thickness throughout and is continuous over the first nitride layer 971 and the top silicon layer 908 .

[0142] The side surface of the first insulating layer 905 contacts the third insulating layer 907. The first insulating layer 905 and the third insulating layer 907 are integrated.

[0143] The third insulating layer 907 may have the same material as the first insulating layer 905 or the second insulating layer 906, or other suitable materials. In other embodiments, the third insulating layer 907 does not exist.

[0144] Then, gate polysilicon material 903 is deposited on the SOI substrate. Gate polysilicon material 903 fills recesses 920, 929 and is on third insulating layer 907. Recesses 920, 929 are completely filled with gate polysilicon material 903, including covering bottom surfaces 924, 931. Gate polysilicon material 903 forms bottom surface 954 of non-recessed gate 950 and bottom surface 934 of recessed gate 930.

[0145] Furthermore, the gate polysilicon material 903 overfills the recesses 920 , 929 and contacts the third insulating layer 971 on the first nitride layer 971 .

[0146] In other embodiments, the gate polysilicon material 903 partially fills the recesses 920 , 929 .

[0147] In other embodiments, the gate polysilicon material 903 does not overfill the recesses 920 , 929 and does not contact the third insulating layer 971 on the first nitride layer 971 .

[0148] At step 810, a plurality of recessed gates 930 and a plurality of non-recessed gates 950 are formed. Fig.9F In the process, chemical mechanical polishing (CMP) is performed to remove excess portions of the gate polysilicon material 903, thereby defining gates 930, 950.

[0149] In other embodiments, forming the gates 930 , 950 includes removing excess gate polysilicon material 903 via a suitable method other than CMP.

[0150] Portions of the third insulating layer 907 are also removed. The removed portions of the third insulating layer 907 include portions on the first nitride layer 971. In some embodiments, the removed portions of the third insulating layer 907 include portions adjacent to the recesses 920,929.

[0151] In some embodiments, a portion of the first nitride layer 971 is removed. The removed portion of the first nitride layer 971 includes a top surface.

[0152] The top surface 942 of the recessed gate 930 is coplanar with the top surface 952 of the non-recessed gate 950. The top surface 942 of the recessed gate 930 is the upper portion 940. The gates 930, 950 are separated by a first nitride layer 971. The exposed top surface of the first nitride layer 971 is coplanar with the top surfaces 942, 952 of the gates 930, 950.

[0153] A portion of the third insulating layer 907 is between the gates 930, 950 and the first nitride layer 971. An exposed top surface of the third insulating layer 907 is coplanar with top surfaces 942, 952 of the gates 930, 950.

[0154] The recessed gates 930 are formed in the second recessed portion 920, wherein each recessed gate 930 is in a corresponding recessed portion 920. The recessed gates 930 are adjacent to each other and spaced apart.

[0155] The non-recessed gates 950 are formed in the first recess 929. The non-recessed gates 950 are adjacent to each other and spaced apart.

[0156] In other embodiments, only one or at least one recessed gate 930 is formed. In other embodiments, only one or at least one non-recessed gate 950 is formed. In other embodiments, no non-recessed gate 950 is formed.

[0157] Then, in Figure 9G In the embodiment of the present invention, the first nitride layer 971 is removed. The side surface of the third insulating layer 907 is exposed. The top surface of the first insulating layer 905 is also exposed.

[0158] In other embodiments, the top surface 914 of the top silicon layer 908 is exposed instead of the first layer 905. In some embodiments, the side surfaces of the gates 930, 950 are exposed instead of the third insulating layer 907.

[0159] In step 812, adjacent Figure 9H The gate electrodes 930 and 950 are connected to each other to form a plurality of spacers 980. The spacers 980 are formed on the first insulating layer 905 and contact the third insulating layer 907.

[0160] In other embodiments where the first insulating layer 905 is not present, the spacers 980 are formed on the top silicon layer 908 .

[0161] Figure 9H is a device 900 according to one embodiment.

[0162] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide further embodiments.

[0163] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted as including all possible embodiments and the full range of equivalents to which these claims are entitled. Therefore, the claims are not limited by this disclosure.

Claims

1. A device comprising: A silicon-on-insulator (SOI) substrate, the SOI substrate comprising: a first silicon layer and a second silicon layer, the first silicon layer having a first surface; a first insulating layer, the first insulating layer being between the first silicon layer and the second silicon layer; and a recess in the first surface of the first silicon layer; a second insulating layer on the first surface of the first silicon layer and in the recess; and A first gate is on the second insulating layer, the first gate has a first gate portion and a second gate portion, the first gate portion is in the recess, the second gate portion is on the first gate portion, and the second gate portion has a different size from the first gate portion in a first direction. 2 . The device according to claim 1 , wherein the recess comprises a sidewall extending from the first surface of the first silicon layer to a second surface in the recess, and the second insulating layer is on the sidewall and the second surface in the recess. 3 . The device of claim 2 , wherein the first gate portion has a first dimension between the sidewalls of the recess, and the second gate portion has a second dimension between a first edge and a second edge, the first dimension being smaller than the second dimension.

4. The device of claim 2, wherein the first gate portion has a first dimension between the sidewalls of the recess, and the second gate portion has a second dimension between a first edge and a second edge, the first dimension being substantially equal to the second dimension. The device according to claim 1 , wherein the recessed portion is bent from a first side to an opposite second side. 6 . The device of claim 5 , wherein the first gate portion has a first dimension between the first side and the second side, and the second gate portion has a second dimension between the first side and the second side, the first dimension being greater than the second dimension. The device of claim 6 , the first gate portion extending beyond the first surface of the first silicon layer. 8 . The device of claim 7 , wherein the second insulating layer is between the first silicon layer and the first gate portion extending beyond the first surface of the first silicon layer.

9. A method comprising: forming a recess in a first surface of a first silicon layer of a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a first insulating layer and a second silicon layer, the first insulating layer being between the first silicon layer and the second silicon layer; forming a second insulating layer on the first surface of the first silicon layer and in the recess; as well as A first gate is formed on the second insulating layer, the first gate having a first gate portion and a second gate portion, the first gate portion being in the recess, the second gate portion having a first end, the first end being on the first gate portion, the second gate portion having a second end, the second end being opposite to a third end, the third end being transverse to the first end.

10. The method according to claim 9, comprising: forming a third insulating layer on the first silicon layer; as well as A first nitride layer is formed on the first surface of the first silicon layer, wherein forming the recess includes etching through the first nitride layer and the third insulating layer.

11. The method according to claim 10, comprising: After forming the second insulating layer and before forming the first gate: forming a second nitride layer on the first nitride layer; as well as The first nitride layer and the second nitride layer are removed.

12. The method according to claim 10, comprising: After forming the recess and before forming the second insulating layer, a portion of the first nitride layer is removed via a nitride pull back.

13. The method according to claim 12, wherein forming the first gate comprises: forming a first conductive layer on the second insulating layer; as well as A portion of the first conductive layer and a portion of the second insulating layer are removed via chemical mechanical polishing (CMP), wherein the portion of the second insulating layer is on the first nitride layer.

14. The method according to claim 13, wherein: After removing a portion of the first conductive layer and a portion of the second insulating layer, a surface of the first gate is coplanar with a surface of the first nitride layer, the first surface of the first gate is opposite to the recess, and the first surface of the first nitride layer is opposite to the first surface of the first silicon layer.

15. The method of claim 14, wherein the first gate portion has a first dimension between sidewalls of the recess, the second gate portion has a second dimension between the second end and the third end, and the first dimension of the first gate portion is smaller than the second dimension of the second gate portion.

16. The method of claim 9, wherein forming the recess comprises: forming a third insulating layer on the first surface of the first silicon layer, the third insulating layer having a nitride layer, wherein forming the third insulating layer comprises: growing the third insulating layer in the concave portion; and The third insulating layer is removed, the recess is bent from a first end to an opposite second end, the first end and the second end extend to the first surface of the first silicon layer, and the nitride layer extends over a portion of the recess.

17. The method according to claim 16, wherein forming the second insulating layer comprises: is formed on the nitride layer.

18. A device comprising: A substrate having a surface, the substrate comprising: A first silicon layer, the surface having the first silicon layer; buried oxide layer; a second silicon layer, the buried oxide layer being on the second silicon layer, and the first silicon layer being on the buried oxide layer, the substrate being a silicon-on-insulator (SOI) substrate; and a curved recess in said surface; a recessed gate having a curved portion in the curved recess and a central portion on the curved portion, the curved portion extending in a first direction to the central portion; and A first oxide layer is provided between the recessed gate and the substrate, the first oxide layer extending on the surface of the substrate and in the curved recess. 19 . The device of claim 18 , wherein the central portion of the recessed gate has a first dimension in the first direction, and the curved portion has a second dimension in the first direction, the second dimension being smaller than the first dimension.

20. The device of claim 19, wherein the central portion of the recessed gate has a third dimension in a second direction, the second direction being transverse to the first direction, and the curved portion has a fourth dimension in the second direction, the fourth dimension being greater than the third dimension.

21. The device of claim 18, wherein the curved portion of the recessed gate has a convex surface in the substrate.

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