Image sensor manufacturing method
By forming a supplementary oxide layer in the PD region before multi-crystalline silicon etching, the method addresses surface damage and plasma interference, significantly improving image sensor performance by reducing dark current and enhancing pixel quality.
Patent Information
- Application Number
- CN202311234811.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-22
- Publication Date
- 2025-03-28
AI Technical Summary
In the manufacturing of CMOS image sensors, the PD region is prone to surface damage during the multi-crystalline silicon etching process, leading to increased plasma interference and dark current, which negatively impacts image quality, especially in low-light environments for large-pixel sensors.
The method involves forming a supplementary oxide layer in the PD region before multi-crystalline silicon etching, allowing for a blanket etch without a mask and reducing plasma interference, thereby minimizing surface damage and dark current.
This approach effectively reduces dark current by up to 25% and enhances pixel performance by forming a thicker oxide layer to protect the PD region during etching.
Smart Images
Figure CN119730423A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to semiconductor manufacturing technology, and in particular to an image sensor manufacturing method. Background Art
[0002] Common Fab (fabrication, chip manufacturing plant) mass-produced small pixel image sensors such as Figure 1 As shown in the figure, during polysilicon etching (Poly Etch), the logic circuit (Logical) area is etched together with the pixel (Pixel) area, but in order to improve the afterimage (Lag) performance of the large pixel PD (Photo-Diode) area (Area), the subsequent N-type implantation is shallow, and the FWC (full well capacity) mainly relies on the shallow N-type implantation in the PD (Photo-Diode) area, requiring the etching damage on the surface of the PD (Photo-Diode) area to be as small as possible.
[0003] In the prior art, the method for forming a CMOS image sensor is as follows: providing a device wafer, which is divided into a logic area and a pixel area, the logic area and the pixel area are separated by a shallow trench isolation structure, the logic area includes a photoelectric conversion area and a pixel transistor area, and the photoelectric conversion area and the pixel transistor area are adjacent. Then, a gate is formed on the logic area and the pixel area respectively, and the gate of the pixel area is located on the pixel transistor area. Then, a first sidewall is formed on both sides of the gate of the logic area and the pixel area, the first sidewall of the pixel area is located in the pixel transistor area, a dielectric layer is formed on the first sidewall, the dielectric layer just covers the first sidewall, and a second sidewall is formed on the dielectric layer, the second sidewall just covers the dielectric layer. However, the method for forming the second sidewall is to first form a silicon nitride layer to cover the upper surface of the dielectric layer and the first gate and the surface of the device wafer between the first gate and the second gate, and then etch a portion of the silicon nitride layer to form a second sidewall that just covers the dielectric layer, and the second sidewall does not cover the surface of the device wafer of the photoelectric conversion area.
[0004] In the existing method of forming CMOS image sensors, during the manufacturing process of CMOS image sensors, when etching the silicon nitride layer, the entire device wafer is etched, which will cause damage to the surface of the device wafer in the PD (Photo-Diode, photoelectric conversion) area. For large-pixel CMOS (Pixel size>5um) image sensors, since the N-type implantation in the PD (Photo-Diode, photoelectric conversion) area is relatively shallow, the etching area is relatively larger during the polysilicon etching (Poly Etch) process, and the surface etching damage has a more serious impact. During the polysilicon etching (Poly Etch), the device wafer surface in the PD (Photo-Diode, photoelectric conversion) area is subject to a high degree of ion (plasma) interference, which in turn generates dark current. In the absence of light, dark current caused by non-light will also be generated in the sensor, affecting the performance of the pixel area. For large-pixel security products, in low-light environments, due to the small photocurrent, the dark current has a fatal impact on the imaging quality.
[0005] More importantly, in the current CMOS process, the oxide layer formed in the PD region before polysilicon (Poly) is generated is very shallow, and the DG (Dual gate) process can only bring The surface oxide layer on the left and right is not enough to block the polysilicon during etching. Summary of the invention
[0006] The technical problem to be solved by the present invention is to provide an image sensor manufacturing method, in which the surface of the PD area can be etched without a mask (blanket etch) during subsequent DG-ET (dual gate etching) and polysilicon etching, and surface damage (damage) caused during etching can be avoided, ion (plasma) interference can be reduced, and ultimately the pixel dark current (Dark current) can be reduced, thereby improving pixel performance.
[0007] In order to solve the above technical problems, the present invention provides an image sensor manufacturing method, which comprises the following steps:
[0008] S1. A shallow trench isolation 101 is formed on the substrate 100, and the shallow trench isolation isolates the substrate into a pixel area 102 and a logic area 103;
[0009] S2. Perform a well process to form a well 111 in the photoelectric conversion region and a well 112 in the pixel region, and a well 113 in the logic region 103 to form a logic transistor region;
[0010] S3. Growing a supplementary oxide layer 114 on the surface of the wafer;
[0011] S4. Covering the first photoresist 115 on the wafer surface;
[0012] S5. Photolithography, removing the first photoresist 115 on the wafer surface outside the photoelectric conversion region, retaining the first photoresist 115 on the wafer surface in the photoelectric conversion region;
[0013] S6. Etching and removing the supplementary oxide layer 114 on the surface of the wafer outside the photoelectric conversion region, and then removing the first photoresist 115;
[0014] S7. Forming a first gate oxide layer 116 on the surface of the wafer;
[0015] S8. Covering the wafer surface with a second photoresist 117;
[0016] S9. Photolithography, removing the second photoresist 117 on the wafer surface of the logic area 103, and retaining the second photoresist 117 on the wafer surface of the pixel area 102;
[0017] S10. Etching to remove the first gate oxide layer 116 on the wafer surface of the logic area 103, retaining the first gate oxide layer 116 on the wafer surface of the pixel area 102, and then removing the second photoresist 117;
[0018] S11. Forming a second gate oxide layer 118 on the surface of the wafer;
[0019] S12. Polysilicon 119 is deposited on the upper surface of the second gate oxide layer 118;
[0020] S13. Perform subsequent processes.
[0021] Preferably, in step S3, the supplementary oxide layer 114 is a high temperature oxide film grown on the surface of the wafer using a furnace process.
[0022] Preferably, the high temperature oxide film is obtained by reacting SiH4 and H2O at 750°C to 850°C.
[0023] Preferably, the thickness of the supplementary oxide layer 114 is
[0024] Preferably, the thickness of the first gate oxide layer 116 is
[0025] Preferably, the subsequent process includes:
[0026] S131. Forming a polysilicon hard mask layer 120;
[0027] S132. Photolithography and etching are performed to remove the polysilicon 119 and the polysilicon hard mask layer 120 on the wafer surface in the middle of the well 113 in the logic transistor area, the photoelectric conversion area and the shallow trench isolation, and the polysilicon 119 and the polysilicon hard mask layer 120 on the wafer surface in the left and right parts of the well 113 in the logic transistor area and the well 112 in the pixel transistor area are retained.
[0028] Preferably, the polysilicon hard mask layer 120 is SIN-SIO2-SIN from bottom to top.
[0029] Preferably, the pixel unit size of the image sensor is larger than 5 um.
[0030] The image sensor manufacturing method of the present invention adds an additional supplementary oxide layer 114 before the gate oxide layer of the PD region of the pixel unit is formed, adds a first photoresist (COX1 photoresist) and uses photolithography to define the non-pixel unit PD region, etches and removes the supplementary oxide layer 114 on the surface of the wafer outside the PD region, retains the supplementary oxide layer 114 in the PD region, and can form a thicker oxide layer in the PD region before polysilicon (Poly) is generated. During the subsequent DG-ET (double gate etching) and polysilicon etching (Poly Etch), the surface of the PD region can be etched without a mask (blanket etch) and surface damage (damage) can be avoided during etching, reducing ion (plasma) interference, and finally reducing the pixel dark current (Dark current) and improving the pixel performance. The image sensor manufacturing method can be completed using existing equipment, is an optimization of existing mature processes, is simple and easy to implement, significantly improves the dark current, and has little side effect (side effect). BRIEF DESCRIPTION OF THE DRAWINGS
[0031] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0032] Figure 1 Schematic diagram of STI formation according to an embodiment of a method for manufacturing an image sensor of the present invention;
[0033] Figure 2 1 is a schematic diagram showing the completion of a well process according to an embodiment of a method for manufacturing an image sensor according to the present invention;
[0034] Figure 3 It is a schematic diagram of growing a supplementary oxide layer according to an embodiment of a method for manufacturing an image sensor according to the present invention;
[0035] Figure 4 Schematic diagram of the first photoresist of photolithography according to an embodiment of the method for manufacturing an image sensor of the present invention;
[0036] Figure 5 It is a schematic diagram of etching and removing the supplementary oxide layer on the surface of the wafer outside the PD area in one embodiment of the method for manufacturing an image sensor according to the present invention;
[0037] Figure 6 It is a schematic diagram of forming a first gate oxide layer on the surface of a wafer according to an embodiment of a method for manufacturing an image sensor of the present invention;
[0038] Figure 7 It is a schematic diagram of removing the second photoresist on the wafer surface of the logic area by photolithography according to an embodiment of the method for manufacturing an image sensor of the present invention;
[0039] Figure 8 It is a schematic diagram of etching and removing the first gate oxide layer on the surface of the wafer in the logic area according to an embodiment of the method for manufacturing an image sensor of the present invention;
[0040] Fig. 9 It is a schematic diagram of forming a second gate oxide layer on the surface of a wafer according to an embodiment of a method for manufacturing an image sensor of the present invention;
[0041] Fig.10 Schematic diagram of depositing polysilicon in an embodiment of a method for manufacturing an image sensor according to the present invention;
[0042] Fig.11 It is a schematic diagram of forming a polysilicon hard mask layer according to an embodiment of a method for manufacturing an image sensor of the present invention;
[0043] Fig.12 It is a DG (Dual gate) photolithography schematic diagram of an embodiment of the image sensor manufacturing method of the present invention;
[0044] Fig.13 It is a schematic diagram of DG (Dual gate) etching according to an embodiment of the method for manufacturing an image sensor of the present invention. DETAILED DESCRIPTION
[0045] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0046] The words "first", "second" and similar terms used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprises" and similar terms mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative position relationships. When the absolute position of the object being described changes, the relative position relationship may also change accordingly.
[0047] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.
[0048] Embodiment 1
[0049] like Figures 1 to 13 As shown, a method for manufacturing an image sensor includes the following steps:
[0050] S1. A STI (shallow trench isolation) 101 is formed on a substrate 100. The STI isolates the substrate into a pixel region 102 and a logic region 103. Figure 1 As shown;
[0051] S2. Perform a well process to form a well 111 in the photoelectric conversion area and a well 112 in the pixel area, and a well 113 in the logic transistor area in the logic area 103. Figure 2 As shown;
[0052] S3. Growing a supplementary oxide layer 114 on the surface of the wafer, such as Figure 3 As shown;
[0053] S4. Covering the surface of the wafer with a first photoresist (COX1 photoresist) 115;
[0054] S5. Photolithography, removing the first photoresist (COX1 photoresist) 115 on the surface of the wafer outside the PD area, retaining the first photoresist (COX1 photoresist) 115 on the surface of the wafer in the PD area, such as Figure 4 As shown;
[0055] S6. Etching and removing the supplementary oxide layer 114 on the surface of the wafer outside the PD region, and then removing the first photoresist (COX1 photoresist) 115, such as Figure 5 As shown;
[0056] S7. Form a first gate oxide layer 116 on the surface of the wafer, such as Figure 6 As shown;
[0057] S8. Covering the surface of the wafer with a second photoresist (DG photoresist) 117;
[0058] S9. Photolithography, removing the second photoresist (DG photoresist) 117 on the wafer surface of the logic area 103, and retaining the second photoresist (DG photoresist) 117 on the wafer surface of the pixel area 102, such as Figure 7 As shown;
[0059] S10. Etching, removing the first gate oxide layer 116 on the wafer surface of the logic area 103, retaining the first gate oxide layer 116 on the wafer surface of the pixel area 102, and then removing the second photoresist (DG photoresist) 117, such as Figure 8 As shown;
[0060] S11. Form a second gate oxide layer 118 on the surface of the wafer, such as Fig. 9 As shown;
[0061] S12. Polysilicon 119 is deposited on the upper surface of the second gate oxide layer 118, such as Fig.10 As shown;
[0062] S13. Perform subsequent processes.
[0063] The image sensor manufacturing method of the first embodiment adds an additional supplementary oxide layer 114 before the gate oxide layer of the PD region of the pixel unit is formed, adds a first photoresist (COX1 photoresist) and uses photolithography to define the non-pixel unit PD region, etches and removes the supplementary oxide layer 114 on the surface of the wafer outside the PD region, retains the supplementary oxide layer 114 in the PD region, and forms a thicker oxide layer in the PD region before polysilicon (Poly) is generated. During the subsequent DG-ET (double gate etching) and polysilicon etching (Poly Etch), the surface of the PD region can be etched without a mask (blanket etch) and surface damage (damage) can be avoided during etching, plasma interference can be reduced, and finally the pixel dark current (Dark current) can be reduced (it is expected that the dark current can be reduced by 25%), thereby improving the pixel performance. The image sensor manufacturing method can be completed using existing equipment, is an optimization of the existing mature process, is simple and easy to implement, significantly improves the dark current, and has little side effect.
[0064] Embodiment 2
[0065] Based on the method for manufacturing an image sensor in the first embodiment, in step S3, the supplementary oxide layer 114 is a high temperature oxide film (HTO) grown on the surface of a wafer using a furnace process.
[0066] Preferably, the high temperature oxide film (HTO) is silicon dioxide (SiO2) or silicon tetroxide (SiO4) obtained by reacting silane (SiH4) and H2O at 750°C to 850°C (eg, 850°C).
[0067] Preferably, the thickness of the supplementary oxide layer 114 is (For example, ).
[0068] Preferably, the thickness of the first gate oxide layer 116 is (For example, ).
[0069] The method for manufacturing an image sensor in the second embodiment retains the high temperature oxide film (HTO) in the PD region, and then continues to grow about 1000 nm at the interface between the high temperature oxide film (HTO) and silicon. The gate oxide layer increases the thickness of the oxide layer on the entire PD area to about It forms an effective barrier for the PD region during the subsequent polysilicon etching (PolyEtch).
[0070] Embodiment 3
[0071] Based on the image sensor manufacturing method of embodiment 1, the subsequent process includes:
[0072] S131. Forming a polysilicon hard mask layer 120, such as Fig.11 As shown;
[0073] S132. Photolithography, such as Fig.12 , Fig.13 As shown, the polysilicon 119 and the polysilicon hard mask layer 120 on the wafer surface in the middle of the well 113 in the logic transistor area, the photoelectric conversion (PD) area and the shallow trench isolation (STI) are removed, and the polysilicon 119 and the polysilicon hard mask layer 120 on the wafer surface in the left and right parts of the well 113 in the logic transistor area and the well 112 in the pixel transistor area are retained.
[0074] Preferably, the polysilicon hard mask layer 120 is SIN-SIO2-SIN from bottom to top.
[0075] Preferably, the image sensor is a CMOS image sensor with a pixel size greater than 5 um.
[0076] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.
Claims
1. A method for manufacturing an image sensor, characterized in that: The following steps are involved: S1. A shallow trench isolation (101) is formed on a substrate (100), wherein the shallow trench isolation isolates the substrate into a pixel region (102) and a logic region (103); S2. Performing a well process to form a well (111) of the photoelectric conversion region and a well (112) of the pixel transistor region in the pixel region, and forming a well (113) of the logic transistor region in the logic region (103); S3. Growing a supplementary oxide layer (114) on the surface of the wafer; S4. Covering the surface of the wafer with a first photoresist (115); S5. Photolithography, removing the first photoresist (115) on the surface of the wafer outside the photoelectric conversion region, and retaining the first photoresist (115) on the surface of the wafer in the photoelectric conversion region; S6. Etching and removing the supplementary oxide layer (114) on the surface of the wafer outside the photoelectric conversion region, and then removing the first photoresist (115); S7. forming a first gate oxide layer (116) on the surface of the wafer; S8. Covering the wafer surface with a second photoresist (117); S9. Photolithography, removing the second photoresist (117) on the wafer surface of the logic area (103), and retaining the second photoresist (117) on the wafer surface of the pixel area (102); S10. Etching to remove the first gate oxide layer (116) on the wafer surface of the logic area (103), retaining the first gate oxide layer (116) on the wafer surface of the pixel area (102), and then removing the second photoresist (117); S11. forming a second gate oxide layer (118) on the surface of the wafer; S12. depositing polysilicon (119) on the upper surface of the second gate oxide layer (118); S13. Perform subsequent processes.
2. The method for manufacturing an image sensor according to claim 1, characterized in that: In step S3, the supplementary oxide layer (114) is a high temperature oxide film grown on the surface of the wafer using a furnace tube process.
3. The method for manufacturing an image sensor according to claim 2, characterized in that: The high temperature oxide film is obtained by the reaction of SiH4 and H2O at 750°C to 850°C.
4. The method for manufacturing an image sensor according to claim 1, characterized in that: The thickness of the supplementary oxide layer (114) is 5. The method for manufacturing an image sensor according to claim 4, characterized in that: The thickness of the first gate oxide layer (116) is 6. The method for manufacturing an image sensor according to claim 1, characterized in that: The subsequent process includes: S131. Forming a polysilicon hard mask layer (120); S132. Photolithography and etching are performed to remove the polysilicon (119) and the polysilicon hard mask layer (120) on the wafer surface in the middle of the well (113) in the logic transistor region, the photoelectric conversion region and the shallow trench isolation, and the polysilicon (119) and the polysilicon hard mask layer (120) on the wafer surface in the left and right parts of the well (113) in the logic transistor region and the well (112) in the pixel transistor region.
7. The method for manufacturing an image sensor according to claim 6, characterized in that: The polysilicon hard mask layer (120) is sequentially SIN-SIO2-SIN from bottom to top.
8. The method for manufacturing an image sensor according to claim 6, characterized in that: The pixel unit size of the image sensor is greater than 5um.