Method for producing microelectromechanical structure

Abstract

A method for manufacturing a microelectromechanical structure comprises providing a carrier substrate (110) having a central layer (140) and a surface and an insulating layer (122) arranged on one side of the central layer and applied on the surface; applying a silicon layer (150a) on the insulating layer; structuring the silicon layer to form a trench (156) extending locally through the silicon layer; passivating the silicon layer wherein the trench is filled and a passivation layer is formed (154); the passivation layer is structured, a sacrificial region (153) and a functional region (152) are formed, and the sacrificial region is locally free of the passivation layer; a portion of the carrier substrate (110) is removed to form a new surface, and a second insulating layer (172) is formed on the new surface. Then, repeated application, structuring and passivation are performed on the second insulating layer for the second silicon layer (180a) and the structuring is repeated for the second passivation layer (184) to form sacrificial regions and functional regions, and all of the sacrificial regions are removed.

Description

Technical Field

[0001] The present invention relates to the field of micro-electromechanical devices and to a method for manufacturing a micro-electromechanical structure. In addition, the present invention also relates to a micro-electromechanical device. Background Art

[0002] DE 10 2006 032 195 A1 describes a method for manufacturing a MEMS structure. DE 10 2009 029 202 A1 discloses a micromechanical system and a method for manufacturing the micromechanical system. DE 10 2015 206 996 A1 discloses a so-called EPyC process (EPyC: epitaxial polysilicon cycle) for manufacturing microelectromechanical structures with a large vertical extension, which uses epitaxial polysilicon as a functional material and a sacrificial material and builds a layer structure of epitaxial polysilicon layers through repeated cycles. Summary of the invention

[0003] According to the invention, a method for producing a microelectromechanical structure and a device having such a microelectromechanical structure are provided.

[0004] According to a first aspect of the present invention, a method for manufacturing a microelectromechanical structure is proposed, the structure being, for example, a structure for a microelectromechanical device, the device being, for example, a device comprising a MEMS (microelectromechanical system). In this case, the method comprises providing a first carrier substrate, which is, for example, at least substantially composed of silicon, the first carrier substrate having one or more core layers. The one or more core layers are preferably one or more single-crystal silicon layers, which preferably have a layer thickness of 0.1 μm to 10.0 μm. Such a single-crystal silicon layer also preferably has a doping, which is preferably designed so that the resistivity of the doped silicon at 20° C. is in the range of 1 mΩ·cm to 5 mΩ·cm. It is also possible to use multiple layers comprising different materials as core layers. The one or more core layers may be structured, for example, with notches and / or gaps, and / or may be structured, for example by an etching process. Thus, electrical connection and insulation can be achieved between these core layers and specific areas of the silicon layer to be applied. For example, structuring can be carried out before carrying out the subsequent steps and / or after partial removal of the first carrier substrate and / or, if the material of the core layer to be structured is suitable, it can also be carried out by a subsequent etching process, for example by a subsequent silicon sacrificial layer etching. In particular, it is also conceivable to directly provide a first carrier substrate with one or more structured core layers. Here, a first insulating layer is formed on the surface of the first carrier substrate, wherein the first insulating layer is arranged on a first side of the one or more core layers and the first insulating layer itself is not part of the first carrier substrate. Such an insulating layer serves for electrical insulation and mechanical insulation / isolation between the substrate and the silicon layer of the subsequent first EPyC cycle. Preferably, the surface of the first carrier substrate is realized by the surface of one of the one or more core layers.

[0005] The first insulating layer is preferably a silicon oxide and / or silicon nitride layer. The first insulating layer is preferably used as an etching stop layer for the subsequent etching of the silicon sacrificial layer. By using such an etching stop layer, complex and highly fluctuating, time-dependent etching processes can be avoided. In particular, in order to establish an electrical connection through the insulating layer, the insulating layer can be structured and / or can be structured before performing further steps.

[0006] A first silicon layer is applied to the first insulating layer, for example by bonding, sputtering and / or preferably by growth, in particular epitaxial growth. Here, the epitaxial growth is carried out in particular at a temperature generally greater than 600° C., preferably greater than 900° C. The structuring of the first insulating layer can be carried out before the growth of the first silicon layer and / or after the removal of the first carrier substrate, i.e. from the opposite side. The applied first silicon layer can, for example, include or be a single crystal silicon layer, a polycrystalline silicon layer and / or an epitaxial polycrystalline silicon layer. Here, an epitaxial polycrystalline silicon layer refers to a polycrystalline silicon layer grown epitaxially, i.e. under epitaxial growth conditions. Such an epitaxial polycrystalline silicon layer usually has a thickness greater than 5 μm, usually also several tens of μm.

[0007] Epitaxial growth on a first insulating layer (e.g., a silicon oxide layer) may include applying a polysilicon start layer on the insulating layer in advance, which is performed, for example, by CVD polysilicon deposition (CVD: chemical vapour deposition), because polysilicon (polycrystalline silicon) cannot usually be grown epitaxially directly on the insulating layer. This also applies to the second insulating layer and passivation layer discussed below. Areas not covered by the insulating layer or passivation layer can be filled by CVD polysilicon deposition, thereby establishing electrical contact with the silicon layer to be grown subsequently. That is, a wiring layer is formed. However, direct epitaxy without a polysilicon start layer can also be achieved by selecting a process control method that automatically forms crystallization nuclei. In the scope of the present application, the term "epitaxial growth" refers to two possible variants, namely indirect epitaxial growth with the use of a start layer that is to be at least partially applied in advance and direct epitaxial growth without a start layer.

[0008] Here, the first carrier substrate with a silicon layer applied on a first insulating layer and with a desired core layer can also be provided directly in the form of a raw silicon wafer, such as an SOI silicon wafer (SOI: Silicon-on-Insulator). The layer thickness of the first silicon layer and the applied further silicon layers can be, for example, 0.5 μm to 100 μm, preferably 20 μm to 60 μm.

[0009] The first silicon layer is structured for forming a trench in the first silicon layer, wherein the trench at least partially extends through the first silicon layer. This structuring can be performed, for example, by reactive ion etching (RIE) and / or deep reactive-ion etching (DRIE) and / or, in particular in the case of relatively thin silicon layers, by a plasma etching process.

[0010] The first silicon layer is then passivated, wherein the trench is filled and a first passivation layer is formed on the side of the first silicon layer facing away from the first insulating layer. The trench is filled by forming the first passivation layer in the trench. The passivation layer preferably covers substantially the entire surface of the first silicon layer including the trench. For passivation, methods such as thermal oxidation and / or tetraethyl orthosilicate deposition (TEOS deposition), silicon carbide deposition (SiC deposition), silicon carbonitride deposition (SiCN deposition), silicon nitride deposition (SiCN deposition), etc. can be used. x N y The invention relates to a passivation technique of silicon oxide deposition (SiON deposition) or silicon oxynitride deposition (SiON deposition). The areas of the silicon layer that should not be etched are protected from etching by the passivation layer. The areas of the silicon layer that can contact the etching medium used for etching (sacrificial areas) can be completely etched. The passivation layer can therefore serve as a lateral and vertical etching stop, i.e. it can have the same function as an insulating layer in this respect. Depending on the passivation technique used, the passivation layer can be composed of different materials, such as silicon oxide and / or silicon nitride. In the process for oxide etching, the part of the passivation layer composed of silicon nitride, for example, can be retained, which can then be used for electrical insulation during the operation of the layer system produced by this method.

[0011] The first passivation layer formed in this way is structured, wherein due to the structuring a first sacrificial region and a first functional region are formed in the first silicon layer and the first sacrificial region is at least partially free of the first passivation layer on a side of the first silicon layer facing away from the first insulation layer.

[0012] A portion of the first carrier substrate is then removed. This is done in such a way that a new surface of the first carrier substrate is formed on the second side of the one or more core layers, wherein none of the one or more core layers is removed. For example, the carrier substrate can be stripped down to the first exposed core layer. In this case, this exposed first core layer can be structured particularly easily, for example by a suitable etching process, for example for making electrical connections. Finally, a second insulating layer is formed on the new surface thus created. Optionally, the second insulating layer can be structured like the first insulating layer, in particular in order to achieve an electrical connection through the second insulating layer. That is, in order to establish an electrical connection, it would be advantageous if the first and / or second insulating layer is structured and / or that the first and / or second insulating layer is structured. It can also be advantageous if the one or more core layers are structured and / or that they are structured.

[0013] The above-mentioned steps of epitaxial application, structuring and passivation are then repeated, this time for the second silicon layer and the second insulating layer instead of the first silicon layer and the first insulating layer. Similarly, the second passivation layer formed in the passivation step is structured like the first passivation layer, so that a second sacrificial area and a second functional area are formed in the second silicon layer. All sacrificial areas are then removed, for example by an etching process (silicon sacrificial layer etching). Depending on the material of the one or more central layers, such silicon sacrificial layer etching can also be used to structure the one or more central layers. This is particularly advantageous for forming a cavity by means of a single silicon sacrificial layer etching, which cavity is composed of sacrificial areas on both sides of the one or more central layers and penetrates the one or more central layers. The premise of this approach is the appropriate structuring of the first and second insulating layers.

[0014] Therefore, according to the present invention, a method for integrating one or more core layers into a microelectromechanical structure constructed by an EPyC process is proposed. By means of the method of the present invention, well-defined layers, such as highly doped single-crystal silicon layers (Si layers) with precise layer thicknesses, can be integrated into complex MEMS. This core layer or these core layers can be predetermined by the raw material of the carrier substrate or applied to the carrier substrate. For more details about the EPyC process, please refer to DE 10 2015206996A1, which is fully incorporated into the present application by reference.

[0015] A particularly advantageous embodiment of the method of the present invention is to repeat the steps of applying (e.g., epitaxial growth), structuring and passivating the first silicon layer as described above. The structuring of the first passivation layer as described above is also repeated. Alternatively or additionally, the corresponding steps can also be repeated for the second silicon layer and the second passivation layer. This repetition can occur multiple times, for example twice, three times, five times or ten times. Within the scope of this repetition, the application is carried out on a structured passivation layer (i.e., the just outermost passivation layer) instead of the insulating layer. Thus, additional silicon layers and additional passivation layers are formed and structured on the first side and / or the second side of the one or more central layers. That is, a layer system can be formed on both sides of the one or more central layers. By forming and structuring the additional silicon layer and the additional passivation layer, additional sacrificial areas and additional functional areas are formed in the additional silicon layer. At the same time, electrical connection and electrical insulation between specific areas of the silicon layer can be achieved by structuring the additional passivation layer. With this configuration of the method of the present invention, a layer sequence on both sides of the central layer can be simply established. In this case, the layers stacked on top of each other can be precisely aligned with respect to each other. Each silicon layer can be structured and configured independently of the other silicon layers. In particular, it is also possible to realize functional areas that mesh with each other and / or overlap each other, especially in terms of vertical extension. The method also enables the free configuration of electrical connections and electrical insulation and mechanical connections and mechanical insulation / insulation within the functional area. Within the scope of this approach, such areas without a passivation layer can be filled with the aid of CVD polysilicon deposition before applying the next silicon layer in order to form a wiring layer. A starting layer can also be generated within the scope of the step of applying the next silicon layer by means of such CVD polysilicon deposition.

[0016] Preferably, after removing all sacrificial regions, at least one of the passivation layers (in some cases thereby exposing the grooves) and / or at least one of the insulating layers, i.e., for example, a portion of the first and / or second passivation layer and / or one or more of the further passivation layers present if necessary and / or the first insulating layer and / or the second insulating layer, is also removed at least partially, for example to establish the desired mobility of the generated structure. This is advantageous in the following cases: by the method according to the present application, the functional regions are advantageously completely fixed relative to each other. For example, notches and / or gaps can be formed in one of the generated passivation layers and / or the grooves can be exposed. The passivation layer can also be completely removed. This can include exposing the grooves. For example, the passivation layer (for example an oxide passivation layer) or parts of the passivation layer can be removed by gas phase etching, plasma etching and / or wet etching. The passivation layer or parts of the passivation layer can thus be removed particularly easily.

[0017] Preferably, before removing the portion of the first carrier substrate and therefore also before forming the second insulating layer, the first carrier substrate (including the layers applied so far and the microelectromechanical structure produced) is rotated, wherein the rotation is preferably about an axis extending parallel to the surface by an angle between 175° and 185°, preferably between 179° and 181°, particularly preferably 180°. It can thereby be achieved that the formation of the second insulating layer and subsequent layers is particularly easy, since due to the similar orientation the device can be used in a similar manner to form the layers on both sides of the one or more central layers. The production process of the microelectromechanical structure to be produced is thus greatly simplified.

[0018] It is particularly advantageous if the portion of the first carrier substrate is removed by chemical mechanical polishing (CMP), which allows, for example, high-precision removal of the carrier substrate down to the first of the core layers that emerge.

[0019] According to a particularly preferred embodiment, before removing the part of the first carrier substrate, a second carrier substrate is applied on the surface of the last formed passivation layer, which preferably consists essentially of silicon. Therefore, after the three-dimensional structure is built on one side of the first carrier substrate, the second carrier substrate is applied, and more precisely on the same side, on which a silicon layer or (or in the case of repetition) a plurality of silicon layers and an insulating layer or (in the case of repetition) a plurality of insulating layers have been formed in the previous step. This can be advantageous for improving the stability of the silicon wafer in subsequent working steps. Such application of the second carrier substrate can, for example, include bonding of the second carrier substrate, such as soldering and / or sintering. The application of the second carrier substrate is preferably carried out before the possible rotation of the first carrier substrate with the layers and structures produced so far and / or before the structuring of the last formed passivation layer. Such structuring of the last formed passivation layer can also be carried out after the second carrier substrate is removed later. The removal of the second carrier substrate is preferably carried out before the removal of all sacrificial areas (usually by etching of the silicon sacrificial layer). It is particularly advantageous to remove the second carrier substrate before all sacrificial regions are removed, since the structures formed by the method are very mechanically sensitive after the sacrificial regions have been removed. This greatly limits the methods that can be selected for removing the carrier substrate when the sacrificial regions have been removed beforehand. The removal of the second carrier substrate is preferably carried out by chemical mechanical polishing (CMP).

[0020] Preferably, at least one of the epitaxially grown silicon layers, for example the first silicon layer and / or the second silicon layer and / or one of the further silicon layers, comprises a monocrystalline silicon layer, a polycrystalline silicon layer and / or an epitaxial polycrystalline silicon layer, or is such a silicon layer. Furthermore, the layer thickness of at least one of the epitaxially grown silicon layers, for example the first silicon layer and / or the second silicon layer and / or one of the further silicon layers, can be, for example, 0.5 μm to 100 μm, preferably 20 μm to 60 μm. Thin silicon layers are suitable, for example, as spring elements for vertical deflection. Thick silicon layers, on the other hand, are advantageous for producing electrode combs, for filling large volumes or for being removed again as sacrificial regions.

[0021] Preferably, the structuring for forming the trenches is achieved by means of trench processes such as reactive ion etching (RIE) and / or deep reactive ion etching (DRIE) and / or by means of a plasma etching process. Here, the plasma etching process is particularly suitable for thin layers (thickness of a few micrometers). For thicker layers, for example, DRIE can be used.

[0022] According to a preferred embodiment of the method of the present application, the structuring of the passivation layer is performed by a dry etching process and / or a wet etching process. Therefore, the passivation layer can be easily removed again without using a special etching process.

[0023] It is also advantageous if, after application of one of the silicon layers, it is subjected to chemical mechanical polishing (CMP) and / or additional doping at least in places by implantation and / or capping. This makes it possible to easily flatten the topological irregularities and height differences that are formed, especially in the case of epitaxial growth of silicon layers. By means of additional doping by implantation or capping, a specific resistance can be easily achieved in the silicon layer. The grown silicon layer can be undoped, p-doped or n-doped.

[0024] Preferably, the sacrificial region is removed at least partially by plasma-free etching and / or plasma-assisted etching, i.e., by a silicon sacrificial layer etching process. In this way, the sacrificial region can be removed particularly easily. For example, such plasma-free etching can be performed by chlorine trifluoride (ClF3), chlorine fluoride (ClF), chlorine pentafluoride (ClF5), trifluorobromide (BrF3), pentafluorobromide (BrF5), iodine pentafluoride (IF5), iodine heptafluoride (IF7), sulfur tetrafluoride (SF4), xenon difluoride (XeF2) or similar substances. Plasma-assisted etching can be performed, for example, by fluorine plasma, chlorine plasma and / or bromine plasma. In particular, etching can also be based on a combination of plasma-free etching and plasma-assisted etching.

[0025] According to a second aspect of the present invention, a microelectromechanical device is provided, for example comprising a MEMS such as a micromirror array, the microelectromechanical device preferably comprising a microelectromechanical structure manufactured by the method of the present invention for manufacturing a microelectromechanical structure. The microelectromechanical device comprises two alternating sequences of structured silicon layers and structured passivation layers and comprises a central layer, for example substantially consisting of single-crystalline silicon, which is arranged between the two alternating sequences of structured silicon layers and structured passivation layers and can be structured, i.e. in particular can have notches and / or gaps.

[0026] Advantages of the invention

[0027] The method of the present invention makes it possible to integrate a clearly defined layer with free characteristics into a micro-electromechanical structure in a simple manner, which is referred to as a core layer in the present application. In particular, the material of the core layer can be flexibly selected, for example, single-crystal silicon can be selected, which has higher electrical and thermal conductivity than polycrystalline silicon. It is also possible, for example, to integrate a particularly thin core layer with a precise layer thickness and low deviation, which cannot be achieved by CMP. Instead, a core layer on the original silicon wafer can be used, which can be reliably quality-identified and controlled. By constructing an alternating sequence of structured silicon layers and passivation layers on both sides of one or more core layers, the desired characteristics of the core layer or multiple core layers can be utilized, and possible problems with the topological structure of the core layer can also be avoided by precise definition. The process of the present invention is also compatible with CMOS and resistant to high temperatures, and is therefore particularly suitable for large-scale production of MEMS. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Embodiments of the present invention will be further illustrated by the accompanying drawings and the following description.

[0029] The accompanying drawings show:

[0030] Figures 1A to 1G is a schematic cross-sectional view for illustrating a method for manufacturing a micro-electromechanical structure according to the present invention;

[0031] Figure 2 is a schematic flow chart for illustrating a method for manufacturing a micro-electromechanical structure according to the present invention;

[0032] Figure 3 is a schematic diagram of a micro-electromechanical device of the present invention. DETAILED DESCRIPTION

[0033] In the following description of embodiments of the invention, identical or similar elements are denoted by the same reference numerals, wherein a repeated description of these elements is omitted in individual cases. The figures merely schematically illustrate the subject matter of the invention.

[0034] exist Figures 1A to 1G In the figures, schematic cross-sectional views are shown for explaining an exemplary method for manufacturing a microelectromechanical structure according to the invention. In these figures, for the sake of greater clarity, the insulating layer and the passivation layer (whether inside or outside the grooves shown) are presented in the same way. Also for the sake of better clarity, layers, grooves and functional and sacrificial areas are marked with reference numerals purely by way of example. Finally, it should be pointed out that these figures only show two-dimensional illustrations. All layers shown in the figures as two-dimensional objects also have a third spatial dimension and can also be structured along this third spatial dimension by the method of the invention, which enables extremely high flexibility.

[0035] Here, Figure 1A A first carrier substrate 110 is shown which is provided and comprises a core layer 140, for example a monocrystalline silicon layer. Furthermore, a first insulating layer 122 is shown, for example made of silicon oxide, which is applied to the surface 120 of the first carrier substrate 110 and lies directly on the core layer 140. The core layer 140 can be structured before the first insulating layer 122 is applied, or the first carrier substrate 110 can be provided directly with a structured core layer 140. Likewise, the first insulating layer 122 can also be structured. This makes it possible, for example, to subsequently establish an electrical connection between the layer systems on both sides of the core layer 140. In the following Figures 1B to 1F In the embodiment, the structured core layer 140 and the structured first insulating layer 122 are taken as the starting point. Figure 1A In FIG. 1 , the recesses 145 of the central layer 140 and the recesses 125 of the first insulating layer 122 produced during the structuring are indicated by dashed lines.

[0036] A first silicon layer 150a is applied to the first insulating layer 122, for example by epitaxial growth, and then structured. Grooves 156a are formed here, which extend through the first silicon layer 150a. The trenches 156a are filled by passivating the first silicon layer 150a, and a first passivation layer 154a is also formed on the side of the first silicon layer 150a facing away from the first insulating layer 122. The first passivation layer 154a is also structured, wherein sacrificial regions and functional regions 158 are formed in the first silicon layer 150a. In order to make it clear that the sacrificial regions and the functional regions 158 are the same in material, i.e., both are composed of silicon from the silicon layer, they are represented by a unified reference numeral 158 in this figure and subsequent figures. In Figure 1F and 1G In the drawings, different reference numerals are used in addition in order to be able to better visually represent the corresponding method steps and the differences between the sacrificial region and the functional region 158 there.

[0037] The structuring of these layers ensures that the sacrificial regions can be removed later by an etching process. Figure 1B In the example shown, the steps of applying, structuring and passivating the first silicon layer 150a and the step of structuring the first passivation layer 154a are repeated once again. Here, a further silicon layer 150b is applied on the first passivation layer 154a, which is structured by means of further trenches 156b. By passivation, the further trenches are filled. Outside the further trenches 156b, a further passivation layer 154b is also formed, which can also be structured at this time or also later (after removing the second carrier substrate 160). In this case, a notch 155 is produced in the example shown. Figure 1B The structure thus formed is shown. In this case, both silicon layers 150 a , 150 b are denoted by the common reference numeral 150 , the common reference numeral 156 denotes the filled trench, and the common reference numeral 154 denotes the passivation layer outside the trench 156 .

[0038] A second carrier substrate 160 can then be applied to the exposed, just applied passivation layer 154b in order to mechanically stabilize the microelectromechanical structure produced so far. Preferably, after the second carrier substrate 160 is applied, the first carrier substrate 110 including the layers and structures produced so far can be rotated, wherein this rotation preferably takes place about an axis 165 extending parallel to the surface 120. In this case, the rotation can take place, for example, at an angle of 180°. Figure 1C After a 180° rotation about an axis 165 parallel to the surface 120, Figure 1B The microelectromechanical structure in and the second carrier substrate 160 are applied (for example by bonding).

[0039] Now, a portion of the first (ie, previous) carrier substrate 110 is removed, but the central layer 140 is not removed. Instead, the first carrier substrate 110 is removed exactly up to the central layer 140. This removal can be achieved, for example, by chemical mechanical polishing. Figure 1D As shown, the central layer 140, which is now exposed on one side, defines a new surface 170. The structuring of the central layer 140 can be present, for example, from the outset in the first carrier substrate 110 provided, or it can be carried out at this time, that is, after the removal of the first carrier substrate 110. The layers and structures formed so far are supported by the second carrier substrate 160. Now, on the new surface 170, that is, on the exposed side of the central layer 140, a second insulating layer 172 is formed, which is structured like the first insulating layer 122.

[0040] Silicon layer 180 can now be applied again, structured and passivated, wherein sacrificial regions and functional regions 158 are formed by structuring passivation layer 184 . Figure 1E3 further silicon layers 180 a , 180 b , 180 c having trenches 186 and three passivation layers 184 a , 184 b , 184 c formed and structured in this way are shown.

[0041] Finally, if Figure 1F As shown in , the second carrier substrate 160 is removed and the resulting structure can now be completely exposed, for example by removing all sacrificial regions 153 by plasma-free etching and / or plasma-assisted etching. The regions of the silicon layer 150 that can come into contact with the etching medium used in the etching process (for example via the recesses 155 and 185 of the outermost passivation layers 154 and 184), i.e. the sacrificial regions 153, are completely etched away. Figure 1F In the embodiment, these sacrificial regions 153 are identified by different hatching. Figure 1B and 1C ), these notches can also be produced after removing the second carrier substrate 160.

[0042] After removing the sacrificial region 153, the functional region 152 remains, such as Figure 1G As shown. Finally, as required, the passivation layers 154 and 184 may be at least partially removed, including exposing the grooves 156 and 186, and / or the insulating layers 122 and 172 may be at least partially removed. Figure 1G ), for example, in order to establish the desired mobility of the generated microelectromechanical structure. Such removal of the passivation layers 154, 184 can be achieved, for example, by gas phase etching, plasma etching or wet etching.

[0043] Figure 2 A schematic flow chart for explaining an exemplary method for producing a microelectromechanical structure according to the invention is shown. After providing 210 a first carrier substrate 110 comprising at least one core layer 140, a first silicon layer 150a is applied to the surface 120 of the first carrier substrate 110, for example by epitaxial growth. Subsequently, the first silicon layer 150a is structured 230 by forming trenches 156, which extend at least partially through the first silicon layer 150a. After the first silicon layer 150a is passivated 240 (accompanied by filling the trenches 156), a first passivation layer 154a is also formed outside the trenches 156. The first passivation layer is located on the side of the first silicon layer 150a facing away from the first insulating layer 122. The first passivation layer 154a thus produced is now structured in step 250 to define sacrificial regions 153 and functional regions 152. These steps for forming the applied, structured silicon layer 150 can now be repeated as many times as desired. This is indicated schematically by arrow 255 .

[0044] Once all the desired silicon layers 150 have been applied, the first carrier substrate 110 is preferably rotated 265 internally with the layers applied so far, preferably around an axis 165 extending parallel to the surface 120. Subsequently, a portion of the first carrier substrate 110 is removed (step 270), but no core layer 140 is removed. Thus, a new surface 170 is formed. In order to mechanically support the structure formed so far, a second carrier substrate 160 can also be applied to the side of the core layer 140 to which the silicon layer 150 has been applied in the previous step. This application of the second carrier substrate 160 is preferably carried out before any rotation 265 and before the removal 270 of the portion of the first carrier substrate 110. A second insulating layer 172 is formed on the new surface 170 (step 280). Subsequently, steps 220 to 250 are repeated (arrow 285) so that a corresponding structure or silicon layer 180 is also formed on the second side of the core layer 140.

[0045] Here too, a further silicon layer 180 can be applied, structured and passivated by repeating 255 steps 220 to 250 any number of times, wherein the formed passivation layer 184 is also structured. When this is completed, the possibly applied second carrier substrate 160 can be removed 260. Finally, a final silicon sacrificial layer etch is performed to remove 290 the newly formed sacrificial region 153, thereby exposing the resulting structure. Gas phase etching, plasma etching and / or wet etching can also be performed to at least partially remove the passivation layer 154. In this way, the microelectromechanical structure is completed and the method of the invention ends.

[0046] Figure 3 An exemplary microelectromechanical device 300 according to the present invention is schematically shown, for example comprising a MEMS. The microelectromechanical device 300 comprises a microelectromechanical structure manufactured by the method of the present invention for manufacturing a microelectromechanical structure. These microelectromechanical structures are composed of two alternating sequences 350, 380 consisting of structured silicon layers 150, 180 and structured passivation layers 154, 184, and a central layer 340 (for example a single-crystal silicon layer) located between them. Here, the central layer 340 can be structured, that is, in particular, it can have notches and / or gaps. By means of the lower alternating sequence 350 consisting of the structured silicon layer 150 and the structured passivation layer 154, for example, a circuit 355 consisting of an electrical connection can be realized, which circuit is used to control an actuator 385, and the actuator 385 can be realized by means of the upper alternating sequence 380 consisting of the structured silicon layer 180 and the structured passivation layer 184. However, micromechanical elements may also be implemented by lower sequence 350 of layers 150 , 154 , just as parts of upper sequence 380 of layers 180 , 184 may be used for circuit 355 . Microelectromechanical device 300 is located on carrier 320 , which may include, for example, further electrical and electronic components for operating microelectromechanical device 300 .

[0047] The invention is not limited to the embodiments described herein and the aspects highlighted therein. On the contrary, there are many variations that a person skilled in the art can make within the scope defined by the claims.

Claims

1. A method for manufacturing a micro-electromechanical structure, comprising the following steps: a. providing (210) a first carrier substrate (110) having one or more core layers (140) and a surface (120), wherein the first carrier substrate (110) is provided with a first insulating layer (122) arranged on a first side of the one or more core layers (140) and formed on the surface (120); b. applying (220) a first silicon layer (150a) onto the first insulating layer (122); c. Structuring (230) the first silicon layer (150a) for forming a trench (156) in the first silicon layer (150a), wherein the trench (156) at least partially extends through the first silicon layer (150a); d. passivating (240) the first silicon layer (150a), wherein the trench (156) is filled and a first passivation layer (154a) is formed on a side of the first silicon layer (150a) facing away from the first insulating layer (122); e. Structuring (250) the first passivation layer (154a), wherein a first sacrificial region (153) and a first functional region (152) are formed in the first silicon layer (150a) and the first sacrificial region (153) is at least partially free of the first passivation layer (154a) on a side of the first silicon layer (150a) facing away from the first insulating layer (122); f. removing (270) a portion of the first carrier substrate (110) so that a new surface (170) of the first carrier substrate (110) is formed on the second side of the one or more core layers (140) and without removing any of the one or more core layers (140); g. forming (280) a second insulating layer (172) on the new surface (170); h. Repeating (285) steps b to e to apply (220), structure (230) and passivate (240) a second silicon layer (180a) on the second insulating layer (172), structure (250) the second passivation layer (184a), thereby forming a second sacrificial region (153) and a second functional region (152) in the second silicon layer (180a); i. Remove (290) all sacrificial areas (153).

2. The method according to claim 1, wherein: Repeat (255) steps b to e of applying (220), structuring (230) and passivating (240) the first silicon layer (150a) and structuring (230) of the first passivation layer (154a) and / or structuring (230) and passivation (240) of the second silicon layer (180a) and structuring (250) of the second passivation layer (184a), wherein the application (220) is carried out on a structured passivation layer (154, 184), respectively, and thereby further silicon layers (150b, 180b, 180c) and further passivation layers (154b, 184b, 184c) are formed and structured on the first side and / or the second side of the one or more central layers (140), thereby forming further sacrificial regions (153) and further functional regions (152) in the further silicon layers (150b, 180b, 180c).

3. The method according to claim 1 or 2, wherein: After all sacrificial regions (153) have been removed (290), at least one of the passivation layers (154, 184) and / or at least one of the insulating layers (122, 172) are at least partially removed.

4. A method according to any one of the preceding claims, wherein: Before removing (270) the portion of the first carrier substrate (110), the first carrier substrate (110) is rotated (265), wherein the rotation (265) is preferably carried out around an axis (165) extending parallel to the surface (120) at an angle between 175° and 185°, preferably between 179° and 181°, and particularly preferably at an angle of 180°.

5. A method according to any one of the preceding claims, wherein: The removal (270) of the portion of the first carrier substrate (110) is performed by chemical mechanical polishing.

6. A method according to any one of the preceding claims, wherein: Before removing (270) the portion of the first carrier substrate (110), a second carrier substrate (160) is applied to the surface of the last formed passivation layer (154a, 154b), wherein the removal (260) of the second carrier substrate (160) is preferably carried out before the removal (290) of all sacrificial areas (153) and / or by chemical mechanical polishing.

7. A method according to any one of the preceding claims, wherein: At least one of the applied silicon layers (150, 180) comprises or is a single-crystalline silicon layer, a polycrystalline silicon layer and / or an epitaxial polycrystalline silicon layer.

8. A method according to any one of the preceding claims, wherein: The layer thickness of at least one of the applied silicon layers (150, 180) is 0.5 μm to 100 μm, preferably 20 μm to 60 μm.

9. A method according to any one of the preceding claims, wherein: The structuring for forming the trenches (156, 186) is performed by trench technology and / or by a plasma etching process.

10. A method according to any one of the preceding claims, wherein: The passivation layer is structured by a dry etching process and / or a wet etching process.

11. A method according to any one of the preceding claims, wherein: After applying (220) one of the silicon layers (150), the silicon layer (150) is chemically mechanically polished and / or additionally doped at least locally by implantation and / or capping.

12. A method according to any one of the preceding claims, wherein: The removal (290) of the sacrificial region (153) is at least partially performed by plasma-free etching and / or plasma-assisted etching.

13. A microelectromechanical device (300), preferably having a microelectromechanical structure produced by a method according to any one of claims 1 to 12, the microelectromechanical device having two alternating sequences (350, 380) of structured silicon layers (150, 180) and structured passivation layers (154, 184), wherein: The microelectromechanical device (300) comprises a central layer (140, 340) located between the two alternating sequences (350, 380) of structured silicon layers (150, 180) and structured passivation layers (154, 184).

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