Selectable error handling modes in memory systems

Abstract

Aspects of the present disclosure configure a system component, such as a memory subsystem controller, to capture debug information in memory subsystem operations in response to a critical event. The memory subsystem controller receives critical event trigger data and determines whether the critical event trigger data corresponds to a fatal condition. The memory subsystem controller selects an error handling mode from a plurality of error handling modes based on determining whether the critical event trigger data corresponds to the fatal condition. A first one of the plurality of error handling modes corresponds to storing a first set of debug information associated with the memory subsystem. A second one of the plurality of error handling modes corresponds to storing a second set of debug information associated with the memory subsystem without interrupting the host. The second set may be a subset of the first set of debug information.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to debugging memory subsystems. Background Art

[0002] The memory subsystem may be a storage system such as a solid state drive (SSD), and may include one or more memory components that store data. For example, the memory components may be non-volatile memory components and volatile memory components. In general, the host system may utilize the memory subsystem to store data at the memory components and retrieve data from the memory components. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure.

[0004] Figure 1 is a block diagram illustrating an example computing environment including a memory subsystem according to some embodiments of the present disclosure.

[0005] Figure 2 is a block diagram of an example error handling module according to some embodiments of the present disclosure.

[0006] Figures 3 to 5 is a flow chart of an example method of performing memory subsystem debug operations according to some embodiments of the present disclosure.

[0007] Figure 6 is a diagrammatic representation of a machine in the form of a computer system within which a set of instructions may be executed for causing the machine to perform any one or more of the methodologies discussed herein according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0008] Aspects of the present disclosure configure a system component, such as a memory subsystem controller, to debug a memory subsystem or initiate a debug operation for a memory subsystem. The memory subsystem controller may selectively execute different types of error handling modes in response to receiving critical event trigger data. The memory subsystem controller may perform a debug operation according to a first error handling mode when the critical event trigger data corresponds to a fatal condition, and may debug an operation according to a second error handling mode when the critical event trigger data corresponds to a non-fatal condition. The determination of whether the critical event trigger data corresponds to a fatal condition or a non-fatal condition may be based on a type or error or error code received or detected by firmware of the memory subsystem controller. In some instances, a debug operation according to the second error handling mode may be performed without interrupting a host, while a debug operation according to the first error handling mode may cause the host to be interrupted. Depending on the type of debug operation being performed, different sets of debug information may be collected and stored. The set of debug information may include a complete snapshot capturing all internal drive data, or a partial snapshot in which only some portions of data from certain internal memory drives are captured. In this way, the memory subsystem controller can continue to operate the memory subsystem based on the detected error type without interrupting the host, which improves the overall efficiency of operating the memory subsystem.

[0009] The memory subsystem may be a memory device, a memory module, or a combination of a memory device and a memory module. Figure 1 Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more memory components, such as a memory device that stores data. The host system may send access requests (e.g., write commands, read commands, sequential write commands, sequential read commands) to the memory subsystem, such as to store data at the memory subsystem and read data from the memory subsystem. Data specified by the host is referred to as "host data" or "user data" hereinafter.

[0010] The host request may include logical address information (e.g., logical block address (LBA), namespace) of the host data, which is a location that the host system associates with the host data and the specific area in which to store or access the host data. The logical address information (e.g., LBA, namespace) may be part of the metadata of the host data. The metadata may also include error handling data (e.g., ECC codewords, parity codes), data version (e.g., used to distinguish the age of written data), valid bitmap (which LBAs or logical transfer units contain valid data), etc.

[0011] The memory subsystem may initiate media management operations, such as write operations, on host data stored on the memory device. For example, as part of a junk collection management operation, the firmware of the memory subsystem may rewrite previously written host data from a location on the memory device to a new location. The data that is rewritten (e.g., initiated by the firmware) is hereinafter referred to as "junk collection data."

[0012] "User data" may include host data and trash collection data. "System data" hereinafter refers to data created and / or maintained by the memory subsystem for performing operations in response to host requests and for media management. Examples of system data include, but are not limited to, system tables (e.g., logical to physical address mapping tables), data from logging, scratch pad data, and the like.

[0013] The memory device may be a non-volatile memory device. A non-volatile memory device is a package of one or more dies. Each die may include one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane includes a set of physical blocks. For some memory devices, a block is the smallest area that can be erased. Each block includes a set of pages. Each page includes a set of memory cells that store data bits. The memory device may be a raw memory device (e.g., NAND), which is managed externally by an external controller, for example. The memory device may be a managed memory device (e.g., managed NAND), which is a raw memory device combined with a local embedded controller for memory management within the same memory device package. The memory device may be divided into one or more regions, each of which is associated with a different set of host data or user data or application programs.

[0014] Conventional memory subsystems instruct the memory subsystem to obtain snapshots in conjunction with various logs when a problem or error is detected. Regardless of the type of error encountered, the type of snapshot captured is the same, and the host is usually always interrupted when an error is encountered. For example, a memory subsystem controller can monitor the progress of memory operations, and once the controller detects a problem, the controller can instruct the memory subsystem to store its current state and notify the host. However, not all errors are fatal, and under certain error conditions, various input / output (I / O) operations can usually continue to be serviced and executed. Therefore, it may be wasteful and inefficient to interrupt the host and stop memory subsystem operations when any error is encountered, thereby slowing down operations.

[0015] Aspects of the present disclosure address the above and other deficiencies by configuring a system component (e.g., a memory subsystem controller) to selectively interrupt a host based on determining whether critical event trigger data corresponds to a fatal condition or a non-fatal condition. In addition, depending on whether the critical event trigger data corresponds to a fatal condition or a non-fatal condition, different types of snapshot and debug operations may be performed to keep the memory subsystem operating in an efficient manner. The critical event trigger data may include at least one of a non-volatile memory express (NVMe) command timeout being triggered, a cyclic redundancy code (CRC) error exceeding a CRC threshold, a PCIe AXI error event, an uncorrectable error (UE) event, a read or write completion latency exceeding a read or write threshold, reset event information, or a memory parity error exceeding a parity threshold.

[0016] In some cases, in order to preserve storage space on the memory subsystem, the memory subsystem controller may selectively replace a previously stored instance of the debug information (e.g., a previous snapshot) when a new instance of debug information (e.g., a new snapshot) is captured. That is, the memory subsystem controller may access and evaluate certain conditions that represent how valuable the new snapshot is relative to the previous snapshot to decide whether to retain the new snapshot by replacing the previous snapshot, or to discard the new snapshot entirely. The conditions may include power cycle counts, power-on time, or counts associated with input / output commands.

[0017] In some embodiments, a memory subsystem controller receives critical event trigger data and determines whether the critical event trigger data corresponds to a fatal condition. The memory subsystem controller selects an error handling mode from a plurality of error handling modes based on determining whether the critical event trigger data corresponds to a fatal condition. A first of the plurality of error handling modes may correspond to storing a first set of debug information associated with the memory subsystem, and a second of the plurality of error handling modes may correspond to storing a second set of debug information associated with the memory subsystem without interrupting the host. The second set may be a subset of the first set of debug information.

[0018] The first set of debug information may include a state of the memory subsystem representing a state of at least one of one or more data structures, one or more queues, or one or more state machines. In some embodiments, the memory subsystem controller may select a first of a plurality of error handling modes in response to determining that the critical event trigger data corresponds to a fatal condition. In some embodiments, the memory subsystem controller transmits an interrupt signal to the host to initiate a debug operation in response to selecting the first of the plurality of error handling modes.

[0019] In some embodiments, the memory subsystem controller selects a second one of the plurality of error handling modes in response to determining that the critical event trigger data corresponds to a non-fatal condition. In some embodiments, the memory subsystem controller generates a second set of debug information according to a specified format and stores the second set of debug information on the set of memory components.

[0020] In some embodiments, the memory subsystem controller initializes a timer for saving the second set of debug information and determines that the timer has reached a threshold. The memory subsystem controller determines whether the second set of debug information has been successfully saved on the set of memory components in response to determining that the timer has reached the threshold. In response to determining that the second set of debug information has not been successfully saved on the set of memory components after the timer has reached the threshold, the memory subsystem controller generates the first set of debug information.

[0021] In some embodiments, the memory subsystem controller resets the memory subsystem and saves the first or second set of debug information on the set of memory components. In response to determining that a first of a plurality of error handling modes has been selected, the memory subsystem controller limits a set of operations of the memory subsystem to operations performed in a basic functional mode (BFM).

[0022] In some embodiments, the memory subsystem controller reserves a first portion of the set of memory components for storing one or more instances of a first set of debug information and reserves a second portion of the set of memory components for storing one or more instances of a second set of debug information. The memory subsystem controller stores the one or more instances of the array debug information in the reserved portion of the set of memory components and receives a new instance of a set of individual debug information corresponding to the selected error handling mode. In response, the memory subsystem controller replaces a target instance of the one or more instances stored in the reserved portion of the set of memory components with the new instance of the set of individual debug information.

[0023] In some embodiments, the memory subsystem controller determines that a value associated with the target instance is lower than a value associated with the new instance. The target instance may be replaced in response to determining that the value associated with the target instance is lower than a value associated with the new instance. The memory subsystem controller determines that the value associated with the target instance is lower than a value associated with the new instance by determining whether one or more conditions for replacing the target instance are met. The one or more conditions include a power cycle count, a power-on time, or a count associated with an input / output command. The target instance may be replaced in response to determining that a power cycle count representing the number of times the memory subsystem has been power cycled exceeds a power cycle threshold. The memory subsystem controller prevents replacement of the target instance with the new instance in response to determining that the power cycle count representing the number of times the memory subsystem has been power cycled fails to exceed the power cycle threshold.

[0024] The target instance may be replaced in response to determining that the memory subsystem has been powered on for more than a threshold period of time and an average number of input / output command completion rates exceed a threshold rate. In response to determining that the memory subsystem has been powered on for less than a threshold period of time and an average number of input / output command completion rates fail to exceed the threshold rate, the memory subsystem controller prevents replacement of the target instance with a new instance. The target instance may be replaced in response to determining that the memory subsystem has been powered on for more than a threshold period of time and a number of input / output commands completed since the target instance was stored exceeds a threshold. The memory subsystem controller replaces the target instance in response to determining that the memory subsystem has been powered on for less than a threshold period of time and a number of input / output commands completed since the target instance was stored fails to exceed a threshold.

[0025] Although various embodiments are described herein as being implemented with respect to a memory subsystem (eg, a controller of a memory subsystem), some or all of portions of the embodiments may be implemented with respect to a host system, such as a software application or operating system of the host system.

[0026] Figure 1 An example computing environment 100 including a memory subsystem 110 according to some examples of the present disclosure is illustrated. The memory subsystem 110 may include media such as memory components 112A-112N (hereinafter also referred to as "memory devices"). The memory components 112A-112N may be volatile memory devices, non-volatile memory devices, or a combination thereof. In some embodiments, the memory subsystem 110 is a storage system. The memory subsystem 110 may be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and non-volatile dual in-line memory modules (NVDIMMs).

[0027] The computing environment 100 may include a host system 120 coupled to a memory system. The memory system may include one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1An example of a host system 120 coupled to one memory subsystem 110 is illustrated. The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110. As used herein, "coupled to" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0028] The host system 120 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device. The host system 120 may include or be coupled to the memory subsystem 110 so that the host system 120 can read data from the memory subsystem 110 or write data to the memory subsystem 110. The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel interface, a Serial Attached SCSI (SAS) interface, etc. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. The host system 120 may further utilize an NVM Express (NVMe) interface to access the memory components 112A to 112N when the memory subsystem 110 is coupled to the host system 120 through the PCIe interface. The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120 (eg, downloading and submitting firmware commands / requests).

[0029] Memory components 112A to 112N may include any combination of different types of non-volatile memory components and / or volatile memory components. Examples of non-volatile memory components include NAND-type flash memory. Each of memory components 112A to 112N may include one or more memory cell arrays, such as single-level cells (SLC) or multi-level cells (MLC) (e.g., TLC or QLC). In some embodiments, a particular memory component 112 may include both an SLC portion and an MLC portion of memory cells. Each of the memory cells may store one or more data bits (e.g., blocks) used by a host system 120. Although non-volatile memory components such as NAND-type flash memory are described, memory components 112A to 112N may be based on any other type of memory, such as volatile memory.

[0030] In some embodiments, memory components 112A to 112N may be, but are not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magnetoresistive random access memory (MRAM), or non-(NOR) flash memory, electrically erasable programmable read-only memory (EEPROM), and a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory cells may perform bit storage based on changes in body resistance in conjunction with a stackable cross-grid data access array. In addition, in contrast to many flash-based memories, cross-point non-volatile memories may perform write-in-place operations, where non-volatile memory cells may be programmed without having to erase the non-volatile memory cells in advance. Furthermore, the memory cells of memory components 112A to 112N may be grouped into memory pages or blocks, which may refer to a unit of memory component 112 for storing data. In some examples, the memory cells of the memory components 112A to 112N may be grouped into a set of different zones of equal or unequal size for storing data of corresponding applications. In such cases, each application may store data in an associated zone of the set of different zones.

[0031] The memory subsystem controller 115 may communicate with the memory components 112A-112N to perform operations such as reading data, writing data, or erasing data at the memory components 112A-112N, and other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor. The memory subsystem controller 115 may include a processor (processing device) 117 configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120. In some embodiments, the local memory 119 may include memory registers that store memory pointers, fetch data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1The example memory subsystem 110 in FIG. 1 has been described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 may not include the memory subsystem controller 115, but may rely on external control (for example, provided by an external host or by a processor 117 or controller separate from the memory subsystem 110).

[0032] In general, the memory subsystem controller 115 may receive I / O commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 112A to 112N. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and ECC operations, decoding operations, encryption operations, cache operations, address translation between logical block addresses and physical block addresses associated with the memory components 112A to 112N, and address translation between application identifiers received from the host system 120 and corresponding regions of a set of regions of the memory components 112A to 112N based on instructions stored in firmware in the active slots or associated with the active firmware slots. This can be used to restrict applications to only write / read data to / from corresponding regions of the set of regions associated with the respective application. In this case, a given application can only write / read data to / from the associated region, e.g., by erasing the data stored in the region and writing new data to the region, even though there may be free space elsewhere on the memory components 112A-112N. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert I / O commands received from the host system 120 into command instructions to access the memory components 112A-112N, and convert responses associated with the memory components 112A-112N into information for the host system 120.

[0033] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., a DRAM or other temporary storage location or device) and address circuitry (e.g., a row decoder and a column decoder) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory components 112A-112N.

[0034] The memory device may be a raw memory device (e.g., NAND), which is managed externally by an external controller (e.g., memory subsystem controller 115), for example. The memory device may be a managed memory device (e.g., managed NAND), which is a raw memory device combined with a local embedded controller (e.g., a local media controller) within the same memory device package for memory management. Any of the memory components 112A to 112N may include a media controller (e.g., media controller 113A and media controller 113N) to manage memory cells of the memory component, communicate with the memory subsystem controller 115, and execute memory requests (e.g., reads or writes) received from the memory subsystem controller 115.

[0035] In some embodiments, the memory subsystem controller 115 may include an error handling module 122. The error handling module 122 monitors the operation of the memory subsystem 110. Based on the operation, the error handling module 122 may generate or receive critical event trigger data. The critical event trigger data is used to identify errors corresponding to one or more fatal conditions. Based on whether the errors in the critical event trigger data correspond to fatal conditions or non-fatal conditions, the error handling module 122 executes an error handling mode selected from different types of error handling modes.

[0036] In some cases, the error handling module 122 may determine that the critical event trigger data corresponds to a non-fatal error. For example, the error handling module 122 may compare the error code associated with the critical event trigger data with the error code list associated with the non-fatal error. If the error code matches one of the error codes on the non-fatal error code list, the error handling module 122 determines that the error is non-fatal. For example, the error handling module 122 may compare the error code associated with the critical event trigger data with the error code list associated with the fatal error. If the error code fails to match one of the error codes on the fatal error code list, the error handling module 122 determines that the error is non-fatal. In such cases, the error handling module 122 may execute a first error handling mode to generate a partial snapshot (e.g., a first set of debug information may be stored) representing the state of one or more specified components or modules of the memory subsystem 110. In such cases, the error handling module 122 generates and stores the snapshot without interrupting the host system 120. The error handling module 122 may notify the host system 120 immediately or at some later point in time that an error exists and a snapshot has been stored, but the error handling module 122 allows one or more I / O operations to continue to be performed by the memory subsystem 110 .

[0037] In some cases, the error handling module 122 may determine that the critical event trigger data corresponds to a fatal error. For example, the error handling module 122 may compare the error code associated with the critical event trigger data with the error code list associated with the fatal error. If the error code matches one of the error codes on the fatal error code list, the error handling module 122 determines that the error is fatal. For example, the error handling module 122 may compare the error code associated with the critical event trigger data with the error code list associated with the non-fatal error. If the error code fails to match one of the error codes on the non-fatal error code list, the error handling module 122 determines that the error is fatal. In such cases, the error handling module 122 may execute a second error handling mode to generate a complete snapshot (e.g., a second set of debug information including a first set of debug information) representing the state of all or substantially all components or modules of the memory subsystem 110. In such cases, the error handling module 122 may generate and store a snapshot and interrupt the host system 120 to indicate the detected error. The error handling module 122 may prevent subsequent I / O operations from being performed by the memory subsystem 110. As described herein, a "partial snapshot" represents the state of a subset of a component represented by a "full snapshot."

[0038] Depending on the embodiment, the error handling module 122 may include logic (e.g., a set of transient or non-transitory machine instructions, such as firmware) or one or more components that cause the memory subsystem 110 (e.g., the memory subsystem controller 115) to perform the operations described herein with respect to the error handling module 122. The error handling module 122 may include tangible or non-tangible units capable of performing the operations described herein.

[0039] Figure 2 is a block diagram of an example error handling module 200 according to some embodiments of the present disclosure. The error handling module 200 may represent Figure 1The error handling module 122 of the embodiment of the present invention is a memory module 120. As illustrated, the error handling module 200 includes a trigger event logic register 220, a debug information module 230, a fatal condition detection module 240, and / or an error handling mode selection module 250. The trigger event logic register 220 stores a list of error events being monitored. For example, the trigger event logic register 220 can be programmed or configured to monitor the status of certain registers, FIFO buffers, command queues, and other memory subsystem 110 components and modules. Based on a combination of the status of the monitored components and modules, the trigger event logic register 220 can be configured to generate different critical event trigger data (e.g., different error codes). The critical event trigger data may include at least one of a non-volatile memory express (NVMe) command timeout being triggered, a cyclic redundancy code (CRC) error exceeding a CRC threshold, a PCIe AXI error event, an uncorrectable error (UE) event, a read or write completion latency exceeding a read or write read or write threshold, reset event information, and / or a memory parity error exceeding a parity threshold.

[0040] In some embodiments, the trigger event logic register 220 communicates the critical event trigger data to the fatal condition detection module 240. The fatal condition detection module 240 searches the error code list to identify one or more error codes corresponding to the critical event trigger data. For example, the fatal condition detection module 240 can determine that the critical event trigger data matches the error code associated with the non-fatal error. In such cases, the fatal condition detection module 240 determines that the critical event trigger data corresponds to the non-fatal error condition. As another example, the fatal condition detection module 240 can determine that the critical event trigger data matches the error code associated with the fatal error. In such cases, the fatal condition detection module 240 determines that the critical event trigger data corresponds to the fatal error condition. The fatal condition detection module 240 communicates the indication of whether the error is fatal or non-fatal to the error handling mode selection module 250.

[0041] The error handling mode selection module 250 may select between a plurality of error handling modes for performing / execution based on an indication of whether the current error is fatal or non-fatal. For example, the error handling mode selection module 250 may select a first error handling mode in response to determining that the error is fatal. This first error handling mode may be referred to as a "panic" mode. In such cases, the error handling mode selection module 250 instructs the debug information module 230 to collect and capture a first set of debug information corresponding to a fatal error. For example, when the error is determined to be fatal, the error handling mode selection module 250 instructs the debug information module 230 to capture a full snapshot. In response to determining that the error is fatal, the error handling mode selection module 250 also generates an interrupt signal, which is transmitted to the host to indicate a fatal error. The error handling mode selection module 250 also instructs the memory subsystem 110 to stop executing additional I / O commands and only allow execution of BFM commands. These BFM commands may be dedicated commands received from the memory controller 115 and / or the host.

[0042] Error handling mode selection module 250 may perform a warm reset or restart of memory subsystem 110 and may selectively store a first set of debug information in a reserved portion of memory components 112A- 112N. In some cases, error handling mode selection module 250 may replace one or more sets of previously stored debug information in the reserved portion with the first set of debug information when any one or a combination of certain conditions are met indicating that the first set of debug information is more valuable to retain than a set of previously stored debug information.

[0043] In some embodiments, the error handling mode selection module 250 detects that a power cycle event has been performed with respect to the memory subsystem 110. In response, the error handling mode selection module 250 determines that the current error handling mode is a panic mode. In such cases, the error handling mode selection module 250 monitors user input to selectively execute one or more BFMs to perform a debug operation or to perform a normal reboot operation.

[0044] In some embodiments, the error handling mode selection module 250 may select a second error handling mode in response to determining that the error is non-fatal. This first error handling mode may be referred to as a "snapshot" mode. In such cases, the error handling mode selection module 250 instructs the debug information module 230 to collect and capture a second set of debug information corresponding to the non-fatal error. For example, when the error is determined to be non-fatal, the error handling mode selection module 250 instructs the debug information module 230 to capture a partial snapshot.

[0045] In such a case, the error handling mode selection module 250 may attempt to store a partial snapshot (e.g., a second set of debug information) in a reserved portion of a group of memory components 112A to 112N. The error handling mode selection module 250 may initialize or start a timer set to a threshold time period. The error handling mode selection module 250 may determine whether the partial snapshot is successfully saved or stored in the reserved portion of a group of memory components 112A to 112N before the timer reaches (counts up or counts down) the threshold time period. In response to determining that the partial snapshot has been successfully saved or stored before the timer reaches the threshold time period, the error handling mode selection module 250 cancels the timer and resumes monitoring future critical event trigger data. In response to determining that the partial snapshot has not been successfully (failed to successfully) saved or stored before the timer reaches the threshold time period, the error handling mode selection module 250 performs operations corresponding to a panic mode. That is, the error handling mode selection module 250 instructs the debug information module 230 to collect and capture a first set of debug information (e.g., a full snapshot) corresponding to a fatal error. The error handling mode selection module 250 also generates an interrupt signal that is transmitted to the host. The error handling mode selection module 250 also instructs the memory subsystem 110 to stop executing other I / O commands and only allow execution of BFM commands. These BFM commands may be special commands received from the memory controller 115 and / or the host.

[0046] In some embodiments, debug information module 230 may store instances of full snapshots (captured at different points in time) in a first reserved portion of a set of memory components 112A through 112N. Debug information module 230 may store instances of partial snapshots (captured at different points in time) in a second reserved portion of a set of memory components 112A through 112N. In this manner, partial snapshots (collected during execution of the second error handling mode) may be accessed and represent the state of memory subsystem 110 separately from full snapshots (collected during execution of the first error handling mode).

[0047] In some embodiments, when a new instance of debug information is received, debug information module 230 may selectively replace or substitute previously stored instances of debug information (full snapshots and / or partial snapshots). Specifically, debug information module 230 may determine that a new partial snapshot has been generated. In response, debug information module 230 may determine whether a second reserved portion of a set of memory components 112A to 112N has sufficient capacity or storage space to accommodate the new instance of the partial snapshot. In response to determining that the second reserved portion fails to include sufficient capacity or storage space, debug information module 230 analyzes or calculates the values ​​of one or more previously stored partial snapshots and the value of the new partial snapshot to determine whether the new partial snapshot is more valuable than the one or more previously stored partial snapshots. For example, debug information module 230 may calculate the first condition by accessing a power cycle count, which represents the number of times the memory subsystem 110 has been power cycled since the one or more previously stored partial snapshots were stored. If the power cycle exceeds a power cycle threshold (e.g., five), or if one or more partial snapshots are associated with a read indication indicating that the partial snapshot was previously read by the host, then debug information module 230 may determine that the first condition is met and replace the one or more partial snapshots with a new partial snapshot.

[0048] As another example, the debug information module 230 may calculate the second condition by accessing the power-on time of the memory subsystem 110, which indicates how long the memory subsystem 110 has been powered on since one or more previously stored partial snapshots were stored. The debug information module 230 may also calculate an average number of I / O command completion rates representing the number of I / O commands that have been completed within a given time period. If the power-on time exceeds or corresponds to a threshold time period or range (e.g., between 60 seconds and 900 seconds), and if the average number of I / O command completion rates exceeds a threshold rate (e.g., 5k I / O commands per second), the debug information module 230 may determine that the second condition is satisfied and replace the one or more partial snapshots with new partial snapshots.

[0049] As another example, the debug information module 230 may calculate the third condition by accessing the power-on time of the memory subsystem 110, which indicates how long the memory subsystem 110 has been powered on since the one or more previously stored partial snapshots were stored. The debug information module 230 may also calculate the number of I / O commands that have been completed since the one or more previously stored partial snapshots were stored. If the power-on time exceeds or corresponds to a threshold time period (e.g., 900 seconds), and if the number of I / O commands exceeds a threshold (e.g., 5 million I / O commands), the debug information module 230 may determine that the third condition is satisfied and replace the one or more partial snapshots with new partial snapshots.

[0050] In some embodiments, the debug information module 230 determines that the first, second, and third conditions are not satisfied or met, or only two of the three conditions are met. In such cases, the debug information module 230 prevents the replacement of one or more partial snapshots with a new partial snapshot. The debug information module 230 deletes the new partial snapshot or fails to store the new partial snapshot, and leaves one or more previously stored partial snapshots in a second reserved portion of a set of memory components 112A to 112N. In some cases, when any of the conditions are met, the debug information module 230 prevents the replacement of the previously stored snapshot with the new snapshot.

[0051] It should be understood that similar operations may also be performed with respect to replacing a previously stored full snapshot with or without a new full snapshot.

[0052] Figure 3 300 is a flow chart of an example method 300 of performing a debug operation according to some embodiments of the present disclosure. The method 300 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 300 is performed by Figure 1 The method 300 may be performed by the memory subsystem controller 115 or a subcomponent of the controller 115. In these embodiments, the method 300 may be performed at least in part by the error handling module 200. Although the processes are shown in a particular sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only; the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0053] Reference now Figure 3 , the method (or process) 300 begins at operation 305, where an error handling module 200 of a memory subsystem (e.g., a processor of a memory subsystem controller 115) receives critical event trigger data. Then, at operation 310, the error handling module 200 determines whether the critical event trigger data corresponds to a fatal condition. At operation 315, the error handling module 200 selects an error handling mode from a plurality of error handling modes based on determining whether the critical event trigger data corresponds to a fatal condition. A first of the plurality of error handling modes may correspond to storing a first set of debug information associated with the memory subsystem, and a second of the plurality of error handling modes may correspond to storing a second set of debug information associated with the memory subsystem without interrupting the host. The second set may be a subset of the first set of debug information.

[0054] Figure 44 is a flow chart of an example method 400 of performing a debug operation according to some embodiments of the present disclosure. The method 400 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 400 is performed by Figure 1 The method 400 may be performed by the memory subsystem controller 115 or a subcomponent of the controller 115. In these embodiments, the method 400 may be performed at least in part by the error handling module 200. Although the processes are shown in a particular sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only; the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0055] Reference now Figure 4 , the method (or process) 400 begins at operation 401, where the error handling module 200 of the memory subsystem (e.g., of the processor of the memory subsystem controller 115) begins error handling operations (e.g., in response to receiving critical trigger event data). At operation 402, the error handling module 200 captures a snapshot (e.g., a full snapshot), and at operation 403, the error handling module 200 formats the snapshot according to a certain specified format for debugging. At operation 404, the error handling module 200 selects an error handling mode between a snapshot mode (in which a partial snapshot is stored) and a panic mode (in which a full snapshot is stored).

[0056] At operation 405, in response to selecting the snapshot mode, the error handling module 200 triggers saving a partial version of the captured snapshot and initializes a timer. At operation 406, the error handling module 200 generates a request to save the partial version of the captured snapshot in a corresponding reserved portion of a set of memory components 112A to 112N. At operation 407, a set of memory components 112A to 112N attempts to save the partial version of the snapshot before the timer reaches a specified threshold. Then, at operation 408, the error handling module 200 cancels the timer in response to determining that the partial version of the snapshot has been successfully saved before the timer reaches the specified threshold. At operation 409, the error handling module 200 determines that the timer reaches the threshold before the partial version of the snapshot is successfully saved. In such a case, the error handling module 200 proceeds to operation 410 in which a full snapshot is captured and / or generated, and performs a hot reset of the memory subsystem 110 at operation 411 to retain the snapshot.

[0057] At operation 412, the error handling module 200 saves a full snapshot on a set of memory components 112A to 112N, and at operation 413, the error handling module 200 determines the selected error handling mode. In response to determining that the error handling mode corresponds to panic mode, the error handling module 200 proceeds to operation 414, where memory operations are restricted to BFM operations. In response to determining that the error handling mode corresponds to snapshot mode, the error handling module 200 proceeds to operation 415, where the memory subsystem 110 is rebooted.

[0058] At operation 420, the error handling module 200 determines, for example, that a power cycle event is received from the host. In response, at operation 422, the error handling module 200 determines the error handling mode that is selected. In response to determining that the error handling mode corresponds to the panic mode, the error handling module 200 proceeds to operation 424 to monitor for user input corresponding to a debug operation (e.g., requesting a BFM command and / or requesting to perform a normal reboot). In response to determining at operation 422 that the error handling mode corresponds to the snapshot mode, the error handling module 200 proceeds to operation 415, where the memory subsystem 110 is rebooted.

[0059] Figure 5 5 is a flow chart of an example method 500 of performing a debug operation according to some embodiments of the present disclosure. The method 500 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 500 is performed by Figure 1 The method 500 may be performed by the memory subsystem controller 115 or a subcomponent of the controller 115. In these embodiments, the method 500 may be performed at least in part by the error handling module 200. Although the processes are shown in a particular sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only; the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0060] Reference now Figure 5, the method (or process) 500 begins at operation 501, where the error handling module 200 of the memory subsystem (e.g., the processor of the memory subsystem controller 115) begins to check whether there is sufficient capacity or space in the reserved portion of a set of memory components 112A to 112N to store a new instance of a snapshot (complete or partial). If not, the error handling module 200 checks one or more conditions including a first condition 512, a second condition 514, and a third condition 516 about the previously stored instance of the snapshot to determine whether the previous instance is more valuable than the new instance of the snapshot.

[0061] In some cases, the first condition corresponds to a power cycle count since the previous instance was stored. The second condition may correspond to an average number of power-on times and I / O command completion rates. The third condition may correspond to power-on times and a number of I / O commands executed or completed since the previous instance was stored.

[0062] At operation 530, the previous instance of the snapshot is replaced with the new instance of the snapshot in response to determining that one or more of the first, second, and third conditions are met. At operation 520, the new instance of the snapshot is discarded and deleted, and the previous instance of the snapshot is retained without replacing the previous instance with the new instance of the snapshot.

[0063] In view of the above disclosure, various examples are described below. It should be noted that within the disclosure of the present application, one or more features of the examples taken alone or in combination should be considered.

[0064] Example 1: A system comprising: a memory subsystem comprising a set of memory components; and a processing device operably coupled to the set of memory components and configured to perform operations comprising: receiving critical event trigger data; determining whether the critical event trigger data corresponds to a fatal condition; and selecting an error handling mode from a plurality of error handling modes based on determining whether the critical event trigger data corresponds to the fatal condition, a first of the plurality of error handling modes corresponding to storing a first set of debug information associated with the memory subsystem, and a second of the plurality of error handling modes corresponding to storing a second set of debug information associated with the memory subsystem without interrupting a host, the second set being a subset of the first set of debug information.

[0065] Example 2. The system of example 1, wherein the first set of debug information includes a state of the memory subsystem representing a state of at least one of one or more data structures, one or more queues, or one or more state machines.

[0066] Example 3, a system according to Example 1 or 2, wherein the critical event trigger data includes at least one of a non-volatile memory express (NVMe) command timeout being triggered, a cyclic redundancy code (CRC) error exceeding a CRC threshold, a PCIe AXI error event, an uncorrectable error (UE) event, a read or write completion latency exceeding a read or write read or write threshold, reset event information, or a memory parity error exceeding a parity threshold.

[0067] Example 4, according to the system described in any one of Examples 1 to 3, the operation includes: selecting the first one of the multiple error handling modes in response to determining that the critical event trigger data corresponds to the fatal condition; and transmitting an interrupt signal to the host to start a debugging operation in response to selecting the first one of the multiple error handling modes.

[0068] Example 5. The system of any of examples 1 to 4, wherein the operation comprises: selecting the second one of the plurality of error handling modes in response to determining that the critical event trigger data corresponds to a non-fatal condition.

[0069] Example 6. The system of example 5, wherein the operations include: generating the second set of debug information according to a specified format; and storing the second set of debug information on the set of memory components.

[0070] Example 7, a system according to Example 6, wherein the operation includes: initializing a timer for saving the second set of debug information; determining that the timer has reached a threshold; and determining whether the second set of debug information has been successfully saved on the set of memory components in response to determining that the timer has reached the threshold.

[0071] Example 8. The system of example 7, wherein the operations include generating the first set of debug information in response to determining that the second set of debug information has not been successfully saved on the set of memory components after the timer has reached the threshold.

[0072] Example 9, a system according to any one of Examples 1 to 8, wherein the operations include: resetting the memory subsystem; saving the first set of adaptation information or the second set of debug information on the set of memory components; and in response to determining that the first one of the multiple error handling modes has been selected, limiting a set of operations of the memory subsystem to operations performed in a basic functional mode.

[0073] Example 10, a system according to any of Examples 1 to 9, wherein the operation includes: reserving a first portion of the set of memory components for storing one or more instances of the first set of debug information; and reserving a second portion of the set of memory components for storing one or more instances of the second set of debug information.

[0074] Example 11, a system according to any of Examples 1 to 10, wherein the operations include: storing one or more instances of array debug information in a reserved portion of the set of memory components; receiving a new instance of a set of individual debug information corresponding to the selected error handling mode; and replacing a target instance of the one or more instances stored in the reserved portion of the set of memory components with the new instance of the set of individual debug information.

[0075] Example 12, a system according to Example 11, wherein the operation includes: determining that a value associated with the target example is lower than a value associated with the new example, wherein the target example is replaced in response to determining that the value associated with the target example is lower than the value associated with the new example.

[0076] Example 13, a system according to example 12, wherein determining that the value associated with the target instance is lower than the value associated with the new instance comprises: determining whether one or more conditions for replacing the target instance are satisfied.

[0077] Example 14. The system of example 13, wherein the one or more conditions include a power cycle count, a power-on time, or a count associated with an input / output command.

[0078] Example 15. The system of any of examples 1 to 14, wherein the target instance is replaced in response to determining that a power cycle count representing a number of times the memory subsystem has been power cycled exceeds a power cycle threshold.

[0079] Example 16, a system according to any of Examples 1 to 15, wherein the operation includes preventing replacement of the target instance with the new instance in response to determining that a power cycle count representing the number of times the memory subsystem has been power cycled has failed to exceed a power cycle threshold.

[0080] Example 17. The system of any of examples 1 to 16, wherein the target instance is replaced in response to determining that the memory subsystem has been powered on for more than a threshold period of time and an average number of input / output command completions exceeds a threshold rate.

[0081] Example 18, a system according to any of examples 1 to 17, wherein the target instance is replaced in response to determining that the memory subsystem has been powered on for more than a threshold period of time and a number of input / output commands completed since the target instance was stored exceeds a threshold.

[0082] Methods and computer-readable storage media having instructions for performing any of the above examples.

[0083] Figure 6 An example machine is illustrated in the form of a computer system 600 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 600 may correspond to a host system (e.g., Figure 1 ) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 110), or may be used to execute operations of the controller (eg, execute an operating system to execute operations corresponding to Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a local area network (LAN), an intranet, an extranet, and / or the Internet. The computer may operate as a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0084] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a network switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by the machine. Further, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0085] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630.

[0086] The processing device 602 represents one or more general purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device 602 may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. The processing device 602 may also be one or more special purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. The computer system 600 may further include a network interface device 608 for communicating over a network 620.

[0087] The data storage system 618 may include a machine-readable storage medium 624 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 626 or software embodying any one or more of the methodologies or functions described herein. During execution of the instructions 626 by the computer system 600, the instructions 626 may also reside, in whole or in part, within the main memory 604 and / or within the processing device 602, which also constitute machine-readable storage media. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 may correspond to Figure 1 Memory subsystem 110.

[0088] In one embodiment, instructions 626 include instructions to implement instructions corresponding to a firmware slot manager (e.g., Figure 1 The functionality of the error handling module 122 of the present disclosure is provided. Although the machine-readable storage medium 624 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0089] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here and generally considered to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily for common sense reasons, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0090] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) numbers within the computer system's registers and memories into physical quantities similarly represented as within the computer system's memories or registers or other such information storage systems.

[0091] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specifically constructed for the intended purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer readable storage medium, such as, but not limited to, any type of magnetic disk, including floppy disks, optical disks, CD-ROMs, and magneto-optical disks; read-only memory (ROM); random access memory (RAM); erasable programmable read-only memory (EPROM); EEPROM; magnetic or optical cards or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0092] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. The structures of various these systems will appear as set forth in the above description. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that the teachings of the present disclosure as described herein may be implemented using various programming languages.

[0093] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine-readable (e.g., computer-readable) storage medium, such as a read-only memory (ROM), a random access memory (RAM), a magnetic disk storage medium, an optical storage medium, a flash memory component, and the like.

[0094] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments of the present disclosure. It will be apparent that various modifications may be made thereto without departing from the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A system comprising: a memory subsystem comprising a set of memory components; and A processing device operably coupled to the set of memory components and configured to perform operations including: Receive key event trigger data; determining whether the critical event trigger data corresponds to a fatal condition; as well as An error handling mode is selected from a plurality of error handling modes based on determining whether the critical event trigger data corresponds to the fatal condition, a first of the plurality of error handling modes corresponding to storing a first set of debug information associated with the memory subsystem, and a second of the plurality of error handling modes corresponding to storing a second set of debug information associated with the memory subsystem without interrupting a host, the second set being a subset of the first set of debug information.

2. The system of claim 1, wherein the first set of debug information includes a state of the memory subsystem representing a state of at least one of one or more data structures, one or more queues, or one or more state machines.

3. The system of claim 1 , wherein the critical event trigger data comprises at least one of a non-volatile memory express (NVMe) command timeout being triggered, a cyclic redundancy code (CRC) error exceeding a CRC threshold, a PCIe AXI error event, an uncorrectable error (UE) event, a read or write completion latency exceeding a read or write threshold, a reset event information, or a memory parity error exceeding a parity threshold.

4. The system of claim 1, wherein the operations comprise: selecting the first of the plurality of error handling modes in response to determining that the critical event trigger data corresponds to the fatal condition; as well as An interrupt signal is transmitted to the host to initiate a debug operation in response to selecting the first of the plurality of error handling modes.

5. The system of claim 1, wherein the operations comprise: The second one of the plurality of error handling modes is selected in response to determining that the critical event trigger data corresponds to a non-fatal condition.

6. The system of claim 5, wherein the operations include: generating the second set of debugging information according to a specified format; as well as The second set of debug information is stored on the set of memory components.

7. The system of claim 6, wherein the operations include: Initializing a timer for storing the second set of debugging information; Determining that the timer has reached a threshold; as well as A determination is made as to whether the second set of debug information has been successfully saved on the set of memory components in response to determining that the timer has reached the threshold.

8. The system of claim 7, wherein the operations include: In response to determining that the second set of debug information has not been successfully saved on the set of memory components after the timer has reached the threshold, the first set of debug information is generated.

9. The system of claim 1, wherein the operations comprise: resetting the memory subsystem; storing the first set of adaptation information or the second set of debug information on the set of memory components; as well as In response to determining that the first of the plurality of error handling modes has been selected, a set of operations of the memory subsystem is restricted to operations performed in a basic functional mode.

10. The system of claim 1, wherein the operations comprise: reserving a first portion of the set of memory components for storing one or more instances of the first set of debug information; as well as A second portion of the set of memory elements is reserved for storing one or more instances of the second set of debug information.

11. The system of claim 1 , wherein the operations comprise: storing one or more instances of array debug information in a reserved portion of the set of memory elements; receiving a new instance of a set of individual debug information corresponding to the selected error handling mode; as well as A target instance of the one or more instances stored in the reserved portion of the set of memory components is replaced with the new instance of the set of individual debug information.

12. The system of claim 11, wherein the operations comprise: A determination is made that a value associated with the target example is lower than a value associated with the new example, wherein the target example is replaced in response to determining that the value associated with the target example is lower than the value associated with the new example.

13. The system of claim 12, wherein determining that the value associated with the target example is lower than the value associated with the new example comprises: A determination is made as to whether one or more conditions for replacing the target instance are satisfied.

14. The system of claim 13, wherein the one or more conditions include a power cycle count, a power-on time, or a count associated with an input / output command.

15. The system of claim 13, wherein the target instance is replaced in response to determining that a power cycle count representing a number of times the memory subsystem has been power cycled exceeds a power cycle threshold.

16. The system of claim 13, wherein the operations include preventing replacement of the target instance with the new instance in response to determining that a power cycle count representing a number of times the memory subsystem has been power cycled has failed to exceed a power cycle threshold.

17. The system of claim 13, wherein the target instance is replaced in response to determining that the memory subsystem has been powered on for more than a threshold period of time and an average number of input / output command completion rates exceeds a threshold rate.

18. The system of claim 13, wherein the target instance is replaced in response to determining that the memory subsystem has been powered on for more than a threshold period of time and a number of input / output commands completed since the target instance was stored exceeds a threshold.

19. A method comprising: Receive key event trigger data; determining whether the critical event trigger data corresponds to a fatal condition; as well as An error handling mode is selected from a plurality of error handling modes based on determining whether the critical event trigger data corresponds to the fatal condition, a first of the plurality of error handling modes corresponding to storing a first set of debug information associated with a memory subsystem, and a second of the plurality of error handling modes corresponding to storing a second set of debug information associated with the memory subsystem without interrupting a host, the second set being a subset of the first set of debug information.

20. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: Receive key event trigger data; determining whether the critical event trigger data corresponds to a fatal condition; as well as An error handling mode is selected from a plurality of error handling modes based on determining whether the critical event trigger data corresponds to the fatal condition, a first of the plurality of error handling modes corresponding to storing a first set of debug information associated with a memory subsystem, and a second of the plurality of error handling modes corresponding to storing a second set of debug information associated with the memory subsystem without interrupting a host, the second set being a subset of the first set of debug information.

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