Inductive structures, filters

Abstract

The application provides an inductance structure and a filter, and relates to the technical field of passive devices. The inductance structure comprises a dielectric substrate, a first conductive structure and a second conductive structure. The dielectric substrate has a plurality of connecting vias penetrating through the thickness of the dielectric substrate in a mode along the thickness, and a connecting electrode is arranged in the connecting via. The first conductive structure and the second conductive structure are electrically connected through the connecting electrode to form a coil of the inductance structure. One of the first conductive structure and the second conductive structure comprises at least three sub-layers, and the other comprises at least one sub-layer. The orthographic projections of two sub-layers in the first conductive structure and the second conductive structure on the dielectric substrate at least partially overlap, and the flowing direction of the current is substantially parallel. The inductance structure is used for preparing a high-performance filter.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an inductor structure and a filter. Background Technology

[0002] With the rapid development of electronic communication technology and the increasing prevalence of 5G technology, the frequency range of signal transmission is becoming wider and wider, greatly improving the speed of signal transmission between devices and promoting the high-speed development of social information transmission. At the same time, various new process technologies are constantly emerging, and integration technology is developing rapidly. More and more devices are integrated into small-sized chips, which on the one hand significantly reduces the size of electronic devices, and on the other hand enriches the various media functions within the devices. Device size has achieved an iteration from the macroscopic centimeter size to the microscopic micrometer and even nanometer size.

[0003] 5G technology first expands the range of signal transmission, and the significant increase in signal frequency places higher demands on the electronic components within the devices. Currently, there is an urgent need for an inductor structure that is small in size and has a high inductance value. Summary of the Invention

[0004] The embodiments of this application adopt the following technical solutions:

[0005] In a first aspect, embodiments of this application provide an inductor structure, comprising:

[0006] A dielectric substrate having a plurality of through-holes extending along its thickness, wherein a connection electrode is disposed in the through-holes, and the dielectric substrate further comprising a first surface and a second surface disposed opposite to each other along its thickness direction.

[0007] A first conductive structure is disposed on the first surface;

[0008] A second conductive structure is disposed on the second surface;

[0009] The first conductive structure and the second conductive structure are electrically connected through the connecting electrode to form the coil of the inductor structure; one of the first conductive structure and the second conductive structure includes at least three sub-layers, and the other includes at least one sub-layer; the orthographic projections of two of the sub-layers in the first conductive structure and the second conductive structure on the dielectric substrate at least partially overlap, and the current flow directions are substantially parallel.

[0010] In at least one embodiment provided in this application, the sublayer in the first conductive structure is referred to as the first conductive sublayer, and the sublayer in the second conductive structure is referred to as the second conductive sublayer.

[0011] Wherein, the first conductive structure includes at least three first conductive sublayers, and the second conductive structure includes at least three second conductive sublayers;

[0012] Alternatively, the first conductive structure may include at least three first conductive sublayers, and the second conductive structure may include one second conductive sublayer.

[0013] In at least one embodiment provided in this application, the orthographic projections of at least two of the first conductive layers on the dielectric substrate at least partially overlap, and the current flow directions of the two layers are parallel.

[0014] In at least one embodiment provided in this application, at least one orthogonal projection of the first conductive sublayer on the dielectric substrate and the orthogonal projection of the second conductive sublayer on the dielectric substrate at least partially overlap, and the current flow directions of the two are parallel.

[0015] In at least one embodiment provided in this application, where the first conductive structure includes at least three first conductive sublayers and the second conductive structure includes one second conductive sublayer,

[0016] The first conductive structure includes an even number of first conductive sublayers, at least two of which have their orthographic projections on the dielectric substrate at least partially overlapping and have the same current flow direction.

[0017] In at least one embodiment provided in this application, at least one orthogonal projection of the first conductive sublayer on the dielectric substrate and the orthogonal projection of the second conductive sublayer on the dielectric substrate at least partially overlap, and the current flow directions of the two are the same.

[0018] In at least one embodiment provided in this application, where the first conductive structure includes at least three first conductive sublayers and the second conductive structure includes one second conductive sublayer,

[0019] The first conductive structure includes an odd number of first conductive sublayers, at least two of which have orthographic projections on the dielectric substrate that at least partially overlap and whose current flow directions are opposite.

[0020] In at least one embodiment provided in this application, at least one orthogonal projection of the first conductive sublayer on the dielectric substrate at least partially overlaps with the orthogonal projection of the second conductive sublayer on the dielectric substrate, and the current flow directions of the two are opposite.

[0021] In at least one embodiment provided in this application, the first conductive structure includes a first first conductive sublayer, a second first conductive sublayer, a third first conductive sublayer, and a fourth first conductive sublayer disposed sequentially along a direction away from the dielectric substrate;

[0022] The first first conductive sublayer includes a plurality of first traces extending along a first direction and arranged along a second direction, and the fourth first conductive sublayer includes a plurality of second traces extending along the first direction and arranged along the second direction; the first direction and the second direction intersect; the orthographic projections of the first traces and the second traces on the dielectric substrate at least partially overlap.

[0023] The second first conductive sublayer includes a third trace, and the third first conductive sublayer includes a plurality of fourth traces extending along a third direction and arranged along a fourth direction; the second conductive sublayer includes a plurality of fifth traces extending along the third direction and arranged along the fourth direction; the third direction and the fourth direction intersect; the orthographic projections of the fourth traces and the fifth traces on the dielectric substrate at least partially overlap; the first direction and the third direction intersect.

[0024] In at least one embodiment provided in this application, the inductor structure includes N first traces arranged in the same row and N second traces arranged in the same row, wherein N is a positive integer and N is greater than or equal to 1; the orthographic projections of the Nth first trace and the Nth second trace on the dielectric substrate overlap and the current flow direction is the same;

[0025] The two connection electrodes are grouped together, and the same connection electrode group is in contact with the same fifth trace; the same connection electrode group includes a first connection electrode and a second connection electrode, the region where the first connection electrode is located overlaps with the orthographic projection of the first end of the fourth trace on the dielectric substrate, and the region where the second connection electrode is located overlaps with the orthographic projection of the second end of the fourth trace on the dielectric substrate; the current flow directions of the first connection electrode and the second connection electrode in the same connection electrode group are opposite.

[0026] In at least one embodiment provided in this application, the inductor structure further includes N fourth traces arranged in the same row and N+1 fifth traces arranged in the same row; the orthographic projections of the Nth fourth trace and the N+1th fifth trace on the dielectric substrate overlap, and the current flow direction is the same.

[0027] In at least one embodiment provided in this application, on the first surface, the second end of the first first trace and the second end of the first second trace are respectively electrically connected to the first end of the first fourth trace, and the first end of the second first trace and the first end of the second second trace are respectively electrically connected to the second end of the first fourth trace.

[0028] The second end of the Nth first trace and the second end of the Nth second trace are electrically connected to the first end of the Nth fourth trace, and the first end of the (N+1)th first trace and the first end of the (N+1)th second trace are electrically connected to the second end of the Nth fourth trace.

[0029] In at least one embodiment provided in this application, the inductor structure includes N+1 sets of connection electrodes arranged in the same row, the first end of the third trace is electrically connected to the N+1th second connection electrode, and the second end of the third trace is electrically connected to the first end of the first first trace and the first end of the first second trace, respectively.

[0030] The first end of the first first trace and the first end of the first second trace are electrically connected to the first second connection electrode, respectively; the first end of the first first trace and the first end of the first second trace are electrically connected to the second first connection electrode, respectively; the first end of the Nth first trace and the first end of the Nth second trace are electrically connected to the Nth second connection electrode, respectively; the second end of the Nth first trace and the second end of the Nth second trace are electrically connected to the (N+1)th first connection electrode, respectively.

[0031] In at least one embodiment provided in this application, the orthographic projection of the third trace, except for its first and second ends, onto the dielectric substrate does not overlap with the area where the connecting electrode group is located.

[0032] In at least one embodiment provided in this application, the inductor structure further includes N+1 fourth traces arranged in the same row and N+1 fifth traces arranged in the same row;

[0033] The orthographic projections of the Nth fourth trace and the Nth fifth trace on the dielectric substrate overlap, and the current flow direction is the same.

[0034] In at least one embodiment provided in this application, on the first surface, the second end of the first fourth trace is electrically connected to the first end of the first first trace and the first end of the first second trace, respectively; the first end of the (N+1)th fourth trace is electrically connected to the second end of the Nth first trace and the second end of the Nth second trace, respectively; and the second end of the (N+1)th fourth trace is electrically connected to the first end of the (N+1)th first trace and the first end of the (N+1)th second trace, respectively.

[0035] In at least one embodiment provided in this application, the inductor structure includes N+1 sets of connection electrodes arranged in the same row, the first end of the third trace is electrically connected to the N+1th second connection electrode, and the second end of the third trace is electrically connected to the first end of the first fourth trace.

[0036] In at least one embodiment provided in this application, the orthographic projections of each of the first traces, each of the second traces, each of the fourth traces, and each of the fifth traces on the dielectric substrate overlap with the orthographic projection of the third trace on the dielectric substrate.

[0037] In at least one embodiment provided in this application, the first conductive structure includes a first first conductive sublayer, a third first conductive sublayer, and a fourth first conductive sublayer disposed sequentially along a direction away from the dielectric substrate;

[0038] The first first conductive sublayer includes a plurality of first traces extending along a first direction and arranged along a second direction, and the fourth first conductive sublayer includes a plurality of second traces extending along the first direction and arranged along the second direction; the first direction and the second direction intersect; the orthographic projections of the first traces and the second traces on the dielectric substrate at least partially overlap.

[0039] The third first conductive sublayer includes a plurality of fourth traces extending along a third direction and arranged along a fourth direction, and the second conductive sublayer includes a plurality of fifth traces extending along the third direction and arranged along the fourth direction; the third direction and the fourth direction intersect; the orthographic projections of the fourth traces and the fifth traces on the dielectric substrate at least partially overlap; the first direction and the third direction intersect.

[0040] In at least one embodiment provided in this application, the inductor structure includes N first traces arranged in the same row, N second traces arranged in the same row, N+1 fourth traces arranged in the same row, and N+1 fifth traces arranged in the same row; wherein, N is a positive integer, and N is greater than or equal to 1;

[0041] The orthographic projections of the Nth first trace and the Nth second trace on the dielectric substrate overlap, and the current flow directions are opposite; the orthographic projections of the Nth fourth trace and the Nth fifth trace on the dielectric substrate overlap, and the current flow directions are opposite.

[0042] The two connection electrodes are grouped together, and the same connection electrode group is in contact with the same fifth trace; the same connection electrode group includes a first connection electrode and a second connection electrode, the region where the first connection electrode is located overlaps with the orthographic projection of the first end of the fourth trace on the dielectric substrate, and the region where the second connection electrode is located overlaps with the orthographic projection of the second end of the fourth trace on the dielectric substrate; the current flow directions of the first connection electrode and the second connection electrode in the same connection electrode group are opposite.

[0043] In at least one embodiment provided in this application, the first first connection electrode is electrically connected to the first end of the first fourth trace and the first end of the first first trace, the second end of the first fourth trace is electrically connected to the first second connection electrode, the second end of the first first trace is electrically connected to the second second connection electrode and the first end of the first second trace, and the second end of the first second trace is electrically connected to the first end of the first first trace and the first end of the first fourth trace.

[0044] The Nth first connecting electrode is electrically connected to the first end of the Nth fourth trace and the first end of the Nth first trace, respectively. The second end of the Nth fourth trace is electrically connected to the Nth second connecting electrode. The second end of the Nth first trace is electrically connected to the (N+1)th second connecting electrode and the first end of the Nth second trace, respectively. The second end of the Nth second trace is electrically connected to the first end of the Nth first trace and the first end of the Nth fourth trace, respectively.

[0045] In at least one embodiment provided in this application, the inductor structure further includes a first insulating layer, a second insulating layer, a third insulating layer, a first protective layer, and a second protective layer;

[0046] The first insulating layer is located between the first first conductive sublayer and the second first conductive sublayer, the second insulating layer is located between the second first conductive sublayer and the third first conductive sublayer, and the third insulating layer is located between the third first conductive sublayer and the fourth first conductive sublayer.

[0047] The first protective layer covers the fourth first conductive sublayer, and the second protective layer covers the second conductive sublayer.

[0048] In at least one embodiment provided in this application, the inductor structure further includes a first insulating layer, a third insulating layer, a first protective layer, and a second protective layer;

[0049] The first insulating layer is located between the first first conductive sublayer and the third first conductive sublayer, and the third insulating layer is located between the third first conductive sublayer and the fourth first conductive sublayer;

[0050] The first protective layer covers the fourth first conductive sublayer, and the second protective layer covers the second conductive sublayer.

[0051] In at least one embodiment provided in this application, the thickness of the first conductive sublayer and the second conductive sublayer both range from 1 μm to 10 μm.

[0052] In at least one embodiment provided in this application, the connecting electrode comprises a metallic material;

[0053] Alternatively, the connecting electrode may comprise resin and a metal material encapsulating the resin.

[0054] In at least one embodiment provided in this application, at least one of the first trace, the second trace, the fourth trace, and the fifth trace includes multiple sub-traces arranged in parallel, with a gap between adjacent sub-traces, and each sub-traces having approximately the same line width.

[0055] In at least one embodiment provided in this application, the included angle between the first direction and the third direction is an acute angle.

[0056] In at least one embodiment provided in this application, the third trace includes multiple sub-traces arranged in parallel, with a gap between adjacent sub-traces, and each sub-trace has a line width that is approximately the same.

[0057] In at least one embodiment provided in this application, the linewidth of the third trace is smaller than the linewidths of the first trace, the second trace, and the fourth trace.

[0058] Secondly, embodiments of this application provide a filter including at least one inductor structure as described in any one of the first aspects and at least one capacitor.

[0059] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0060] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0061] Figure 1 and Figure 3 These are schematic diagrams of the first inductor structure provided in the embodiments of this application;

[0062] Figure 2 for Figure 1 A schematic diagram of the intermediate structure of the inductor structure without the fourth first conductive layer;

[0063] Figure 4 for Figure 1 The right view;

[0064] Figure 5 for Figure 1 A top view of the first conductive structure in the inductor structure shown;

[0065] Figure 6 for Figure 1 A top view;

[0066] Figure 7 A schematic diagram of the intermediate structure of the second inductor structure provided in the embodiments of this application when the third and fourth first conductive sublayers are not provided;

[0067] Figure 8 A schematic diagram of a second inductor structure provided for an embodiment of this application;

[0068] Figure 9 for Figure 8 The right view;

[0069] Figure 10 for Figure 8 A top view of the first conductive structure in the inductor structure shown;

[0070] Figure 11 A schematic diagram of the intermediate structure of the third inductor structure provided in the embodiments of this application when the fourth first conductive layer is not provided;

[0071] Figure 12 A schematic diagram of a third inductor structure provided for an embodiment of this application;

[0072] Figure 13 for Figure 12 A top view of the first conductive structure in the inductor structure shown;

[0073] Figure 14 for Figure 12 The right view;

[0074] Figure 15 This is a schematic diagram of the structure of a filter;

[0075] Figures 16A-16H This is a schematic diagram of the intermediate structure during the fabrication process of an inductor structure provided in an embodiment of this application. Specific Implementation

[0076] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0077] In the embodiments of this application, the terms "first", "second", "third", "fourth" are used to distinguish the same or similar items with essentially the same function and effect, only for the purpose of clearly describing the technical solution of the embodiments of this application, and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

[0078] In the embodiments of this application, the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0079] In the description of this specification, the terms "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0080] In the embodiments of this application, "multiple" means two or more, and "at least one" means one or more, unless otherwise explicitly defined.

[0081] The features such as "parallel," "perpendicular," and "identical" used in the embodiments of this application include features in the strict sense of "parallel," "perpendicular," and "identical," as well as cases where "approximately parallel," "approximately perpendicular," and "approximately identical" include certain tolerances. Taking into account the measurement and the tolerances associated with the measurement of a specific quantity (e.g., limitations of the measurement system), they represent the acceptable deviation range for a specific value as determined by a person skilled in the art. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of said value.

[0082] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and encompassing, that is, "including, but not limited to".

[0083] In this application, "same layer" refers to the relationship between multiple film layers formed from the same material after undergoing the same step (e.g., a patterning process). "Same layer" here does not always mean that multiple film layers have the same thickness or the same height in a cross-sectional view. The polygons used in this specification are not strictly defined; they can be approximate triangles, parallelograms, trapezoids, pentagons, or hexagons, and may have minor deformations due to tolerances.

[0084] With the rapid development of electronic communication technology and the increasing prevalence of 5G technology, the frequency range of signal transmission is becoming wider and wider, greatly improving the speed of signal transmission between devices and promoting the high-speed development of social information transmission. At the same time, various new process technologies are constantly emerging, and integration technology is developing rapidly. More and more devices are integrated into small-sized chips, which on the one hand significantly reduces the size of electronic devices, and on the other hand enriches the various media functions within the devices. Device size has achieved an iteration from the macroscopic centimeter size to the microscopic micrometer and even nanometer size.

[0085] 5G technology firstly expands the range of signal transmission, and the significant increase in signal frequency places higher demands on the electronic components within devices, especially in common mobile terminals. Secondly, the increased signal frequency requires electronic components to transmit signals better and faster, necessitating further increases in the rated power of devices. Achieving higher performance per unit volume has become a new goal.

[0086] The development of IPD (Integrated Passive Device) technology has greatly improved device integration, becoming a manufacturing method that meets the requirements of electronic communication technology development. This process has changed traditional process dimensions and placed higher demands on the design of passive devices. Traditional copper wire-wound inductors have been replaced by planar spiral inductors. With the development of substrate processing technology, 3D inductors have also been greatly developed. These passive devices can be used in discrete devices as well as in RF modules. Therefore, the improvement of IPD device performance will contribute to the further development of RF technology.

[0087] Based on this, embodiments of this application provide an inductor structure and filter based on IPD technology. The inductor structure includes a dielectric substrate, a first conductive structure disposed on a first surface, and a second conductive structure disposed on a second surface. The dielectric substrate has a plurality of connecting vias extending along its thickness, and connecting electrodes are disposed within the connecting vias. The first and second conductive structures are electrically connected through the connecting electrodes to form a coil of the inductor structure. One of the first and second conductive structures includes at least three sublayers, and the other includes at least one sublayer. The orthographic projections of two sublayers of the first and second conductive structures onto the dielectric substrate at least partially overlap, and the current flow directions are approximately parallel. The inductor structure provided by embodiments of this application, under existing fabrication process conditions, can significantly improve the inductance value and inductance density per unit volume, and reduce the size of the inductor structure through design changes. This allows for wider and more flexible applications of the inductor structure, and improves its performance without increasing the difficulty or cost of the fabrication process.

[0088] The inductor structure and filter provided in the embodiments of this application will be described and explained in detail below with reference to the accompanying drawings.

[0089] Embodiments of this application provide an inductor structure, such as Figure 4 , Figure 9 and Figure 14 As shown, it includes:

[0090] The dielectric substrate 1 has a plurality of connection vias Via that extend through its thickness, and connection electrodes DJ are disposed in the connection vias. The dielectric substrate 1 also includes a first surface B1 and a second surface B2 disposed opposite to each other along its thickness direction.

[0091] The first conductive structure 6 is disposed on the first surface B1;

[0092] The second conductive structure 7 is disposed on the second surface B2;

[0093] The first conductive structure 6 and the second conductive structure 7 are electrically connected via connecting electrode DJ to form a coil of inductor structure; one of the first conductive structure 6 and the second conductive structure 7 includes at least three sub-layers, and the other includes at least one sub-layer (e.g., combined with...). Figure 1 and Figure 4 As shown, the first conductive structure 6 includes sublayers D1-1, D1-2, D1-3, and D1-4; the second conductive structure 7 includes sublayer D2; the orthographic projections of two of the sublayers in the first conductive structure 6 and the second conductive structure 7 on the dielectric substrate 1 at least partially overlap, and the current flow directions are approximately parallel.

[0094] The main material of the dielectric substrate 1 is an insulating material, and the specific type of material of the dielectric substrate 1 is not limited here.

[0095] In some embodiments, the main material of the dielectric substrate 1 may be a rigid material.

[0096] For example, the dielectric substrate 1 can be a standard silicon wafer with embedded chips, a high-resistivity silicon substrate, a glass substrate, a ceramic substrate, or a low-k molding material with embedded chips in the eWLB (embedded wafer-level ball grid array) packaging process.

[0097] In other embodiments, the primary material of the dielectric substrate 1 may be a flexible material.

[0098] For example, the dielectric substrate 1 may be a polyimide (PI) substrate or a bisbenzocyclobutene (BCB) substrate.

[0099] The dimensions and thickness of the dielectric substrate 1 described above are not limited here.

[0100] For example, the thickness of the dielectric substrate 1 can be in the range of 0.2 mm to 0.5 mm, for example, 0.3 mm or 0.4 mm.

[0101] The aforementioned multiple connection vias (Via) refer to two or more connection vias (Via), wherein the connection vias (Via) are filled with at least conductive material to form connection electrodes (DJ). Therefore, the structure of the connection vias (Via) is not directly shown in the accompanying drawings provided in the embodiments of this application.

[0102] The specific number of the aforementioned Via (or DJ) connection ports is not limited here.

[0103] In some embodiments, the number of the aforementioned connecting vias (or connecting electrodes DJ) is even, so that a loop is formed between the first conductive structure 6 and the second conductive structure 7 on both sides of the dielectric substrate 101. For example, the number of the aforementioned connecting vias (or connecting electrodes DJ) can be two, four, six, eight, etc.

[0104] The three-dimensional shape of the aforementioned connecting via is not limited here. For example, the three-dimensional shape of the aforementioned connecting via can be cylindrical, such as a cylinder or a prism; for example, the three-dimensional shape of the aforementioned connecting via can be frustum-shaped or frustum-shaped.

[0105] The shape of the cross-sectional shape of the aforementioned connecting via is not limited here. For example, the cross-sectional shape of the connecting via can be quadrilateral, such as rectangle, square, or trapezoid.

[0106] The number and shape of the connecting electrodes DJ are related to the number and shape of the connecting vias Via, which will not be elaborated here.

[0107] The dimensions of the planar pattern of the aforementioned Via connection are not limited here. For example, the planar pattern of the Via connection is approximately circular, wherein the diameter of the circle ranges from 30μm to 100μm. For example, the diameter of the circle is 33μm, 35μm, 40μm, 43μm, 45μm, 48μm, 55μm, 60μm, 63μm, 65μm, 68μm, 70μm, 75μm, 78μm, 80μm, 86μm, 88μm, 90μm, 93μm, 95μm, or 98μm.

[0108] For example, when the planar shape of the connecting via is a polygon, the size of the maximum diagonal of the polygon ranges from 30μm to 100μm. For example, the size of the maximum diagonal of the polygon is 33μm, 35μm, 40μm, 43μm, 45μm, 48μm, 55μm, 60μm, 63μm, 65μm, 68μm, 70μm, 75μm, 78μm, 80μm, 86μm, 88μm, 90μm, 93μm, 95μm, or 98μm.

[0109] For example, when the three-dimensional shape of the connecting via is frustum or truncated cone, the dimensions of the planar patterns of the upper and lower openings of the connecting via are different. In this case, the dimensions of the planar patterns of the upper and lower openings are both in the range of 30μm to 100μm.

[0110] For example, the three-dimensional shape of the Via can be the shape of two frustum or pyramidal structures joined together (hourglass shape). That is, the three-dimensional shape of the Via has an upper and lower opening that are larger than the size of the planar shape in the middle area. It can be understood that the cross-sectional shape is the shape of two trapezoids joined together, wherein the upper base of the upper trapezoid is joined together with the upper base of the lower trapezoid, and the lower bases of the two trapezoids are located on both sides.

[0111] In an exemplary embodiment, the first surface B1 and the second surface B2 described above may be parallel to each other (generally parallel). Exemplarily, both the first surface B1 and the second surface B2 may be planar.

[0112] The shape of the specific conductive patterns of the first conductive structure 6 and the second conductive structure 7 is not limited here. For example, the orthographic projections of the conductive patterns in the first conductive structure 6 and the conductive patterns in the second conductive structure 7 onto the dielectric substrate 1 at least partially overlap, wherein "at least partially overlap" includes, but is not limited to, partial overlap and complete overlap.

[0113] The specific materials of the first conductive structure 6 and the second conductive structure 7 described above are not limited here. For example, the materials of the first conductive structure 6 and the second conductive structure 7 may include any one of copper, silver, aluminum, nickel, molybdenum and titanium, or a combination of several metals stacked together.

[0114] In an exemplary embodiment, one of the first conductive structure 6 and the second conductive structure 7 includes at least three sublayers, and the other includes at least one sublayer, including but not limited to the following:

[0115] First, the first conductive structure 6 includes at least three sublayers, and the second conductive structure 7 includes at least one sublayer.

[0116] For example, the first conductive structure 6 includes at least three sublayers, and the second conductive structure 7 includes one sublayer. In this case, the sublayers in the first conductive structure 6 are electrically connected to each other to serve as a first conductor.

[0117] For example, the first conductive structure 6 includes at least three sub-layers, and the second conductive structure 7 includes at least three sub-layers. In this case, the sub-layers in the first conductive structure 6 are electrically connected to each other to serve as a first conductor; the sub-layers in the second conductive structure 7 are electrically connected to each other to serve as a second conductor. The first conductor and the second conductor are electrically connected through the connecting electrode DJ to form a conductive loop and constitute a coil of inductor structure.

[0118] Second, the second conductive structure 7 includes at least three sublayers, and the first conductive structure 6 includes at least one sublayer.

[0119] For example, the second conductive structure 7 includes at least three sublayers, and the first conductive structure 6 includes one sublayer. In this case, the sublayers in the second conductive structure 7 are electrically connected to each other to serve as a second conductor.

[0120] For example, the second conductive structure 7 includes at least three sub-layers, and the first conductive structure 6 includes at least three sub-layers. In this case, the sub-layers in the first conductive structure 6 are electrically connected to each other to serve as a first conductor; the sub-layers in the second conductive structure 7 are electrically connected to each other to serve as a second conductor. The first conductor and the second conductor are electrically connected through the connecting electrode DJ to form a conductive loop and constitute a coil of inductance structure.

[0121] For example, the material of the at least one sublayer may include any one of copper, silver, aluminum, nickel, molybdenum and titanium, or a combination of several metals stacked together.

[0122] In some embodiments, the material of the at least one sublayer may include a molybdenum nickel-titanium alloy (MoNiTi) layer, a copper metal layer, and a molybdenum niobium alloy (MoNb) layer stacked sequentially. The molybdenum nickel-titanium alloy layer can increase the nucleation density of copper metal grains in the electroplating process, and the molybdenum niobium alloy layer can prevent copper metal oxidation.

[0123] In other embodiments, the aforementioned at least one sublayer may include a molybdenum-niobium alloy layer, a copper metal layer, and a protective layer stacked sequentially. The protective layer may include any one of copper-nickel alloy (CuNi), nickel, or indium tin oxide (ITO). The molybdenum-niobium alloy layer enhances the adhesion between the copper metal and the film layer near the dielectric substrate 1, while the protective layer prevents oxidation of the copper metal.

[0124] In some embodiments, the thickness of the at least one sublayer can range from 0.5 to 10 μm, for example, the thickness can be 0.5 μm, 1 μm, 1.8 μm, 2.7 μm or 10 μm.

[0125] In other embodiments, the thickness of the at least one sublayer may range from 1.5 μm to 7 μm, for example, the thickness may be 1.5 μm, 2 μm, 4 μm, 6.5 μm or 7 μm.

[0126] Wherein, the orthographic projections of two sublayers of the first conductive structure 6 and the second conductive structure 7 onto the dielectric substrate 1 at least partially overlap, and the current flow directions are substantially parallel, including but not limited to the following:

[0127] The first type, the first conductive structure 6 includes at least three sub-layers, wherein the orthographic projections of two sub-layers in the first conductive structure 6 on the dielectric substrate 1 at least partially overlap, and the current flow directions are approximately parallel.

[0128] The second type, the second conductive structure 7 includes at least three sub-layers, wherein the orthographic projections of two sub-layers in the second conductive structure 7 on the dielectric substrate 1 at least partially overlap, and the current flow directions are generally parallel.

[0129] The third type involves a first conductive structure 6 comprising at least three sublayers and a second conductive structure 7 comprising at least one sublayer; or, a first conductive structure 6 comprising at least one sublayer and a second conductive structure 7 comprising at least three sublayers. The orthographic projections of one sublayer of the first conductive structure 6 and one sublayer of the second conductive structure 7 onto the dielectric substrate 1 at least partially overlap, and the current flow directions are substantially parallel.

[0130] It should be noted that the above "at least partially overlapping" includes partial or complete overlap.

[0131] The above-mentioned parallel flow directions of current can include two cases: the flow directions of current are the same (i.e., identical) or the flow directions of current are opposite.

[0132] The theoretical formulas for calculating inductance and mutual inductance are provided below:

[0133]

[0134]

[0135] Where LZ represents the inductance value of the inductor structure, L M This represents the mutual inductance value in the inductor structure. Increasing the mutual inductance value will increase the overall inductance value of the inductor structure.

[0136] In the above formula (1), μ is the magnetic permeability of the material of the dielectric substrate 1. The wires provided in the first conductive structure 6 are called the first wires, the wires provided in the second conductive structure 7 are called the second wires, and the connecting electrode DJ is the third wire. For the first conductive structure 6 and the second conductive structure 7, L represents the effective length of the wire, W represents the width of the wire, and t represents the thickness of the wire. For the connecting electrode DJ, taking the columnar connecting electrode DJ as an example, W represents the diameter of the circle when the planar shape is circular, t represents the height of the columnar connecting electrode DJ, and L also represents the diameter of the circle.

[0137] In the above formula (2), μ is the magnetic permeability of the material of the dielectric substrate 1. The wires provided in the first conductive structure 6 are called the first wires, the wires provided in the second conductive structure 7 are called the second wires, and the connecting electrode DJ is the third wire. L represents the effective length of the wire, W represents the width of the wire, t represents the thickness of the wire, and D represents the spacing between the wires. For the connecting electrode DJ, taking the columnar connecting electrode DJ as an example, W represents the diameter of the circle when the planar shape is circular, t represents the height of the columnar connecting electrode DJ, L also represents the diameter of the circle, and D represents the spacing between the connecting electrodes DJ.

[0138] It should be noted that when the current directions of two conductive structures are in the same direction, the larger the area of ​​their overlapping region, the greater the mutual inductance.

[0139] In the inductor structure provided in the embodiments of this application, reference is made to... Figure 4 or Figure 9 or Figure 14 On the one hand, by setting one of the first conductive structure 6 and the second conductive structure 7 to include at least three sub-layers, and the other to include at least one sub-layer (e.g., combined with...) Figure 1 and Figure 4 As shown, the first conductive structure 6 includes sublayers D1-1, D1-2, D1-3, and D1-4; the second conductive structure 7 includes sublayer D2. This increases the number of conductive layers constituting the conductor (coil), thereby extending the effective length of the coil forming the inductor structure, increasing the inductance density, and improving the inductance value. Furthermore, by ensuring that the orthographic projections of two sublayers in the first conductive structure 6 and the second conductive structure 7 on the dielectric substrate 1 at least partially overlap, the mutual inductance of the inductor structure can be effectively increased when the current flows in the same direction, further increasing the inductance value and improving the performance of the inductor structure. This enhances the application flexibility of the inductor structure and expands its application areas while maintaining essentially the same inductor structure dimensions.

[0140] In at least one embodiment provided in this application, combined with Figure 1 and Figure 4 As shown, the sublayer in the first conductive structure 6 is called the first conductive sublayer D1 (e.g., sublayer D1-1, sublayer D1-2, sublayer D1-3 and sublayer D1-4), and the sublayer in the second conductive structure 7 is called the second conductive sublayer D2.

[0141] In some embodiments, the first conductive structure 6 includes at least three first conductive sublayers D1, and the second conductive structure 7 includes at least three second conductive sublayers D2.

[0142] Alternatively, in some other embodiments, combined with Figure 1 and Figure 4 As shown, combined Figure 8 and Figure 9 As shown or in combination Figure 12 and Figure 14 As shown, the first conductive structure 6 includes at least three first conductive sublayers D1, and the second conductive structure 7 includes one second conductive sublayer D2.

[0143] In at least one embodiment provided in this application, the orthographic projections of at least two first conductive layers D1 on the dielectric substrate 1 at least partially overlap, and the current flow directions of the two layers are parallel.

[0144] For example, there may be two first conductive sublayers D1 whose orthogonal projections on the dielectric substrate 1 at least partially overlap, and whose current flow directions are parallel.

[0145] For example, the orthographic projections of the two first conductive sublayers D1 on the dielectric substrate 1 at least partially overlap, and the current flow directions of the two layers are consistent (the same).

[0146] For example, the orthographic projections of the two first conductive layers D1 on the dielectric substrate 1 at least partially overlap, and the current flow directions of the two layers are opposite.

[0147] For example, the orthographic projections of three first conductive sublayers D1 on the dielectric substrate 1 may at least partially overlap, and the current flow directions of the two layers may be parallel.

[0148] For example, the orthographic projections of the first and second first conductive sublayers D1 on the dielectric substrate 1 at least partially overlap, and their current flow directions are the same; the orthographic projections of the second and third first conductive sublayers D1 on the dielectric substrate 1 at least partially overlap, and their current flow directions are opposite.

[0149] For example, the orthographic projections of the three first conductive layers D1 on the dielectric substrate 1 at least partially overlap, and the current flow directions of both layers are the same.

[0150] In at least one embodiment provided in this application, the orthographic projection of at least one first conductive sublayer D1 on the dielectric substrate 1 at least partially overlaps with the orthographic projection of the second conductive sublayer D2 on the dielectric substrate 1, and the current flow directions of the two are parallel.

[0151] For example, there may be a first conductive sublayer D1 whose orthogonal projection on the dielectric substrate 1 at least partially overlaps with the orthogonal projection of the second conductive sublayer D2 on the dielectric substrate 1, and the current flow directions of the two are parallel.

[0152] For example, the orthographic projection of a first conductive sublayer D1 on the dielectric substrate 1 at least partially overlaps with the orthographic projection of a second conductive sublayer D2 on the dielectric substrate 1, and the current flow directions of the two are the same.

[0153] For example, there may be two first conductive sublayers D1 whose orthogonal projections on the dielectric substrate 1 at least partially overlap with the orthogonal projections of the second conductive sublayers D2 on the dielectric substrate 1, and the current flow directions of the two are parallel.

[0154] For example, the orthographic projection of one of the two first conductive sublayers D1 on the dielectric substrate 1 at least partially overlaps with the orthographic projection of the second conductive sublayer D2 on the dielectric substrate 1, and the current flow directions of the two are the same; the orthographic projection of the other on the dielectric substrate 1 at least partially overlaps with the orthographic projection of the second conductive sublayer D2 on the dielectric substrate 1, and the current flow directions of the two are opposite.

[0155] For example, the orthographic projections of the two first conductive sublayers D1 on the dielectric substrate 1 and the orthographic projections of the second conductive sublayer D2 on the dielectric substrate 1 at least partially overlap, and the current flow directions of both are the same.

[0156] In at least one embodiment provided in this application, when the first conductive structure 6 includes at least three first conductive sublayers D1 and the second conductive structure 7 includes one second conductive sublayer D2, when the first conductive structure 6 includes an even number of first conductive sublayers D1...

[0157] In some examples, the orthographic projections of at least two first conductive sublayers D1 on the dielectric substrate 1 at least partially overlap, and the current flow directions of the two layers are the same.

[0158] In other examples, at least one orthogonal projection of a first conductive layer D1 onto a dielectric substrate at least partially overlaps with the orthogonal projection of a second conductive layer D2 onto a dielectric substrate, and both have the same current flow direction.

[0159] For example, the first conductive structure 6 includes 4 first conductive sublayers D1, 6 first conductive sublayers D1, 8 first conductive sublayers D1, or 10 first conductive sublayers D1.

[0160] In the inductor structure provided in the embodiments of this application, one of the first conductive structure 6 and the second conductive structure 7 includes at least three sub-layers, and the other includes at least one sub-layer (e.g., combined with...). Figure 1 and Figure 4 As shown, the first conductive structure 6 includes sublayers D1-1, D1-2, D1-3, and D1-4; the second conductive structure 7 includes sublayer D2), which increases the number of conductive layers constituting the conductor (coil), thereby extending the effective length of the coil forming the inductor structure, and thus increasing the inductance density of the inductor structure and improving the inductance value.

[0161] Furthermore, when the first conductive structure 6 includes an even number of first conductive sublayers D1, by setting two of the sublayers in the first conductive structure 6 and the second conductive structure 7 to have at least partial overlap on the dielectric substrate 1, when the current flow directions of the two are the same, the mutual inductance of the inductor structure can be effectively increased, further increasing the inductance value of the inductor structure and improving the performance of the inductor structure; while keeping the inductor structure size basically unchanged, the application flexibility of the inductor structure is improved, and the application field of the inductor structure is expanded.

[0162] In at least one embodiment provided in this application, when the first conductive structure 6 includes at least three first conductive sublayers D1 and the second conductive structure 7 includes one second conductive sublayer D2, when the first conductive structure 6 includes an odd number of first conductive sublayers D1...

[0163] In some examples, the orthographic projections of at least two first conductive layers D1 on the dielectric substrate 1 at least partially overlap, and the current flow directions of the two layers are opposite.

[0164] In other examples, at least one orthogonal projection of a first conductive layer D1 onto a dielectric substrate 1 at least partially overlaps with the orthogonal projection of a second conductive layer D2 onto a dielectric substrate 1, and the current flow directions of the two layers are opposite.

[0165] For example, the first conductive structure 6 includes 3 first conductive sublayers D1, 5 first conductive sublayers D1, 7 first conductive sublayers D1, 9 first conductive sublayers D1, or 11 first conductive sublayers D1, etc.

[0166] In the inductor structure provided in the embodiments of this application, when the first conductive structure 6 includes an odd number of first conductive sublayers D1, it is achieved by setting one of the first conductive structure 6 and the second conductive structure 7 to include at least three sublayers, and the other to include at least one sublayer (e.g., combined with...). Figure 1 and Figure 4 As shown, the first conductive structure 6 includes sublayers D1-1, D1-2, D1-3, and D1-4; the second conductive structure 7 includes sublayer D2. This increases the number of conductive layers constituting the conductor (coil), thereby extending the effective length of the coil forming the inductor structure, increasing the inductance density, improving the inductance value, and enhancing the performance of the inductor structure. While maintaining a relatively constant inductor structure size, this increases the application flexibility of the inductor structure and expands its application areas.

[0167] In at least one embodiment provided in this application, combined with Figure 1 , Figure 2 , Figure 3 and Figure 4 As shown, or, in combination Figure 7 , Figure 8 and Figure 9 As shown, the first conductive structure 6 includes a first first conductive sublayer D1-1, a second first conductive sublayer D1-2, a third first conductive sublayer D1-3, and a fourth first conductive sublayer D1-4 arranged sequentially along the direction away from the dielectric substrate 1;

[0168] It should be noted that, Figure 4 yes Figure 3 The right view of the inductor structure shown. Figure 1 and Figure 3 The same inductor structure is drawn in the example. To avoid too many labels and make it unclear, the current flow direction of each trace in the inductor structure is marked on the diagram. Figure 3 middle.

[0169] Among them, combined Figure 1 , Figure 2 , Figure 3 and Figure 4 As shown, or, in combination Figure 7 , Figure 8 and Figure 9 As shown, the first first conductive sublayer D1-1 includes a plurality of first traces L1 extending along the first direction F1 and arranged along the second direction F2, and the fourth first conductive sublayer D1-4 includes a plurality of second traces L2 extending along the first direction and arranged along the second direction; the first direction F1 and the second direction F2 intersect; the orthographic projections of the first traces L1 and the second traces L2 on the dielectric substrate 1 at least partially overlap.

[0170] The second first conductive sublayer D1-2 includes a third trace L3, the third first conductive sublayer D1-3 includes a plurality of fourth traces L4 extending along a third direction F3 and arranged along a fourth direction F4, and the second conductive sublayer D2 includes a plurality of fifth traces L5 extending along a third direction F3 and arranged along a fourth direction F4; the third direction F3 and the fourth direction F4 intersect; the orthographic projections of the fourth traces L4 and the fifth traces L5 on the dielectric substrate 1 at least partially overlap; the first direction F1 and the third direction F3 intersect.

[0171] In an exemplary embodiment, the materials of the first first conductive sublayer D1-1, the second first conductive sublayer D1-2, the third first conductive sublayer D1-3, and the fourth first conductive sublayer D1-4 may all include any one of copper, silver, aluminum, nickel, molybdenum, and titanium, or a combination of several metals stacked together.

[0172] For example, at least one of the first conductive electronic layers D1 is made of a molybdenum nickel-titanium alloy (MoNiTi) layer, a copper metal layer and a molybdenum niobium alloy (MoNb) layer stacked sequentially. The molybdenum nickel-titanium alloy layer can increase the nucleation density of copper metal grains in the electroplating process, and the molybdenum niobium alloy layer can prevent copper metal oxidation.

[0173] For example, the material of the at least one first conductive electronic layer D1 may include a molybdenum-niobium alloy layer, a copper metal layer, and a protective layer stacked sequentially. The protective layer may include any one of copper-nickel alloy (CuNi), nickel, or indium tin oxide (ITO). The molybdenum-niobium alloy layer serves to improve the adhesion between the copper metal and the film layer near the dielectric substrate 1, while the protective layer serves to prevent the copper metal from oxidizing.

[0174] There is no limitation on whether the materials of the first first conductive sublayer D1-1, the second first conductive sublayer D1-2, the third first conductive sublayer D1-3, and the fourth first conductive sublayer D1-4 are the same. They can be determined according to the design requirements of the conductivity of the inductor structure.

[0175] There is no limitation on whether the length and width (also known as line width) of the first trace L1, the second trace L2, the third trace L3, the fourth trace L4, and the fifth trace are the same.

[0176] In some embodiments, the first trace L1 and the second trace L2 have the same length.

[0177] In some embodiments, the third trace L4 and the fifth trace L5 have the same length.

[0178] In some embodiments, the length of the third trace L3 is greater than the lengths of the first trace L1, the second trace L2, the third trace L4, and the fifth trace L5.

[0179] In some examples, the first trace L1 and the second trace L2 have the same line width.

[0180] In some examples, the third trace L4 and the fifth trace L5 have the same line width.

[0181] In some examples, the width of the third trace L3 is smaller than the widths of the first trace L1, the second trace L2, the third trace L4, and the fifth trace L5.

[0182] There is no limitation on whether the thicknesses of the first trace L1, the second trace L2, the third trace L3, the fourth trace L4, and the fifth trace are the same.

[0183] In some examples, at least some of the first trace L1, the second trace L2, the third trace L3, the fourth trace L4, and the fifth trace have approximately the same thickness.

[0184] In some examples, at least some of the first trace L1, the second trace L2, the third trace L3, the fourth trace L4, and the fifth trace may include straight lines;

[0185] Alternatively, at least some of the first routing line L1, the second routing line L2, the third routing line L3, the fourth routing line L4, and the fifth routing line may include arcs;

[0186] Alternatively, at least some of the first routing line L1, the second routing line L2, the third routing line L3, the fourth routing line L4, and the fifth routing line may include broken line segments composed of straight line segments;

[0187] Alternatively, at least some of the first routing line L1, the second routing line L2, the third routing line L3, the fourth routing line L4, and the fifth routing line may include a combination of straight lines and arcs.

[0188] In at least one embodiment provided in this application, combined with Figure 1 , Figure 2 and Figure 3As shown, the inductor structure includes N first traces L1 arranged in the same row and N second traces L2 arranged in the same row, where N is a positive integer and N is greater than or equal to 1; Figure 5 As shown, the orthographic projections of the Nth first trace L1 and the Nth second trace L2 on the dielectric substrate 1 overlap, and the current flow directions are the same; wherein, Figure 3 The direction indicated by the dashed arrow in the image can be the direction of current flow.

[0189] It should be noted that, in order to clearly show the positional relationship of the orthographic projections of the Nth first trace L1 and the Nth second trace L2 on the dielectric substrate 1, in Figure 5 and Figure 6 In the above examples, the orthographic projections of the Nth first trace L1 and the Nth second trace L2 on the dielectric substrate 1 are partially overlapped. In some embodiments, the orthographic projections of the Nth first trace L1 and the Nth second trace L2 on the dielectric substrate 1 can completely overlap.

[0190] In an exemplary embodiment, two connection electrodes DJ are grouped together, and the same connection electrode group is in contact with the same fifth trace L5. The same connection electrode group includes a first connection electrode DJ1 and a second connection electrode DJ2. The orthographic projection of the region where the first connection electrode DJ1 is located and the first end of the fourth trace L4 on the dielectric substrate 1 overlaps, and the orthographic projection of the region where the second connection electrode DJ2 is located and the second end of the fourth trace L4 on the dielectric substrate 1 overlaps. The current flow directions of the first connection electrode DJ1 and the second connection electrode DJ2 in the same connection electrode group are opposite.

[0191] It should be noted that in this specification, the first and second ends of each trace are named according to the direction of current flow, such as... Figure 3 Taking the current flow direction marked in the middle as an example, the current flows from the first end of the trace to the second end. The first and second ends of the first trace L1, the second trace L2, the third trace L3, the fourth trace L4, and the fifth trace L5 are named according to this rule, which will not be repeated later.

[0192] In an exemplary embodiment, such as Figure 3 As shown, the orthographic projections of the first connecting electrode DJ1 and the second connecting electrode DJ2 in the same connecting electrode group onto the film layer where the fifth trace L5 is located fall into the same region where the fifth trace L5 is located.

[0193] It should be noted that, in this specification, the first connecting electrode DJ1 and the second connecting electrode DJ2 can be determined based on the projection positions of the first and second ends of the fourth trace L4 relative to the two connecting electrodes DJ in the same connecting electrode group; wherein, the connecting electrode whose projection overlaps with the first end of the fourth trace L4 is the first connecting electrode DJ1, and the connecting electrode whose projection overlaps with the second end of the fourth trace L4 is the second connecting electrode DJ2, and the first and second ends of the fourth trace L4 are related to the current flow direction in the fourth trace L4; when the current flow direction in the fourth trace L4 is opposite, the positions of the first connecting electrode DJ1 and the second connecting electrode DJ2 are interchanged.

[0194] In at least one embodiment provided in this application, combined with Figure 1 or Figure 3 As shown, the inductor structure also includes N fourth traces L4 arranged in the same row and N+1 fifth traces L5 arranged in the same row; the orthographic projections of the Nth fourth trace L4 and the N+1 fifth trace L5 on the dielectric substrate 1 overlap, and the current flow direction is the same.

[0195] For example, the number of fifth routing lines L5 is 1 greater than the number of fourth routing lines L4.

[0196] For example, the orthographic projections of the first fourth trace L4 and the second fifth trace L5 on the dielectric substrate 1 overlap, and the current flow direction is the same; the orthographic projections of the second fourth trace L4 and the third fifth trace L5 on the dielectric substrate 1 overlap, and the current flow direction is the same; the orthographic projections of the third fourth trace L4 and the fourth fifth trace L5 on the dielectric substrate 1 overlap, and the current flow direction is the same.

[0197] In the embodiments of this application, such as Figure 3 As shown, starting from the left side of the inductor structure, the fourth trace L4 is referred to as the first fourth trace L4, the second fourth trace L4, the third fourth trace L4, and so on. The ordering of other traces such as the first trace L1, the second trace L2, and the fifth trace L5 is also done from the left side of the inductor structure.

[0198] In at least one embodiment provided in this application, combined with Figure 1 or Figure 3As shown, on the first surface B1, the second end of the first first trace L1 (the direction of the arrow is the second end) and the second end of the first second trace L1 (the direction of the arrow is the second end) are electrically connected to the first end of the first fourth trace L4 (the direction of the arrow is the first end), respectively. The first end of the second first trace L1 (the direction of the arrow is the first end) and the first end of the second second trace L2 (the direction of the arrow is the first end) are electrically connected to the second end of the first fourth trace L4 (the direction of the arrow is the second end), respectively.

[0199] The second end of the Nth first trace L1 and the second end of the Nth second trace L2 are electrically connected to the first end of the Nth fourth trace L4, and the first end of the (N+1)th first trace L1 and the first end of the (N+1)th second trace L2 are electrically connected to the second end of the Nth fourth trace L4.

[0200] For example, when N=2, the second end of the second first trace L1 and the second end of the second second trace L2 are electrically connected to the first end of the second fourth trace L4, and the first end of the third first trace L1 and the first end of the third second trace L2 are electrically connected to the second end of the second fourth trace L4.

[0201] For example, when N=3, the second end of the third first trace L1 and the second end of the third second trace L2 are electrically connected to the first end of the third fourth trace L4, and the first end of the fourth first trace L1 and the first end of the fourth second trace L2 are electrically connected to the second end of the third fourth trace L4.

[0202] For example, when N=5, the second end of the fifth first trace L1 and the second end of the fifth second trace L2 are electrically connected to the first end of the fifth fourth trace L4, and the first end of the sixth first trace L1 and the first end of the sixth second trace L2 are electrically connected to the second end of the fifth fourth trace L4.

[0203] For example, when N=6, the second end of the 6th first trace L1 and the second end of the 6th second trace L2 are electrically connected to the first end of the 6th fourth trace L4, and the first end of the 7th first trace L1 and the first end of the 7th second trace L2 are electrically connected to the second end of the 6th fourth trace L4.

[0204] In at least one embodiment provided in this application, combined with Figure 1 or Figure 3As shown, the inductor structure includes N+1 sets of connecting electrodes arranged in the same row. The first end of the third trace L3 (the direction of the arrow is the first end) is electrically connected to the N+1th second connecting electrode DJ2. The second end of the third trace L3 (the direction of the arrow is the first end) is electrically connected to the first end of the first first trace L1 (the direction of the arrow is the first end) and the first end of the first second trace L2 (the direction of the arrow is the first end), respectively. The first ends of the first first trace L1 and the first second trace L2 are electrically connected to the first second connecting electrode DJ2, respectively. The first ends of the first first trace L1 and the first second trace L2 are electrically connected to the second first connecting electrode DJ1, respectively. The first ends of the Nth first trace L1 and the Nth second trace L2 are electrically connected to the Nth second connecting electrode DJ2, respectively. The second ends of the Nth first trace L1 and the Nth second trace L2 are electrically connected to the N+1th first connecting electrode DJ1, respectively.

[0205] For example, when N=2, the first end of the second first trace L1 and the first end of the second second trace L2 are electrically connected to the second second connecting electrode DJ2, and the second end of the second first trace L1 and the second end of the second second trace L2 are electrically connected to the third first connecting electrode DJ1.

[0206] For example, when N=3, the first end of the third first trace L1 and the first end of the third second trace L2 are electrically connected to the third second connecting electrode DJ2, and the second end of the third first trace L1 and the second end of the third second trace L2 are electrically connected to the fourth first connecting electrode DJ1.

[0207] For example, when N=5, the first end of the fifth first trace L1 and the first end of the fifth second trace L2 are electrically connected to the fifth second connecting electrode DJ2, and the second end of the fifth first trace L1 and the second end of the fifth second trace L2 are electrically connected to the sixth first connecting electrode DJ1.

[0208] In at least one embodiment provided in this application, such as Figures 1-3 , Figures 5-6 As shown, the orthographic projection of the third trace L3, except for its first and second ends, onto the dielectric substrate 1 does not overlap with the area where the connecting electrode group is located.

[0209] For example, the area of ​​the third trace L3 other than its first and second ends can be referred to as the main body of the third trace L3.

[0210] In some examples, the orthographic projection of the main body of the third trace L3 on the dielectric substrate 1 does not overlap with the orthographic projections of the first trace L1, the second trace L2, the fourth trace L4, and the fifth trace L5 on the dielectric substrate 1.

[0211] In the embodiments of this application, by setting the orthographic projection of the main body of the third trace L3 on the dielectric substrate 1 to be non-overlapping with the orthographic projections of the first trace L1, the second trace L2, the fourth trace L4, and the fifth trace L5 on the dielectric substrate 1, the interference of the current in the third trace L3 on the mutual inductance between the first trace L1 and the second trace L2, and the interference of the mutual inductance between the fourth trace L4 and the fifth trace L5 can be reduced to a large extent. This maximizes the mutual inductance in the inductor structure, further increases the inductance value of the inductor structure, and improves the performance of the inductor structure. With the inductor structure size remaining basically unchanged, the application flexibility of the inductor structure is improved, and the application field of the inductor structure is expanded.

[0212] In at least one embodiment of this application, such as Figures 7-9 As shown, the inductor structure includes N first traces L1 arranged in the same row and N second traces L2 arranged in the same row, where N is a positive integer and N is greater than or equal to 1; Figure 10 As shown, the orthographic projections of the Nth first trace L1 and the Nth second trace L2 on the dielectric substrate 1 overlap, and the current flow directions are the same; wherein, Figure 7 and Figure 8 The direction indicated by the dashed arrow in the image can be the direction of current flow. Figure 9 for Figure 8 The right view.

[0213] It should be noted that, in order to clearly show the positional relationship of the orthographic projections of the Nth first trace L1 and the Nth second trace L2 on the dielectric substrate 1, in Figure 10 In this example, the orthographic projections of the Nth first trace L1 and the Nth second trace L2 on the dielectric substrate 1 are partially overlapping. In some embodiments, the orthographic projections of the Nth first trace L1 and the Nth second trace L2 on the dielectric substrate 1 can completely overlap.

[0214] In an exemplary embodiment, such as Figure 7 and Figure 8As shown, the two connecting electrodes DJ are grouped together, and the same connecting electrode group is in contact with the same fifth trace L5. The same connecting electrode group includes a first connecting electrode DJ1 and a second connecting electrode DJ2. The orthographic projection of the region where the first connecting electrode DJ1 is located and the first end of the fourth trace L4 on the dielectric substrate 1 overlaps, and the orthographic projection of the region where the second connecting electrode DJ2 is located and the second end of the fourth trace L4 on the dielectric substrate 1 overlaps. The current flow directions of the first connecting electrode DJ1 and the second connecting electrode DJ2 in the same connecting electrode group are opposite.

[0215] In at least one embodiment provided in this application, such as Figure 7 and Figure 8 As shown, the inductor structure also includes N+1 fourth traces L4 arranged in the same row and N+1 fifth traces L5 arranged in the same row; the orthographic projections of the Nth fourth trace L4 and the Nth fifth trace L5 on the dielectric substrate 1 overlap, and the current flow direction is the same.

[0216] In at least one embodiment provided in this application, combined with Figure 7 and Figure 8 As shown, on the first surface B1, the second end of the first fourth trace L4 (the direction of the arrow is the second end) is electrically connected to the first end of the first first trace L1 (the direction of the arrow is the first end) and the first end of the first second trace L2 (the direction of the arrow is the first end), respectively. The first end of the (N+1)th fourth trace L4 is electrically connected to the second end of the Nth first trace L1 and the second end of the Nth second trace L2, respectively. The second end of the (N+1)th fourth trace L4 is electrically connected to the first end of the (N+1)th first trace L1 and the first end of the (N+1)th second trace L2, respectively.

[0217] For example, when N=3, the first end of the fourth fourth trace L4 is electrically connected to the second end of the third first trace L1 and the second end of the third second trace L2, respectively, and the second end of the fourth fourth trace L4 is electrically connected to the first end of the fourth first trace L1 and the first end of the fourth second trace L2, respectively.

[0218] For example, when N=4, the first end of the fifth fourth trace L4 is electrically connected to the second end of the fourth first trace L1 and the second end of the fourth second trace L2, respectively, and the second end of the fifth fourth trace L4 is electrically connected to the first end of the fifth first trace L1 and the first end of the fifth second trace L2, respectively.

[0219] For example, when N=5, the first end of the sixth fourth trace L4 is electrically connected to the second end of the fifth first trace L1 and the second end of the fifth second trace L2, respectively, and the second end of the sixth fourth trace L4 is electrically connected to the first end of the sixth first trace L1 and the first end of the sixth second trace L2, respectively.

[0220] In at least one embodiment provided in this application, combined with Figure 7 and Figure 8 As shown, the inductor structure includes N+1 sets of connecting electrodes arranged in the same row. The first end of the third trace L3 is electrically connected to the N+1th second connecting electrode DJ2, and the second end of the third trace L3 is electrically connected to the first end of the first fourth trace L4.

[0221] In at least one embodiment provided in this application, combined with Figure 7 and Figure 8 As shown, the orthographic projections of each first trace L1, each second trace L2, each fourth trace L4, and each fifth trace L5 on the dielectric substrate 1 overlap with the orthographic projection of the third trace L3 on the dielectric substrate 1.

[0222] The orthographic projection of the third trace L3 on the dielectric substrate 1 overlaps with the orthographic projections of each of the first traces L1, the second traces L2, the fourth traces L4, and the fifth traces L5 on the dielectric substrate 1.

[0223] In addition, such as Figure 7 , Figure 8 and Figure 10 As shown, the extension direction of the orthographic projection of the third trace L3 on the dielectric substrate 1 intersects the extension direction of the orthographic projection of each of the first traces L1, each of the second traces L2, each of the fourth traces L4 and each of the fifth traces L5 on the dielectric substrate 1.

[0224] In at least one embodiment provided in this application, combined with Figure 11 , Figure 12 and Figure 14 As shown, the first conductive structure 6 includes a first first conductive sublayer D1-1, a third first conductive sublayer D1-3, and a fourth first conductive sublayer D1-4 sequentially disposed along a direction away from the dielectric substrate 1; wherein, Figure 14 yes Figure 12 The right view.

[0225] Combination Figure 12 and Figure 14As shown, the first first conductive sublayer D1-1 includes a plurality of first traces L1 extending along the first direction F1 and arranged along the second direction F2, and the fourth first conductive sublayer D1-4 includes a plurality of second traces L2 extending along the first direction F1 and arranged along the second direction F2; the first direction F1 and the second direction F2 intersect; the orthographic projections of the first traces L1 and the second traces L2 on the dielectric substrate 1 at least partially overlap.

[0226] The third first conductive sublayer D1-3 includes a plurality of fourth traces L4 extending along the third direction F3 and arranged along the fourth direction F4, and the second conductive sublayer D2 includes a plurality of fifth traces L5 extending along the third direction F3 and arranged along the fourth direction F4; the third direction F3 and the fourth direction F4 intersect; the orthographic projections of the fourth traces L4 and the fifth traces L5 on the dielectric substrate 1 at least partially overlap; the first direction F1 and the third direction F3 intersect.

[0227] In some examples, the second direction F2 can be approximately parallel to the fourth direction F4.

[0228] The materials of the first first conductive layer D1-1, the third first conductive layer D1-3, and the fourth first conductive layer D1-4 can be referred to the previous description and will not be repeated here.

[0229] There is no limitation on whether the length and width (also known as line width) of the first trace L1, the second trace L2, the fourth trace L4, and the fifth trace are the same.

[0230] In some embodiments, the first trace L1 and the second trace L2 have the same length.

[0231] In some embodiments, the third trace L4 and the fifth trace L5 have the same length.

[0232] In some examples, the first trace L1 and the second trace L2 have the same line width.

[0233] In some examples, the third trace L4 and the fifth trace L5 have the same line width.

[0234] There is no limitation on whether the thicknesses of the first trace L1, the second trace L2, the third trace L3, the fourth trace L4, and the fifth trace are the same.

[0235] In some examples, at least some of the first trace L1, the second trace L2, the third trace L3, the fourth trace L4, and the fifth trace have approximately the same thickness.

[0236] In some examples, at least some of the first routing line L1, the second routing line L2, the third routing line L3, the fourth routing line L4, and the fifth routing line may include straight lines; or, at least some of the first routing line L1, the second routing line L2, the third routing line L3, the fourth routing line L4, and the fifth routing line may include arcs; or, at least some of the first routing line L1, the second routing line L2, the third routing line L3, the fourth routing line L4, and the fifth routing line may include broken line segments composed of straight line segments; or, at least some of the first routing line L1, the second routing line L2, the third routing line L3, the fourth routing line L4, and the fifth routing line may include a combination of straight lines and arcs.

[0237] In at least one embodiment provided in this application, combined with Figure 11 , Figure 12 and Figure 14 As shown, the inductor structure includes N first traces L1 arranged in the same row, N second traces L2 arranged in the same row, N+1 fourth traces L4 arranged in the same row, and N+1 fifth traces L5 arranged in the same row; where N is a positive integer and N is greater than or equal to 1.

[0238] refer to Figure 11 and Figure 12 As indicated by the arrows marked in the middle (the arrow direction indicates the direction of current flow), the orthographic projections of the Nth first trace L1 and the Nth second trace L2 on the dielectric substrate 1 overlap and the current flow directions are opposite. The orthographic projections of the Nth fourth trace L4 and the Nth fifth trace L5 on the dielectric substrate 1 overlap and the current flow directions are opposite.

[0239] It should be noted that, in order to clearly show the positional relationship of the orthographic projections of the Nth first trace L1 and the Nth second trace L2 on the dielectric substrate 1, in Figure 13 In this example, the orthographic projections of the Nth first trace L1 and the Nth second trace L2 on the dielectric substrate 1 are partially overlapping. In some embodiments, the orthographic projections of the Nth first trace L1 and the Nth second trace L2 on the dielectric substrate 1 can completely overlap.

[0240] Two connecting electrodes are grouped together, and the same connecting electrode group is in contact with the same fifth trace L5. The same connecting electrode group includes a first connecting electrode DJ1 and a second connecting electrode DJ2. The orthographic projection of the area where the first connecting electrode DJ1 is located and the first end of the fourth trace L4 on the dielectric substrate 1 overlaps, and the orthographic projection of the area where the second connecting electrode DJ2 is located and the second end of the fourth trace L4 on the dielectric substrate 1 overlaps. The current flow directions of the first connecting electrode DJ1 and the second connecting electrode DJ2 in the same connecting electrode group are opposite.

[0241] It should be noted that in this specification, the first and second ends of each trace are named according to the direction of current flow, with current flowing from the first end to the second end of the trace. At this time, Figure 12 The inductor structure shown is different Figure 3 or Figure 8 The inductor structure shown has a different position at the first end of the fourth trace L4 due to the change in current direction. Therefore, compared to... Figure 3 or Figure 8 The inductor structure shown, in Figure 12 The positions of the first connecting electrode DJ1 and the second connecting electrode DJ2 in the inductor structure shown have been swapped.

[0242] In an exemplary embodiment, such as Figure 12 As shown, the orthographic projections of the first connecting electrode DJ1 and the second connecting electrode DJ2 in the same connecting electrode group onto the film layer where the fifth trace L5 is located fall into the same region where the fifth trace L5 is located.

[0243] In at least one embodiment provided in this application, combined with Figure 11 and Figure 12 As shown, the first first connecting electrode DJ1 is electrically connected to the first end (in the direction opposite to the arrow) of the first fourth trace L4 and the first end (in the direction opposite to the arrow) of the first first trace L1, respectively. The second end (in the direction the arrow points) of the first fourth trace L4 is electrically connected to the first second connecting electrode DJ2. The second end of the first first trace L2 is electrically connected to the second second connecting electrode DJ2 and the first end of the first second trace L2, respectively. The second end of the first second trace L2 is electrically connected to the first end of the first first trace L1 and the first end of the first fourth trace L4, respectively.

[0244] The Nth first connecting electrode DJ1 is electrically connected to the first end of the Nth fourth trace L4 and the first end of the Nth first trace L1, respectively. The second end of the Nth fourth trace L4 is electrically connected to the Nth second connecting electrode DJ2. The second end of the Nth first trace L1 is electrically connected to the first end of the (N+1)th second connecting electrode DJ2 and the Nth second trace L2, respectively. The second end of the Nth second trace L2 is electrically connected to the first end of the Nth first trace L1 and the first end of the Nth fourth trace L4, respectively.

[0245] For example, when N=4, the fourth first connection electrode DJ1 is electrically connected to the first end of the fourth fourth trace L4 and the first end of the fourth first trace L1, the second end of the fourth fourth trace L4 is electrically connected to the fourth second connection electrode DJ2, the second end of the fourth first trace L1 is electrically connected to the first end of the fifth second connection electrode DJ2 and the first end of the fourth second trace L2, and the second end of the fourth second trace L2 is electrically connected to the first end of the fourth first trace L1 and the first end of the fourth fourth trace L4.

[0246] For example, when N=5, the fifth first connection electrode DJ1 is electrically connected to the first end of the fifth fourth trace L4 and the first end of the fifth first trace L1, the second end of the fifth fourth trace L4 is electrically connected to the fifth second connection electrode DJ2, the second end of the fifth first trace L1 is electrically connected to the first end of the sixth second connection electrode DJ2 and the fifth second trace L2, and the second end of the fifth second trace L2 is electrically connected to the first end of the fifth first trace L1 and the first end of the fifth fourth trace L4.

[0247] For example, when N=6, the sixth first connection electrode DJ1 is electrically connected to the first end of the sixth fourth trace L4 and the first end of the sixth first trace L1, the second end of the sixth fourth trace L4 is electrically connected to the sixth second connection electrode DJ2, the second end of the sixth first trace L1 is electrically connected to the first end of the seventh second connection electrode DJ2 and the first end of the sixth second trace L2, and the second end of the sixth second trace L2 is electrically connected to the first end of the sixth first trace L1 and the first end of the sixth fourth trace L4.

[0248] In at least one embodiment provided in this application, such as Figure 4 and Figure 9 As shown, the inductor structure also includes a first insulating layer 2, a second insulating layer 3, a third insulating layer 4, a first protective layer 5, and a second protective layer 8; the first insulating layer 2 is located between the first first conductive sublayer D1-1 and the second first conductive sublayer D1-2, the second insulating layer 3 is located between the second first conductive sublayer D1-2 and the third first conductive sublayer D1-3, and the third insulating layer 4 is located between the third first conductive sublayer D1-3 and the fourth first conductive sublayer D1-4; the first protective layer 5 covers the fourth first conductive sublayer D1-4, and the second protective layer 8 covers the second conductive sublayer D2.

[0249] In at least one embodiment provided in this application, such as Figure 14As shown, the inductor structure also includes a first insulating layer 2, a third insulating layer 4, a first protective layer 5, and a second protective layer 8; the first insulating layer 2 is located between the first first conductive sublayer D1-1 and the third first conductive sublayer D1-3, the third insulating layer 4 is located between the third first conductive sublayer D1-3 and the fourth first conductive sublayer D1-4; the first protective layer 5 covers the fourth first conductive sublayer D1-4, and the second protective layer 8 covers the second conductive sublayer D2.

[0250] The materials of the first insulating layer 2, the second insulating layer 3, the third insulating layer 4, the first protective layer 5, and the second protective layer 8 are all insulating materials; wherein, the insulating materials may include organic insulating materials or inorganic insulating materials.

[0251] For example, organic insulating materials may include photoresists and resins, such as epoxy resins, polyimides, acrylic resins, etc.

[0252] For example, inorganic insulating materials may include at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0253] In the embodiments of this application, the first insulating layer 2, the second insulating layer 3, the third insulating layer 4, the first protective layer 5, and the second protective layer 8 are all made of organic materials as an example for illustration.

[0254] In at least one embodiment provided in this application, the thickness of the first conductive sublayer D1 and the second conductive sublayer D2 are both in the range of 1 μm to 10 μm.

[0255] For example, the thickness of the first conductive layer D1 and the second conductive layer D2 is in the range of 1.5μm to 7μm. For example, the thickness can be 1.5μm, 2μm, 4μm, 6.5μm or 7μm.

[0256] There is no limitation on whether the thickness of the first conductive sublayer D1 and the second conductive sublayer D2 are the same. For example, the thickness can be set according to the material and conductivity requirements of the traces set in the first conductive sublayer D1 and the second conductive sublayer D2.

[0257] In practical applications, when the materials of the first conductive sublayer D1 and the second conductive sublayer D2 both meet the conductivity requirements, the thicknesses of the first conductive sublayer D1 and the second conductive sublayer D2 can be set to be approximately the same to simplify the preparation process and reduce the difficulty of the preparation process.

[0258] In some examples, since the thickness of the first conductive layer D1 and the second conductive layer D2 are both in the range of 1μm to 10μm, which is relatively thick, in order to improve the stability between two adjacent conductive film layers, the thickness of at least part of the insulating layer can be set to be greater than the thickness of the conductive layer.

[0259] For example, the thickness of the first insulating layer 2 is greater than or equal to the thickness of the first first conductive layer D1-1.

[0260] For example, the thickness of the second insulating layer 3 is greater than or equal to the thickness of the second first conductive layer D1-2.

[0261] For example, the thickness of the third insulating layer 4 is greater than or equal to the thickness of the third first conductive layer D1-3.

[0262] For example, the thickness of the first protective layer 5 is greater than or equal to the thickness of the fourth first conductive electronic layer D1-4.

[0263] For example, the thickness of the second protective layer 8 is greater than or equal to the thickness of the second conductive electronic layer D2.

[0264] In at least one embodiment provided in this application, the connecting electrode DJ comprises a metallic material;

[0265] Alternatively, the connecting electrode DJ may consist of resin and a metal material encapsulating the resin.

[0266] It should be noted that when filling the via with conductive material using electroplating, the conductive material preferentially deposits on the sidewalls of the via. Gaps may appear in the center of the via due to incomplete filling. In this case, resin material is used to fill the gaps to improve the mechanical strength of the connecting electrode DJ and its support for other film layers. When the connecting electrode DJ comprises resin and a metal material encapsulating the resin, the planar shape of the conductive region near the first surface B1 and / or the second surface B2 can be annular, such as a circular ring or a polygonal ring.

[0267] In at least one embodiment provided in this application, at least one of the first trace L1, the second trace L2, the fourth trace L4 and the fifth trace L5 includes multiple sub-traces arranged in parallel, with gaps between adjacent sub-traces, and each sub-traces having approximately the same line width.

[0268] In the embodiments of this application, by setting at least one of the first trace L1, the second trace L2, the fourth trace L4, and the fifth trace L5 to include multiple sub-traces arranged in parallel, with gaps between adjacent sub-traces, the mutual inductance generated between the sub-traces of the first trace L1, the second trace L2, the fourth trace L4, and the fifth trace L5 can be increased, thereby further improving the inductance density and inductance value of the inductor structure with a fixed size.

[0269] In at least one embodiment provided in this application, the included angle between the first direction F1 and the third direction F3 is an acute angle, which can minimize the layout space of each trace, thereby reducing the spatial size of the inductor structure.

[0270] In at least one embodiment provided in this application, the third trace L3 includes multiple sub-traces arranged in parallel, with a gap between adjacent sub-traces and each sub-traces having approximately the same line width. This enables the mutual inductance generated between the sub-traces, thereby further improving the inductance density and inductance value of the inductor structure while keeping the size of the inductor structure fixed.

[0271] In at least one embodiment provided in this application, the line width of the third trace L3 is smaller than that of the first trace L1, the second trace L2 and the fourth trace L4. This can greatly reduce the interference of the current in the third trace L3 on the mutual inductance between the first trace L1 and the second trace L2, and the mutual inductance between the fourth trace L4 and the fifth trace L5, thereby further improving the inductance density and inductance value of the inductor structure with a fixed size.

[0272] Embodiments of this application provide a filter, such as Figure 15 As shown, the filter includes at least one inductor structure L as described above and at least one capacitor C; wherein the insulating dielectric in capacitor C is marked JZ. Additionally, the filter includes solder balls or conductive posts 9 for electrically connecting the filter to other components in the RF module.

[0273] The filter provided in the embodiments of this application includes a 3D inductor structure. By setting this inductor structure, on the one hand, one of the first conductive structure 6 and the second conductive structure 7 includes multiple sub-layers, and the other includes at least one sub-layer, increasing the number of conductive layers constituting the wire (coil), thereby extending the effective length of the coil forming the inductor structure, and thus increasing the inductance density of the inductor structure and improving the inductance value. On the other hand, the orthographic projections of two sub-layers of the first conductive structure 6 and the second conductive structure 7 on the dielectric substrate 1 at least partially overlap. When the current flow directions of the two are the same, the mutual inductance of the inductor structure can be effectively increased, further increasing the inductance value of the inductor structure and improving the performance of the inductor structure. With the inductor structure size remaining basically unchanged, the application flexibility of the inductor structure is improved, and the application field of the inductor structure is expanded.

[0274] Embodiments of this application provide a packaging substrate including at least one inductor structure L as described above.

[0275] The packaging substrate provided in the embodiments of this application includes a 3D inductor structure. By setting this inductor structure, on the one hand, one of the first conductive structure 6 and the second conductive structure 7 in the inductor structure includes at least three sublayers, and the other includes at least one sublayer (e.g., combined with...). Figure 1 and Figure 4 As shown, the first conductive structure 6 includes sublayers D1-1, D1-2, D1-3, and D1-4; the second conductive structure 7 includes sublayer D2. This increases the number of conductive layers constituting the conductor (coil), thereby extending the effective length of the coil forming the inductor structure, increasing the inductance density, and improving the inductance value. Furthermore, the orthographic projections of two sublayers in the first conductive structure 6 and the second conductive structure 7 onto the dielectric substrate 1 at least partially overlap. When the current flows in the same direction in both, the mutual inductance of the inductor structure can be effectively increased, further increasing the inductance value and improving the performance of the inductor structure. With the inductor structure dimensions remaining essentially unchanged, this improves the application flexibility of the inductor structure and expands its application areas.

[0276] The embodiments of this application provide a method for fabricating an inductor structure, the specific description of which is as follows:

[0277] S01, Select as follows Figure 16A The substrate (dielectric substrate 1) shown is fabricated with vias (connection vias) at the pre-reserved holes in the substrate, resulting in the following: Figure 16B The structure shown.

[0278] For example, the thickness of the dielectric substrate 1 is 0.2 to 0.5 mm.

[0279] For example, the dielectric substrate 1 can be a glass substrate, a silicon substrate, a ceramic substrate, etc.

[0280] For example, the diameter of the via can be 30-100um, and the cross-sectional shape of the via can be columnar or hourglass-shaped depending on the via technology.

[0281] S02. Metallize and fill the connection vias to obtain the following result: Figure 16C The connection electrode DJ is shown.

[0282] In some embodiments, the metal interconnection within the via can be achieved by injecting copper metal into the via using electroplating technology to conduct the circuit within the via. It should be noted that when filling the via with conductive material using electroplating, the conductive material is preferentially deposited on the sidewall of the via. There may be incomplete filling of conductive material and gaps at the center of the via. In this case, resin material is used to fill the gaps to improve the mechanical strength of the connecting electrode DJ and its support for other film layers.

[0283] S03. A conductive structure is fabricated on the second surface B2 of the dielectric substrate 1 to obtain, as shown in the figure. Figure 16D The second conductive structure 7 shown includes a fifth trace L5.

[0284] S04, forming as follows Figure 16D The second protective layer 8 shown covers the second conductive structure 7.

[0285] For example, the thickness of the second protective layer 8 is greater than or equal to 2 μm.

[0286] S05, sequentially forming the following on the first surface B1 Figure 16E The first conductive sublayer D1-1 (including the first trace L1) and the first insulating layer 2 are shown, as follows: Figure 16F The second first conductive sublayer D1-2 (including the third trace L3) and the second insulating layer 3 are shown, as follows: Figure 16G The third first conductive sublayer D1-3 (including the fourth trace L4) and the third insulating layer 4 are shown, as follows Figure 16H The fourth first conductive layer D1-4 (including the second trace L2) and the first protective layer 5 are shown.

[0287] The first first conductive sublayer D1-1 (including the first trace L1), the second first conductive sublayer D1-2 (including the third trace L3), the third first conductive sublayer D1-3 (including the fourth trace L4), and the fourth first conductive sublayer D1-4 (including the second trace L2) can all be prepared by electroplating. Specifically, the patterned first conductive sublayer D1 can be formed by electroplating, photoresist coating, exposure, and etching.

[0288] It should be noted that this section only introduces the fabrication process of the structure related to the invention point. The specific components and materials of the inductor structure can be found in the previous description and will not be repeated here.

[0289] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An inductor structure, wherein, include: A dielectric substrate having a plurality of through-holes extending along its thickness direction, wherein a connection electrode is disposed in the through-holes, and the dielectric substrate further includes a first surface and a second surface disposed opposite to each other along its thickness direction; the number of the through-holes or the connection electrodes is even. A first conductive structure is disposed on the first surface; A second conductive structure is disposed on the second surface; The first conductive structure and the second conductive structure are electrically connected through the connecting electrode to form the coil of the inductor structure; one of the first conductive structure and the second conductive structure includes at least three sub-layers, and the other includes at least one sub-layer; the orthographic projections of two of the sub-layers in the first conductive structure and the second conductive structure on the dielectric substrate at least partially overlap, and the current flow directions are substantially parallel; the at least one sub-layer includes a molybdenum-niobium alloy layer, a copper metal layer, and a protective layer stacked sequentially, and the protective layer includes any one of copper-nickel alloy, nickel, or indium tin oxide; The sublayer in the first conductive structure is called the first conductive sublayer, and the sublayer in the second conductive structure is called the second conductive sublayer; Wherein, the first conductive structure includes at least three first conductive sublayers, and the second conductive structure includes at least three second conductive sublayers; Alternatively, the first conductive structure may include at least three first conductive sublayers, and the second conductive structure may include one second conductive sublayer.

2. The inductor structure according to claim 1, wherein, At least two of the first conductive layers have orthographic projections on the dielectric substrate that at least partially overlap, and the current flow directions of the two layers are parallel.

3. The inductor structure according to claim 1, wherein, At least one of the orthographic projections of the first conductive sublayer on the dielectric substrate at least partially overlaps with the orthographic projection of the second conductive sublayer on the dielectric substrate, and the current flow directions of the two are parallel.

4. The inductor structure according to claim 1, wherein, In the case where the first conductive structure includes at least three first conductive sublayers and the second conductive structure includes one second conductive sublayer. The first conductive structure includes an even number of first conductive sublayers, at least two of which have their orthographic projections on the dielectric substrate at least partially overlapping and have the same current flow direction.

5. The inductor structure according to claim 4, wherein, At least one of the orthographic projections of the first conductive sublayer on the dielectric substrate and the orthographic projections of the second conductive sublayer on the dielectric substrate at least partially overlap, and the current flow directions of both are the same.

6. The inductor structure according to claim 1, wherein, In the case where the first conductive structure includes at least three first conductive sublayers and the second conductive structure includes one second conductive sublayer. The first conductive structure includes an odd number of first conductive sublayers, at least two of which have orthographic projections on the dielectric substrate that at least partially overlap and whose current flow directions are opposite.

7. The inductor structure according to claim 6, wherein, At least one of the orthographic projections of the first conductive sublayer on the dielectric substrate at least partially overlaps with the orthographic projection of the second conductive sublayer on the dielectric substrate, and the current flow directions of the two are opposite.

8. The inductor structure according to claim 4 or 5, wherein, The first conductive structure includes a first first conductive sublayer, a second first conductive sublayer, a third first conductive sublayer, and a fourth first conductive sublayer disposed sequentially along a direction away from the dielectric substrate; The first first conductive sublayer includes a plurality of first traces extending along a first direction and arranged along a second direction, and the fourth first conductive sublayer includes a plurality of second traces extending along the first direction and arranged along the second direction; the first direction and the second direction intersect; the orthographic projections of the first traces and the second traces on the dielectric substrate at least partially overlap. The second first conductive sublayer includes a third trace, and the third first conductive sublayer includes a plurality of fourth traces extending along a third direction and arranged along a fourth direction; the second conductive sublayer includes a plurality of fifth traces extending along the third direction and arranged along the fourth direction; the third direction and the fourth direction intersect; the orthographic projections of the fourth traces and the fifth traces on the dielectric substrate at least partially overlap; the first direction and the third direction intersect.

9. The inductor structure according to claim 8, wherein, The inductor structure includes N first traces arranged in the same row and N second traces arranged in the same row, wherein N is a positive integer and N is greater than or equal to 1; the orthographic projections of the Nth first trace and the Nth second trace on the dielectric substrate overlap and the current flow direction is the same; The two connection electrodes are grouped together, and the same connection electrode group is in contact with the same fifth trace; the same connection electrode group includes a first connection electrode and a second connection electrode, the region where the first connection electrode is located overlaps with the orthographic projection of the first end of the fourth trace on the dielectric substrate, and the region where the second connection electrode is located overlaps with the orthographic projection of the second end of the fourth trace on the dielectric substrate; the current flow directions of the first connection electrode and the second connection electrode in the same connection electrode group are opposite.

10. The inductor structure according to claim 9, wherein, The inductor structure also includes N fourth traces arranged in the same row and N+1 fifth traces arranged in the same row; the orthographic projections of the Nth fourth trace and the N+1th fifth trace on the dielectric substrate overlap, and the current flow direction is the same.

11. The inductor structure according to claim 10, wherein, On the first surface, the second end of the first first trace and the second end of the first second trace are electrically connected to the first end of the first fourth trace, and the first end of the second first trace and the first end of the second second trace are electrically connected to the second end of the first fourth trace, respectively. The second end of the Nth first trace and the second end of the Nth second trace are electrically connected to the first end of the Nth fourth trace, and the first end of the (N+1)th first trace and the first end of the (N+1)th second trace are electrically connected to the second end of the Nth fourth trace.

12. The inductor structure according to claim 11, wherein, The inductor structure includes N+1 sets of connection electrodes arranged in the same row. The first end of the third trace is electrically connected to the N+1th second connection electrode, and the second end of the third trace is electrically connected to the first end of the first first trace and the first end of the first second trace, respectively. The first end of the first first trace and the first end of the first second trace are electrically connected to the first second connection electrode, respectively; the first end of the first first trace and the first end of the first second trace are electrically connected to the second first connection electrode, respectively; the first end of the Nth first trace and the first end of the Nth second trace are electrically connected to the Nth second connection electrode, respectively; the second end of the Nth first trace and the second end of the Nth second trace are electrically connected to the (N+1)th first connection electrode, respectively.

13. The inductor structure according to claim 12, wherein, The orthographic projection of the third trace, except for its first and second ends, onto the dielectric substrate does not overlap with the area where the connecting electrode group is located.

14. The inductor structure according to claim 9, wherein, The inductor structure also includes N+1 fourth traces arranged in the same row and N+1 fifth traces arranged in the same row; The orthographic projections of the Nth fourth trace and the Nth fifth trace on the dielectric substrate overlap, and the current flow direction is the same.

15. The inductor structure according to claim 14, wherein, On the first surface, the second end of the first fourth trace is electrically connected to the first end of the first first trace and the first end of the first second trace, respectively; the first end of the (N+1)th fourth trace is electrically connected to the second end of the Nth first trace and the second end of the Nth second trace, respectively; and the second end of the (N+1)th fourth trace is electrically connected to the first end of the (N+1)th first trace and the first end of the (N+1)th second trace, respectively.

16. The inductor structure according to claim 15, wherein, The inductor structure includes N+1 sets of connection electrodes arranged in the same row. The first end of the third trace is electrically connected to the N+1th second connection electrode, and the second end of the third trace is electrically connected to the first end of the first fourth trace.

17. The inductor structure according to claim 16, wherein, The orthographic projections of each of the first traces, the second traces, the fourth traces, and the fifth traces on the dielectric substrate overlap with the orthographic projection of the third trace on the dielectric substrate.

18. The inductor structure according to claim 6 or 7, wherein, The first conductive structure includes a first first conductive sublayer, a third first conductive sublayer, and a fourth first conductive sublayer disposed sequentially along a direction away from the dielectric substrate; The first first conductive sublayer includes a plurality of first traces extending along a first direction and arranged along a second direction, and the fourth first conductive sublayer includes a plurality of second traces extending along the first direction and arranged along the second direction; the first direction and the second direction intersect; the orthographic projections of the first traces and the second traces on the dielectric substrate at least partially overlap. The third first conductive sublayer includes a plurality of fourth traces extending along a third direction and arranged along a fourth direction, and the second conductive sublayer includes a plurality of fifth traces extending along the third direction and arranged along the fourth direction; the third direction and the fourth direction intersect; the orthographic projections of the fourth traces and the fifth traces on the dielectric substrate at least partially overlap; the first direction and the third direction intersect.

19. The inductor structure according to claim 18, wherein, The inductor structure includes N first traces arranged in the same row, N second traces arranged in the same row, N+1 fourth traces arranged in the same row, and N+1 fifth traces arranged in the same row; wherein, N is a positive integer, and N is greater than or equal to 1; The orthographic projections of the Nth first trace and the Nth second trace on the dielectric substrate overlap, and the current flow directions are opposite; the orthographic projections of the Nth fourth trace and the Nth fifth trace on the dielectric substrate overlap, and the current flow directions are opposite. The two connection electrodes are grouped together, and the same connection electrode group is in contact with the same fifth trace; the same connection electrode group includes a first connection electrode and a second connection electrode, the region where the first connection electrode is located overlaps with the orthographic projection of the first end of the fourth trace on the dielectric substrate, and the region where the second connection electrode is located overlaps with the orthographic projection of the second end of the fourth trace on the dielectric substrate; the current flow directions of the first connection electrode and the second connection electrode in the same connection electrode group are opposite.

20. The inductor structure according to claim 19, wherein, The first first connection electrode is electrically connected to the first end of the first fourth trace and the first end of the first first trace, respectively; the second end of the first fourth trace is electrically connected to the first second connection electrode, respectively; the second end of the first first trace is electrically connected to the second second connection electrode and the first end of the first second trace, respectively; the second end of the first second trace is electrically connected to the first end of the first first trace and the first end of the first fourth trace, respectively. The Nth first connecting electrode is electrically connected to the first end of the Nth fourth trace and the first end of the Nth first trace, respectively. The second end of the Nth fourth trace is electrically connected to the Nth second connecting electrode. The second end of the Nth first trace is electrically connected to the (N+1)th second connecting electrode and the first end of the Nth second trace, respectively. The second end of the Nth second trace is electrically connected to the first end of the Nth first trace and the first end of the Nth fourth trace, respectively.

21. The inductor structure according to any one of claims 9 to 17, wherein, The inductor structure further includes a first insulating layer, a second insulating layer, a third insulating layer, a first protective layer, and a second protective layer; The first insulating layer is located between the first first conductive sublayer and the second first conductive sublayer, the second insulating layer is located between the second first conductive sublayer and the third first conductive sublayer, and the third insulating layer is located between the third first conductive sublayer and the fourth first conductive sublayer. The first protective layer covers the fourth first conductive sublayer, and the second protective layer covers the second conductive sublayer.

22. The inductor structure according to claim 19 or 20, wherein, The inductor structure further includes a first insulating layer, a third insulating layer, a first protective layer, and a second protective layer; The first insulating layer is located between the first first conductive sublayer and the third first conductive sublayer, and the third insulating layer is located between the third first conductive sublayer and the fourth first conductive sublayer; The first protective layer covers the fourth first conductive sublayer, and the second protective layer covers the second conductive sublayer.

23. The inductor structure according to any one of claims 1-7, 9-17, and 19-20, wherein, The thickness of both the first conductive sublayer and the second conductive sublayer ranges from 1 μm to 10 μm.

24. The inductor structure according to any one of claims 9-17 and 19-20, wherein, The connecting electrode comprises a metallic material; Alternatively, the connecting electrode may comprise resin and a metal material encapsulating the resin.

25. The inductor structure according to any one of claims 9-17 and 19-20, wherein, At least one of the first trace, the second trace, the fourth trace, and the fifth trace includes multiple sub-traces arranged in parallel, with gaps between adjacent sub-traces, and each sub-traces having approximately the same line width.

26. The inductor structure according to claim 8, wherein, The angle between the first direction and the third direction is an acute angle.

27. The inductor structure according to claim 8, wherein, The third routing includes multiple sub-routes arranged in parallel, with gaps between adjacent sub-routes, and each sub-route has approximately the same line width.

28. The inductor structure according to claim 8, wherein, The line width of the third trace is smaller than that of the first trace, the second trace, and the fourth trace.

29. A filter, wherein, It includes at least one inductor structure as described in any one of claims 1-28 and at least one capacitor.

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