Semiconductor module and method for manufacturing semiconductor module

Abstract

The mounting substrate has a mounting surface. The semiconductor device includes a device layer on which an electronic circuit including a semiconductor element is formed, an insulating layer disposed on one surface of the device layer, and a plurality of bumps disposed on the other surface of the device layer. The semiconductor device is mounted on a mounting substrate such that a surface of a device layer on which a plurality of bumps are disposed faces a mounting surface. The resin layer is disposed on a surface of the insulating layer opposite to the device layer side, and the molding member is disposed in a region of the mounting surface outside the semiconductor device in plan view, a side surface of the semiconductor device, and at least a side surface of the resin layer. A dielectric loss tangent of the resin layer is smaller than a dielectric loss tangent of the molded member.

Description

Technical Field

[0001] The present invention relates to a semiconductor module and a method for manufacturing the semiconductor module. Background Art

[0002] In high-frequency integrated circuits using silicon (Si) substrates, electrical losses are caused by the resistance of the conductive Si substrate and the parasitic capacitance between the wiring on the Si substrate and the Si substrate. In the case where the high-frequency integrated circuit is a switch or a low-noise amplifier, the resistance of the Si substrate and the parasitic capacitance between the wiring and the Si substrate have a negative impact on the loss characteristics and noise characteristics.

[0003] By using an SOI substrate having a buried oxide layer inserted between an element formation layer on which semiconductor elements are formed and a Si substrate, the resistance of the Si substrate and the influence of parasitic capacitance between the Si substrate and wiring can be reduced. Furthermore, by removing the Si substrate and leaving the element formation layer and the buried oxide layer, the influence of the resistance of the Si substrate and the parasitic capacitance between the Si substrate and wiring can be removed (for example, refer to Patent Document 1).

[0004] Patent Document 1: International Publication No. 2018 / 031995 Summary of the invention

[0005] In the case of manufacturing a high-frequency module by mounting a bare chip having a structure with a residual element forming layer and a buried oxide layer on a mounting substrate after removing a Si substrate from an SOI substrate, the bare chip mounted on the mounting substrate is usually molded by a molding resin. The dielectric loss tangent of the molding component is usually larger than the dielectric loss tangent of an insulating layer, etc. Therefore, electric loss is generated due to the high-frequency power leaking from the high-frequency circuit of the element forming layer to the molding component. The object of the present invention is to provide a semiconductor module and a method for manufacturing the same that can reduce the electric loss caused by the molding component.

[0006] According to one aspect of the present invention, there is provided a semiconductor module comprising: a mounting substrate having a mounting surface; a semiconductor device having a device layer on which an electronic circuit including a semiconductor element is formed, an insulating layer arranged on one surface of the device layer, and a plurality of bumps arranged on another surface of the device layer, wherein the semiconductor device is mounted on the mounting substrate so that the surface of the device layer on which the plurality of bumps are arranged faces the mounting surface; a resin layer arranged on a surface of the insulating layer on a side opposite to the device layer side; and a molding member arranged on the mounting surface in an area outside the semiconductor device when viewed from above, a side surface of the semiconductor device, and at least a side surface of the resin layer, wherein the dielectric loss tangent of the resin layer is smaller than the dielectric loss tangent of the molding member.

[0007] According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor module, comprising the steps of preparing an SOI wafer having an insulating layer and a device layer formed of a semiconductor stacked on a base substrate formed of a semiconductor, dividing the wafer into a plurality of chip regions, forming a plurality of semiconductor elements in each of the plurality of chip regions of the device layer, forming a plurality of wiring layers on the device layer on which the plurality of semiconductor elements are formed, forming a plurality of bumps on the plurality of wiring layers, removing the base substrate after forming the plurality of bumps to thin the SOI wafer, disposing a resin layer on an exposed surface of the insulating layer of the thinned SOI wafer, manufacturing a plurality of semiconductor devices by singulating the SOI wafer and the resin layer after disposing the resin layer, flip-chip mounting one of the plurality of semiconductor devices on a mounting surface of a mounting substrate, covering a region of the mounting surface outside the semiconductor device when viewed from above and at least a side surface of the semiconductor device with a molding member, wherein a dielectric loss tangent of the resin layer is smaller than a dielectric loss tangent of the molding member.

[0008] Since the dielectric loss tangent of the resin layer is smaller than that of the mold member, the electrical loss caused by the dielectric loss tangent can be reduced compared with a structure in which the semiconductor device is covered with the mold member without providing a resin layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a cross-sectional view of the semiconductor module according to the first embodiment.

[0010] Figure 2 This is an enlarged cross-sectional view of a part of the semiconductor module according to the first embodiment.

[0011] FIG. 3A to FIG. 3D The accompanying drawing is a schematic cross-sectional view of a semiconductor module of the first embodiment at an intermediate stage of manufacturing.

[0012] Figure 4 is a cross-sectional view of a semiconductor module according to a second embodiment.

[0013] Figure 5 This is an enlarged cross-sectional view of a part of the semiconductor module according to the second embodiment.

[0014] Figure 6 It is a diagram showing the positional relationship of a plurality of bumps in a plan view.

[0015] Figure 7 is a cross-sectional view of a semiconductor module according to a third embodiment.

[0016] FIG. 8A to FIG. 8G The accompanying drawing is a cross-sectional view of a semiconductor module of the third embodiment at a mid-stage of manufacturing.

[0017] Fig.9A as well as Fig. 9B FIG. 1 is a cross-sectional view of a semiconductor module according to a third embodiment at an intermediate stage of manufacturing.

[0018] Fig.10 is a cross-sectional view of a semiconductor module according to a fourth embodiment. DETAILED DESCRIPTION

[0019] [First embodiment]

[0020] Reference Figures 1 to 3D The semiconductor module of the first embodiment is described with reference to the accompanying drawings.

[0021] Figure 1 1 is a cross-sectional view of a semiconductor module of the first embodiment. The semiconductor module of the first embodiment includes a semiconductor device 10, a mounting substrate 80, a resin layer 50, and a molding member 86. The semiconductor device 10 includes a device layer 30, an insulating layer 20, and a plurality of bumps 70. An electronic circuit including a plurality of semiconductor elements such as transistors is formed in the device layer 30. The insulating layer 20 is arranged on one surface of the device layer 30. The plurality of bumps 70 are arranged on the other surface of the device layer 30.

[0022] The semiconductor device 10 is flip-chip mounted on a mounting surface 80A, which is one surface of the mounting substrate 80. That is, the plurality of bumps 70 are respectively fixed to a plurality of pads (not shown) arranged on the mounting surface 80A of the mounting substrate 80 and are electrically connected to the plurality of pads. A cavity is formed between the device layer 30 and the mounting substrate 80.

[0023] The resin layer 50 is disposed on the surface of the insulating layer 20 opposite to the device layer 30. When the mounting surface 80A is viewed from above (hereinafter referred to as "viewed from above"), the edges of the device layer 30, the insulating layer 20, and the resin layer 50 are substantially aligned.

[0024] The molding member 86 is in close contact with the region of the mounting surface 80A that is outside the semiconductor device 10 when viewed from above, the side surface of the semiconductor device 10, and the side surface of the resin layer 50. The top surface of the resin layer 50 and the top surface of the molding member 86 are approximately located on the same virtual plane. Here, the "top surface" means the surface facing the side opposite to the mounting substrate 80 side. The molding member 86 isolates the cavity between the device layer 30 and the mounting substrate 80 from the outside.

[0025] The mounting substrate 80 uses, for example, a printed wiring substrate. The resin layer 50 uses, for example, an epoxy resin containing a filler. The molding member 86 uses, for example, an epoxy resin or an epoxy resin containing a filler. The dielectric loss tangent of the resin layer 50 is smaller than the dielectric loss tangent of the molding member 86. As an example, by using an epoxy resin containing a filler for the resin layer 50 and adjusting the filling rate of the filler, the dielectric loss tangent of the resin layer 50 can be easily made smaller than the dielectric loss tangent of the molding member 86.

[0026] Figure 2 FIG. 1 is a cross-sectional view of a portion of the semiconductor module of the first embodiment. Figure 2 In the figure, the ratio of the dimensions of the components and the ratio of the dimensions of the components in the thickness direction and the in-plane direction do not represent the actual ratio. Figure 2 In Figure 1 The semiconductor module is represented by the upside-down inversion of

[0027] The semiconductor device 10 includes a device layer 30, an insulating layer 20, a protective film 61, and a bump 70. Figure 1 The description of the protective film 61 is omitted. Figure 2 , one of the plurality of bumps 70 is shown. The insulating layer 20 is formed of, for example, silicon oxide. As the bump 70, for example, a solder bump, a Cu column bump, an Au bump, or the like is used.

[0028] The semiconductor device 10 is mounted on a mounting substrate 80. Figure 2 In the description, the direction from the semiconductor device 10 toward the mounting substrate 80 is defined as an upward direction. The device layer 30 is arranged on the upward surface of the insulating layer 20 , and the resin layer 50 is arranged on the downward surface of the insulating layer 20 .

[0029] The device layer 30 includes: an element formation layer 39 made of semiconductor in contact with the insulating layer 20, and a multilayer wiring layer 38 arranged on the element formation layer 39. The element formation layer 39 has an active region made of silicon and an insulating element isolation region 39I surrounding the active region. In the active region of the element formation layer 39, a plurality of source regions 31S, a plurality of drain regions 31D, and a plurality of channel regions 31C of a semiconductor element 31 as a MOSFET are arranged.

[0030] The plurality of source regions 31S and the plurality of drain regions 31D are spaced apart from each other in one direction (in Figure 2The drain region 31D and the source region 31S extend from one surface of the element formation layer 39 in the thickness direction of the element formation layer 39 to the other surface. The channel region 31C is divided between the source region 31S and the drain region 31D adjacent to each other. A gate electrode 31G is arranged on the channel region 31C via a gate insulating film (not shown).

[0031] The multilayer wiring layer 38 on the element forming layer 39 includes a plurality of interlayer insulating films 60. The plurality of interlayer insulating films 60 use, for example, a low dielectric constant material (Low-k material). The through hole provided in the interlayer insulating film 60 at the bottom of the multilayer wiring layer 38 is filled with a source contact electrode 33S and a drain contact electrode 33D. The source contact electrode 33S makes ohmic contact with the source region 31S, and the drain contact electrode 33D makes ohmic contact with the drain region 31D. The source contact electrode 33S and the drain contact electrode 33D are formed, for example, of W. A close contact layer such as TiN may also be configured for the purpose of improving close contact as needed. In addition, the following structure may be used, in which a film composed of metal silicides such as CoSi and NiSi is formed on the surface of each of the source region 31S and the drain region 31D to reduce the resistance of the contact portion.

[0032] A plurality of wirings 34 or a plurality of through holes 35 are respectively arranged on the plurality of interlayer insulating films 60 above the second layer. The wirings 34 or through holes 35 are formed by a damascene method, a dual damascene method, or a subtractive method. A plurality of wirings 34T are arranged on the uppermost wiring layer of the device layer 30, and a plurality of pads 34P are arranged on the uppermost interlayer insulating film 60. As an example, the wirings 34, 34T, and the pads 34P are formed of Cu or Al, and the through holes are formed of Cu or W. In addition, a bonding layer such as TiN may be arranged for the purpose of preventing diffusion and improving bonding as needed. A metal layer 37 called a guard ring is arranged on the periphery of the multilayer wiring layer.

[0033] A protective film 61 made of an organic insulating material is arranged on the device layer 30 to cover the pad 34P. Examples of organic insulating materials used for the protective film 61 include polyimide, benzocyclobutene (BCB), etc. A plurality of openings are provided in the protective film 61 to expose the upper surfaces of the plurality of pads 34P, and bumps 70 are arranged on the pads 34P in the openings. When a Cu column bump is used as the bump 70, the bump 70 is composed of a lower bump metal layer, a Cu column, and a solder layer thereon. The bump 70 is connected to the pad 81 of the mounting substrate 80, so that the semiconductor device 10 is flip-chip mounted on the mounting substrate 80.

[0034] The side surfaces of the semiconductor device 10 and the resin layer 50 are in close contact with the mold member 86. Furthermore, the mold member 86 is in close contact with a region of the mounting surface 80A of the mounting substrate 80 that is outside the semiconductor device 10 in a plan view.

[0035] Next, refer to FIG. 3A to FIG. 3D The method for manufacturing the semiconductor module according to the first embodiment is described with reference to the accompanying drawings. FIG. 3A to FIG. 3D The accompanying drawing is a schematic cross-sectional view of a semiconductor module of the first embodiment at an intermediate stage of manufacturing.

[0036] like Figure 3A As shown, an intermediate product including a base substrate 91 made of silicon, an insulating layer 20 made of silicon oxide, a device layer 30, and a plurality of bumps 70 is produced. The intermediate product can be produced by using an SOI substrate and applying a general semiconductor wafer process and a dicing process. The base substrate 91, the insulating layer 20, and the element formation layer 39 ( Figure 2 ) correspond to the silicon substrate, the buried oxide layer, and the SOI layer composed of single crystal silicon, which are respectively equivalent to the SOI substrate. The intermediate product is flip-chip mounted on the mounting substrate 80.

[0037] like Figure 3B As shown, the intermediate product is molded using a molding member 86. At this stage, the molding member 86 covers the side and top surfaces of the base substrate 91. Between the device layer 30 and the mounting substrate 80 is a cavity.

[0038] like Figure 3C As shown in FIG. 8 , the top surface of the base substrate 91 is exposed by grinding or polishing the molding member 86 from the upper surface of the molding member 86. Figure 3D As shown, the exposed base substrate 91 ( Figure 3C ) is etched away. Thus, a recess 86A is formed, and the insulating layer 20 is exposed at its bottom. By filling the recess 86A with a resin layer 50 ( Figure 1 ), thereby completing the semiconductor module.

[0039] Next, the excellent effects of the first embodiment will be described.

[0040] Figure 3C The base substrate 91 made of silicon shown in the figure has conductivity. In the structure where the base substrate 91 remains, parasitic capacitance is generated between the high-frequency circuit of the device layer 30 and the base substrate 91. The parasitic capacitance has a negative impact on the loss characteristics and noise characteristics. In the first embodiment, the base substrate 91 is removed and an insulating resin layer 50 ( Figure 1 ), thus reducing parasitic capacitance.

[0041] The thickness of the insulating layer 20 corresponding to the buried oxide layer of the SOI substrate is generally thin, about several μm, so the device layer 30 ( Figure 1 ) leaks the power of the high-frequency signal transmitted in the circuit inside the resin layer 50 ( Figure 1 ), resulting in electric loss caused by the dielectric loss tangent of the resin layer 50. In the first embodiment, the dielectric loss tangent of the resin layer 50 is smaller than the dielectric loss tangent of the molding member 86, so compared with the structure of covering the insulating layer 20 with the molding member 86, the electric loss caused by the dielectric loss tangent can be reduced.

[0042] In addition, since it is not necessary to use a material with a small dielectric loss tangent as the molded member 86, the degree of freedom in selecting the molded member is increased. Therefore, it is possible to select a material excellent in various characteristics (molding characteristics) required of the molded member, such as high adhesion, low stress, moisture resistance, and ease of molding.

[0043] Furthermore, since the mold member 86 having excellent molding characteristics is in close contact with the side surface of the semiconductor device 10 , an excellent effect of improving reliability is obtained.

[0044] Next, a modification of the first embodiment will be described.

[0045] In the first embodiment, the resin layer 50 ( Figure 1 ) uses epoxy resin containing fillers, but a dielectric material having a dielectric loss tangent smaller than that of the molded member 86, such as epoxy resin-based dielectrics, fluororesins (PTFE), liquid crystal polymer (LCP) resins, polyphenylene ether (PPE), fluorine-based elastomers, etc. may also be used. For example, it is preferred that the resin layer 50 uses a dielectric material having a dielectric loss tangent less than 0.003.

[0046] Next, other modified examples of the first embodiment will be described.

[0047] In the first embodiment, the molding member 86 is in close contact with the region outside the semiconductor device 10 in a plan view of the mounting surface of the mounting substrate 80, the side of the semiconductor device 10, and the side of the resin layer 50, but it is not necessarily necessary to be in close contact with the entire region of these surfaces. For example, an air gap may be provided between the molding member 86 and at least a portion of the region of the mounting surface 80A of the mounting substrate 80, the side of the semiconductor device 10, and the side of the resin layer 50. If a structure is adopted in which an air gap is provided between the molding member 86 and at least a portion of the region of the side of the semiconductor device 10 and the side of the resin layer 50, when the semiconductor device 10 includes a high-frequency amplifier circuit, the degradation of the distortion characteristics and loss of the semiconductor module can be suppressed.

[0048] [Second embodiment]

[0049] Next, refer to Figure 4 , Figure 5 ,as well as Figure 6 The semiconductor module of the second embodiment is described below. Figures 1 to 3D The common structure of the semiconductor module of the first embodiment described with reference to the accompanying drawings is omitted.

[0050] Figure 4 is a cross-sectional view of a semiconductor module of the second embodiment. Figure 1 ), there is a cavity between the device layer 30 and the mounting substrate 80. In contrast, in the second embodiment, a first component 85 is disposed between the device layer 30 and the mounting substrate 80. As the first component 85, for example, an epoxy resin containing filler is used. The dielectric loss tangent of the first component 85 is smaller than the dielectric loss tangent of the molding member 86. The first component 85 is, for example, Figure 3A In the manufacturing mid-stage shown, the capillary flow process can be used for filling. In addition, it is not necessary to fill the entire area of ​​the space between the device layer 30 and the mounting substrate 80 with the first member 85, and the first member 85 can be arranged only in a part.

[0051] Next, the excellent effects of the second embodiment will be described.

[0052] In the second embodiment, the resistance to external force and stress can be improved by filling the first component 85. In addition, since the dielectric loss tangent of the first component 85 is smaller than the dielectric loss tangent of the mold member 86, it is possible to suppress the increase in electric loss caused by the power of the high-frequency signal transmitted in the circuit of the device layer 30 leaking into the first component 85. In particular, the wiring 34T (see FIG. 1 ) on the top layer of the multilayer wiring layer 38 is Figure 5 ) easily leaks into the first component 85. In the case where the wiring for transmitting the high-frequency signal in the uppermost wiring 34T is long, an excellent effect of reducing the dielectric loss tangent of the first component 85 is significantly exhibited.

[0053] Next, refer to Figure 5 as well as Figure 6 , the preferred magnitude relationship between the dielectric loss tangent of the resin layer 50 and the dielectric loss tangent of the first member 85 is described.

[0054] Figure 5 This is a cross-sectional view of a portion of the semiconductor module of the second embodiment. A protective film 61 is disposed on the surface of the device layer 30 that faces the mounting substrate 80. A first component 85 is filled between the protective film 61 and the mounting substrate 80. The thickness of the protective film 61 is marked as T1, and the thickness of the insulating layer 20 is marked as T2.

[0055] Figure 6 : is a diagram showing the positional relationship of a plurality of bumps 70 when viewed from above. As an example, one of the plurality of bumps 70 is used as a terminal RFin for inputting a high-frequency signal, the other two bumps 70 are used as terminals RFout for outputting a high-frequency signal, and the other plurality of bumps 70 are used as terminals GND for grounding. The length of the longest line segment among the line segments connecting the geometric center of the input terminal RFin and the geometric center of the output terminal RFout is marked as Lio. Figure 6 In FIG. 1 , the shapes of the input terminal RFin and the output terminal RFout when viewed from above are shown as circles, but they do not necessarily need to be circles. For example, they may be rounded squares, or strips that are long in one direction.

[0056] In addition, there may be a case where a plurality of input terminals RFin are arranged. In this case, the length of the longest line segment among a plurality of line segments connecting the geometric centers of the plurality of terminals RFin and the geometric centers of the plurality of terminals RFout may be denoted as Lio.

[0057] In the device layer 30 ( Figure 5 ) is a power amplifier circuit for high-frequency signals, the high-frequency signal input from the input terminal RFin is transmitted in the wiring 34 in the multi-layer wiring layer 38, amplified by the semiconductor element 31, and output from the output terminal RFout. The input terminal RFin and the output terminal RFout are connected to the wiring 34T of the uppermost layer, and the wiring 34T of the uppermost layer is led in the in-plane direction. Therefore, usually, if the length Lio becomes longer, the wiring 34T of the uppermost layer for transmitting the high-frequency signal becomes longer.

[0058] As the wiring 34T of the uppermost layer becomes longer or as the thickness T1 of the protective film 61 becomes thinner, the power of the high-frequency signal transmitted in the device layer 30 is more likely to leak to the first component 85 than to the resin layer 50. In the case where the power of the high-frequency signal is more likely to leak to the first component 85 than to the resin layer 50, the dielectric loss tangent of the first component 85 can be made smaller than the dielectric loss tangent of the resin layer 50. For example, in the case where the length Lio is greater than 100 μm or the thickness T1 of the protective film 61 is thinner than the thickness T2 of the insulating layer 20, the dielectric loss tangent of the first component 85 can be made smaller than the dielectric loss tangent of the resin layer 50. In particular, in the case where the length Lio is greater than 100 μm and the thickness T1 is thinner than the thickness T2, the dielectric loss tangent of the first component 85 can be made smaller than the dielectric loss tangent of the resin layer 50. By varying the filling rate of the filler contained in the matrix resin, the dielectric loss tangent of the first member 85 and the resin layer 50 can be adjusted.

[0059] When the length Lio is less than 100 μm and the thickness T2 is equal to or less than the thickness T1 , the dielectric loss tangent of the resin layer 50 can be made smaller than the dielectric loss tangent of the first member 85 .

[0060] [Third embodiment]

[0061] Next, refer to Figures 7 to 9B The semiconductor module and the manufacturing method thereof according to the third embodiment are described with reference to the accompanying drawings. Figures 1 to 3D The common structure of the semiconductor module and the manufacturing method of the first embodiment described with reference to the accompanying drawings is omitted.

[0062] Figure 7 is a cross-sectional view of a semiconductor module according to a third embodiment. Figure 1 ), the top surface of the resin layer 50 is exposed. In contrast, in the semiconductor module of the third embodiment, the top surface and the side surfaces of the resin layer 50 are covered by the molding member 86.

[0063] Next, refer to FIG. 8A to FIG. 9B The method for manufacturing a semiconductor module according to the third embodiment is described with reference to the accompanying drawings. FIG. 8A to FIG. 9B The accompanying drawing is a cross-sectional view of a semiconductor module of the third embodiment at a mid-stage of manufacturing.

[0064] First, if Fig. 8A As shown in FIG. 1 , an SOI wafer 95 is prepared, which includes a base substrate 91 made of silicon, an insulating layer 20, and an element formation layer 39 made of single crystal silicon. A plurality of chip regions are divided in the SOI wafer 95. Fig. 8A ) of the plurality of chip regions respectively form semiconductor elements 31 ( Figure 5 ), on which a multilayer wiring layer 38 ( Figure 5 ). Therefore, if Figure 8B As shown, a device layer 30 is formed. A plurality of bumps 70 are formed on the device layer 30. In these steps, a general semiconductor wafer step is used.

[0065] like Figure 8C As shown in FIG. 1 , a temporary support substrate 92 is bonded to the front end surfaces of the plurality of bumps 70. Fig.8D As shown, the base substrate 91 is removed by etching. Thus, the insulating layer 20 is exposed. In a state where the base substrate 91 is removed, the temporary support substrate 92 mechanically supports the relatively thin insulating layer 20 and the device layer 30.

[0066] like Fig. 8E As shown in FIG. 1 , a resin layer 50 is bonded to the exposed surface of the insulating layer 20. As the resin layer 50, a resin substrate, an adhesive tape, etc. can be used. Fig.8FAs shown, the resin layer 50 is attached to the dicing tape 93. Then, as shown in FIG. Figure 8G As shown, the resin layer 50 , the insulating layer 20 , and the device layer 30 are cut into pieces.

[0067] exist Fig.9A 2 is a cross-sectional view of a singulated semiconductor device 10 and a resin layer 50. Fig. 9B As shown in FIG. 8 , the semiconductor device 10 is mounted on the mounting substrate 80. Then, as shown in FIG. Figure 7 As shown, a region of the mounting surface 80A outside the semiconductor device 10 in a plan view, side surfaces of the semiconductor device 10 , and side surfaces and a top surface of the resin layer 50 are covered with the molding member 86 .

[0068] Next, the excellent effects of the third embodiment will be described.

[0069] In the third embodiment as well, the dielectric loss tangent of the resin layer 50 disposed on the semiconductor device 10 is smaller than the dielectric loss tangent of the mold member 86. Therefore, similarly to the first embodiment, the electrical loss caused by the dielectric loss tangent can be reduced.

[0070] In the first embodiment, if Figure 3D As shown, after the semiconductor device 10 is singulated and mounted on the mounting substrate 80 and molded using the molding member 86, the resin layer 50 ( Figure 1 ). In contrast, in the third embodiment, as Fig. 8E As shown, the resin layer 50 is formed at the wafer level before being singulated. Therefore, the number of steps after mounting the semiconductor device 10 on the mounting substrate 80 can be reduced.

[0071] [Fourth embodiment]

[0072] Next, refer to Fig.10 The semiconductor module of the fourth embodiment is described below. Figures 7 to 9B The common structure of the semiconductor module of the third embodiment described with reference to the accompanying drawings is omitted.

[0073] Fig.10 is a cross-sectional view of a semiconductor module according to a fourth embodiment. Figure 7 ), there is a cavity between the device layer 30 and the mounting substrate 80. In contrast, in the semiconductor module of the fourth embodiment, the semiconductor module ( Figure 4 ) Similarly, a first member 85 is disposed between the device layer 30 and the mounting substrate 80. The dielectric loss tangent of the first member 85 is smaller than the dielectric loss tangent of the molding member 86.

[0074] Next, the excellent effects of the fourth embodiment will be described.

[0075] In the fourth embodiment, as in the third embodiment, the electric loss caused by the dielectric loss tangent can be reduced. Also, as in the second embodiment, the resistance to external force and stress can be improved. The preferred magnitude relationship between the dielectric loss tangent of the resin layer 50 and the dielectric loss tangent of the first component 85 is the same as in the second embodiment.

[0076] The above-mentioned embodiments are for illustration only. Of course, it is possible to partially replace or combine the structures shown in different embodiments. The same effects brought about by the same structures of multiple embodiments are not mentioned in sequence in each embodiment. In addition, the present invention is not limited to the above-mentioned embodiments. For example, it is obvious to those skilled in the art that various changes, improvements, combinations, etc. can be made.

[0077] Description of Reference Numerals

[0078] 10…semiconductor device; 20…insulating layer; 30…device layer; 31…semiconductor element; 31C…channel region; 31D…drain region; 31G…gate electrode; 31S…source region; 33D…drain contact electrode; 33S…source contact electrode; 34…wiring; 34P…solder pad; 34T…topmost wiring; 35…through hole; 37…guard ring; 38…multilayer wiring layer; 39…element forming layer; 39I…element separation region; 40…insulating layer; 50…resin layer; 60…interlayer insulating film; 61…protective film; 70…bump; 80…mounting substrate; 80A…mounting surface; 81…solder pad; 85…first component; 86…molding member; 86A…recess; 91…base substrate; 92…temporary supporting substrate; 93…dicing tape; 95…SOI wafer.

Claims

1. A semiconductor module, wherein: have: A mounting substrate having a mounting surface; A semiconductor device having a device layer formed with an electronic circuit including a semiconductor element, an insulating layer arranged on one surface of the device layer, and a plurality of bumps arranged on the other surface of the device layer, wherein the semiconductor device is mounted on the mounting substrate so that the surface of the device layer on which the plurality of bumps are arranged faces the mounting surface; A resin layer disposed on a surface of the insulating layer on a side opposite to the device layer side; as well as a molding member disposed on a region of the mounting surface that is outside the semiconductor device when viewed from above, a side surface of the semiconductor device, and at least a side surface of the resin layer, The dielectric loss tangent of the resin layer is smaller than that of the molding member.

2. The semiconductor module according to claim 1, wherein: The molding member covers a surface of the resin layer opposite to a surface facing the mounting substrate.

3. The semiconductor module according to claim 1 or 2, wherein: further comprising a first member made of resin, the first member being arranged in a space between the device layer and the mounting surface of the mounting substrate, The dielectric loss tangent of the first component is smaller than the dielectric loss tangent of the molded member.

4. The semiconductor module according to claim 3, wherein: The device layer includes an element formation layer on which the semiconductor element is formed, and a multilayer wiring layer stacked on the element formation layer, wherein the element formation layer is arranged between the multilayer wiring layer and the insulating layer. The semiconductor device further includes an insulating protective film disposed on a surface of the multilayer wiring layer that faces a side opposite to the element forming layer side. The thickness of the protective film is thinner than that of the insulating layer, and the dielectric loss tangent of the first member is smaller than that of the resin layer.

5. The semiconductor module according to claim 4, wherein: At least one of the multiple bumps is used as a terminal for inputting high-frequency signals, and at least one of the other bumps is used as a terminal for outputting high-frequency signals. The length of the shortest line segment among the line segments connecting the geometric center of the input terminal and the geometric center of the output terminal when viewed from above is greater than 100 μm.

6. The semiconductor module according to claim 3, wherein: The device layer includes an element formation layer on which the semiconductor element is formed, and a multilayer wiring layer stacked on the element formation layer, wherein the element formation layer is arranged between the multilayer wiring layer and the insulating layer. The semiconductor device further includes an insulating protective film disposed on a surface of the multilayer wiring layer that faces a side opposite to the element forming layer side. The thickness of the protective film is equal to or greater than the thickness of the insulating layer, and the dielectric loss tangent of the resin layer is smaller than the dielectric loss tangent of the first member.

7. The semiconductor module according to claim 6, wherein: At least one of the multiple bumps is used as a terminal for inputting high-frequency signals, and at least one of the other bumps is used as a terminal for outputting high-frequency signals. The length of the shortest line segment among the line segments connecting the geometric center of the input terminal and the geometric center of the output terminal when viewed from above is less than 100 μm.

8. The semiconductor module according to any one of claims 1 to 7, wherein: The molding member is in close contact with a region of the mounting surface that is outside the semiconductor device in a plan view, a side surface of the semiconductor device, and at least a side surface of the resin layer.

9. The semiconductor module according to any one of claims 1 to 7, wherein: An air gap is provided between the side surface of the semiconductor device and at least a portion of the side surface of the resin layer and the molding member.

10. A method for manufacturing a semiconductor module, wherein: The process includes: An SOI wafer is prepared in which an insulating layer and a device layer composed of a semiconductor are stacked on a base substrate composed of a semiconductor, and a plurality of chip regions are divided. A plurality of semiconductor elements are respectively formed in the plurality of chip regions of the device layer, forming a multilayer wiring layer on the device layer on which the plurality of semiconductor elements are formed, forming a plurality of bumps on the multi-layer wiring layer, After forming the plurality of bumps, the base substrate is removed to thin the SOI wafer. A resin layer is disposed on the exposed surface of the insulating layer of the SOI wafer after thinning. After the resin layer is disposed, the SOI wafer and the resin layer are singulated to produce a plurality of semiconductor devices. flip-chip mounting one of the plurality of semiconductor devices on a mounting surface of a mounting substrate, covering a region of the mounting surface that is outside the semiconductor device in a plan view and at least a side surface of the semiconductor device with a molding member, The dielectric loss tangent of the resin layer is smaller than that of the molding member.

11. The method for manufacturing a semiconductor module according to claim 10, wherein: After mounting the semiconductor device on the mounting substrate and before covering with the molding member, a first member including resin and having a dielectric loss tangent smaller than that of the molding member is disposed between the device layer and the mounting substrate.

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