A resource allocation board for testing machine and detection method thereof

Abstract

The present invention relates to the technical field of chip testing equipment, and specifically discloses a resource allocation board for a testing machine and a detection method thereof, wherein the board comprises a resource board and a motherboard, the power supply and input control signals of the digital channel board, the power supply board, and the high-current PMU board are all input from a backboard, the input control signal originates from a system control board in a power cabinet, and the interface definitions and connectors of the three resource boards and the backboard are exactly the same; the resource boards are all connected to the motherboard through connectors for output, and the connectors used for connecting the digital channel board, the power supply board, and the high-current PMU board to the motherboard are exactly the same; the connectors in the motherboard are redistributed in a high-fidelity test interface through cables and connected to a probe card for wafer testing.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing equipment, and in particular to a resource allocation board for a testing machine and a detection method thereof. Background Art

[0002] With the continuous advancement of electronic technology, personal computers, workstations, smart devices, monitoring equipment, etc. are widely popularized. These devices use a large number of memory chips, control chips, logic chips, etc., making the importance of chip testing equipment increasingly prominent. When testing memory chips, in order to improve the test efficiency, multi-channel simultaneous testing is usually adopted, which requires the tester to have many channels.

[0003] At present, most designed load boards often use fixed area interfaces and channels in circuit design, and the board compatibility is poor. When faced with different test requirements, the board has to be redesigned, which not only increases the cost, but also consumes a lot of time and energy. Take our company's memory chip tester as an example, it includes digital channel board, power channel board, high current channel board, and the total number of channels is over 10,000. Such a large number of channels need to be integrated on the motherboard, and then connected to the probe card through cables. There are many problems in practical applications: on the one hand, the large number of channels leads to a large number of transfer cables, the installation space of the motherboard and cable is tight, and the installation and removal operations are cumbersome; on the other hand, it is very important to detect the connectivity of the motherboard and cable before installation, but the existing detection methods are not convenient and efficient enough. At the same time, when locating channel problems, the traditional control variable method of exchanging various boards is inefficient, which is not conducive to the rapid maintenance of equipment.

[0004] In addition, when storing calibration data, the existing technology has a contradiction between accuracy and storage space. To improve accuracy, a large-capacity flash memory is required to store calibration data, resulting in insufficient flexibility in the storage and use of calibration data. In the entire test system, due to the complex connection links from the resource board to the terminal, the existing detection method is difficult to accurately determine whether the problem in the calibration process is caused by a short circuit or the resource board itself. Summary of the invention

[0005] The purpose of the present invention is to provide a resource allocation board for a test machine and a detection method thereof to solve the above technical problems: The purpose of the present invention can be achieved through the following technical solutions: A resource allocation board for a test machine, comprising a resource board and a motherboard, wherein the resource board comprises a digital channel board, a power board and a high-current PMU board; The power supply and input control signals of the digital channel card, power card, and high-current PMU card are all input from the backplane, and the input control signal originates from the system control card in the power cabinet, and the interface definitions and connectors of the three resource cards and the backplane are exactly the same; The digital channel board, the power board and the high-current PMU board are all connected to the motherboard through connectors for output, and the connectors used by the digital channel board, the power board and the high-current PMU board to connect to the motherboard are completely consistent; The connectors in the motherboard are redistributed in a high-fidelity test interface through cables and docked with a probe card for wafer testing.

[0006] As a further solution of the present invention: the sequence of the slots on the motherboard is fixedly defined by the backplane through the control board in the power cabinet, and each control board corresponds to a resource board at a fixed position; Each resource board is connected to the motherboard through four connectors. The connector located at the back of the motherboard is defined as the Site side; the connector located at the front of the motherboard and used for connecting with the high-fidelity test interface is defined as the LIF side.

[0007] As a further solution of the present invention: the channels in the digital channel card connector are output in one-to-one correspondence with the channels in the LIF side connector; the channels in the power card and the high-current PMU card are output in the LIF side connector in a laterally uniformly distributed manner.

[0008] As a further solution of the present invention: the motherboard also includes MB-I and MB-J, wherein MB-I connects power supplies and ground planes in different quadrants, and MB-J connects the motherboard and the backplane to introduce control signals in the control board.

[0009] A detection circuit for a resource allocation board of a test machine, the detection circuit comprising a detection board, a measurement board and a motherboard: The connector in the detection board is connected to the LIF side connector in the motherboard through a cable. When the circuit is connected and there is no open or short circuit problem in the motherboard, the light-emitting diode in the detection board emits light normally. The backplane is connected to the Site side of the motherboard to provide an external 5V input level; The measurement board is a multiplexing and analog-to-digital converter module in the system resource board. The signals in the motherboard are connected to the multiplexing selector in the measurement board. The signals include 1 PMU signal, 33 DPS signals, 82 PE signals and 10 Ubit signals. These signals collect voltage through the analog-to-digital converter of the control board, and the open circuit or short circuit situation is judged according to the collected voltage. During the test, the MB-J board connecting the motherboard and the backplane is not used. Instead, the connector interface of the MB-J is used to connect to the measurement board through a cable, and the test results of the motherboard are displayed synchronously.

[0010] A method for detecting a resource allocation board of a test machine, the method comprising: Conduct circuit continuity test through the detection circuit: Connect the detection board to the LIF side connector of the motherboard through a cable. The backplane provides a 5V input level to the Site side of the motherboard. Preliminary judgment on whether the motherboard has an open or short circuit problem is made based on whether the LED in the detection board emits light normally. If there is a problem channel, the time domain reflection method is used to locate the problem point: the resource board generates a step signal for the channel with the on-off problem. The signal is transmitted through the resource board, connector, motherboard, connector and cable, high-fidelity test interface, and probe card path, and then the reflected voltage is collected; according to the reflected voltage, the formula is used Calculate the impedance value at the suspected breakpoint; Where Z dut is the impedance at the suspected breakpoint, Z0 is the known characteristic impedance, V i is the incident voltage, V r is the reflected voltage; According to the performance of the impedance value on the time axis and the signal propagation speed, the location of the breakpoint is calculated, and the TDR curve is generated and displayed.

[0011] As a further solution of the present invention: before performing wafer testing, the entire system path is firstly tested for open and short circuits to eliminate the influence of path open and short circuits on the calibration results.

[0012] The beneficial effects of the present invention are as follows: by designing a compatible resource board interface and a flexibly designed motherboard, different test requirements can be met by simply replacing the motherboard, avoiding the need to redesign the board each time, and reducing costs and design cycles; the detection circuit is slightly modified on the basis of the original system, and only the interface board in contact with the chip to be tested needs to be replaced to operate in the e-commerce work platform (EWS), and multiple functions of the original system can be reused. Each pin is connected to a light-emitting diode, which can visually observe the on-off results of different channels, and is convenient for quickly detecting the motherboard and cable connectivity before installation and on-site troubleshooting; the time domain reflection technology is used to locate the channel problem point, which greatly improves the positioning efficiency compared to the traditional control variable method, and is convenient for maintenance personnel to quickly determine the breakpoint position, and replace the components or boards at the specified position in time, thereby enhancing the maintainability of the equipment; after the installation is completed and before calibration, the entire system path open and short circuit detection is introduced to eliminate the influence of the path open and short circuit on the calibration result, and improve the accuracy of calibration. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The present invention will be further described below in conjunction with the accompanying drawings.

[0014] Figure 1 It is a structural schematic diagram of a resource allocation board for a test machine according to the present invention; Figure 2 It is a structural diagram of the template of the present invention; Figure 3 It is a structural schematic diagram of the detection circuit of the present invention; Figure 4 It is a schematic diagram of the principle of impedance calculation of the present invention; Figure 5 It is a schematic diagram of the breakpoint position of the present invention. DETAILED DESCRIPTION

[0015] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0016] The present invention is a resource allocation board for a test machine. The test head (Tester Header) is divided into 4 quadrants, each quadrant is as follows: Figure 1 As shown: The system's resource boards are divided into three types: digital channel board (HSU320), power board (PSU128) and high-current PMU board (HCU512); 1) The power supply and input control signals are input from the backplane. The control signals are from the system control board (SMB) in the power cabinet. The interface definitions and connectors of the three resource boards and the backplane are exactly the same.

[0017] 2) The outputs of the three resource boards are connected to the motherboard (MotherBoard or MB) through connectors (the connectors of the three boards are exactly the same) for output.

[0018] 3) Due to the input compatibility and output connector compatibility, the three boards are compatible, and only a new motherboard needs to be designed to meet different types of test requirements.

[0019] 4) The connector in the motherboard is redistributed in the high-fidelity test interface (HIFIX) through cable and docked with the probecard for wafer testing.

[0020] Motherboard block diagram Figure 2 As shown: 1) The sequence of channels (slots) is fixedly defined through the backplane using the SMB control board in the power cabinet, and each slot corresponds to a resource board in a fixed position.

[0021] 2) Each resource board has four connectors that connect to the Mother Board. They are plugged into the back of the Mother Board and are called the Site side. The connectors that connect to the HIFIX are placed on the front of the Mother Board and are called the LIF side.

[0022] 3) The channels in the digital board HSU320 connector correspond to the channels in the LIF side connector one by one, and the channels in the power board PSU128 and the high current board HCU512 are evenly distributed in the horizontal direction and output in the LIF side connector.

[0023] 4) MB-I connects the power and ground planes in different quadrants, which facilitates the calibration of the power and ground planes in different quadrants. MB-J connects the Mother Board and the backplane, so that the control signals in the SMB can be introduced.

[0024] The detection circuit is composed of Figure 3 As shown in the figure, the connector in the check board is connected to the LIF side connector in the Mother Board through a cable. When the circuit is connected and the Mother Board has no open or short circuit problem, the LED in the Check Board lights up normally. The backplane is connected to the Site side of the Mother Board to provide an external 5V input level. The signals in the Mother Board are connected to the multiplexer in the Measure Board. The signals in each connector include 17 PMU signals, 33 DPS signals, 82 PE signals, and 10 Ubit signals. Finally, the detection results of the Mother Board will be synchronously displayed in the EWS for user reference.

[0025] like Figure 4 As shown, a detection method for a resource allocation board of a test machine includes: Use the time domain reflectometry method to check the problem point: 1) Since there are many connections used in the entire path from the resource board to the terminal: resource board-connector-motherboard-connector and harness-HiFix-Probe Card. In the third step, we use the detection circuit to find out all the channels. If there is a problem, we need to find the point where the problem occurs in the entire path, which is very difficult to maintain the entire system. Therefore, we added the time domain reflection method after the detection circuit is on and off to locate the point where the problem occurs in this channel, which greatly increases the maintainability of the entire system.

[0026] 2) The principle of time domain reflection: For channels with continuity issues, a step signal will be generated inside the resource board. After passing through the above path, the reflected voltage will be collected. The impedance value of the impedance discontinuity (which may be the breakpoint) will be calculated based on the reflected voltage. The position of the breakpoint will be calculated based on the performance of the impedance value on the entire time axis. Finally, the final TDR curve is obtained through integration and displayed in the EWS for user reference.

[0027] 3) Impedance calculation at suspected breakpoints: Assume that the DUT (chip under test) is a transmission line with a 60ohm characteristic impedance and a 250ps delay. The voltage curve measured at point A is shown in the figure below. Based on the voltage waveform at point A, the impedance information of the subsequent DUT can be calculated as follows: Z0 and Z dut The incident voltage and reflected voltage at the junction point are V i ,V r . Then the reflection coefficient formula is: V r / V i =(Z dut -Z0) / (Z dut +Z0); Then Z dut =Z0*(V i +V r ) / (V i -V r ); Depend on Figure 4 We can see V r is equal to 0.091V, and Z dut =50*(1+0.091) / (1+0.091)=60.

[0028] 4) Calculation of the location of suspected breakpoints like Figure 5As shown, a 48ohm, 5-inch line, at a propagation speed of 6mil / ps, and then the wave propagates twice the transmission distance back and forth, it can be obtained that it takes about 1.66ns, which is almost consistent with the time in the figure: t=2*5000mil / (6mil / ps)=1.66ns; Conversely, we can also get the position of the distance sampling point based on the time of the impedance discontinuity point in the image.

[0029] That is: l=(1.66ns*6mil / ps) / 2=5inch; In other words, if there is a breakpoint somewhere from the resource board to the terminal, the distance of the suspected breakpoint can be calculated based on the relationship between time and impedance in time domain reflection and the time of the high impedance point, and the breakpoint can be determined based on the distance.

[0030] The above is a detailed description of an embodiment of the present invention, but the content is only a preferred embodiment of the present invention and cannot be considered to limit the scope of implementation of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of the patent coverage of the present invention.

Claims

1. A resource allocation board for a test machine, characterized in that: It includes resource boards and motherboards, wherein the resource boards include digital channel boards, power boards and high-current PMU boards; The power supply and input control signals of the digital channel card, power card, and high-current PMU card are all input from the backplane, and the input control signal originates from the system control card in the power cabinet, and the interface definitions and connectors of the three resource cards and the backplane are exactly the same; The digital channel board, the power board and the high-current PMU board are all connected to the motherboard through connectors for output, and the connectors used by the digital channel board, the power board and the high-current PMU board to connect to the motherboard are completely consistent; The connectors in the motherboard are redistributed in a high-fidelity test interface through cables and docked with a probe card for wafer testing.

2. A resource allocation board for a test machine according to claim 1, characterized in that: The sequence of the slots on the motherboard is fixedly defined by the backplane through the control board in the power cabinet, and each control board corresponds to a resource board at a fixed position; Each resource board is connected to the motherboard through four connectors. The connector located at the back of the motherboard is defined as Siteside; the connector located at the front of the motherboard and used for connecting with the high-fidelity test interface is defined as LIF side.

3. A resource allocation board for a test machine according to claim 2, characterized in that: The channels in the digital channel card connector are output in one-to-one correspondence with the channels in the LIF side connector; the channels in the power card and the high-current PMU card are output in the LIF side connector in a uniformly distributed manner in the horizontal direction.

4. A resource allocation board for a test machine according to claim 2, characterized in that: The motherboard also includes MB-I and MB-J, wherein MB-I connects power supplies and ground planes in different quadrants, and MB-J connects the motherboard and the backplane to introduce control signals in the control board.

5. A detection circuit for a resource allocation board of a test machine, characterized in that: Applied to the resource allocation board according to any one of claims 1 to 4, the detection circuit comprises a detection board, a measurement board and a motherboard: The connector in the detection board is connected to the LIF side connector in the motherboard through a cable. When the circuit is connected and there is no open or short circuit problem in the motherboard, the light-emitting diode in the detection board emits light normally. The backplane is connected to the Site side of the motherboard to provide an external 5V input level; The measurement board is a multiplexing and analog-to-digital converter module in the system resource board. The signals in the motherboard are connected to the multiplexing selector in the measurement board. The signals include 1 PMU signal, 33 DPS signals, 82 PE signals and 10 Ubit signals. These signals collect voltage through the analog-to-digital converter of the control board, and the open circuit or short circuit situation is judged according to the collected voltage. During the test, the MB-J board connecting the motherboard and the backplane is not used. Instead, the connector interface of the MB-J is used to connect to the measurement board through a cable, and the test results of the motherboard are displayed synchronously.

6. A method for testing a resource allocation board of a test machine, characterized in that: Applied to the detection circuit of claim 5, the method comprises: Conduct circuit continuity test through the detection circuit: Connect the detection board to the LIF side connector of the motherboard through a cable. The backplane provides a 5V input level to the Site side of the motherboard. Preliminary judgment on whether the motherboard has an open or short circuit problem is made based on whether the LED in the detection board emits light normally. If there is a problem channel, the time domain reflection method is used to locate the problem point: the resource board generates a step signal for the channel with on-off problem. The signal is transmitted through the resource board, connector, motherboard, connector and cable, high-fidelity test interface, and probe card path, and then the reflected voltage is collected; according to the reflected voltage, the formula is used Calculate the impedance value at the suspected breakpoint; Where Z dut is the impedance at the suspected breakpoint, Z0 is the known characteristic impedance, V i is the incident voltage, V r is the reflected voltage; According to the performance of the impedance value on the time axis and the signal propagation speed, the location of the breakpoint is calculated, and the TDR curve is generated and displayed.

7. A method for detecting a resource allocation board of a test machine according to claim 6, characterized in that: Before conducting wafer testing, the entire system path is first tested for open and short circuits to eliminate the impact of path open and short circuits on calibration results.

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