A method and system for selecting a wafer stacking scheme

Abstract

The present invention relates to the field of semiconductor stacking technology, and particularly relates to a method and system for selecting a wafer stacking scheme. A wafer has a plurality of valid die and invalid die. The method includes: selecting at least one first wafer from candidate wafers according to a first selection rule, and a plurality of second wafers can be stacked on the first wafer; continuing to select at least one second wafer group corresponding to the first wafer from the candidate wafers, and the second wafer group includes: m second wafers; calculating stacking metrics of at least one simulated stacking scheme by using a stacking evaluation model; wherein, the simulated stacking scheme is a scheme formed by stacking the first wafer and the second wafer group; determining whether the stacking metrics are greater than a set first stacking threshold, and if so, outputting the corresponding simulated stacking scheme. The selection method proposed by the present invention can improve the yield of semiconductor stacking, that is, improve the utilization rate of candidate wafers and reduce the cost of stacking.

Description

Technical Field

[0001] The present invention relates to the technical field of wafer stacking, and specifically relates to a method and system for selecting a wafer stacking scheme. Background Art

[0002] Currently, the yield of wafer-level stacked semiconductor devices is greatly affected by the process yield during wafer manufacturing or bonding. If there is a functional abnormality in one layer of the stacked chips, the entire stacked chips will be damaged, resulting in a decrease in process yield. To solve the yield problem, improve production efficiency, and improve the performance of stacked chips, the related art may adopt the method of reconstructing wafers. However, since organic materials are introduced during wafer reconstruction, the complexity of the wafer reconstruction process increases, the reconstructed wafers are deformed greatly, and the process line width increases, which cannot meet the requirements of high-density hybrid bonding processes, making it difficult to achieve multi-layer stacking of wafers.

[0003] In addition, Patent Application CN108701675A also discloses a corrective die for wafer / die stacking. In this method, corrections can be provided for defective dies in wafer-to-wafer stacking or die stacking. The corrective die is coupled to the die in the stack including the defective die. The corrective die electrically replaces the defective die. This method attempts to reduce the stacking cost increased due to defects by setting corrective dies.

[0004] However, with the application of wafer-level stacked semiconductor devices in various fields such as accelerating AI, big data, and supercomputing, the current requirements for the computing power performance, yield, etc. of wafer-level stacked semiconductor devices are also getting higher and higher. Especially when the functional integration degree of semiconductor devices increases, the number of stacking layers to be set and the number of effective functional regions in one layer also increase significantly. However, the traditional yield optimization methods still have great limitations when facing these challenges.

[0005] Therefore, there is an urgent need for a method that can control the yield of semiconductor devices during the stacking process. Summary of the Invention

[0006] The purpose of the present invention is to provide a method and system for selecting a wafer stacking scheme, which can partially solve or alleviate the above deficiencies in the prior art, and can improve the effective utilization rate of wafers and reduce the stacking cost.

[0007] To solve the above-mentioned technical problems, the present invention specifically adopts the following technical solutions:

[0008] In the first aspect of the present invention, a method for selecting a wafer stacking scheme is provided. A plurality of dies are spacedly arranged on the wafer. The dies include: effective dies and invalid dies. Correspondingly, the method includes the steps:

[0009] S101. Select at least one first wafer from the candidate wafers according to the first selection rule. Multiple second wafers can be stacked on the first wafer. The first selection rule requires that the number of valid die in the first wafer is greater than or equal to a preset first valid quantity T1.

[0010] S102. Continue to select at least one second wafer group corresponding to the first wafer from the candidate wafers. The second wafer group includes: m pieces of the second wafers;

[0011] S103. Calculate the stacking metrics of at least one simulated stacking scheme using a stacking evaluation model. Among them, the simulated stacking scheme is a scheme composed of stacking the first wafer and the second wafer group, and the stacking evaluation model is:

[0012] L = aX + bY ;

[0013] Y = m + 1 ;

[0014] L is the stacking metric, a is the first weight, b is the second weight, X is the effective quantity of effective channels, Y is the number of layers of effective stacking. Among them, when the die of multiple candidate wafers in the first wafer and the second wafer group are all valid die under the same coordinate, it is considered that the corresponding valid die form an effective channel;

[0015] S104. Judge whether the stacking metric is greater than a set first stacking threshold. If so, output the corresponding simulated stacking scheme; if not, return to S102.

[0016] In some embodiments, the valid die are divided into first-class valid die and second-class valid die. Among them, the first-class valid die are in a workable state, and the second-class valid die can be repaired to a workable state through at least one repair process.

[0017] In some embodiments, the stacking evaluation model is:

[0018] L = aX + bY ;

[0019] Y = m + 1 ;

[0020] ;

[0021] Wherein, n is the number of the second type of effective grains in the effective channels, is the th repair cost of the second type of effective grains, is the set maximum repair cost.

[0022] In some embodiments, it further includes steps:

[0023] Partition α candidate partitions in the candidate wafers;

[0024] Calculate the effective grain metrics in the candidate partitions respectively, where the effective grain metric is the number of effective grains, or the effective grain metric is the proportion of the number of effective grains in the grains;

[0025] Divide multiple candidate wafers into multiple candidate combinations according to the effective grain metrics, wherein one candidate combination includes: multiple candidate wafers; in the same candidate combination, the number of candidate partitions with a first correlation between one candidate wafer and another candidate wafer is greater than a first correlation threshold; wherein, when the difference between the effective grain metrics of two candidate partitions at the same position of two candidate wafers is less than or equal to the set first effective threshold, it is considered that the two candidate partitions have a first correlation with each other.

[0026] In some embodiments, S102 includes steps:

[0027] For the current first wafer selected in the current S101, select multiple first candidate wafers from the first candidate combination, and the first candidate combination is the candidate combination to which the first wafer belongs.

[0028] In some embodiments, it further includes steps:

[0029] When the stacking metric of the simulated stacking scheme is less than or equal to the first stacking threshold, it is considered that the current second wafer group belongs to a sub-optimal stacking scheme;

[0030] Correspondingly, S102 further includes:

[0031] Select at least one second candidate wafer from the second candidate combination; wherein, the number of candidate partitions with a first correlation between the candidate wafers in the second candidate combination and the current first wafer is greater than a second correlation threshold and less than or equal to the first correlation threshold;

[0032] Form a new second wafer group by combining the at least one second candidate wafer with the multiple first candidate wafers;

[0033] And re-enter S103 according to the new second wafer group.

[0034] In some embodiments, it further includes the steps of:

[0035] Set a first invalid candidate count for the first candidate combination; wherein, when the second wafer group selected from the first candidate combination belongs to a sub-optimal stacking scheme, record that the first candidate set has generated one invalid candidate;

[0036] Monitor the first invalid candidate count within a first time period;

[0037] When the first invalid candidate count is greater than a set invalid threshold, it is recommended to update the grouping of the candidate combination.

[0038] The present invention also provides a system for selecting a wafer stacking scheme. A plurality of die are spacedly arranged on the wafer, and the die include: valid die and invalid die. Correspondingly, the system:

[0039] A first selection module, configured to select at least one first wafer from candidate wafers according to a first selection rule. Multiple second wafers can be stacked on the first wafer, and the first selection rule requires that the number of valid die in the first wafer is greater than or equal to a preset first valid quantity T1;

[0040] A second selection module, configured to further select at least one second wafer group corresponding to the first wafer from the candidate wafers. The second wafer group includes: m second wafers;

[0041] An evaluation module, configured to calculate stacking metrics of at least one simulated stacking scheme by using a stacking evaluation model; wherein, the simulated stacking scheme is a scheme formed by stacking the first wafer and the second wafer group, and the stacking evaluation model is:

[0042] L = aX + bY ;

[0043] Y = m + 1 ;

[0044] L is the stacking metric, a is the first weight, b is the second weight, X is the valid channel metric, Yis an effective stacking index; wherein, when the dies of the first wafer and multiple candidate wafers in the second wafer group at the same coordinate are all effective dies, it is considered that a corresponding effective channel is formed by the effective dies.

[0045] A recommendation module, configured to determine whether the stacking index is greater than a set first stacking threshold. If so, output the corresponding simulated stacking scheme; if not, return to the second selection module.

[0046] In some embodiments, the effective dies are classified into first-class effective dies and second-class effective dies; wherein, the first-class effective dies are in a workable state, and the second-class effective dies can be repaired to a workable state through at least one repair process.

[0047] In some embodiments, the stacking evaluation model is:

[0048] L = aX + bY ;

[0049] Y = m + 1 ;

[0050] ;

[0051] Wherein, n is the number of the second-class effective dies in the effective channel, is the repair cost of the th second-class effective die, is the set maximum repair cost.

[0052] Beneficial technical effects:

[0053] The present invention provides a method for selecting a wafer stacking scheme, that is, a wafer selection method. This wafer selection method can quickly screen multiple candidate wafers from two dimensions of stacking yield and stacking performance, so as to comprehensively screen out a better second wafer group. And, from the perspective of candidate wafers, the overall evaluation of stacking yield and performance can improve the effective utilization rate of candidate wafers, and simulate the best stacking scheme in the current candidate wafer library. Thus, the present invention can reduce the stacking cost increased due to invalid stacking (such as too low available stacking layers, or too few effective channels after stacking).

[0054] Furthermore, the present invention also provides a hierarchical selection mode based on the evaluation of relevant candidate partitions. Specifically, the massive candidate wafers are grouped by using the regional relevance evaluation, and then the second wafer group is screened step by step according to the candidate priorities corresponding to the groups, so as to improve the efficiency of the selection process and reduce the amount of invalid calculations to a certain extent when facing a large number of available candidate wafers.

[0055] Furthermore, the present invention also provides an update mechanism for updating the grouping mode based on the application time and screening accuracy. For example, the present invention monitors the candidate results (such as the success rate of the candidate stacking scheme), and flexibly adjusts the division and grouping rules of the candidate partitions in combination with the candidate results, so as to improve the accuracy and reliability of the candidate priority classification, thereby further improving the efficiency of the selection process. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts do not necessarily draw according to the actual scale. Obviously, the following drawings are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained according to these drawings without creative efforts.

[0057] Figure 1 It is a schematic structural diagram of an exemplary candidate wafer in the present invention;

[0058] Figure 2 It is a schematic structural diagram of another exemplary candidate wafer in the present invention;

[0059] Figure 3 It is a schematic diagram of the setting of candidate partitions for candidate wafers in an exemplary embodiment of the present invention;

[0060] Figure 4 It is a schematic diagram of the setting of candidate partitions for candidate wafers in another exemplary embodiment of the present invention;

[0061] Figure 5 It is a schematic diagram of the stacking relationship of wafers in an exemplary embodiment of the present invention;

[0062] Figure 6 It is a schematic flowchart of the stacking scheme selection method in an exemplary embodiment of the present invention;

[0063] Figure 7 It is a schematic diagram of the module structure of the stacking scheme selection system in an exemplary embodiment of the present invention.

[0064] Summary of reference numeral identification: wafer 01, die 010, first wafer 011, second wafer 012, wafer A 012a, wafer E 012e, first candidate partition 10, second candidate partition 20, third candidate partition 30. Detailed implementation manners

[0065] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0066] In this document, suffixes such as "module", "component", or "unit" used to represent elements are only for facilitating the description of the present invention and have no specific meaning in themselves. Therefore, "module", "component", or "unit" can be used interchangeably.

[0067] In this document, terms such as "upper", "lower", "inner", "outer", "front", "rear", "one end", "the other end", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for facilitating the description of the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0068] In this document, unless otherwise clearly specified and defined, terms such as "installed", "provided with", "connected", etc. shall be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0069] In this document, "and / or" includes any and all combinations of one or more of the listed related items.

[0070] In this document, "a plurality of" means two or more, that is, it includes two, three, four, five, etc.

[0071] As used in this specification, the term "about" typically means + / - 5% of the stated value, more typically + / - 4% of the stated value, more typically + / - 3% of the stated value, more typically + / - 2% of the stated value, even more typically + / - 1% of the stated value, and even more typically + / - 0.5% of the stated value.

[0072] In this specification, certain embodiments may be disclosed in a format that is within a certain range. It should be understood that this description of "within a certain range" is merely for convenience and brevity and should not be construed as a rigid limitation on the disclosed range. Therefore, the description of a range should be considered to have specifically disclosed all possible sub-ranges and the individual numerical values within that range. For example, the description of the range 1 - 6 should be considered to have specifically disclosed sub-ranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., as well as the individual numbers within that range, such as 1, 2, 3, 4, 5, and 6. The above rules apply regardless of the breadth of the range.

[0073] In this context, a wafer refers to a silicon wafer used to fabricate silicon semiconductor circuits. A "die" can be a small piece cut from a wafer and is also referred to as a "Die". A "die" with a circuit structure processed thereon can also be referred to as a "chip". For example, see Figure 1 As shown, a plurality of dies 010 are formed at intervals on a wafer 01, and the die marked "G" indicates that the die is a valid die, that is, the die can communicate with other dies normally (such as electrical signal communication) after stacking.

[0074] Generally, a plurality of dies need to be stacked to form a complete semiconductor device. For example, on a mother die (for example, it can be a packaging substrate, that is, Substrate (abbreviated as SUB)), or it can be a packaging substrate with multiple wafer layers stacked in sequence. Among them, one wafer layer includes a plurality of dies. In particular, one wafer layer refers to 1 wafer with a plurality of dies.

[0075] See Figure 5 As shown, a plurality of wafers are stacked in sequence from bottom to top to form a semiconductor device. In the exemplary stacking process of the present invention, first, a first wafer 011 can be selected from a plurality of candidate wafers, and the first wafer 011 is packaged as the bottommost wafer. Subsequently, a plurality of second wafers 012 (such as wafer A012a... wafer E012e, etc.) are selected from the remaining plurality of candidate wafers and stacked on top of the first wafer in sequence to form a semiconductor device.

[0076] As Figure 1 、 Figure 2As shown, a wafer is provided with multiple dies. When the dies located at the same coordinates in multiple wafers are all valid dies, an effective path can be formed between the multiple dies, that is, normal signal connection can be performed. And when there are a relatively large number of effective paths in a semiconductor device, it can be regarded as an effective product.

[0077] Embodiment 1

[0078] Refer to Figure 6 As shown, the present invention provides a method for selecting a wafer stacking scheme. Multiple dies are spacedly arranged on the wafer. The dies include: valid dies and invalid dies. Correspondingly, the method includes the steps:

[0079] S101, select at least one first wafer from candidate wafers. Multiple second wafers can be stacked on the first wafer.

[0080] For example, in some embodiments, the first wafer is selected from candidate wafers according to a first selection rule. Specifically, the first selection rule requires that the number of valid dies in the first wafer is greater than or equal to a preset first valid number T1.

[0081] Again, for example, in some embodiments, a first wafer is directly selected arbitrarily from the wafers marked as good products.

[0082] S102, continue to select at least one second wafer group corresponding to the first wafer from the candidate wafers. The second wafer group includes: m candidate wafers (equivalent to selecting multiple second wafers);

[0083] S103, calculate the stacking metrics of at least one simulated stacking scheme by using a stacking evaluation model; wherein, the simulated stacking scheme is a scheme formed by stacking the first wafer and the second wafer group, and the stacking evaluation model is:

[0084] L = aX + bY ;

[0085] Y = m + 1 ;

[0086] L is the stacking metric, a is the first weight, b is the second weight, X is the effective number of effective channels, Yis the number of layers for effective stacking; wherein, when the dies of the first wafer and multiple candidate wafers in the second wafer group at the same coordinate are all effective dies, it is considered that a corresponding effective channel is formed by the effective dies;

[0087] In this embodiment, the yield of the semiconductor product with a reactive stack is characterized by the effective number of effective channels.

[0088] For example, in some embodiments, the effective number of effective channels X is the actual number of effective channels.

[0089] Again, for example, in some embodiments, the effective number of effective channels X can also be the relative number of effective channels.

[0090] Further, the method further includes the step: S104, determining whether the stacking index is greater than a set first stacking threshold. If so, output the corresponding simulation stacking scheme (equivalent to outputting as a recommended scheme); if not, return to S102.

[0091] In some embodiments, multiple second wafer groups can be selected simultaneously, and the stacking indexes of the multiple simulation stacking schemes formed can be calculated simultaneously.

[0092] For example, in some embodiments, one or more simulation stacking schemes with the largest stacking index can be selected as the recommended scheme.

[0093] In some embodiments, there can be a same second wafer between any two selected second wafer groups.

[0094] In some embodiments, the number of second wafers in the second wafer group can be about 1 - 10. Of course, as the requirement for the integration degree of semiconductor devices (also known as: stacked devices) is getting higher and higher, the number of second wafers can also increase accordingly. In this embodiment, the number of stacked layers is used to characterize the functional integration degree, that is, the performance, of the stacked semiconductor devices.

[0095] The present invention provides a method for selecting a wafer stacking scheme, that is, a wafer selection method. This wafer selection method can quickly screen multiple candidate wafers from two dimensions of stacking yield and stacking performance, so as to comprehensively screen out a group of better second wafer groups. And, from the perspective of candidate wafers, the overall evaluation of stacking yield and performance can improve the effective utilization rate of candidate wafers and simulate the best stacking scheme in the current candidate wafer library. Thus, the present invention can reduce the stacking cost increased due to ineffective stacking (such as too low available number of stacked layers, or too few effective channels after stacking).

[0096] In some embodiments, the effective grains are divided into first-class effective grains and second-class effective grains. Among them, the first-class effective grains are in a workable state, that is, they can be normally electrically connected to adjacent grains, and the second-class effective grains can be repaired to a workable state through at least one repair process.

[0097] Generally, when there are certain defects on a grain, it may lead to certain failures in its electrical connection performance. Therefore, such grains can be classified as second-class effective grains. Moreover, due to the different types and quantities of the generated defects, the repair processes required for different second-class effective grains will also vary. Correspondingly, the repair difficulties or repair costs required for different second-class effective grains are also different. Among them, when the defects of a grain are too many to be repaired, or the repair cost is too high to meet the cost requirements, it can be classified as an ineffective grain.

[0098] In some embodiments, the second-class effective grains can be further divided into more subcategories according to their repair difficulties or repair costs, such as first-second-class grains, second-second-class grains, third-second-class grains, and so on.

[0099] For example, in some embodiments, grains that can be repaired with only one repair process can be classified as first-second-class grains, and grains that can be repaired with only two repair processes can be classified as second-second-class grains... Also, for example, in some embodiments, grains with a repair cost less than a first repair cost can be classified as first-second-class grains, and grains with a repair cost greater than or equal to the first repair cost and less than a second repair cost can be classified as second-second-class grains...

[0100] Furthermore, in some embodiments, the effective levels of the effective channels can also be scored.

[0101] For example, in some embodiments, the effective level .

[0102] Among them, λ is a set coefficient, is the number of first-class effective grains in an effective channel, is the total number of grains in an effective channel;

[0103] For example, in some embodiments, is the average value of the first-class effective grains in multiple effective channels. Correspondingly, the effective quantity , is the total number of effective channels.

[0104] Also, for example, the effective quantity ; is the total number of effective channels, is the j th effective level of the , correspondingly, the effective quantity . Among them, f 1、 f 2…… f x are respectively the quantities of a type of effective grains in each effective channel.

[0105] Furthermore, in some embodiments, ; among them, is the first coefficient, is the quantity of a type of effective grains, is the second coefficient, is the quantity of a second type of effective grains.

[0106] Particularly, in some embodiments, refers to the quantity of the first and second types of effective grains, that is, the second type of effective grains with a relatively small repair cost.

[0107] In the present invention, by comprehensively considering the stacking performance, stacking yield, and repair cost of the simulated stacked device, the overall product performance of the final actual stacked device is further controlled, that is, the effective utilization rate of the candidate wafer is further improved. Among them, the improvement of the effective utilization rate reduces the stacking cost of the stacked device (that is, reduces the probability of invalid stacking) on the one hand, and can improve the yield and service life of the stacked device on the other hand.

[0108] In some embodiments, the stacking evaluation model is:

[0109] L = aX + bY ;

[0110] Y = m + 1 ;

[0111] ;

[0112] Among them, n is the quantity of the second type of effective grains in the effective channel, is the th repair cost of the second type of effective grains, is the set maximum repair cost.

[0113] Preferably, in this embodiment, only when the repair cost does not exceed the maximum repair cost, is it allowed to output the corresponding stacking index or simulated stacking scheme.

[0114] In this embodiment, by comprehensively evaluating the number of stacked layers, the number of effective channels, and the repair cost, a collaborative evaluation of the simulation stacking scheme is achieved in terms of the two key dimensions of the overall performance and cost of the simulation stacking scheme. Preferably, only when the application effect and stacking cost of the simulation stacking scheme are both reasonable, it is output as a recommended scheme to quickly assist the user in selecting a stacking scheme with a higher yield.

[0115] From another perspective, the stacking scheme selection method (also known as the wafer selection method) in the present invention can improve the effective utilization rate of candidate wafers, thereby greatly reducing the stacking cost generated during the stacking process due to ineffective stacking (such as excessive defects in the stacking scheme and too low a yield to be usable).

[0116] In some embodiments, it further includes the steps of: grouping the candidate wafers according to set grouping conditions; the grouping conditions include: the number α of candidate partitions, and the set value of the first effective threshold.

[0117] Among them, the step of grouping the candidate wafers includes:

[0118] Dividing α candidate partitions in the candidate wafers;

[0119] Calculating the effective die indicators in the candidate partitions respectively, where the effective die indicator is the number of effective dies, or the effective die indicator is the proportion of the number of effective dies in the dies;

[0120] Dividing the multiple candidate wafers into multiple candidate combinations according to the effective die indicators, where one candidate combination includes: multiple candidate wafers;

[0121] In the same candidate combination, the number of candidate partitions with a first correlation between one candidate wafer and another candidate wafer is greater than the first correlation threshold; where when the difference between the effective die indicators of two candidate partitions at the same position of two candidate wafers is less than or equal to the set first effective threshold, it is considered that the two candidate partitions have a first correlation with each other.

[0122] That is to say, when the number of effective dies of the wafers and the similarity degree of the distribution trends are relatively high, they can be divided into the same candidate combination. In this embodiment, by pre-regionally evaluating the candidate wafers through the candidate partitions, it is convenient to set candidate priorities for the subsequent selection of the second wafer.

[0123] Correspondingly, when multiple second wafers need to be selected for the first wafer, it is preferably selected from the same candidate combination.

[0124] For example, see Figure 3As shown, the wafer can be gradually divided into three candidate partitions, namely the first candidate partition 10, the second candidate partition 20, and the third candidate partition 30, in the direction from the center to the edge of the wafer.

[0125] For another example, in some other embodiments, other partitioning methods can also be adopted for partitioning, such as Figure 4 As shown, it can be divided into the first candidate partition 10, the second candidate partition 20,... according to the horizontal and vertical coordinates.

[0126] In this embodiment, a method is proposed for grouping candidate wafers according to the correlation of multiple candidate partitions, so as to preliminarily grade the matching between the candidate wafers and the first wafer in combination with the regional correlation, thereby improving the efficiency of selecting a suitable recommendation scheme and further reducing the screening cost.

[0127] In other words, this embodiment actually provides a hierarchical selection mode based on the evaluation of candidate partitions by correlation. Specifically, the massive candidate wafers are grouped by using the regional correlation evaluation, and then the second wafer group is screened step by step according to the candidate priorities corresponding to the groups when screening the second wafer group, so as to improve the efficiency of the selection process and reduce the amount of invalid calculations to a certain extent when facing a large number of available candidate wafers.

[0128] In some embodiments, the candidate combinations are divided into different candidate sets, which is equivalent to being divided into different candidate priorities; correspondingly, in step S102:

[0129] For the current first wafer selected in the current S101, multiple first candidate wafers are selected from the first candidate combination (equivalent to the candidate combination being marked with the first candidate priority) as the second wafer group, and the first candidate combination is the candidate combination to which the first wafer belongs.

[0130] Furthermore, in some embodiments, the method further includes:

[0131] When the stacking index of the simulated stacking scheme is less than or equal to the first stacking threshold, it is considered that the current second wafer group belongs to the sub-optimal stacking scheme;

[0132] Correspondingly, S102 further includes:

[0133] At least one second candidate wafer is selected from the second candidate combination (equivalent to being marked with the second candidate priority); wherein, the number of candidate partitions with the first correlation between the candidate wafers in the second candidate combination and the current first wafer is greater than the second correlation threshold and less than or equal to the first correlation threshold;

[0134] The at least one second candidate wafer and the multiple first candidate wafers are combined to form a new second wafer group;

[0135] And enter S103 again according to the new second wafer group.

[0136] In some embodiments, it further includes the steps of:

[0137] Set a first invalid candidate count for the first candidate set; wherein, when the second wafer group selected from the first candidate set belongs to a sub-optimal stacking scheme, record that the first candidate set has generated an invalid candidate once.

[0138] Monitor the first invalid candidate count within the first time period.

[0139] When the first invalid candidate count is greater than a set first invalid threshold, it is recommended to update the grouping of the candidate combination. For example, a first prompt signal can be issued, and this first prompt signal is used to remind the user to judge whether the grouping needs to be updated. Or, a second prompt signal can also be issued, and this second prompt signal is used to initiate the step of updating the grouping of the candidate combination.

[0140] For example, in some embodiments, the step of updating the grouping of the candidate combination includes:

[0141] Update the grouping conditions, and the grouping conditions include: the number α of candidate partitions, the set value of the first valid threshold.

[0142] Group the currently remaining candidate wafers again according to the grouping conditions.

[0143] Or, in some other embodiments, a new plurality of candidate wafers can also be obtained to perform an overall classification on the currently remaining candidate wafers and the newly obtained candidate wafers.

[0144] For example, in some embodiments, the step of updating the grouping conditions includes: increasing the number α.

[0145] That is to say, the present invention also provides an update mechanism for updating the grouping mode based on the application time and screening accuracy. For example, the present invention monitors the candidate results (such as the success rate of the candidate stacking scheme) to flexibly adjust the division and grouping rules of the candidate partitions in combination with the candidate results, so as to improve the accuracy and reliability of the candidate priority classification, thereby further improving the efficiency of the selection process.

[0146] In some embodiments, it further includes the steps of:

[0147] Record the second invalid candidate count of the candidate wafer; wherein, when the simulated stacking scheme composed of the candidate wafers is identified as a sub-optimal stacking scheme, it is recorded that the candidate wafer has generated one invalid candidate count, and the record of the second invalid candidate count is incremented by one;

[0148] When the second invalid candidate count is greater than the set second invalid threshold, it is recommended to delete the candidate wafer from the corresponding candidate combination to update the candidate combination.

[0149] In this embodiment, when the matching degree between the candidate wafer and the first wafer is too low, it is selected to be deleted from the candidate combination in a timely manner to reduce the amount of invalid calculation.

[0150] That is to say, a filtering mechanism for updating the candidate wafer is also proposed in the present invention. By filtering and updating the candidate wafer, the selection efficiency in the candidate process can be further improved.

[0151] Embodiment 2

[0152] On the other hand, the present invention also provides a selection system for a wafer stacking scheme. A plurality of dies are spacedly arranged on the wafer, and the dies include: valid dies and invalid dies. Correspondingly, referring to Figure 7 As shown, the system:

[0153] A first selection module 11, configured to select at least one first wafer from the candidate wafers according to a first selection rule. A plurality of second wafers can be stacked on the first wafer, and the first selection rule requires that the number of valid dies in the first wafer is greater than or equal to a preset first valid quantity T1;

[0154] A second selection module 12, configured to continue to select at least one group of second wafers corresponding to the first wafer from the candidate wafers. The group of second wafers includes: m second wafers;

[0155] An evaluation module 13, configured to calculate the stacking index of at least one simulated stacking scheme by using a stacking evaluation model; wherein, the simulated stacking scheme is a scheme stacked by the first wafer and the group of second wafers, and the stacking evaluation model is:

[0156] L = aX + bY ;

[0157] Y = m + 1 ;

[0158] L is the stacking index, a is the first weight,b is the second weight, X is the effective channel index, Y is the effective stacking index; wherein, when all the die of the first wafer and multiple candidate wafers in the second wafer group at the same coordinate are valid die, it is considered that a corresponding effective channel is formed by the valid die;

[0159] The recommendation module 14 is configured to determine whether the stacking index is greater than a set first stacking threshold. If so, output the corresponding simulated stacking scheme; if not, return to the second selection module.

[0160] In some embodiments, the valid die are divided into first-class valid die and second-class valid die; wherein, the first-class valid die are in a workable state, and the second-class valid die can be repaired to a workable state through at least one repair process.

[0161] In some embodiments, the stacking evaluation model is:

[0162] L = aX + bY ;

[0163] Y = m + 1 ;

[0164] ;

[0165] wherein, n is the number of the second-class valid die in the effective channel, is the th repair cost of the second-class valid die, is the set maximum repair cost.

[0166] In some embodiments, it further includes: a grouping module, configured to group the candidate wafers according to set grouping conditions.

[0167] In some embodiments, the grouping module includes:

[0168] A partitioning unit, configured to partition α candidate partitions in the candidate wafers;

[0169] A calculation unit, configured to calculate the effective die index in the candidate partitions respectively, where the effective die index is the number of the effective die, or the effective die index is the proportion of the number of the effective die in the number of all die;

[0170] A grouping unit, configured to divide a plurality of the candidate wafers into a plurality of candidate combinations according to the valid grain index, wherein one candidate combination includes: a plurality of candidate wafers; in the same candidate combination, the number of the candidate partitions having a first correlation between one candidate wafer and another candidate wafer is greater than a first correlation threshold; wherein, when the difference between the valid grain indexes of two candidate partitions at the same position of two candidate wafers is less than or equal to a set first valid threshold, it is considered that the two candidate partitions have a first correlation with each other. Correspondingly, when selecting a plurality of second wafers for the first wafer, selection is first performed from the same candidate combination.

[0171] Further, in some embodiments, for the currently selected first wafer in the first selection module 11, a plurality of first candidate wafers are selected from the first candidate combination as the second wafer group, and the first candidate combination is the candidate combination to which the first wafer belongs.

[0172] In some embodiments, when the stacking index of the simulated stacking scheme is less than or equal to the first stacking threshold, it is considered that the current second wafer group belongs to a secondary stacking scheme; correspondingly, the second selection module 12 further includes:

[0173] A selection unit, configured to select at least one second candidate wafer from the second candidate combination; wherein, in the second candidate combination, the number of the candidate partitions having a first correlation between the candidate wafer and the current first wafer is greater than a second correlation threshold and less than or equal to the first correlation threshold;

[0174] A combining unit, configured to form a new second wafer group by combining the at least one second candidate wafer with the plurality of first candidate wafers;

[0175] A re-evaluation unit, configured to re-enter the evaluation module 13 according to the new second wafer group.

[0176] In some embodiments, it further includes: a candidate grouping update module, configured to set a first invalid candidate count for the first candidate combination; wherein, when the second wafer group selected from the first candidate combination belongs to a secondary stacking scheme, it is recorded that the first candidate set has generated an invalid candidate once; monitor the first invalid candidate count within a first time period; when the first invalid candidate count is greater than a set invalid threshold, it is recommended to update the grouping of the candidate combination.

[0177] It should be noted that in this text, the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "comprising a..." does not exclude the presence of additional identical elements in the process, method, article or device comprising that element.

[0178] From the description of the above embodiments, those skilled in the art can clearly understand that the above-described example methods can be implemented by means of software plus a necessary general hardware platform. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation. Based on this understanding, the technical solution of the present invention, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions for causing a computer terminal (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in various embodiments of the present invention.

[0179] The embodiments of the present invention have been described above in conjunction with the accompanying drawings. However, the present invention is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Under the inspiration of the present invention, those of ordinary skill in the art can also make many forms without departing from the spirit and scope protected by the claims of the present invention. All of these are within the protection scope of the present invention.

Claims

1. A method for selecting a wafer stacking scheme, characterized in that A plurality of dies are disposed at intervals on a wafer. The dies include: valid dies and invalid dies. Correspondingly, the method includes the steps of: S101, selecting at least one first wafer from candidate wafers according to a first selection rule. A plurality of second wafers can be stacked on the first wafer. The first selection rule requires that the number of valid dies in the first wafer is greater than or equal to a preset first valid number; S102, continue to select at least one second wafer group corresponding to the first wafer from the candidate wafers, the second wafer group including: m such second wafers; S103, calculating stacking metrics of at least one simulated stacking scheme by using a stacking evaluation model. Wherein, the simulated stacking scheme is a scheme formed by stacking the first wafer and the second wafer group. The stacking evaluation model includes: L = aX + bY ； Y = m + 1 ； L is the stacking index, a is the first weight, b is the second weight, X is the effective number of effective channels, Y is the number of layers of the effective stack; wherein, when the dies of the first wafer and multiple candidate wafers in the second wafer group at the same coordinate are all effective dies, it is considered that one effective channel is formed by the corresponding effective dies; S104, determining whether the stacking metrics are greater than a set first stacking threshold. If so, outputting the corresponding simulated stacking scheme; if not, returning to S102.

2. The method for selecting a wafer stacking scheme according to claim 1, characterized in that The valid dies are divided into first-class valid dies and second-class valid dies. Wherein, the first-class valid dies are in a workable state, and the second-class valid dies can be repaired to a workable state through at least one repair process.

3. The method for selecting a wafer stacking scheme according to claim 2, wherein The stacking evaluation model includes: L = aX + bY ； Y = m + 1 ； ； Wherein, n is the number of the second type of effective grains in the effective channel, is the repair cost of the nth second type of effective grain, is the set maximum repair cost.

4. The method for selecting a wafer stacking scheme according to claim 1, characterized in that It further includes the steps of: Partition within the candidate wafer α candidate partitions; Calculating valid die metrics for the candidate partitions respectively. The valid die metric is the number of valid dies, or the valid die metric is the proportion of the number of valid dies in the dies; Dividing the plurality of candidate wafers into a plurality of candidate combinations according to the valid die metrics. Wherein, one candidate combination includes: a plurality of candidate wafers. In the same candidate combination, the number of candidate partitions with a first correlation between one candidate wafer and another candidate wafer is greater than a first correlation threshold. Wherein, when the difference between the valid die metrics of two candidate partitions at the same position of two candidate wafers is less than or equal to a set first valid threshold, it is considered that the two candidate partitions have a first correlation with each other.

5. The method for selecting a wafer stacking scheme according to claim 4, wherein The steps included in S102 are: For the current first wafer selected in the current S101, selecting a plurality of first candidate wafers from a first candidate combination as the second wafer group. The first candidate combination is the candidate combination to which the first wafer belongs.

6. The method for selecting a wafer stacking scheme according to claim 5, wherein It further includes the steps of: When the stacking metrics of the simulated stacking scheme are less than or equal to the first stacking threshold, it is considered that the current second wafer group belongs to a sub-optimal stacking scheme; Correspondingly, S102 further includes: Selecting at least one second candidate wafer from a second candidate combination. Wherein, the number of candidate partitions with a first correlation between the candidate wafers in the second candidate combination and the current first wafer is greater than a second correlation threshold and less than or equal to the first correlation threshold; Forming a new second wafer group with the at least one second candidate wafer and the plurality of first candidate wafers; And re-entering S103 according to the new second wafer group.

7. The method for selecting a wafer stacking scheme according to claim 6, characterized in that It further includes the steps of: Setting a first invalid candidate count for the first candidate combination. Wherein, when the second wafer group selected from the first candidate combination belongs to a sub-optimal stacking scheme, it is recorded that the first candidate combination has generated an invalid candidate once; Monitor the first number of invalid candidates within the first period; When the first number of invalid candidates is greater than the set invalid threshold, it is recommended to update the grouping of the candidate combination.

8. A selection system for a wafer stacking scheme, characterized in that, A plurality of die are disposed at intervals on the wafer, and the die include: valid die and invalid die. Correspondingly, the system includes: A first selection module for selecting at least one first wafer from candidate wafers by using a first selection rule, on which a plurality of second wafers can be stacked, and the first selection rule requires that the number of valid die in the first wafer is greater than or equal to a preset first valid number; A second selection module, configured to further select at least one second wafer group corresponding to the first wafer from the candidate wafers, where the second wafer group includes: m such second wafers; An evaluation module for calculating a stacking index of at least one simulated stacking scheme by using a stacking evaluation model; wherein, the simulated stacking scheme is a scheme formed by stacking the first wafer and the second wafer group, and the stacking evaluation model includes: L = aX + bY ； Y = m + 1 ； L is the stacking metric, a is the first weight, b is the second weight, X is the effective channel metric, Y is the effective stacking metric; wherein, when the dies of the first wafer and multiple candidate wafers in the second wafer group at the same coordinate are all valid dies, it is considered that a corresponding valid die forms an effective channel; A recommendation module for determining whether the stacking index is greater than a set first stacking threshold. If so, output the corresponding simulated stacking scheme; if not, return to the second selection module.

9. The selection system for a wafer stacking scheme according to claim 8, wherein The valid die are divided into first-class valid die and second-class valid die; wherein, the first-class valid die are in a workable state, and the second-class valid die can be repaired to a workable state through at least one repair process.

10. The selection system for a wafer stacking scheme according to claim 9, wherein, The stacking evaluation model includes: L = aX + bY ； Y = m + 1 ； ； Among them, n is the number of the second type of effective grains in the effective channel, is the repair cost of the nth second type of effective grain, is the set maximum repair cost.

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