Method for improving performance of MOS (Metal Oxide Semiconductor) device

Abstract

The invention provides a method for improving the performance of an MOS (Metal Oxide Semiconductor) device. A work function layer is provided; forming a barrier layer on the work function layer; and a metal layer is formed on the barrier layer, the metal layer is made of tungsten, the thickness of the metal layer is # imgabs0 #, and the metal layer, the barrier layer and the work function layer are etched to form a gate structure. According to the invention, the gate material AL in the traditional 22nm process is replaced by tungsten, and the bonding layer Ti and the barrier layer TiN under the AL gate are replaced by the # imgabs1 # barrier layer TiN, so that the gate resistance of the MOS device is greatly reduced, the channel tensile stress is improved, and the performance of the NMOS device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for improving the performance of MOS devices. Background Art

[0002] The gate material of the current 22nm technology is Al, which has serious diffusion problems and requires a barrier layer to prevent diffusion. The gate resistance is large, and the diffused Al affects the work function WF of the PMOS, making the PMOS device slower.

[0003] Currently, 22nm technology relies on SiGe to improve the performance of PMOS devices, with significant results, while NMOS can only rely on the etch stop layer CESL to improve device performance, so it is necessary to further improve the performance of NMOS devices. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for improving the performance of a MOS device, so as to solve the problem in the prior art that the performance of an NMOS device is reduced due to the diffusion of Al, a gate material.

[0005] To achieve the above-mentioned object and other related objects, the present invention provides a method for improving the performance of a MOS device, which at least comprises:

[0006] Step 1: providing a work function layer;

[0007] Step 2: forming a barrier layer on the work function layer;

[0008] Step 3: forming a metal layer on the barrier layer, wherein the material of the metal layer is tungsten and the thickness of the metal layer is

[0009] Step 4: etching the metal layer, the barrier layer and the work function layer to form a gate structure.

[0010] Preferably, the work function layer in step 1 is a work function layer for forming a gate structure of an NMOS device.

[0011] Preferably, the work function layer in step 1 is TiAl, and the thickness of the work function layer is

[0012] Preferably, the barrier layer in step 2 is a TiN layer.

[0013] Preferably, the thickness of the barrier layer in step 2 is

[0014] Preferably, the metal layer in step three is used to form a metal gate in a gate structure of a MOS device.

[0015] Preferably, the thickness of the metal layer in step 3 is

[0016] Preferably, the method is applicable to the process of manufacturing MOS gates at a 22nm technology node.

[0017] Preferably, the method reduces the gate resistance of the MOS device and increases the tensile stress of the channel.

[0018] As described above, a method for improving the performance of a MOS device according to the present invention has the following beneficial effects: the present invention replaces the gate material AL in the conventional 22nm process with tungsten, and replaces the adhesion layer Ti and the barrier layer TiN under the AL gate with The barrier layer TiN of the present invention greatly reduces the gate resistance of the MOS device and increases the channel tensile stress, thereby improving the performance of the NMOS device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Shown is a schematic diagram of the gate structure of the MOS device in the present invention;

[0020] Figure 2 Shown is a flow chart of the method for improving the performance of MOS devices in the present invention. DETAILED DESCRIPTION

[0021] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0022] See also Figure 1 to Figure 2 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0023] The present invention provides a method for improving the performance of a MOS device, such as Figure 2 As shown, Figure 2 The flowchart of the method for improving the performance of MOS devices in the present invention is shown, and the method at least comprises the following steps:

[0024] Step 1: providing a work function layer;

[0025] In the present invention, the work function layer in step 1 of this embodiment is a work function layer for forming a gate structure of an NMOS device. The work function layer in step 1 of this embodiment is TiAl, and the thickness of the work function layer is

[0026] like Figure 1 As shown, Figure 1 The schematic diagram of the gate structure of the MOS device in the present invention is shown. The step 1 provides the work function layer 01; in this embodiment, the work function layer 01 is used to form the gate structure of the NMOS device. In other embodiments, it can also be used to form the gate structure of the PMOS device. In this embodiment, the work function layer 01 is TiAl, and the thickness of the work function layer 01 is

[0027] Step 2: forming a barrier layer on the work function layer; Figure 1 As shown, in step 2, the barrier layer 02 is formed on the work function layer 01. In the present invention, the barrier layer 02 in step 2 of this embodiment is a TiN layer. The thickness of the barrier layer 02 in step 2 of this embodiment is

[0028] Step 3: forming a metal layer on the barrier layer, wherein the material of the metal layer is tungsten and the thickness of the metal layer is

[0029] Furthermore, in the present invention, the metal layer in step three of this embodiment is used to form a metal gate in a gate structure of a MOS device.

[0030] The present invention further, in step 3 of this embodiment, the thickness of the metal layer is

[0031] like Figure 1 As shown, in step three, a metal layer 03 is formed on the barrier layer 02. The material of the metal layer 03 is tungsten, and the thickness of the metal layer 03 is The metal layer in step 3 of this embodiment is used to form a metal gate in the gate structure of the MOS device, and the thickness of the metal layer is In other embodiments, the metal layer may also be used to form a metal gate in a gate structure of a PMOS device.

[0032] Step 4: etching the metal layer, the barrier layer and the work function layer to form a gate structure.

[0033] Furthermore, the method of this embodiment of the present invention is applicable to the process of manufacturing MOS gates at a 22nm technology node.

[0034] Furthermore, the method of this embodiment of the present invention is used to reduce the gate resistance of the MOS device and increase the tensile stress of the channel.

[0035] Figure 1 The fourth step is to etch the metal layer, barrier layer and work function layer formed in steps one to three to form a gate structure. Figure 1 The gate structure shown.

[0036] The present invention replaces the Al gate material with a W gate material. Adhesive layer Ti and The barrier layer TiN is replaced by The barrier layer TiN greatly reduces the gate resistance and increases the channel tensile stress, thereby improving the performance of NMOS devices.

[0037] After the present invention is replaced with a W metal gate, the NMOS gate resistance is reduced by 67%, and the PMOS gate resistance is reduced by 33%. The performance of the NMOS device is improved by 8%, and the performance of the PMOS device remains unchanged.

[0038] In summary, the present invention replaces the gate material AL in the conventional 22nm process with tungsten, and replaces the adhesion layer Ti and the barrier layer TiN under the AL gate with The present invention greatly reduces the gate resistance of MOS devices and increases the channel tensile stress, thereby improving the performance of NMOS devices. Therefore, the present invention effectively overcomes various shortcomings of the prior art and has a high industrial utilization value.

[0039] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for improving the performance of a MOS device, characterized in that: At least: Step 1: providing a work function layer; Step 2: forming a barrier layer on the work function layer; Step 3: forming a metal layer on the barrier layer, wherein the material of the metal layer is tungsten and the thickness of the metal layer is Step 4: etching the metal layer, the barrier layer and the work function layer to form a gate structure.

2. The method for improving MOS device performance according to claim 1, characterized in that: The work function layer in step 1 is a work function layer used to form a gate structure of an NMOS device.

3. The method for improving MOS device performance according to claim 2, characterized in that: The work function layer in step 1 is TiAl, and the thickness of the work function layer is 4. The method for improving MOS device performance according to claim 1, characterized in that: The barrier layer in step 2 is a TiN layer.

5. The method for improving MOS device performance according to claim 4, characterized in that: The thickness of the barrier layer in step 2 is 6. The method for improving MOS device performance according to claim 1, characterized in that: The metal layer in step three is used to form a metal gate in a gate structure of a MOS device.

7. The method for improving MOS device performance according to claim 6, characterized in that: The thickness of the metal layer in step 3 is 8. The method for improving MOS device performance according to claim 1, characterized in that: The method is applicable to the process of MOS gate at 22nm technology node.

9. The method for improving MOS device performance according to claim 1, characterized in that: The method is used to reduce the gate resistance of the MOS device and increase the tensile stress of the channel.

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