Fault detection method and device for multi-core controller, storage medium and electronic equipment

Abstract

The application discloses a fault detection method and device for a multi-core controller, a storage medium and an electronic device. The method comprises the following steps: in the running process of the multi-core controller, the multi-core controller is controlled to perform a target detection task according to a first period, and the multi-core controller is controlled to perform a target monitoring task according to a second period; in the case that the first quantity of heartbeat detection messages received by a target processing unit meets a first detection condition, it is determined that a reference processing unit is in an abnormal running state; in the case that the second quantity of heartbeat message requests received by the reference processing unit meets a second detection condition, it is determined that the target processing unit is in the abnormal running state; in the case that it is monitored that the reference processing unit fails to send notification information, it is determined that the reference processing unit is in the abnormal running state. The application solves the technical problems of inaccurate fault detection and low efficiency of the related art for the multi-core controller.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of automatic driving, in particular, to a fault detection method and device for a multi-core controller, a storage medium and an electronic device. BACKGROUND

[0002] The intelligent degree of the automobile industry is getting higher and higher. As an effective auxiliary driving product, corner radar can help drivers judge the distance between the vehicle and the obstacle, and has become an indispensable part of intelligent vehicles. Since the functions performed by the corner radar may affect the safety of vehicles and personnel, such products usually choose chips with functional safety levels. The operating system (OS) of the chip is an essential part of the controller, and the correct execution of any function depends on the correct and timely scheduling of various tasks by the OS.

[0003] Generally, corner radar needs to meet the functional safety requirements of correct sending of point cloud and track information and level ASIL B. For example, a common radar chip can be divided into two sub-modules of DSP and ARM. The ARM core usually deploys basic software (BSW) based on the AutoSAR architecture, and its operating system can be considered as SafeOS. The DSP core usually deploys a manufacturer's self-developed operating system based on a common open source OS. The latter cannot fully meet the requirements of ASIL B in terms of preventing systematic failures and preventing possible faults of the OS itself. That is, the prior art has the technical problem of inaccurate and low-efficiency fault detection for a multi-core controller. SUMMARY

[0004] The embodiments of the present application provide a fault detection method and device for a multi-core controller, a storage medium and an electronic device to at least solve the technical problem of inaccurate and low-efficiency fault detection for a multi-core controller in the related art.

[0005] According to an aspect of the embodiments of the present application, a fault detection method for a multi-core controller is provided, including: in a running process of the multi-core controller, controlling the multi-core controller to perform a target detection task according to a first period and to perform a target monitoring task according to a second period, wherein the target detection task is to control a target processing unit to send a heartbeat message request to a reference processing unit in the multi-core controller, the reference processing unit returns a heartbeat detection message to the target processing unit in response to the heartbeat message request, and the target monitoring task is to monitor a sending operation of the reference processing unit to send a radar data processing result to the target processing unit; in a case where a first quantity of the heartbeat detection messages received by the target processing unit satisfies a first detection condition, determining that the reference processing unit is in an abnormal running state; in a case where a second quantity of the heartbeat message requests received by the reference processing unit satisfies a second detection condition, determining that the target processing unit is in the abnormal running state; and in a case where a sending of notification information by the reference processing unit is monitored to fail, determining that the reference processing unit is in the abnormal running state, wherein the notification information is used to indicate that the reference processing unit has sent the radar data processing result to the target processing unit.

[0006] According to another aspect of the embodiments of the present application, a fault detection device for a multi-core controller is also provided, including: an execution unit, which, in a running process of the multi-core controller, controls the multi-core controller to perform a target detection task according to a first period and to perform a target monitoring task according to a second period, wherein the target detection task is to control a target processing unit to send a heartbeat message request to a reference processing unit in the multi-core controller, the reference processing unit returns a heartbeat detection message to the target processing unit in response to the heartbeat message request, and the target monitoring task is to monitor a sending operation of the reference processing unit to send a radar data processing result to the target processing unit; a first determination unit, which, in a case where a first quantity of the heartbeat detection messages received by the target processing unit satisfies a first detection condition, determines that the reference processing unit is in an abnormal running state; a second determination unit, which, in a case where a second quantity of the heartbeat message requests received by the reference processing unit satisfies a second detection condition, determines that the target processing unit is in the abnormal running state; and a third determination unit, which, in a case where a sending of notification information by the reference processing unit is monitored to fail, determines that the reference processing unit is in the abnormal running state, wherein the notification information is used to indicate that the reference processing unit has sent the radar data processing result to the target processing unit.

[0007] As an optional solution, the fault detection device for the multi-core controller further includes a third determination module configured to acquire a reference count value matched with the first number at a current time, wherein the reference count value is used to indicate a number of times that the reference processing unit continuously fails to respond to a request within a target detection period; determine that the reference processing unit is in an abnormal running state if the reference count value is greater than or equal to a first threshold value; acquire a target count value matched with the second number at the current time, wherein the target count value is used to indicate a number of times that the target processing unit continuously fails to send a request within the target detection period; and determine that the target processing unit is in an abnormal running state if the target count value is greater than or equal to a second threshold value.

[0008] As an optional solution, the third determination module includes a counting module configured to increase the reference count value by 1 if the target processing unit does not receive the heartbeat detection packet returned by the reference processing unit, and reset the reference count value to 0 if the target processing unit successfully receives the heartbeat detection packet returned by the reference processing unit; and a counting module configured to increase the target count value by 1 if the reference processing unit does not receive the heartbeat packet request sent by the target processing unit, and reset the target count value to 0 if the reference processing unit successfully receives the heartbeat packet request sent by the target processing unit.

[0009] As an optional solution, the third determination module includes an execution module configured to determine to perform a reset operation on the multi-core controller if the reference count value is greater than a target first threshold value, wherein the target first threshold value is greater than the first threshold value; and determine to perform a reset operation on the multi-core controller if the target count value is greater than a target second threshold value, wherein the target second threshold value is greater than the second threshold value.

[0010] As an optional solution, the third determination module includes an acquisition module configured to acquire a maximum reference count value within a previous detection period; take the maximum reference count value matched with the previous detection period as the first threshold value matched with a current detection period; acquire a maximum target count value within the previous detection period; and take the maximum target count value matched with the previous detection period as the second threshold value matched with the current detection period.

[0011] As an optional solution, the third determination unit includes a sending unit configured to cause the reference processing unit to perform digital processing on the received radar signal data to obtain the radar data processing result, and send the radar data processing result to the target processing unit; and cause the reference processing unit to send notification information to the target processing unit at a target time.

[0012] As an optional solution, the sending unit comprises a fourth determining module configured to determine that the reference processing unit is in the abnormal operation state if the target processing unit does not receive the notification information before a first reference time point; and determine to perform a reset operation on the multi-core controller if the target processing unit does not receive the notification information before a second reference time point, wherein a first time interval between the target time point and the first reference time point is less than a second time interval between the target time point and the second reference time point.

[0013] As an optional solution, the executing unit comprises an obtaining module configured to obtain a first detection result matched with the target detection task and a second monitoring result matched with the target monitoring task, wherein a reliability coefficient of the second monitoring result is greater than a reliability coefficient of the first detection result; and perform weighted summation on the first detection result and the second monitoring result respectively according to the reliability coefficients corresponding to the first detection result and the second monitoring result, and determine the operation state of the multi-core controller according to a result of the weighted summation.

[0014] As an optional solution, the executing unit comprises a configuring module configured to configure the multi-core controller with task description information, wherein the task description information indicates that the fault detection task is a low-priority task and the system task is a high-priority task; and the multi-core controller executes the tasks according to the priority order indicated in the task description information.

[0015] According to still another aspect of the embodiments of the present application, a computer program product or computer program is provided, which comprises computer instructions stored in a computer readable storage medium. A processor of a computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions to enable the computer device to perform the fault detection method for the multi-core controller.

[0016] According to still another aspect of the embodiments of the present application, an electronic device is also provided, which comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the fault detection method for the multi-core controller through the computer program.

[0017] Through the above-mentioned embodiments of the present application, in the running process of the multi-core controller, the target detection task is controlled to be executed by the multi-core controller according to a first period, and the target monitoring task is controlled to be executed by the multi-core controller according to a second period, wherein the target detection task is to control the target processing unit to send a heartbeat message request to the reference processing unit in the multi-core controller, the reference processing unit returns a heartbeat detection message to the target processing unit in response to the heartbeat message request, and the target monitoring task is to monitor the sending operation of the reference processing unit to send the radar data processing result to the target processing unit; further, in the case that the first quantity of the heartbeat detection messages received by the target processing unit satisfies a first detection condition, it is determined that the reference processing unit is in an abnormal running state; in the case that the second quantity of the heartbeat message requests received by the reference processing unit satisfies a second detection condition, it is determined that the target processing unit is in an abnormal running state; in the case that the sending of the notification information by the reference processing unit fails, it is determined that the reference processing unit is in an abnormal running state, which not only can monitor the fault of the non-safety OS, but also can monitor the safety OS, thereby solving the technical problems of inaccurate fault detection and low efficiency of the multi-core controller in the related art. BRIEF DESCRIPTION OF DRAWINGS

[0018] The accompanying drawings, which are included to provide a further understanding of the present application, form a part of the present application and illustrate the illustrative embodiments of the present application and its description, which do not constitute improper limitations to the present application. In the drawings:

[0019] Figure 1 is a schematic diagram of an optional application environment of a fault detection method for a multi-core controller according to an embodiment of the present application;

[0020] Figure 2 is a flowchart of an optional fault detection method for a multi-core controller according to an embodiment of the present application;

[0021] Figure 3 is a schematic diagram of an optional fault detection method for a multi-core controller according to an embodiment of the present application;

[0022] Figure 4 is a flowchart of another optional fault detection method for a multi-core controller according to an embodiment of the present application;

[0023] Figure 5 is a flowchart of still another optional fault detection method for a multi-core controller according to an embodiment of the present application;

[0024] Figure 6 is a flowchart of still another optional fault detection method for a multi-core controller according to an embodiment of the present application;

[0025] Figure 7is a schematic view of a fault detection device for a multi-core controller according to an embodiment of the present application;

[0026] Figure 8 is a structural schematic view of an optional electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0027] In order to enable persons skilled in the art to better understand the scheme of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by persons skilled in the art without creative labor should fall within the scope of protection of the present application.

[0028] It should be noted that the terms "first", "second", and the like in the specification and claims of the present application and in the above-described drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to only those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to the process, method, product, or device.

[0029] According to an aspect of an embodiment of the present application, a fault detection method for a multi-core controller is provided. Optionally, the above-mentioned fault detection method for a multi-core controller can be applied in a hardware environment as shown in Figure 1 Optionally, the above-mentioned fault detection method for a multi-core controller provided by the present application can be applied in a vehicle terminal. Figure 1 A side view of the vehicle terminal 101 is shown, which can travel on a travel surface 113. The vehicle terminal 101 includes a memory 102 storing an on-board navigation system 103, a digital road map 104, a space monitoring system 117, a vehicle controller 109, a GPS (Global Positioning System) sensor 110, an HMI (Human / Machine Interface) device 111, and further includes an autonomous controller 112 and a telematics controller 114.

[0030] In one embodiment, the space monitoring system 117 includes one or more space sensors and systems for monitoring the visual area 105 in front of the vehicle terminal 101, and a space monitoring controller 118. The space sensors for monitoring the visual area 105 include a lidar sensor 106, a radar sensor 107, a camera 108, etc. The space monitoring controller 118 can be configured to generate data related to the visual area 105 based on data inputs from the space sensors. The space monitoring controller 118 can determine the linear range, relative speed, and trajectory of the vehicle terminal 101 based on inputs from the space sensors, e.g., determine the current speed of the ego vehicle and the relative speed compared to the preceding vehicle. The space sensors of the vehicle terminal space monitoring system 117 can include object localization sensing devices, which can include range sensors that can be used to localize objects in front, e.g., the preceding vehicle object.

[0031] The camera 108 is advantageously mounted and positioned on the vehicle terminal 101 in a position that allows capturing images of the visual area 105, where at least a portion of the visual area 105 includes a portion of the travel surface 113 in front of the vehicle terminal 101 and including the trajectory of the vehicle terminal 101. The visual area 105 can also include the surrounding environment. Other cameras can also be employed, e.g., including a second camera disposed on a rear portion or a side portion of the vehicle terminal 101 to monitor the rear of the vehicle terminal 101 and one of the right or left sides of the vehicle terminal 101.

[0032] The autonomous controller 112 is configured to implement autonomous driving or advanced driver assistance system (ADAS) vehicle terminal functionality. Such functionality can include a vehicle terminal on-board control system capable of providing a certain level of driving automation. Driving automation can include a range of dynamic driving and vehicle terminal operations. Driving automation can include a certain level of automatic control or intervention involving individual vehicle terminal functions (e.g., steering, acceleration, and / or braking). For example, the autonomous controller described above can be used to generate a vehicle travel scenario for the vehicle terminal by performing the following steps:

[0033] S102, during the running of the multi-core controller, controlling the multi-core controller to perform a target detection task according to a first period, and controlling the multi-core controller to perform a target monitoring task according to a second period, wherein the target detection task is to control a target processing unit to send a heartbeat message request to a reference processing unit in the multi-core controller, and the reference processing unit returns a heartbeat detection message to the target processing unit in response to the heartbeat message request, and the target monitoring task is to monitor a sending operation of the reference processing unit sending a radar data processing result to the target processing unit;

[0034] S104, in a case where the first quantity of the heartbeat detection packets received at the target processing unit satisfies a first detection condition, determining that the reference processing unit is in an abnormal running state;

[0035] S106, in a case where the second quantity of the heartbeat packet requests received at the reference processing unit satisfies a second detection condition, determining that the target processing unit is in an abnormal running state;

[0036] S108, in a case where it is monitored that the reference processing unit fails to send the notification information, determining that the reference processing unit is in an abnormal running state, wherein the notification information is used to indicate that the reference processing unit has sent the radar data processing result to the target processing unit.

[0037] The HMI device 111 provides human-machine interaction for the purpose of guiding the infotainment system, GPS (Global Positioning System) sensors 110, on-board navigation system 103, and similar operations, and includes a controller. The HMI device 111 monitors operator requests and provides the operator with status, service, and maintenance information of the vehicle terminal system. The HMI device 111 communicates with and / or controls the operation of a plurality of operator interface devices. The HMI device 111 can also communicate with one or more devices that monitor biometric data associated with the vehicle terminal operator. For simplicity of description, the HMI device 111 is depicted as a single device, but in embodiments of the system described herein, can be configured as multiple controllers and associated sensing devices.

[0038] Operator controls can be included in the passenger cabin of the vehicle terminal 101 and can include, by way of non-limiting example, a steering wheel, an accelerator pedal, a brake pedal, and operator input devices that are elements of the HMI device 111. The operator controls enable the vehicle terminal operator to interact with the operating vehicle terminal 101 and direct the operation of the vehicle terminal 101 to provide passenger transportation.

[0039] The on-board navigation system 103 employs a digital road map 104 for the purpose of providing navigation support and information to the vehicle terminal operator. The autonomous controller 112 employs the digital road map 104 for the purpose of controlling autonomous vehicle terminal operation or ADAS vehicle terminal functions.

[0040] The vehicle terminal 101 can include a telematics controller 114 that includes a wireless telematics communication system capable of external vehicle terminal communication, including communication with a communication network 115 having wireless and wired communication capabilities. Included in the wireless telematics communication system is an off-board server 116 capable of short-range wireless communication with a mobile terminal.

[0041] As an optional implementation, as shown in Figure 2 The fault detection method of the multi-core controller can be executed by the electronic device, and the specific steps include:

[0042] S202, during the operation of the multi-core controller, the target detection task is executed by the multi-core controller according to a first period, and the target monitoring task is executed by the multi-core controller according to a second period, wherein the target detection task is to control the target processing unit to send a heartbeat message request to the reference processing unit in the multi-core controller, and the reference processing unit returns a heartbeat detection message to the target processing unit in response to the heartbeat message request, and the target monitoring task is to monitor the sending operation of the reference processing unit to send the radar data processing result to the target processing unit;

[0043] S204, in the case that the first number of the heartbeat detection messages received by the target processing unit satisfies the first detection condition, it is determined that the reference processing unit is in an abnormal operation state;

[0044] S206, in the case that the second number of the heartbeat message requests received by the reference processing unit satisfies the second detection condition, it is determined that the target processing unit is in an abnormal operation state;

[0045] S208, in the case that the reference processing unit fails to send the notification information, it is determined that the reference processing unit is in an abnormal operation state, wherein the notification information is used to indicate that the reference processing unit has sent the radar data processing result to the target processing unit.

[0046] In S202 in the above embodiment, during the operation of the multi-core controller, the target detection task is executed by the multi-core controller according to a first period, and the target monitoring task is executed by the multi-core controller according to a second period, wherein the target detection task is to control the target processing unit to send a heartbeat message request to the reference processing unit in the multi-core controller, and the reference processing unit returns a heartbeat detection message to the target processing unit in response to the heartbeat message request, and the target monitoring task is to monitor the sending operation of the reference processing unit to send the radar data processing result to the target processing unit; The above-mentioned first period and second period can be dynamically determined time periods; The above-mentioned target processing unit can be an ARM core in particular, and the above-mentioned reference processing unit can be a DSP core in particular. The above-mentioned digital processing of the radar signal can be the process of forming perception data by DSP processing radio frequency module data, and in particular, the above-mentioned target detection task is used to detect the successful sending and receiving of the heartbeat message request at the bottom layer, and the above-mentioned target monitoring task is used to monitor the sending situation of the radar signal processing result at the function layer.

[0047] Optionally, as shown in Figure 3As shown, normally, in the car driving environment, the DSP core processes the signals from the radar SOC built-in firmware (Radar Front End module) for digital processing, and sends the processed sensing results to the ARM core, which continues to process the point cloud and track signals after receiving the results, and ensures the normal operation of the vehicle controller to realize vehicle control.

[0048] Further, in the step S204, in a case where the first number of the heartbeat detection packets received by the target processing unit satisfies the first detection condition, it is determined that the reference processing unit is in an abnormal operation state; the first number can be the total number of failures in receiving the heartbeat detection packet within a period, and in a case where the first number includes multiple continuous failure events, that is, 10 response failures include continuous failure events 3 times, the first time 2 times of continuous response failure, the second time 3 times of continuous response failure, and the third time 5 times of continuous response failure, the maximum number of failures is 5 times; the first detection condition can be that the number of continuous response failure events greater than the first preset value exists, or the number of events in which the number of continuous response failures within a period is greater than the first preset value is greater than the first preset fixed value.

[0049] As an optional implementation, for example, in a case where the target processing unit sends N times of heartbeat packet requests to the reference processing unit within a period of time, and the maximum number of continuous times that the target processing unit does not receive the heartbeat detection packet returned by the reference processing unit is M, the ratio of M / N is greater than a first preset threshold value, or M is greater than a second preset threshold value, etc., it is determined that the reference processing unit is in an abnormal operation state, otherwise, it is determined that the reference processing unit is in a normal operation state.

[0050] In step S206, in a case where the second number of the heartbeat packet requests received by the reference processing unit satisfies the second detection condition, it is determined that the target processing unit is in an abnormal operation state; the second number can be the total number of failures in sending the heartbeat packet request within a period, and in a case where the second number includes multiple continuous failure events, that is, 10 times of sending request failures include continuous failure events 3 times, the first time 3 times of continuous sending request failure, the second time 2 times of continuous sending request failure, and the third time 5 times of continuous sending request failure, the maximum number of sending request failures is 5 times; the second detection condition can be that the number of continuous sending request failures is greater than a second preset value, or the number of events in which the number of continuous sending request failures within a period is greater than the second preset value is greater than a second preset fixed value.

[0051] For example, it can be determined that the target processing unit is in an abnormal running state in the case that the target processing unit sends heartbeat message requests X times to the reference processing unit within a period of time, and the maximum number of times that the reference processing unit continuously fails to receive a heartbeat message request is Y, the ratio of Y / X is greater than a third preset threshold value, or Y is greater than a fourth preset threshold value, and the like. Otherwise, it is determined that the target processing unit is in a normal running state.

[0052] In the step S208, it is determined that the reference processing unit is in an abnormal running state in the case that it is monitored that the reference processing unit fails to send notification information, wherein the notification information is used to indicate that the reference processing unit has sent a radar data processing result to the target processing unit. The notification information can be information reported by the DSP that the sensing data is successfully sent. The radar data processing result can be sensing data formed by the DSP receiving radio frequency data and processing.

[0053] As an optional implementation, the DSP core receives original radar signal data from the radio frequency module, forms a radar data processing result, i.e., sensing data, through a signal processing algorithm, such as pulse compression, range-doppler processing, target detection, and the like, and sends the sensing data to the ARM core through a shared memory, a message queue, or a DMA, and the like. At the same time, the DSP core sends a notification information to the ARM core, indicating that the radar data processing result has been successfully sent.

[0054] It should be noted that the present scheme firstly configures the heartbeat monitoring task priority in the DSP core as non-preemptive and low priority based on the consideration of the task scheduling priority. If the DSP can normally execute the low priority task, the possibility that the OS can normally schedule all tasks is high, thereby ensuring the effectiveness of the OS heartbeat monitoring mechanism and preliminarily judging the presence or absence of the DSP. Further, the radar function is ensured to be normally executed through the application layer function monitoring, thereby covering a part of the OS failure that cannot be detected by the heartbeat mechanism. That is, even if the DSP successfully performs the question and answer with the ARM, it can only indicate that the DSP core can work. However, due to the complexity of the operating system, working does not mean that it can correctly schedule all tasks. In the case that the first detection task detects that the heartbeat receiving and sending are normal and the operating system bottom function is normal, the function layer is further monitored. If the ARM does not receive the information reported by the DSP that the sensing data is successfully sent within a target time, it is determined that the DSP fails, i.e., the function layer task cannot be normally executed, and the processing unit has a failure, thereby improving the accuracy of the failure judgment.

[0055] In the corner radar system, a dual-core design is adopted, one core (ARM core) runs a safe operating system (SafeOS), and the other core (DSP core) runs a non-safe operating system (Non-SafeOS). In order to more accurately and efficiently check faults, during the running of the multi-core controller, the multi-core controller is controlled to perform a target detection task according to a first period, and the multi-core controller is controlled to perform a target monitoring task according to a second period. The target detection task is that a target processing unit (such as an ARM) sends a heartbeat message request to a reference processing unit (such as a DSP) in the multi-core controller, and the reference processing unit returns a heartbeat detection message to the target processing unit in response to the heartbeat message request. The target monitoring task is to monitor the sending operation of the reference processing unit to send a radar data processing result to the target processing unit. Then, in a case where a first number of heartbeat detection messages received by the target processing unit satisfies a first detection condition, it is determined that the reference processing unit is in an abnormal running state. In a case where a second number of heartbeat message requests received by the reference processing unit satisfies a second detection condition, it is determined that the target processing unit is in an abnormal running state. Through the above bidirectional detection, that is, monitoring the SafeOS of the ARM core while detecting whether the Non-SafeOS of the DSP core normally responds to the request message, the deficiency of only focusing on the non-safe operating system is made up, and it is ensured that even the failure of the safe OS cannot be avoided. The failure is discovered in time. In addition, in a case where the reference processing unit fails to send notification information, it is determined that the reference processing unit is in an abnormal running state. By monitoring the response of the notification information in the function layer, the failure of the processing unit is further judged according to the correct execution of the key function. Through the above target detection task and target monitoring task, not only the failure of the non-safe OS can be monitored, but also the safe OS can be monitored, and it can be further judged whether the failure problem of the processing unit is in the bottom operating system or the function execution of the application layer, thereby solving the technical problems of inaccurate and low-efficiency fault detection of the multi-core controller in related technologies.

[0056] In an optional implementation, in a case where the first number of heartbeat detection messages received by the target processing unit satisfies the first detection condition, it is determined that the reference processing unit is in an abnormal running state, including:

[0057] S1, obtaining a reference count value matched with the first number at the current time, wherein the reference count value is used to indicate the number of times that the reference processing unit continuously fails to respond to the request within the target detection period; in a case where the reference count value is greater than or equal to a first threshold value, it is determined that the reference processing unit is in an abnormal running state;

[0058] In a case where the second number of heartbeat message requests received by the reference processing unit satisfies the second detection condition, it is determined that the target processing unit is in an abnormal running state, including:

[0059] S2, obtaining a target count value matched with the second number at the current time, wherein the target count value is used to indicate the number of times that the target processing unit continuously fails to send a request in a target detection period; and determining that the target processing unit is in an abnormal running state if the target count value is greater than or equal to the second threshold value.

[0060] In the step S1, a reference count value matched with the first number at the current time is obtained, wherein the reference count value is used to indicate the number of times that the reference processing unit continuously fails to respond to a request in a target detection period; and determining that the reference processing unit is in an abnormal running state if the reference count value is greater than or equal to the first threshold value.

[0061] As an optional implementation, the reference count value is set to 0 at the system startup or at the beginning of each detection period, and the target processing unit periodically sends a heartbeat request or other forms of request to the reference processing unit for response in the target detection period. After each request is sent, the target processing unit waits for a response from the reference processing unit. If no response from the reference processing unit is received within a preset response time, the monitoring system records the event as a response failure, and the reference count value is increased by 1. If the reference count value is greater than or equal to the first threshold value, the system determines that the reference processing unit is in an abnormal running state. Further, a series of fault handling processes are triggered, such as fault recording, alarm, automatic reset or switching to a backup processing unit, to prevent the abnormal state of the reference processing unit from affecting the functional safety of the entire system. This is only an example.

[0062] In the step S2, a target count value matched with the second number at the current time is obtained, wherein the target count value is used to indicate the number of times that the target processing unit continuously fails to send a request in a target detection period; and determining that the target processing unit is in an abnormal running state if the target count value is greater than or equal to the second threshold value.

[0063] As an optional implementation, the target count value is also set to 0 at the system initialization or at the beginning of each target detection period. In the target detection period, the monitoring system monitors whether the target processing unit can successfully send a request. If the target processing unit fails to send the request within a preset sending time, or the reference processing unit does not receive the request packet, a sending failure event is recorded, and the target count value is increased by 1. If the target count value is greater than or equal to the second threshold value, it is determined that the target processing unit is in an abnormal running state.

[0064] It should be noted that the above threshold values can be dynamically adjusted based on the current running state of the system. For example, in a high-load environment, the system can need to lower the first threshold value and the second threshold value to facilitate faster detection of abnormal behavior; and in a low-load or maintenance state, the threshold values can be increased to reduce system interruption; the first threshold value and the second threshold value in the dynamic adjustment mode, for example, if the target processing unit detects an increase in network communication delay, it can automatically increase the second threshold value to reduce the false positive rate. At the same time, if the hardware resource utilization of the reference processing unit increases, the target processing unit can correspondingly reduce the first threshold value to increase the sensitivity to potential faults of the reference processing unit;

[0065] The first threshold value and the second threshold value described above can also have a correlation, for example, when the vehicle is in a high-density traffic environment, the system generates a large amount of data processing demand, and the hardware resource is tight, the first threshold value needs to be increased (allowing the reference processing unit to fail to respond to the request for a longer period of time) to avoid false positives in high load; At the same time, increase the second threshold value (allow the target processing unit to fail to successfully send a request for a longer period of time) to reduce false positives due to network congestion. Or the vehicle is driving on a highway, which needs to quickly respond to potential safety risks, and the first threshold value can be reduced (to reduce the time allowed for the reference processing unit to fail to respond to the request) to more quickly detect the failure of the reference processing unit; At the same time, increase the second threshold value (allow the target processing unit to fail to successfully send a request for a longer period of time), because in this case, the high sensitivity of the target processing unit can cause false positives, and increasing the second threshold value can reduce such false positives.

[0066] Through the above embodiments of the present application, periodic monitoring of the sending anomaly of the target processing unit and the response anomaly of the reference processing unit can ensure the safety and reliability of complex systems such as corner radar controllers. Further, dynamically setting the target detection period, the first threshold value and the second threshold value in different situations can balance the timeliness of fault detection and the false positive rate, and further enhance the adaptive ability and fault handling efficiency of the system.

[0067] In an optional embodiment, before determining that the reference processing unit is in an abnormal running state, further comprising:

[0068] S1, in the case where the target processing unit does not receive the heartbeat detection packet returned by the reference processing unit, the reference count value is increased by 1; in the case where the target processing unit successfully receives the heartbeat detection packet returned by the reference processing unit, the reference count value is set to 0;

[0069] Before determining that the target processing unit is in an abnormal running state, further comprising:

[0070] S2, in case that the target processing unit fails to receive the heartbeat packet request sent by the reference processing unit, the target count value is added by 1; in case that the target processing unit successfully receives the heartbeat packet request sent by the reference processing unit, the target count value is set to 0.

[0071] In step S1, in case that the target processing unit fails to receive the heartbeat detection packet returned by the reference processing unit, the reference count value is added by 1; in case that the target processing unit successfully receives the heartbeat detection packet returned by the reference processing unit, the reference count value is set to 0.

[0072] As an optional implementation, the target processing unit sends a heartbeat packet request to the reference processing unit, and after sending the heartbeat packet request, the target processing unit enters a waiting state to wait for receiving the heartbeat detection packet returned by the reference processing unit within a preset time window. If the target processing unit fails to receive the heartbeat detection packet returned by the reference processing unit within the preset time window, the reference count value is added by 1 to record the number of times that the target processing unit fails to receive the heartbeat packet request or fails to respond to the request. On the contrary, if the target processing unit successfully receives the heartbeat detection packet returned by the reference processing unit and responds successfully, it indicates that the reference processing unit is currently in a normal working state and can normally respond to the heartbeat packet request. The reference count value is set to 0 to clear the previously recorded number of times of non-response, that is, the heartbeat state of the reference processing unit has been verified to be healthy, and the previous non-response record is no longer valid.

[0073] In step S2, in case that the target processing unit fails to receive the heartbeat packet request sent by the reference processing unit, the target count value is added by 1; in case that the target processing unit successfully receives the heartbeat packet request sent by the reference processing unit, the target count value is set to 0.

[0074] As an optional implementation, the reference processing unit enters a listening state to wait for the target processing unit to send a request according to a preset heartbeat period. If the reference processing unit fails to receive the heartbeat packet request sent by the target processing unit within a preset time window, it is determined that the target processing unit fails to send the request, which may be caused by abnormal situations such as failure, network transmission problem or processing delay. Further, the target count value is added by 1 to record the number of times of sending request failure. If the reference processing unit successfully receives the heartbeat packet request sent by the target processing unit within the preset time window, it indicates that the target processing unit can currently normally send the heartbeat packet. The target count value is set to 0 to clear the previously recorded number of times of sending request failure, which indicates that the heartbeat state of the target processing unit has been verified to be normal, and the previous record is no longer valid.

[0075] If the target count value accumulates to a preset threshold (for example, threshold A) within a period, it is determined that the target processing unit is in abnormal operation and needs to take corresponding measures, such as reporting fault information, starting a redundant processing unit, requesting a system-level reset, and the like, to ensure the functional safety and stability of the entire system.

[0076] Through the above steps, the target processing unit can continuously monitor the heartbeat state of the reference processing unit and timely discover possible abnormal operation, and the reference processing unit can also continuously monitor the heartbeat request sending state of the target processing unit. The bidirectional verification and detection mechanism can timely discover possible abnormal operation and take appropriate measures to report or recover faults, thereby improving the overall stability and safety of the system, helping the system to identify and handle potential faults in the early stage, reducing false positives, and improving the accuracy of fault detection.

[0077] In an optional implementation, after determining that the reference processing unit is in an abnormal operation state, the method further includes:

[0078] S1, in a case where the reference count value is greater than a target first threshold value, determining to perform a reset operation on the multi-core controller, wherein the target first threshold value is greater than the first threshold value;

[0079] After determining that the target processing unit is in an abnormal operation state, the method further includes:

[0080] S2, in a case where the target count value is greater than a target second threshold value, determining to perform a reset operation on the multi-core controller, wherein the target second threshold value is greater than the second threshold value.

[0081] The process S1 is described below in a complete implementation step, as shown in the following table: Figure 4

[0082] S402, ARM / DSP starts; S404, DSP failure event is set to 0; S406, DSP waits for the ARM to send a heartbeat request;

[0083] Further judgment S408, does the ARM need to send a heartbeat detection? If not, the execution ends; if the ARM needs to send a heartbeat detection, S410 is executed, the DSP receives a heartbeat request.

[0084] If no heartbeat detection request is received, S412 is executed, the DSP failure event is incremented by 1; further judgment S414, is the failure event less than X?

[0085] If the failure event is less than X, continue to return to S406, the DSP waits for the ARM to send a heartbeat request;

[0086] ​If the failure event exceeds X, continue to determine S416, failure event < Y? If the response request failure event exceeds X times but is less than Y times, execute S416-1, record the failure, for example, the failure event information can be stored in the failure record log this time;

[0087] If the response request failure event exceeds Y times, execute S416-2, request reset.

[0088] If S410 is executed, the DSP receives the heartbeat request? After receiving the heartbeat request, determine S410-1, failure event > 0?

[0089] If the failure event is greater than 0, return to execute S404 to modify the count value of the failure event to 0, that is, as long as the reception is successful, the failure event count is cleared to 0, and it is determined whether the cumulative failure number determines the processing unit to be faulty;

[0090] If the failure event is equal to 0, continue to execute S406, and the DSP waits for the ARM to send a heartbeat request. The above execution process realizes the automatic fault detection of the reference processing unit in the multi-core processor, and improves the fault detection efficiency and accuracy.

[0091] The following describes the process S2 in a complete implementation step, as shown in Figure 5

[0092] S502, ARM / DSP starts; S504, ARM failure event is set to 0; S506, ARM waits for the DSP to send a heartbeat packet;

[0093] Further determine S508, does the ARM need to accept the heartbeat packet? If not, execute end; if the ARM needs to accept the heartbeat packet, execute S510, the ARM receives the heartbeat packet?

[0094] If the heartbeat packet is not received, execute S512, ARM failure event + 1; further determine S514, failure event < A?

[0095] If the failure event does not exceed A, continue to return to S506, and the ARM waits for the DSP to send a heartbeat packet;

[0096] If the failure event exceeds A, continue to determine S516, failure event < B? If the response request failure event exceeds A times but is less than B times, execute S516-1, record the failure, for example, the failure event information can be stored in the failure record log this time;

[0097] If the response request failure event exceeds B times, execute S516-2, request reset.

[0098] If S510 is executed, the ARM receives the heartbeat packet? After receiving the heartbeat packet, determine S510-1, failure event > 0?​

[0099] If the failure events are greater than 0, return to execute S504 to modify the count value of the failure events to 0, i.e. clear the count of the failure events as long as the reception is successful, and determine whether the cumulative number of failures of the processing unit is faulty;

[0100] If the failure events are equal to 0, continue to execute S506, and the ARM waits for the DSP to send a heartbeat request. The above execution process realizes the automatic fault detection of the target processing unit in the multi-core processor, and improves the fault detection efficiency and accuracy.

[0101] In an optional embodiment, before determining that the reference processing unit is in an abnormal running state, the method further comprises:

[0102] S1, obtaining a maximum reference count value in a previous detection period; and taking the maximum reference count value matched with the previous detection period as a first threshold value matched with a current detection period;

[0103] Before determining that the target processing unit is in an abnormal running state, the method further comprises:

[0104] S2, obtaining a maximum target count value in a previous detection period; and taking the maximum target count value matched with the previous detection period as a second threshold value matched with a current detection period.

[0105] In the above step S1, a maximum reference count value in a previous detection period is obtained; and the maximum reference count value matched with the previous detection period is taken as a first threshold value matched with a current detection period. As an optional embodiment, the first threshold value for determining whether the reference processing unit is faulty can be dynamically determined based on historical detection results, for example, in a previous detection period, the first continuous response failure occurs twice, the second continuous response failure occurs three times, and the third continuous response failure occurs five times, and the first threshold value of the current detection period is set to 5.

[0106] In the above step S2, a maximum target count value in a previous detection period is obtained; and the maximum target count value matched with the previous detection period is taken as a second threshold value matched with a current detection period. As an optional embodiment, the second threshold value for determining whether the target processing unit is faulty can be dynamically determined based on historical detection results, for example, in a previous detection period, the first continuous sending request failure occurs four times, the second continuous sending request failure occurs six times, and the third continuous sending request failure occurs two times, and the second threshold value of the current detection period is set to 6.

[0107] As an optional implementation, the ARM sends the first heartbeat packet request at a first time, the DSP receives the heartbeat packet request sent by the ARM at a second time, and returns a heartbeat detection packet to the ARM after T time intervals (target time intervals), i.e., at a third time. After the ARM receives the response packet, the ARM sends a second heartbeat packet request after T1 time intervals, and repeats the above process to realize periodic question and answer. Reasonable setting of the sending and response time intervals improves the stability and reliability of the system.

[0108] By dynamically adjusting the time intervals at which the processing units send and respond in the fault detection period, for example, if the number of low-level faults is high and the number of high-level faults is low in the migration detection period as indicated in the fault description information, the sending and response time intervals of the processing units can be extended to reduce the load; on the contrary, if multiple fault events have been found in the historical detection period, the sending and response time intervals of the heartbeat request and the heartbeat detection packet need to be reduced in the current detection period to facilitate prompt action, reduce risks, adapt to different operating environments and conditions, and improve the accuracy of fault detection.

[0109] In an optional implementation, before determining that the reference processing unit is in an abnormal operating state, the first period in the case where the sending of the notification information by the reference processing unit is monitored to fail further includes:

[0110] S1, the reference processing unit performs digital processing on the received radar signal data to obtain a radar data processing result, and sends the radar data processing result to the target processing unit;

[0111] S2, the reference processing unit sends notification information to the target processing unit at a target time.

[0112] In the above steps S1-S2, the reference processing unit performs digital processing on the received radar signal data to obtain a radar data processing result, and sends the radar data processing result to the target processing unit; and the reference processing unit sends notification information to the target processing unit at a target time.

[0113] The reference processing unit DSP performs digital signal processing algorithms such as filtering, signal enhancement, data analysis, etc. to extract useful information for subsequent analysis, such as the distance, speed and direction of obstacles, and specifically can process radio frequency module data to form perception data. Further, the reference processing unit will send the processed perception data to the target processing unit (usually an ARM Core, responsible for higher-level data analysis and decision-making) at a preset target time (this time is calculated based on the system clock and processing time to ensure the timeliness and accuracy of the data).

[0114] In the above embodiment, the DSP core sends a confirmation message to the ARM core at the target time, indicating that the data has been successfully transmitted. The failure of the processing unit can be further determined based on the reception of the notification information by the ARM core. The failure of the DSP core and the communication link can be detected in time, and the normal operation of the system can be restored through a failure response mechanism (such as reset) to prevent potential systemic failure and improve the robustness and safety of the system.

[0115] In an optional embodiment, after the reference processing unit sends the notification information to the target processing unit at the target time, the method further comprises:

[0116] S1, in the case that the target processing unit does not receive the notification information before the first reference time, determining that the reference processing unit is in an abnormal operation state;

[0117] S2, in the case that the target processing unit does not receive the notification information before the second reference time, determining to perform a reset operation on the multi-core controller, wherein the first time interval between the target time and the first reference time is less than the second time interval between the target time and the second reference time.

[0118] In the above steps S1-S2, when the target processing unit receives the data from the reference processing unit, a first reference time is set, which is usually set to a period of time after the target time to allow network transmission and processing delay. If the target processing unit fails to receive the perception data sent by the reference processing unit before the first reference time, it is determined that the reference processing unit has a failure, such as data processing delay, hardware failure or network communication problem. At this time, the target processing unit will record the failure and take corresponding measures, such as starting a redundant reference processing unit, increasing the failure detection frequency or notifying the system operator.

[0119] If the target processing unit still does not receive the perception data before the second reference time, it is determined that the failure is a more serious system failure, for example, the reference processing unit is stuck or the target processing unit itself has a communication failure. In this case, the multi-core controller will perform a system-level reset operation, i.e. restart the entire controller or related module, to try to restore the normal operation of the system. The first time interval between the target time and the first reference time is less than the second time interval between the target time and the second reference time, which can respond in time when a slight failure is detected, and take more aggressive measures such as system reset when a serious failure is detected.

[0120] In an optional embodiment, during the operation of the multi-core controller, the method further comprises:

[0121] S1, obtaining a first detection result matched with a target detection task and a second monitoring result matched with a target monitoring task, wherein a reliability coefficient of the second monitoring result is greater than a reliability coefficient of the first detection result;

[0122] S2, performing weighted summation on the first detection result and the second monitoring result according to respective reliability coefficients corresponding thereto, and determining a running state of the multi-core controller according to a weighted summation result.

[0123] In the above steps S1-S2, the reliability coefficient is used to indicate the accuracy of the fault task judgment result. As an optional implementation, the multi-core controller performs the target detection task to generate the first detection result (for example, the detection result of the DSP failure rate is 0.2) and the reliability coefficient R1 attached thereto. Further, the target monitoring task is performed to generate the second detection result (for example, the detection result of the DSP failure rate is 0.8) and the reliability coefficient R2 attached thereto. The first detection result is multiplied by the reliability coefficient R1 to obtain a weighted value W1, and the second detection result is multiplied by the reliability coefficient R2 to obtain a weighted value W2, and then a weighted summation value S is obtained. If S is higher than a preset threshold, it may mean that the DSP is faulty; if S is lower than the threshold, it can be that the DSP is not faulty.

[0124] Through the above implementation of the present application, the completion of different tasks on the same target detection task and the reliability of the respective results are comprehensively considered. Through weighted summation, it is ensured that the comprehensive evaluation result reflects the actual running state of the system and the accuracy of data processing, improves the accuracy of confirming the fault, more accurately identifies the potential processing abnormality, makes a timely response, and supports stable operation under functional safety requirements.

[0125] In an optional implementation, during the running of the multi-core controller, before the target processing unit in the multi-core controller sends a heartbeat packet request to the reference processing unit in the multi-core controller according to the first period, the method further comprises:

[0126] S1, configuring task description information for the multi-core controller, wherein the task description information indicates that the fault detection task is a low-priority task and the system task is a high-priority task;

[0127] S2, the multi-core controller executes the tasks according to the priority order indicated in the task description information.

[0128] In the steps S1-S2, the task description information is configured for the multi-core controller, wherein the task description information indicates that the fault detection task is a low priority task and the system task is a high priority task; the multi-core controller executes the tasks according to the priority order indicated in the task description information. It should be noted that the priority of the heartbeat monitoring task in the DSP core is configured as non-preemptive and low. If the DSP can normally execute the low priority task, the possibility that the OS can normally schedule all tasks is high. Therefore, the fault detection task is configured as a low priority task, which firstly ensures whether the underlying scheduling task can be normally executed, and then executes the fault detection task after the scheduling task is executed, thereby improving the accuracy of the detection result.

[0129] The scheme described in the present application is fully explained below with a specific embodiment:

[0130] Firstly, the DSP heartbeat is monitored by using the ARM core, so as to detect the fault of the DSP core operating system and report the fault. Secondly, the heartbeat request detection is also designed for the ARM core in the DSP core, so as to avoid false reporting of the DSP core fault caused by the ARM fault. The specific implementation steps are as follows:

[0131] S1, the DSP core and the ARM core are started respectively.

[0132] S2, the ARM core sends a heartbeat packet request to the DSP core once every T1 time.

[0133] S3, the DSP core receives the heartbeat packet request from the ARM core and accumulates 1 successful event, otherwise accumulates 1 failure event.

[0134] S4, the DSP core sends a heartbeat detection packet once every T time.

[0135] S5, the ARM core receives the heartbeat packet from the DSP core and accumulates 1 successful event, otherwise accumulates 1 failure event.

[0136] Based on the mechanism, the possible situations and responses are as follows: if the system is normal, the ARM and the DSP perform the question and answer according to the set period; if the ARM core accumulates A times of not receiving the heartbeat packet, a fault is recorded, accumulates B times (B>A) of not receiving the heartbeat packet, and then requests the system to reset; if the heartbeat packet is successfully received before the accumulated number is reached, the accumulation is restarted; if the DSP core accumulates X times of not receiving the heartbeat packet request, a fault is recorded, accumulates Y times (Y>X) of not receiving the heartbeat packet request, and then requests the system to reset; if the heartbeat packet request is successfully received before the accumulated number is reached, the accumulation is restarted; wherein the values of A, B, X, Y, T and T1 can be set according to the actual fault response time of the project.

[0137] On this basis, since the heartbeat monitoring is only one of the many tasks performed by the operating system, even if the DSP successfully answers the ARM, it can only show that the DSP core can work, but due to the complexity of the operating system, working does not mean that it can correctly schedule all tasks. That is, the above process is to monitor whether the DSP is "yes" or "no", and the following two processes are also designed in the scheme:

[0138] S1, configure the heartbeat monitoring task priority in the DSP core as non-preemptive and low, if the DSP can normally execute the low priority task, then the possibility of the OS normally scheduling all tasks is high;

[0139] S2, considering that the operating system is the bottom layer, and the final performance of the product is in the functional layer (application layer), task monitoring is added for the application layer function deployed in the DSP core, which can basically ensure that the radar can normally schedule tasks and finally send out point cloud and track, and the specific implementation manner is as shown in Figure 6

[0140] S602, the DSP accepts the radio module data.

[0141] S604, the DSP processes the radio module data (forms perception data).

[0142] S606, the DSP sends the perception data to the ARM core responsible for processing the perception interface.

[0143] S608, the DSP core notifies the ARM of successful sending of the perception data.

[0144] If the ARM does not receive the information of the DSP reporting successful sending of the perception data within T2 time, record the fault; if the ARM does not receive the information of the DSP reporting successful sending of the perception data within T3 (T3>T2) time, request external reset; wherein, T2, T3 and the task priority need to be set according to the actual fault response time of the project.

[0145] Through the above implementation mode, for the fault caused by the OS of the DSP, task monitoring is set from the bottom layer and the application layer respectively, the system running state is managed in time, the safety and reliability of the system are effectively improved, not only the non-safety OS can be monitored for fault, but also the safety OS can be monitored, the double-core mutual monitoring is realized, and the safety of the system is improved.

[0146] ​It should be noted that, for the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations, but those skilled in the art should know that the present application is not limited by the action sequence described, because according to the present application, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily necessary for the present application.

[0147] According to another aspect of the embodiments of the present application, a fault detection device for a multi-core controller is also provided for implementing the above-mentioned fault detection method for a multi-core controller. As shown in the figure, the device comprises: Figure 7

[0148] The execution unit 702 controls the multi-core controller to execute a target detection task according to a first period and a target monitoring task according to a second period during the operation of the multi-core controller, wherein the target detection task is to control the target processing unit to send a heartbeat message request to the reference processing unit in the multi-core controller, and the reference processing unit returns a heartbeat detection message to the target processing unit in response to the heartbeat message request, and the target monitoring task is to monitor the sending operation of the reference processing unit to send the radar data processing result to the target processing unit;

[0149] The first determination unit 704 determines that the reference processing unit is in an abnormal operation state when the first number of heartbeat detection messages received by the target processing unit meets the first detection condition;

[0150] The second determination unit 706 determines that the target processing unit is in an abnormal operation state when the second number of heartbeat message requests received by the reference processing unit meets the second detection condition.

[0151] The third determination unit 708 determines that the reference processing unit is in an abnormal operation state when it is monitored that the reference processing unit fails to send notification information, wherein the notification information is used to indicate that the reference processing unit has sent the radar data processing result to the target processing unit.

[0152] ​Optionally, the fault detection apparatus for the multi-core controller further comprises a third determination module configured to: acquire a reference count value matched with the first number at a current time, wherein the reference count value is used to indicate a number of times that the reference processing unit continuously fails to respond to a request within a target detection period; determine that the reference processing unit is in an abnormal running state if the reference count value is greater than or equal to a first threshold value; acquire a target count value matched with the second number at the current time, wherein the target count value is used to indicate a number of times that the target processing unit continuously fails to send a request within the target detection period; and determine that the target processing unit is in an abnormal running state if the target count value is greater than or equal to a second threshold value.

[0153] Optionally, the third determination module comprises: a counting module configured to increase the reference count value by 1 if the target processing unit fails to receive the heartbeat detection packet returned by the reference processing unit, and reset the reference count value to 0 if the target processing unit successfully receives the heartbeat detection packet returned by the reference processing unit; and a counting module configured to increase the target count value by 1 if the reference processing unit fails to receive the heartbeat packet request sent by the target processing unit, and reset the target count value to 0 if the reference processing unit successfully receives the heartbeat packet request sent by the target processing unit.

[0154] Optionally, the third determination module comprises: an execution module configured to determine to perform a reset operation on the multi-core controller if the reference count value is greater than a target first threshold value, wherein the target first threshold value is greater than the first threshold value; and an execution module configured to determine to perform a reset operation on the multi-core controller if the target count value is greater than a target second threshold value, wherein the target second threshold value is greater than the second threshold value.

[0155] Optionally, the third determination module comprises: an acquisition module configured to acquire a maximum reference count value within a previous detection period; and an acquisition module configured to acquire a maximum target count value within the previous detection period.

[0156] Optionally, the third determination unit comprises: a sending unit configured to cause the reference processing unit to perform digital processing on the received radar signal data to obtain the radar data processing result, and send the radar data processing result to the target processing unit; and a sending unit configured to cause the reference processing unit to send notification information to the target processing unit at a target time.

[0157] Optionally, the sending unit comprises a fourth determining module configured to determine that the reference processing unit is in the abnormal operation state if the target processing unit does not receive the notification information before a first reference time point; and determine to perform a reset operation on the multi-core controller if the target processing unit does not receive the notification information before a second reference time point, wherein a first time interval between the target time point and the first reference time point is less than a second time interval between the target time point and the second reference time point.

[0158] Optionally, the executing unit comprises an obtaining module configured to obtain a first detection result matched with the target detection task and a second monitoring result matched with the target monitoring task, wherein a reliability coefficient of the second monitoring result is greater than a reliability coefficient of the first detection result; and perform weighted summation on the first detection result and the second monitoring result respectively according to the reliability coefficients corresponding thereto, and determine the operation state of the multi-core controller according to a weighted summation result.

[0159] Optionally, the executing unit comprises a configuring module configured to configure task description information for the multi-core controller, wherein the task description information indicates that the fault detection task is a low-priority task and the system task is a high-priority task; and the multi-core controller executes tasks according to the priority order indicated in the task description information.

[0160] The specific embodiments can refer to the examples shown in the above-mentioned method for detecting faults of a multi-core controller, which will not be described herein again in this example.

[0161] The memory 802 can be used to store software programs and modules, such as program instructions / modules of the method and device for detecting faults of a multi-core controller, and the processor 804 executes various functional applications and data processing by running the software programs and modules stored in the memory 802, that is, implements the above-mentioned method for detecting faults of a multi-core controller. The memory 802 can include a high-speed random access memory, and can also include a non-volatile memory, such as one or more magnetic storage devices, flash memories, or other non-volatile solid-state memories. In some examples, the memory 802 can further include a memory remotely arranged with respect to the processor 804, which can be connected to the terminal through a network. Examples of the above-mentioned network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. Specifically, the memory 802 can be but is not limited to used for storing target files and other file information. As an example, the memory 802 can be used to store a target file, and the processor 804 can be configured to execute the target file to implement the method for detecting faults of a multi-core controller. Figure 8As shown, the memory 802 can include, but is not limited to, the execution unit 702, the first determination unit 704, the second determination unit 706, and the third determination unit 708 in the fault detection apparatus for the multi-core controller. In addition, the memory 802 can also include, but is not limited to, other module units in the fault detection apparatus for the multi-core controller, which are not described herein.

[0162] Optionally, the transmission device 806 is configured to receive or send data via a network. The network can include, but is not limited to, a wired network and a wireless network. In an example, the transmission device 806 includes a network adapter (NIC), which can be connected to other network devices and routers through a network cable to communicate with the Internet or a local area network. In an example, the transmission device 806 is a radio frequency (RF) module, which is configured to communicate with the Internet in a wireless manner.

[0163] In addition, the electronic device further includes a display 808 and a connection bus 810, which are configured to connect various module components in the electronic device.

[0164] According to an aspect of the present application, a computer program product is provided, which includes computer programs / instructions containing program codes for executing the methods shown in the flowcharts. In such an embodiment, the computer program can be downloaded and installed from a network through a communication part, and / or installed from a detachable medium. When the computer program is executed by a central processing unit, various functions provided by the embodiments of the present application are performed.

[0165] The serial numbers of the embodiments of the present application are only for description, and do not represent the advantages or disadvantages of the embodiments.

[0166] It should be noted that the computer system of the electronic device is only an example, and should not limit the functions and use range of the embodiments of the present application.

[0167] In particular, according to the embodiments of the present application, the processes described in the various method flowcharts can be implemented as a computer software program. For example, the embodiments of the present application include a computer program product, which includes a computer program carried on a computer readable medium, and the computer program contains program codes for executing the methods shown in the flowcharts. In such an embodiment, the computer program can be downloaded and installed from a network through a communication part, and / or installed from a detachable medium. When the computer program is executed by a central processing unit, various functions defined in the system of the present application are performed.

[0168] According to an aspect of the present application, a computer readable storage medium is provided, from which a processor of a computer device reads computer instructions, and the processor executes the computer instructions to enable the computer device to perform the method provided in the various optional implementation manners.

[0169] Optionally, in the embodiment, the computer readable storage medium can be configured to store a computer program for performing the following steps:

[0170] S1. During the operation of the multi-core controller, the multi-core controller is controlled to perform a target detection task according to a first period and to perform a target monitoring task according to a second period, wherein the target detection task is to control a target processing unit to send a heartbeat message request to a reference processing unit in the multi-core controller, and the reference processing unit returns a heartbeat detection message to the target processing unit in response to the heartbeat message request, and the target monitoring task is to monitor a sending operation of the reference processing unit to send a radar data processing result to the target processing unit;

[0171] S2. In a case where a first number of the heartbeat detection messages received by the target processing unit satisfies a first detection condition, it is determined that the reference processing unit is in an abnormal operation state;

[0172] S3. In a case where a second number of the heartbeat message requests received by the reference processing unit satisfies a second detection condition, it is determined that the target processing unit is in an abnormal operation state;

[0173] S4. In a case where it is monitored that the reference processing unit fails to send notification information, it is determined that the reference processing unit is in an abnormal operation state, wherein the notification information is used to indicate that the reference processing unit has sent the radar data processing result to the target processing unit.

[0174] Optionally, in the embodiment, those skilled in the art can understand that all or part of the steps in the various methods of the above-mentioned embodiments can be completed by instructing the hardware related to the electronic device through a program, and the program can be stored in a computer readable storage medium, and the storage medium can include a flash disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0175] The serial numbers of the embodiments of the present application are only for description, and do not represent the advantages or disadvantages of the embodiments.

[0176] The integrated units in the above embodiments, if implemented in the form of software function units and sold or used as independent products, can be stored in the above computer-readable storage medium. Based on such understanding, the technical solutions of the present application, essentially or in other words, the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes a number of instructions to make one or more computer devices (which can be personal computers, servers or network devices, etc.) execute all or part of the steps of the methods of the various embodiments of the present application.

[0177] In the above embodiments of the present application, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0178] In the several embodiments provided by the present application, it should be understood that the disclosed user equipment can be implemented in other ways. Of course, the unit division in the above device embodiment is only a logical function division, and there can be another division manner in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between the units can be indirect couplings or communication connections through some interfaces, accessors or modules, and can be electrical or other forms.

[0179] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., can be located in one place, or can be distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the present embodiment.

[0180] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present alone, or two or more units can be integrated in one unit. The above integrated unit can be realized in the form of hardware or in the form of a software function unit.

[0181] The above is only the preferred embodiment of the present application, and it should be pointed out that for those skilled in the art, without departing from the principle of the present application, a number of improvements and refinements can be made, which should be considered as the protection scope of the present application.

Claims

1. A method for detecting a failure of a multi-core controller, the method comprising: Comprising: During the operation of the multi-core controller, the target detection task is controlled to be executed by the multi-core controller according to a first period, and the target monitoring task is controlled to be executed by the multi-core controller according to a second period, wherein the target detection task is to control a target processing unit to send a heartbeat message request to a reference processing unit in the multi-core controller, and the reference processing unit returns a heartbeat detection message to the target processing unit in response to the heartbeat message request, and the target monitoring task is to monitor the sending operation of the reference processing unit to send a radar data processing result to the target processing unit; obtaining a first detection result matched with the target detection task and a second monitoring result matched with the target monitoring task, wherein the reliability coefficient of the second monitoring result is greater than the reliability coefficient of the first detection result; the first detection result and the second monitoring result are respectively weighted and summed according to the corresponding reliability coefficients, and the running state of the multi-core controller is determined according to the weighted sum result; In the case that the first number of the heartbeat detection messages received by the target processing unit satisfies the first detection condition, it is determined that the reference processing unit is in an abnormal running state; In the case that the second number of the heartbeat message requests received by the reference processing unit satisfies the second detection condition, it is determined that the target processing unit is in an abnormal running state; The reference processing unit performs digital processing on the received radar signal data to obtain the radar data processing result, and sends the radar data processing result to the target processing unit; and the reference processing unit sends notification information to the target processing unit at a target time; In the case that the target processing unit does not receive the notification information before a first reference time, it is determined that the reference processing unit is in the abnormal running state; and in the case that the target processing unit does not receive the notification information before a second reference time, a reset operation is performed on the multi-core controller, wherein a first time interval between the target time and the first reference time is less than a second time interval between the target time and the second reference time; In the case that the reference processing unit fails to send the notification information, it is determined that the reference processing unit is in the abnormal running state, wherein the notification information is used to indicate that the reference processing unit has sent the radar data processing result to the target processing unit.

2. The method of claim 1, wherein In the case that the first number of the heartbeat detection messages received by the target processing unit satisfies the first detection condition, it is determined that the reference processing unit is in an abnormal running state, comprising: obtaining a reference count value matched with the first number at a current time, wherein the reference count value is used to indicate the number of continuous response request failures of the reference processing unit within a target detection period; and in the case that the reference count value is greater than or equal to a first threshold value, it is determined that the reference processing unit is in the abnormal running state. The second quantity of the heartbeat packet requests received by the reference processing unit satisfies a second detection condition, and the target processing unit is determined to be in an abnormal running state. A target count value matched with the second quantity at the current time is obtained, where the target count value is used to indicate the number of continuous sending request failures of the target processing unit within the target detection period; and the target processing unit is determined to be in the abnormal running state when the target count value is greater than or equal to a second threshold value.

3. The method of claim 2, wherein, Before the reference processing unit is determined to be in the abnormal running state, the method further comprises: the reference count value is increased by 1 when the target processing unit fails to receive the heartbeat detection packet returned by the reference processing unit; and the reference count value is set to 0 when the target processing unit successfully receives the heartbeat detection packet returned by the reference processing unit. Before the target processing unit is determined to be in the abnormal running state, the method further comprises: the target count value is increased by 1 when the reference processing unit fails to receive the heartbeat packet request sent by the target processing unit; and the target count value is set to 0 when the reference processing unit successfully receives the heartbeat packet request sent by the target processing unit.

4. The method of claim 2, wherein, After the reference processing unit is determined to be in the abnormal running state, the method further comprises: a reset operation is performed on the multi-core controller when the reference count value is greater than a target first threshold value, where the target first threshold value is greater than the first threshold value. After the target processing unit is determined to be in the abnormal running state, the method further comprises: the reset operation is performed on the multi-core controller when the target count value is greater than a target second threshold value, where the target second threshold value is greater than the second threshold value.

5. The method of claim 2, wherein, Before the reference processing unit is determined to be in the abnormal running state, the method further comprises: a maximum reference count value in a previous detection period is obtained; and the maximum reference count value matched with the previous detection period is taken as the first threshold value matched with a current detection period. Before the target processing unit is determined to be in the abnormal running state, the method further comprises: a maximum target count value in a previous detection period is obtained; and the maximum target count value matched with the previous detection period is taken as the second threshold value matched with a current detection period.

6. The method of claim 1, wherein, Before the target processing unit in the multi-core controller is controlled to send the heartbeat packet request to the reference processing unit in the multi-core controller according to the first period during the running of the multi-core controller, the method further comprises: task description information is configured for the multi-core controller, where the task description information indicates that a fault detection task is a low-priority task and a system task is a high-priority task; the multi-core controller executes tasks according to the priority order indicated in the task description information.

7. A fault detection apparatus for a multi-core controller, the apparatus comprising: ​ The execution unit controls the multi-core controller to perform a target detection task according to a first period and to perform a target monitoring task according to a second period during the operation of the multi-core controller, the target detection task is to control a target processing unit to send a heartbeat message request to a reference processing unit in the multi-core controller, the reference processing unit returns a heartbeat detection message to the target processing unit in response to the heartbeat message request, the target monitoring task is to monitor a sending operation of the reference processing unit to send a radar data processing result to the target processing unit, a first detection result matched with the target detection task and a second monitoring result matched with the target monitoring task are obtained, the reliability coefficient of the second monitoring result is greater than the reliability coefficient of the first detection result, the first detection result and the second monitoring result are weighted and summed according to the corresponding reliability coefficients, and the operation state of the multi-core controller is determined according to the weighted and summed result; The first determination unit determines that the reference processing unit is in an abnormal operation state when a first number of the heartbeat detection messages received by the target processing unit meets a first detection condition; The second determination unit determines that the target processing unit is in an abnormal operation state when a second number of the heartbeat message requests received by the reference processing unit meets a second detection condition; The third determination unit determines that the reference processing unit is in the abnormal operation state when the target processing unit does not receive the notification information before a first reference time, determines to perform a reset operation on the multi-core controller when the target processing unit does not receive the notification information before a second reference time, and determines that the reference processing unit is in the abnormal operation state when the sending of the notification information by the reference processing unit is monitored to fail, wherein the first time interval between the target time and the first reference time is less than the second time interval between the target time and the second reference time, the notification information is used to indicate that the reference processing unit has sent the radar data processing result to the target processing unit.

8. A computer readable storage medium, characterized in that, The computer-readable storage medium includes a stored program, wherein the program is run by an electronic device to perform the method in any one of claims 1 to 6.

9. An electronic device comprising a memory and a processor, characterized in that The memory stores a computer program, and the processor is configured to execute the method in any one of claims 1 to 6 by the computer program.

10. A computer program product comprising a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method in any one of claims 1 to 6.

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