A segmented compensated bandgap reference voltage source

Abstract

This invention belongs to the field of analog integrated circuit design, and particularly relates to a segmented compensated bandgap reference voltage source. It includes: a first-order compensated bandgap reference circuit, a segmented compensation circuit, and a bias circuit. The first-order compensated bandgap reference circuit is connected to the segmented compensation circuit, and the segmented compensation circuit is connected to the bias circuit. The first-order compensated bandgap reference circuit provides a bandgap reference voltage that eliminates the first-order temperature coefficient. The segmented compensation circuit provides a temperature characteristic voltage for the bandgap reference voltage, the voltage curve of which is an upward-opening parabola. The bias circuit provides a bias voltage for both the first-order compensated bandgap reference circuit and the segmented compensation circuit. This invention provides an upward-opening parabolic temperature characteristic voltage through the segmented compensation circuit to compensate for the higher-order temperature coefficient of VBE, thereby reducing the temperature drift of the bandgap reference voltage source.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit design, and particularly relates to a segmented compensated bandgap reference voltage source. Background Technology

[0002] Bandgap voltage references are common voltage sources in analog integrated circuit design, widely used in various DACs, ADCs, power management chips, and sensor chips. Their most prominent feature is their high accuracy, independent of power supply voltage and temperature. Bandgap voltage references are generally used as modules providing reference voltages; their accuracy determines the accuracy of the entire circuit. With the market's increasing demands for circuit accuracy, the design of bandgap references with excellent temperature characteristics has become an important topic of concern for integrated circuit designers.

[0003] Bandgap voltage reference sources have various traditional structures, but their basic principles are essentially the same. Generally, they use a weighted, adjustable voltage with a positive temperature coefficient to add to a voltage with a negative temperature coefficient, thereby eliminating the first-order voltage temperature coefficient. The positive temperature coefficient voltage is usually chosen as the thermal voltage VT, while the negative temperature coefficient voltage is generally the base-emitter voltage VBE of a transistor.

[0004] In reality, since VBE is not an ideal first-order negative temperature coefficient voltage and has a high-order curvature, the output bandgap reference voltage in the traditional structure will have a second-order or higher temperature coefficient, which affects the accuracy of the circuit. In order to further improve the accuracy of the circuit, it is necessary to design a compensation circuit for the second-order or higher temperature coefficient. Summary of the Invention

[0005] This invention provides a segmented compensated bandgap reference voltage source, which solves the defects of the traditional first-order compensation circuit mentioned in the background art. It performs segmented compensation for higher-order temperature coefficients, thereby reducing the temperature drift of the bandgap reference voltage source.

[0006] The technical solution of the present invention is as follows: A segmented compensated bandgap reference voltage source includes: a first-order compensated bandgap reference circuit, a segmented compensation circuit, and a bias circuit. The first-order compensated bandgap reference circuit is connected to the segmented compensation circuit, and the segmented compensation circuit is connected to the bias circuit. The first-order compensated bandgap reference circuit is used to provide a bandgap reference voltage that eliminates the first-order temperature coefficient. The segmented compensation circuit is used to provide a temperature characteristic voltage for the bandgap reference voltage. The voltage curve of the temperature characteristic voltage is an upward-opening parabola. The bias circuit provides a bias voltage for the first-order compensated bandgap reference circuit and the segmented compensation circuit.

[0007] Furthermore, the first-order compensated bandgap reference circuit includes a common-source cascode current mirror and a bipolar reference output circuit. The common-source cascode current mirror is connected to the power supply voltage and the bipolar reference output circuit. The common-source cascode current mirror is used to copy the power supply voltage to the bipolar reference output circuit. The bipolar reference output circuit is used to generate a bandgap reference voltage that eliminates the first-order temperature coefficient based on the power supply voltage.

[0008] Further, the common-source common-gate current mirror includes: a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, and a first NMOS transistor MN1. The sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are both connected to the power supply voltage. The gates of the first PMOS transistor MP1 and the second PMOS transistor MP2 are both connected to the drain of the fourth PMOS transistor MP4. The drain of the first PMOS transistor MP1 is connected to the source of the third PMOS transistor MP3. The gate of the third PMOS transistor MP3 is connected to the gate of the fourth PMOS transistor MP4. The drain of the third PMOS transistor MP3 is connected to the gate of the first NMOS transistor MN1. The drain of the second PMOS transistor MP2 is connected to the source of the fourth PMOS transistor MP4. The drain of the fourth PMOS transistor MP4 is connected to the drain of the first NMOS transistor MN1. The gate of the first NMOS transistor MN1 is connected to a segmented compensation circuit.

[0009] Furthermore, the bipolar reference output circuit includes: a first transistor QN1, a second transistor QN2, a second resistor R2, and a first resistor R1. The collector of the first transistor QN1 is connected to the gate of the first NMOS transistor MN1, the base of the first transistor QN1 is connected to the base of the second transistor QN2, the collector of the second transistor QN2 is connected to the source of the first NMOS transistor MN1, the emitter of the first transistor QN1 is connected to one end of the first resistor R1, the emitter of the second transistor QN2 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is connected to signal ground. The bases of the first transistor QN1 and the second transistor QN2 output a bandgap reference voltage that eliminates the first-order temperature coefficient.

[0010] Furthermore, the segmented compensation circuit includes: a fifth PMOS transistor MP5, a second NMOS transistor MN2, a third transistor QN3, a fourth transistor QN4, a fifth transistor QN5, a sixth transistor QN6, a seventh transistor QN7, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6.

[0011] The source of the fifth PMOS transistor MP5 is connected to the power supply voltage. The gate of the fifth PMOS transistor MP5 is connected to a first-order compensated bandgap reference circuit. The drain of the fifth PMOS transistor MP5 is connected to the collector and base of the third transistor QN3 and the base of the fifth transistor QN5. The emitter of the collector of the third transistor QN3 is connected to the collector and base of the fourth transistor QN4. The emitter of the fourth transistor QN4 is connected to signal ground. The collector of the fifth transistor QN5 is connected to a bandgap reference voltage that eliminates the first-order temperature coefficient. The emitter of the fifth transistor QN5 is connected to one end of the third resistor R3. The other end of the third resistor R3 is connected to the emitter of the sixth transistor QN6 and one end of the fourth resistor R4. The other end of the fourth resistor R4 is connected to signal ground. The collector of the sixth transistor QN6 is connected to the power supply voltage. The base of the sixth transistor QN6 is connected to the bias circuit. The drain of the second NMOS transistor MN2 is connected to the power supply voltage. The gate of the second NMOS transistor MN2 is connected to the first-order compensated bandgap reference circuit. The source of the second NMOS transistor MN2 is connected to one end of the fifth resistor R5. The other end of the fifth resistor R5 is connected to the bandgap reference voltage that eliminates the first-order temperature coefficient and the collector of the seventh transistor QN7. The base of the seventh transistor QN7 is connected to the bias circuit. The emitter of the seventh transistor QN7 is connected to one end of the sixth resistor R6. The other end of the sixth resistor R6 is connected to signal ground.

[0012] Furthermore, the bias circuit includes: an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a seventh resistor R7, an eighth resistor R8, an eighth transistor QN8, a ninth resistor R9, and a tenth resistor R10.

[0013] The source of the eighth PMOS transistor MP8 and the gate and source of the ninth PMOS transistor MP9 are both connected to the power supply voltage. The gate of the eighth PMOS transistor MP8 is connected to a first-order compensated bandgap reference circuit. The drain of the eighth PMOS transistor MP8 is connected to one end of the seventh resistor R7 and provides a second bias voltage VB2. The other end of the seventh resistor R7 is connected to one end of the eighth resistor R8. The other end of the eighth resistor R8 is connected to one end of the ninth resistor R9 and provides a third bias voltage VB3. The other end of the ninth resistor R9 is connected to signal ground. The drain of the ninth PMOS transistor MP9 is connected to the collector of the eighth transistor QN8 and provides a first bias voltage VB1. The base of the eighth transistor QN8 is connected to one end of the eighth resistor R8 and the emitter of the eighth transistor QN8. The emitter of the eighth transistor QN8 is connected to one end of the tenth resistor R10. The other end of the tenth resistor R10 is connected to signal ground.

[0014] The beneficial effects of this invention are as follows: This invention provides a voltage with an upward-opening parabolic temperature characteristic through a segmented compensation circuit to compensate for the higher-order temperature coefficient of VBE. This invention can reduce the temperature drift of the bandgap reference voltage source. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the structure of the present invention.

[0016] Figure 2 This is a schematic diagram of the voltage characteristics of the present invention. Detailed Implementation

[0017] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. The described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0018] In the technical solution of the present invention, Figure 1 This is a structural schematic diagram provided by the present invention regarding a specific structure of a segmented compensated bandgap reference voltage source, as shown below. Figure 1 As shown, the present invention includes: a first-order compensated bandgap reference circuit 1, a segmented compensation circuit 2, and a bias circuit 3. The first-order compensated bandgap reference circuit 1 is connected to the segmented compensation circuit 2, and the segmented compensation circuit 2 is connected to the bias circuit. The first-order compensated bandgap reference circuit 1 is used to provide a bandgap reference voltage that eliminates the first-order temperature coefficient. The segmented compensation circuit 2 is used to provide a temperature characteristic voltage for the bandgap reference voltage. The voltage curve of the temperature characteristic voltage is an upward-opening parabola. The bias circuit 3 provides a bias voltage for the first-order compensated bandgap reference circuit 1 and the segmented compensation circuit 2.

[0019] In one embodiment of the present invention, the first-order compensated bandgap reference circuit 1 includes a common-source cascode current mirror and a bipolar reference output circuit. The common-source cascode current mirror is connected to the power supply voltage and the bipolar reference output circuit. The common-source cascode current mirror is used to copy the power supply voltage to the bipolar reference output circuit. The bipolar reference output circuit is used to generate a bandgap reference voltage that eliminates the first-order temperature coefficient based on the power supply voltage.

[0020] In one embodiment of the present invention, the common-source common-gate current mirror includes: a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, and a first NMOS transistor MN1. The sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are both connected to the power supply voltage. The gates of the first PMOS transistor MP1 and the second PMOS transistor MP2 are both connected to the drain of the fourth PMOS transistor MP4. The drain of the first PMOS transistor MP1 is connected to the source of the third PMOS transistor MP3. The gate of the third PMOS transistor MP3 is connected to the gate of the fourth PMOS transistor MP4. The drain of the third PMOS transistor MP3 is connected to the gate of the first NMOS transistor MN1. The drain of the second PMOS transistor MP2 is connected to the source of the fourth PMOS transistor MP4. The drain of the fourth PMOS transistor MP4 is connected to the drain of the first NMOS transistor MN1. The gate of the first NMOS transistor MN1 is connected to the segmented compensation circuit 2.

[0021] In one embodiment of the present invention, the bipolar reference output circuit includes: a first transistor QN1, a second transistor QN2, a second resistor R2, and a first resistor R1. The collector of the first transistor QN1 is connected to the gate of the first NMOS transistor MN1, the base of the first transistor QN1 is connected to the base of the second transistor QN2, the collector of the second transistor QN2 is connected to the source of the first NMOS transistor MN1, the emitter of the first transistor QN1 is connected to one end of the first resistor R1, the emitter of the second transistor QN2 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is connected to signal ground. The bases of the first transistor QN1 and the second transistor QN2 output a bandgap reference voltage that eliminates the first-order temperature coefficient.

[0022] In one embodiment of the present invention, the segmented compensation circuit 2 includes: a fifth PMOS transistor MP5, a second NMOS transistor MN2, a third transistor QN3, a fourth transistor QN4, a fifth transistor QN5, a sixth transistor QN6, a seventh transistor QN7, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6.

[0023] The source of the fifth PMOS transistor MP5 is connected to the power supply voltage. The gate of the fifth PMOS transistor MP5 is connected to the first-order compensated bandgap reference circuit 1. The drain of the fifth PMOS transistor MP5 is connected to the collector and base of the third transistor QN3 and the base of the fifth transistor QN5. The emitter of the collector of the third transistor QN3 is connected to the collector and base of the fourth transistor QN4. The emitter of the fourth transistor QN4 is connected to signal ground. The collector of the fifth transistor QN5 is connected to the bandgap reference voltage that eliminates the first-order temperature coefficient. The emitter of the fifth transistor QN5 is connected to one end of the third resistor R3. The other end of the third resistor R3 is connected to the emitter of the sixth transistor QN6 and one end of the fourth resistor R4. The other end of the fourth resistor R4 is connected to signal ground. The collector of the sixth transistor QN6 is connected to the power supply voltage. The base of the sixth transistor QN6 is connected to the bias circuit 3. The drain of the second NMOS transistor MN2 is connected to the power supply voltage. The gate of the second NMOS transistor MN2 is connected to the first-order compensated bandgap reference circuit 1. The source of the second NMOS transistor MN2 is connected to one end of the fifth resistor R5. The other end of the fifth resistor R5 is connected to the bandgap reference voltage that eliminates the first-order temperature coefficient and the collector of the seventh transistor QN7. The base of the seventh transistor QN7 is connected to the bias circuit 3. The emitter of the seventh transistor QN7 is connected to one end of the sixth resistor R6. The other end of the sixth resistor R6 is connected to signal ground.

[0024] In one embodiment of the present invention, the bias circuit 3 includes: an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a seventh resistor R7, an eighth resistor R8, an eighth transistor QN8, a ninth resistor R9, and a tenth resistor R10.

[0025] The source of the eighth PMOS transistor MP8 and the gate and source of the ninth PMOS transistor MP9 are both connected to the power supply voltage. The gate of the eighth PMOS transistor MP8 is connected to the first-order compensated bandgap reference circuit 1. The drain of the eighth PMOS transistor MP8 is connected to one end of the seventh resistor R7 and provides a first bias voltage VB1. The other end of the seventh resistor R7 is connected to one end of the eighth resistor R8. The other end of the eighth resistor R8 is connected to one end of the ninth resistor R9 and provides a third bias voltage VB3. The other end of the ninth resistor R9 is connected to signal ground. The drain of the ninth PMOS transistor MP9 is connected to the collector of the eighth transistor QN8. The base of the eighth transistor QN8 is connected to the emitter of the eighth transistor QN8. The emitter of the eighth transistor QN8 is connected to one end of the tenth resistor R10. The other end of the tenth resistor R10 is connected to signal ground.

[0026] The working principle of this invention is as follows:

[0027] In the first-order bandgap reference circuit 1, NPN transistors QN1 and QN2, and resistors R1 and R2 constitute a traditional Brokaw reference structure. PMOS transistors MP1, MP2, MP3, and MP4 form a common-source cascode current mirror, ensuring that the current flowing through NPN transistors QN1 and QN2 is essentially the same. NMOS transistor MN1 acts as an isolation element to prevent VB4 from being pulled low during startup, thus preventing a transient large current from entering the reference.

[0028] Based on circuit analysis, the output of the first-order bandgap reference circuit (1) is:

[0029]

[0030] For VBE1, there is

[0031]

[0032] Among them, V G0 (T r () is the silicon bandgap voltage at reference temperature T r The value of V T This is the thermal voltage, η is a process-dependent constant, and ζ is the order of the transistor's collector current-temperature characteristic. When the current flowing through the transistor is PTAT, this term is 1; when a negative temperature coefficient current flows, this term is -1; and when a temperature-independent current flows, this term is 0. From the above equation, it can be seen that the temperature function of VBE consists of a constant term, a first-order term, and a higher-order term. After first-order compensation, this voltage also has... In this part, the temperature-voltage graph is similar to the function y = -xlnx, which is a parabola with a downward opening. Therefore, by simply adding the voltage of a temperature-voltage curve with an upward-opening parabola graph to a first-order bandgap reference, a bandgap reference with smaller temperature drift can be obtained. In this invention, this function is implemented by the segmented compensation circuit 2.

[0033] In segmented compensation circuit 2, PMOS transistor MP5, NPN transistors QN3, QN4, and QN5, and resistors R3 and R4 form one branch, while NMOS transistor QN7 and resistor R6 form the other branch. These two branches provide the current for segmented compensation. NMOS transistor MN2 and resistor R5 convert the segmented compensation current into a compensation voltage, which is superimposed on the output of the first-order bandgap reference 1.

[0034] Let the current flowing through R5 be I1, the current flowing through QN5 and R3 be I11, the current flowing through QN7 and R6 be I12, and the current flowing through QN6 be I2. Let the saturation conduction voltage of the triodes QN5 and QN6 be VBE0. First, analyze I12. When the temperature is too low, due to the negative temperature characteristic of VBE, the voltage VBE0 required for conduction at this time > the bias voltage VB3, and the triode is not conducting, and the current is approximately 0. When the temperature rises and VBE0 < VB3, an equation can be listed for I12 at this time as follows Since the temperature coefficient of R6 is small and will cancel out the temperature coefficient of R5, the influence of R6 can be ignored. Since the temperature coefficient of -VBE7 is positive, overall, I12 is a positive temperature coefficient current with a certain concave high-order curvature; then analyze I11. When the temperature is too high, due to the negative temperature characteristic of VBE, VBE1 + VBE6 < VBE0 + V3 + V4, and the triode QN5 is not conducting, and the current is approximately 0. When the temperature drops and VBE1 + VBE6 rises to make the triode QN5 conduct, an equation can be listed for the circuit as follows:

[0035]

[0036] The solution of the equation is

[0037]

[0038] Among them, VBE all have negative temperature coefficients. By selecting appropriate sizes for the triodes QN3, QN5, QN5, and QN6, it is possible to make V BE3 +V BE4 +V BE6 -V BE5 In this, the temperature coefficients of QN3, QN4, and QN6 are greater than the temperature coefficient of QN5, and this voltage is generally a negative temperature coefficient voltage with a certain convex high-order curvature. The magnitude of VB2 is the reference voltage superimposed with the voltage of R7. Since the current flowing through R7 is a mirror image of the reference PTAT, the current flowing through R7 has a first-order positive temperature coefficient, and thus VB2 also has a first-order positive temperature coefficient. Overall, at this time, I11 can be regarded as the sum of two negative temperature coefficient currents, and its property is a negative temperature coefficient current with a certain convex high-order curvature. Since the temperature coefficient of R3 is small and will cancel out the temperature coefficient of R5, the influence of R3 can be ignored.

[0039] Let the conduction temperature of QN6 be T1 and the conduction temperature of QN7 be T2. By adjusting the ratio of resistors R8 and R9, and the sizes of transistors QN3 and QN4, the values of T1 and T2 can be adjusted such that T1 < T2. From the circuit, it can be seen that I1 is the sum of the two branch currents I11 and I12. At this time, the temperature characteristic of I1 is: when T < T1, it is a negative temperature coefficient current; when T1 < T < T2, the current is approximately 0; when T2 < T, it is a positive temperature coefficient current. The overall current-temperature graph is approximately a parabola opening upwards.

[0040] The overall output of the circuit is

[0041]

[0042] Among them, the second term compensates for the first-order temperature coefficient of VBE1. In the third term, I1 is a segmented compensation current, R5 is a resistor with a low temperature coefficient, and the voltage on R5 is the product of these two terms, which is used to compensate for the high-order curvature of the circuit. The final compensation process is as Figure 2 shown, Figure 2 In the first curve graph in [reference], it is the first-order compensation result after the first and second terms in Equation (5) cancel each other out, and the overall performance is a parabola waveform opening upwards. Figure 2 In the second curve graph in [reference], it is a schematic diagram of the third term in Equation (5), and the overall is approximately a parabola graph opening downwards. Finally, the fluctuation of the overall bandgap reference voltage after compensation is as Figure 2 shown in the third curve graph in [reference]. The temperature graph of the bandgap reference voltage is similar to a cubic function, and the temperature drift is reduced.

[0043] In the bias circuit 3, the PMOS transistor MP9, the NPN transistor QN8, and the resistor R10 provide a bias voltage for the cascode current mirror. The PMOS transistor MP3, and the resistors R7, R8, and R9 provide a bias voltage for the segmented compensation circuit.

[0044] Finally, it should be noted that the above specific implementation manners are only used to illustrate the technical solutions of the present invention rather than to limit them. Although the present invention has been described in detail with reference to the examples, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention, and they should all be covered within the scope of the claims of the present invention.

Claims

1. A segmented compensated bandgap reference voltage source, characterized in that, include: The circuit consists of a first-order compensated bandgap reference circuit (1), a segmented compensation circuit (2), and a bias circuit (3). The first-order compensated bandgap reference circuit (1) is connected to the segmented compensation circuit (2), and the segmented compensation circuit (2) is connected to the bias circuit. The first-order compensated bandgap reference circuit (1) is used to provide a bandgap reference voltage that eliminates the first-order temperature coefficient. The segmented compensation circuit (2) is used to provide a temperature characteristic voltage for the bandgap reference voltage. The voltage curve of the temperature characteristic voltage is a parabola with its opening facing upwards. The bias circuit (3) provides a bias voltage for the first-order compensated bandgap reference circuit (1) and the segmented compensation circuit (2). The segmented compensation circuit (2) includes: a fifth PMOS transistor MP5, a second NMOS transistor MN2, a third transistor QN3, a fourth transistor QN4, a fifth transistor QN5, a sixth transistor QN6, a seventh transistor QN7, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6. The source of the fifth PMOS transistor MP5 is connected to the power supply voltage. The gate of the fifth PMOS transistor MP5 is connected to the first-order compensated bandgap reference circuit (1). The drain of the fifth PMOS transistor MP5 is connected to the collector and base of the third transistor QN3 and the base of the fifth transistor QN5. The emitter of the third transistor QN3 is connected to the collector and base of the fourth transistor QN4. The emitter of the fourth transistor QN4 is connected to signal ground. The collector of the fifth transistor QN5 is connected to the bandgap reference voltage that eliminates the first-order temperature coefficient. The emitter of the fifth transistor QN5 is connected to one end of the third resistor R3. The other end of the third resistor R3 is connected to the emitter of the sixth transistor QN6 and one end of the fourth resistor R4. The other end of resistor R4 is connected to signal ground. The collector of the sixth transistor QN6 is connected to the power supply voltage. The base of the sixth transistor QN6 is connected to the bias circuit (3). The drain of the second NMOS transistor MN2 is connected to the power supply voltage. The gate of the second NMOS transistor MN2 is connected to the first-order compensated bandgap reference circuit (1). The source of the second NMOS transistor MN2 is connected to one end of the fifth resistor R5. The other end of the fifth resistor R5 is connected to the bandgap reference voltage that eliminates the first-order temperature coefficient and the collector of the seventh transistor QN7. The base of the seventh transistor QN7 is connected to the bias circuit (3). The emitter of the seventh transistor QN7 is connected to one end of the sixth resistor R6. The other end of the sixth resistor R6 is connected to signal ground.

2. The segmented compensated bandgap reference voltage source as described in claim 1, characterized in that, The first-order compensated bandgap reference circuit (1) includes a common-source cascode current mirror and a bipolar reference output circuit. The common-source cascode current mirror is connected to the power supply voltage and the bipolar reference output circuit. The common-source cascode current mirror is used to copy the power supply voltage to the bipolar reference output circuit. The bipolar reference output circuit is used to generate a bandgap reference voltage that eliminates the first-order temperature coefficient based on the power supply voltage.

3. The segmented compensated bandgap reference voltage source as described in claim 2, characterized in that, The common-source common-gate current mirror includes: a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, and a first NMOS transistor MN1. The sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are both connected to the power supply voltage. The gates of the first PMOS transistor MP1 and the second PMOS transistor MP2 are both connected to the drain of the fourth PMOS transistor MP4. The drain of the first PMOS transistor MP1 is connected to the source of the third PMOS transistor MP3. The gate of the third PMOS transistor MP3 is connected to the gate of the fourth PMOS transistor MP4. The drain of the third PMOS transistor MP3 is connected to the gate of the first NMOS transistor MN1. The drain of the second PMOS transistor MP2 is connected to the source of the fourth PMOS transistor MP4. The drain of the fourth PMOS transistor MP4 is connected to the drain of the first NMOS transistor MN1. The gate of the first NMOS transistor MN1 is connected to the segmented compensation circuit (2).

4. The segmented compensated bandgap reference voltage source as described in claim 3, characterized in that, The bipolar reference output circuit includes: a first transistor QN1, a second transistor QN2, a second resistor R2, and a first resistor R1. The collector of the first transistor QN1 is connected to the gate of the first NMOS transistor MN1, the base of the first transistor QN1 is connected to the base of the second transistor QN2, the collector of the second transistor QN2 is connected to the source of the first NMOS transistor MN1, the emitter of the first transistor QN1 is connected to one end of the first resistor R1, the emitter of the second transistor QN2 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is connected to signal ground. The bases of the first transistor QN1 and the second transistor QN2 output a bandgap reference voltage that eliminates the first-order temperature coefficient.

5. The segmented compensated bandgap reference voltage source as described in claim 1, characterized in that, The bias circuit (3) includes: an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a seventh resistor R7, an eighth resistor R8, an eighth transistor QN8, a ninth resistor R9, and a tenth resistor R10. The source of the eighth PMOS transistor MP8 and the gate and source of the ninth PMOS transistor MP9 are both connected to the power supply voltage. The gate of the eighth PMOS transistor MP8 is connected to a first-order compensated bandgap reference circuit (1). The drain of the eighth PMOS transistor MP8 is connected to one end of the seventh resistor R7 and provides a second bias voltage VB2. The other end of the seventh resistor R7 is connected to one end of the eighth resistor R8. The other end of the eighth resistor R8 is connected to one end of the ninth resistor R9 and provides a third bias voltage VB3. The other end of the ninth resistor R9 is connected to signal ground. The drain of the ninth PMOS transistor MP9 is connected to the collector of the eighth transistor QN8 and provides a first bias voltage VB1. The base of the eighth transistor QN8 is connected to one end of the eighth resistor R8 and the emitter of the eighth transistor QN8. The emitter of the eighth transistor QN8 is connected to one end of the tenth resistor R10. The other end of the tenth resistor R10 is connected to signal ground.

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