Chip binning method and device, electronic device, and computer-readable medium
By marking the single module test signal in the chip, the result marking signal is obtained to determine the chip test results, which solves the problem that traditional bin technology is difficult to adapt to high-complexity chips, and achieves a more efficient bin process.
Patent Information
- Application Number
- CN202311292053.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-28
- Publication Date
- 2025-04-04
AI Technical Summary
Traditional chip split bin technology is difficult to adapt quickly when facing high-complexity chips and rapidly changing test vectors, which increases the difficulty of split bins and reduces efficiency.
By obtaining the test signals of multiple single modules in the chip to be tested, marking processing is performed to obtain the result marking signal, which is used to determine the test results of the chip and classify them based on this.
It reduces the difficulty and improves efficiency of the bin, and can quickly identify single-module test results, adapt to changes in the bin scheme and test vector, without affecting the efficiency of the bin.
Smart Images
Figure CN119759668A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to chip testing technology, and in particular to a chip binning method and device, electronic equipment, and computer-readable medium. Background Art
[0002] With the continuous reduction of chip manufacturing process size and the increase of transistor density, how to improve chip yield is one of the technologies that must be considered in the chip design, manufacturing and testing stages. Chip binning (also known as chip binning) technology can divide chips into different categories according to certain rules, adapting to different scenarios to improve chip yield. Traditional binning technology relies on human observation, that is, the integrated circuit automatic test equipment (ATE) machine needs to rely on the test vector of the functional module on the input side that is constructed separately or the test vector of the functional module that is output separately on the output side, and use professional test software to perform a huge amount of analysis work to obtain a fault-free (PASS) or faulty (FAIL) result. However, with the gradual increase in chip scale and complexity and the exponential growth of chip test vectors. Faced with highly complex chips, the design stage often undergoes multiple iterations, and the test vectors and binning schemes need to change frequently. Traditional binning technology needs to be updated multiple times to adapt to the changes in chip iterations, which increases the difficulty of binning and reduces the efficiency of binning. Summary of the invention
[0003] The main purpose of this application is to propose a chip binning method and device, electronic device, and computer-readable medium to reduce the difficulty of binning and improve the efficiency of binning.
[0004] In a first aspect, an embodiment of the present application provides a chip binning method, comprising:
[0005] Obtain test signals of multiple single modules in the chip under test;
[0006] Marking the test signal of the single module to obtain a result marking signal of the test signal; the result marking signal is used to identify whether the single module has a fault;
[0007] Determining a test result of the chip to be tested based on result marking signals of the test signals of the multiple single modules;
[0008] The chip is classified based on the test result to obtain a classification result.
[0009] In some embodiments, before determining the test result of the chip to be tested based on the result mark signals of the test signals of the multiple single modules, the method further includes:
[0010] The test signal of the single module marked as faulty is shielded, and then the chip to be tested is retested.
[0011] In some embodiments, the test signal comprises a memory built-in self-test MBIST signal, and the MBIST test signal comprises a ready state bit signal and a fail state bit signal;
[0012] The step of performing marking processing on the test signal of the single module to obtain a result marking signal of the test signal includes:
[0013] Performing an inversion process on the ready state bit signal to obtain an inverted ready state bit signal;
[0014] A result flag signal of the test signal is obtained based on the ready state bit negation signal and the fail state bit signal.
[0015] In some embodiments, the test signal comprises a scanning test signal;
[0016] The step of performing marking processing on the test signal of the single module to obtain a result marking signal of the test signal includes:
[0017] Performing compression processing on the scanning test signal of the single module to obtain a test compression feature vector;
[0018] Based on the comparison between the test compression feature vector and a preset ideal feature vector, a result marking signal of the test signal is obtained.
[0019] In some embodiments, the scan test signal of the single module includes n groups of scan test vectors, each group of the scan test vectors includes k cycles, where n and k are integers and are greater than or equal to 1;
[0020] For the i-th cycle, performing compression processing based on the i-th group of scan test signals, the i-1-th group of test compression feature vectors and feedback coefficients, obtaining the i-th group of test compression feature vectors;
[0021] For the (i+1)th cycle, based on the (i+1)th group of scanned test vectors, the (i)th group of test compressed feature vectors and feedback coefficients, the (i+1)th group of test compressed feature vectors is obtained.
[0022] In some embodiments, the step of obtaining a result marking signal of the test signal based on comparing the test compression feature vector with a preset ideal feature vector includes:
[0023] Comparing the test compressed feature vector with a preset ideal feature vector to obtain a vector comparison result;
[0024] A result flag signal of the test signal is obtained based on the vector comparison result.
[0025] In some embodiments, the test compressed feature vector, the ideal feature vector, and the vector comparison result have the same number of bits;
[0026] The step of comparing the test compression feature vector with a preset ideal feature vector to obtain a vector comparison result includes:
[0027] Comparing the eigenvalues at the same bit position in the test compressed eigenvector and the ideal eigenvector to obtain a bit position comparison result;
[0028] When the characteristic values are different, the bit comparison result is a first preset value;
[0029] When the characteristic values are the same, the bit comparison result is a second preset value;
[0030] The vector comparison result is determined based on the bit comparison results of the plurality of bits.
[0031] In some embodiments, obtaining a result flag signal of the test signal based on the vector comparison result includes:
[0032] In the vector comparison result, if there is a bit comparison result that is the first preset value, then the result mark signal of the test signal is a fault signal;
[0033] In the vector comparison result, if all the bit comparison results are the second preset value, the result mark signal of the test signal is a fault-free signal.
[0034] In some embodiments, before compressing the scan test signal of the single module to obtain the test compression feature vector, the method further includes:
[0035] The scan test vector is processed with a circuit unknown state value to remove or mask the unknown state of the circuit to be tested.
[0036] In some embodiments, after obtaining the result mark signal of the test signal, the method further includes:
[0037] transferring, storing and downloading the result marker signal of the test signal through a data transfer network,
[0038] In some embodiments, classifying the chip based on the test result to obtain a classification result includes:
[0039] The chip is classified based on the function of the single module corresponding to the result marking signal without fault in the test result to obtain the classification result.
[0040] In a second aspect, an embodiment of the present application provides a chip binning device, comprising:
[0041] An acquisition module is used to acquire test signals of multiple single modules in the chip to be tested;
[0042] A marking module, used for marking the test signal of the single module to obtain a result marking signal of the test signal; the result marking signal is used to identify whether the single module test is fault-free;
[0043] A determination module, configured to determine a test result of the chip to be tested based on result marking signals of the test signals of the multiple single modules;
[0044] The classification module is used to classify the chip based on the test result to obtain a classification result.
[0045] In some embodiments, the apparatus further comprises:
[0046] The shielding module is used to shield the test signal of a single module marked as having a fault.
[0047] In some embodiments, the acquisition module includes an MBIST unit, and the test signal output by the MBIST unit includes a ready state bit signal and a failure state bit signal;
[0048] The marking module is used to invert the ready state bit signal to obtain a ready state bit inversion signal; and to perform an OR operation on the ready state bit inversion signal and the failure state bit signal to obtain a result marking signal of the test signal.
[0049] In some embodiments, the acquisition module includes a scanning unit, and the scanning unit includes:
[0050] A test response subunit, used for obtaining a scanning test signal;
[0051] A feature compression subunit, used for compressing the scan test signal to obtain a test compression feature vector;
[0052] The comparison circuit subunit is used to compare the test compression feature vector with a preset ideal feature vector to obtain a result marking signal of the test signal.
[0053] In some embodiments, the scanning unit further comprises:
[0054] A link subunit is provided between the feature compression subunit and the comparison circuit subunit, and is used for transmitting the test compression feature vector to the comparison circuit subunit.
[0055] In some embodiments, the feature compression subunit includes a plurality of linear feedback shift registers, and the plurality of linear feedback shift registers are signal-connected in sequence.
[0056] In some embodiments, the classification module is used to classify the chip based on the function of the single module corresponding to the result marking signal of no fault in the test result to obtain the classification result.
[0057] In a third aspect, an embodiment of the present application provides an electronic device, including:
[0058] one or more processors;
[0059] A storage device having one or more programs stored thereon, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement a chip binning method;
[0060] One or more I / O interfaces are connected between the processor and the memory and are configured to implement information interaction between the processor and the memory.
[0061] In a fourth aspect, an embodiment of the present application provides a storage medium on which a computer program is stored, and when the program is executed by a processor, a chip binning method provided according to an embodiment of the present application is implemented.
[0062] The chip binning method provided in the embodiment of the present application performs a marking process on the test signal of a single module to obtain a result marking signal of the test signal. Since the result marking signal is used to identify whether the single module has a fault, and each single module has a corresponding result marking signal, when testing the chip, it is only necessary to determine the test result of the chip to be tested based on the result marking signal of the test signal of multiple single modules, and no longer directly based on the test signal, which reduces the difficulty of analysis, thereby reducing the difficulty of binning and improving the efficiency of binning; and, since the chip test is only based on the result marking signal of a single module, even if the binning scheme and / or the test vector change, the result marking signal is not affected, and does not affect the efficiency of binning. In addition, since each single module has a corresponding result marking signal, the test result of a single module can be quickly identified from many modules including mirror modules. BRIEF DESCRIPTION OF THE DRAWINGS
[0063] Figure 1 A flowchart of a chip binning method provided in an embodiment of the present application;
[0064] Figure 2 A schematic diagram of a chip binning device is also provided for the embodiment of the present application;
[0065] Figure 3 A schematic diagram of the principle of automatic identification and shielding of a memory built-in self-test (MBIST) provided in an embodiment of the present application;
[0066] Figure 4 This is a schematic diagram of the principle of performing Mask logic on a test signal in an embodiment of the present application;
[0067] Figure 5 This is a schematic diagram of the structure of the scanning unit in the embodiment of the present application;
[0068] Figure 6 A circuit diagram of a scanning unit and a shielding module provided in an embodiment of the present application;
[0069] Figure 7 A schematic diagram of the structure of a feature compression subunit provided in an embodiment of the present application;
[0070] Figure 8 A schematic diagram of the structure of a data transfer network provided in an embodiment of the present application;
[0071] Fig. 9 This is a schematic diagram of the DFY control module writing and reading compressed information in efuse in an embodiment of the present application;
[0072] Fig.10 A schematic structural diagram of an electronic device is provided for an embodiment of the present application. DETAILED DESCRIPTION
[0073] In order to enable those skilled in the art to better understand the technical solution of the present application, the server provided by the present application is described in detail below in conjunction with the accompanying drawings.
[0074] Example embodiments will be described more fully below with reference to the accompanying drawings, but the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, the purpose of providing these embodiments is to make this application thorough and complete and to enable those skilled in the art to fully understand the scope of this application.
[0075] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.
[0076] The terms used herein are only used to describe specific embodiments and are not intended to limit the present application. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof is not excluded.
[0077] The embodiments described herein may be described with reference to plan views and / or cross-sectional views by means of idealized schematic diagrams of the present application. Therefore, the example illustrations may be modified according to manufacturing techniques and / or tolerances. Therefore, the embodiments are not limited to the embodiments shown in the drawings, but include modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings have schematic properties, and the shapes of the regions shown in the drawings illustrate the specific shapes of the regions of the elements, but are not intended to be limiting.
[0078] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this application, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined herein.
[0079] The chips produced on the wafer are often not perfect and need to be classified according to indicators such as functional modules, stable clock frequency and required voltage. The binned chips can be used in different usage scenarios, making the best use of each chip and thus improving the overall yield of the chip.
[0080] Currently, a wafer can be divided into several to hundreds of different "bins". Traditional binning technology relies on manual observation on the output side, that is, the ATE machine needs to rely on separately constructed functional module test vectors or separately output functional module test vectors, and use test software to perform a huge amount of analysis work to bin the chip. However, with the gradual increase in chip size and complexity and the exponential growth of chip test vectors, traditional binning technology faces the following disadvantages:
[0081] 1) The huge number of test vectors and the complexity of binning scenarios place extremely high demands on the analysis software of ATE machines.
[0082] 2) For many modules including mirror modules, traditional binning technology cannot quickly identify and locate faulty modules, which greatly affects the binning efficiency.
[0083] 3) When faced with highly complex chips, the design phase often goes through multiple iterations, and test vectors and binning schemes need to change frequently. Traditional binning technology needs to be updated multiple times to adapt to changes in chip iterations, which increases the difficulty of binning and reduces the efficiency of binning.
[0084] Therefore, how to reduce the difficulty of binning and improve the efficiency of binning has become one of the technologies that needs to be solved urgently.
[0085] The present application embodiment provides a chip binning method. Figure 1 A flowchart of a chip binning method provided in an embodiment of the present application. Figure 1 As shown, the chip binning method includes:
[0086] Step S101, obtaining test signals of multiple single modules in the chip to be tested.
[0087] The test signal is the structural data signal inside the chip under test when the test vector is input into the chip under test. The test vector is the data vector used to test the chip.
[0088] Step S102, marking processing is performed on the test signal of the single module to obtain a result marking signal of the test signal.
[0089] The result mark signal is used to identify whether a single module has a fault. The test signal of each single module can be marked to obtain a corresponding result mark signal.
[0090] It should be noted that a single module can also be called a single-function module. Multiple single modules are arranged in the chip, and the functions of these single modules can be the same or different.
[0091] Step S103 , determining the test result of the chip to be tested based on the result marking signals of the test signals of the multiple single modules.
[0092] Step S104: classify the chips based on the test results to obtain classification results.
[0093] The chip binning method provided in the embodiment of the present application performs a marking process on the test signal of a single module to obtain a result marking signal of the test signal. Since the result marking signal is used to identify whether the single module has a fault, and each single module has a corresponding result marking signal, when testing the chip, it is only necessary to determine the test result of the chip to be tested based on the result marking signal of the test signal of multiple single modules, and no longer directly based on the test signal, which reduces the difficulty of analysis, thereby reducing the difficulty of binning and improving the efficiency of binning; and, since the chip test is only based on the result marking signal of a single module, even if the binning scheme and / or the test vector change, the result marking signal is not affected, and the efficiency of binning is not affected. In addition, since each single module has a corresponding result marking signal, many modules including mirror modules can be quickly distinguished, and the positioning of the modules can be quickly realized.
[0094] In some embodiments, step S103, before determining the test result of the chip to be tested based on the result marking signals of the test signals of multiple single modules, further includes: shielding the test signal of the single module marked as faulty, and then retesting the chip to be tested.
[0095] In some embodiments, the test signal is masked by masking the logic selection test signal to achieve the purpose of masking the test signal of the single module with faults. After the faulty test signal is masked, the test vector is input into the chip and retested through steps S101-S104 until the test signals of the single modules that are not masked are all fault-free.
[0096] In some embodiments, the test signal of a single module includes a memory built-in self-test MBIST signal and a scan test signal. The embodiment of the present application can mark the MBIST test signal and the scan test signal respectively to obtain a corresponding result mark signal.
[0097] In some embodiments, the MBIST test signal includes a ready status bit signal (ready_sms) and a fail status bit signal (sms_fail).
[0098] When the test signal of the single module is an MBIST test signal, step S102, marking the test signal of the single module to obtain a result marking signal of the test signal, including: inverting the ready state bit signal to obtain a ready state bit inverted signal; and obtaining the result marking signal of the test signal based on the ready state bit inverted signal and the failure state bit signal.
[0099] For example, the ready_sms signal is inverted to obtain the inverted signal of ready_sms, and then the inverted signal of ready_sms is ORed with the sms_fail signal to obtain a result marking signal of the test signal.
[0100] When the ready state bit signal ready_sms is 1, the sms_fail signal is 0, and the result mark signal is 0, it indicates that the MBIST test signal has no fault. The result mark signals of other cases are all 1, indicating that the MBIST test signal has a fault, as shown in Table 1.
[0101] Table 1 is the relationship between ready_sms, fail_sms and BIST test results
[0102]
[0103] When the test signal of a single module is a scanning test signal, step S102, the test signal of the single module is marked to obtain a result marking signal of the test signal, including: compressing the scanning test signal of the single module to obtain a test compression feature vector; and obtaining a result marking signal of the test signal based on comparison between the test compression feature vector and a preset ideal feature vector.
[0104] In some embodiments, the scan test signal of a single module includes n groups of scan test vectors, each group of scan test vectors includes k cycles, wherein n and k are integers and are greater than or equal to 1.
[0105] For the i-th cycle, compression processing is performed based on the i-th group of scan test signals, the i-1-th group of test compression feature vectors and feedback coefficients to obtain the i-th group of test compression feature vectors;
[0106] For the (i+1)th cycle, based on the (i+1)th group of scanned test vectors, the (i)th group of test compressed feature vectors and the feedback coefficients, the (i+1)th group of test compressed feature vectors is obtained.
[0107] Specifically, each set of scan test vectors can be represented by a vector matrix D:
[0108] D=[D 0 D 1 … D i … D k-1 ]
[0109] in,
[0110] For the i-th cycle, the i-th group of scan test vectors D i After compression, the i-th group of test compressed feature vectors Y are obtained. i .
[0111]
[0112] For the i+1th cycle, the i+1th group of test compressed feature vectors Y i+1The feature vector Y can be compressed by the i-th group test i and the i+1th group of scan test vectors D i+1 get:
[0113] Y i+1 =MISR(Y i ,D i+1 )
[0114] g n is the MISR feedback coefficient. Each feedback coefficient corresponds to the connection relationship between the register and the XOR gate. The feedback coefficient determines the difference in the algorithm for generating the eigenvalue.
[0115] The MISR principle is expressed in vector matrix form as follows:
[0116]
[0117] Among them, Y i+1 represents the i+1th group of test compressed feature vectors, Y i represents the i-th group of test compressed feature vectors, d i represents the i-th scan test vector, g i Represents the feedback coefficient corresponding to the i-th scan test vector.
[0118] The above compression process is an effective feature compression processing mode, through which the test compressed feature vector is processed into a group of feature vectors.
[0119] In some embodiments, obtaining a result marking signal of the test signal based on comparing the test compressed feature vector with a preset ideal feature vector includes: obtaining a vector comparison result based on comparing the test compressed feature vector with a preset ideal feature vector; and obtaining a result marking signal of the test signal based on the vector comparison result.
[0120] The ideal eigenvector refers to the eigenvector of the correct circuit output. Before binning, the ideal eigenvector of the correct circuit output can be known in advance.
[0121] In some embodiments, the test compressed feature vector, the ideal feature vector and the vector comparison result have the same number of bits, for example, 8 bits.
[0122] Based on the comparison between the test compressed feature vector and the preset ideal feature vector, a vector comparison result is obtained, including: comparing the eigenvalues on the same bit in the test compressed feature vector and the ideal feature vector to obtain a bit comparison result; when the eigenvalues are different, the bit comparison result is a first preset value; when the eigenvalues are the same, the bit comparison result is a second preset value; based on the bit comparison results of multiple bits, the vector comparison result is determined.
[0123] This embodiment does not limit the first preset value and the second preset value. For example, the first preset value is "1" and the second preset value is "0". When the characteristic values are different, the bit comparison result is 1, and when the characteristic values are the same, the bit comparison result is 0.
[0124] When the number of bits is 8, the vector comparison result includes 8 bit comparison results.
[0125] In some embodiments, a result marking signal of a test signal is obtained based on a vector comparison result, including: in the vector comparison result, if there is a bit comparison result that is a first preset value, then the result marking signal of the test signal is a faulty signal; in the vector comparison result, if all bit comparison results are a second preset value, then the result marking signal of the test signal is a non-faulty signal.
[0126] In an embodiment of the present application, the test signal is marked according to the comparison result of each bit in the vector comparison result. When there is a bit comparison result of "1" in the vector comparison result, that is, as long as there is a bit comparison result of "1" in the vector comparison result, the result marking signal of the test signal is a faulty signal; if all bit comparison results are "0", the result marking signal of the test signal is a non-faulty signal.
[0127] In some embodiments, the scanning test signal of a single module is compressed and processed, and before obtaining the test compression feature vector, it also includes: processing the scan test vector with unknown circuit state values, removing or shielding the unknown state of the circuit to be tested, and ensuring that the test vector has no uncertain state values.
[0128] In the actual binning process, the unknown value (X state) of the circuit in the chip is the main factor affecting the correctness of feature compression. Generally speaking, the X state comes from the uninitialized memory unit, non-scan trigger, undriven input, analog-to-digital conversion error behavior and clock domain crossing in the circuit. In the test vector generation process, multi-cycle paths will also bring certain X-state pollution (X-pollution) problems. Ultimately, the X state will destroy the compression features accumulated in multiple test cycles, which will cause the correctness of feature compression to decrease or even fail. Therefore, in the test vector generation process, it is necessary to solve the X-state problem through technologies such as X-state removal (X-clean) and X-state constraint (X-bounding), so as to obtain a higher quality test signal. This embodiment does not limit the circuit unknown value processing technology, for example, X-state removal (X-clean) and X-state constraint (X-bounding) technology.
[0129] In some embodiments, after obtaining the result mark signal of the test signal, the method further includes: transferring, storing and downloading the result mark signal of the test signal to the yield design one-time programmable memory through a data transfer network.
[0130] The result mark signal of the test signal is stored in the yield design one-time programmable memory (DFY_efuse). When necessary, it can be compared through the comparison enable signal (comp_en signal). When the comp_en signal is pulled high, the comparison result is output.
[0131] In some embodiments, step S104, classifying the chips based on the test results to obtain the classification results, includes: classifying the chips based on the functions of the single modules corresponding to the result marking signals without faults in the test results to obtain the classification results.
[0132] The chip includes multiple single modules with different functions, which can be classified based on the functions of the single modules. For example, single modules with a first function and no faults are classified into the first category, and single modules with a second function and no faults are classified into the second category. The result marking signal can be used to determine which single modules are fault-free and which are faulty. The chip can be classified by combining the fault-free single modules and the result marking signal.
[0133] The embodiment of the present application also provides a chip binning device. Figure 2 A schematic diagram of a chip binning device is also provided for the embodiment of the present application. Figure 2 As shown, the chip binning device 20 includes:
[0134] The acquisition module 21 is used to acquire test signals of multiple single modules in the chip to be tested.
[0135] The test signal is the structural data signal inside the chip under test when the test vector is input into the chip under test. The test vector is the data vector used to test the chip.
[0136] The marking module 22 is used to perform marking processing on the test signal of a single module to obtain a result marking signal of the test signal.
[0137] The result mark signal is used to identify whether a single module has a fault. The test signal of each single module can be marked to obtain a corresponding result mark signal.
[0138] The determination module 23 is used to determine the test result of the chip to be tested based on the result marking signals of the test signals of the multiple single modules.
[0139] The classification module 24 is used to classify the chips based on the test results to obtain classification results.
[0140] In some embodiments, the classification module is used to classify the chips based on the functions of the single modules corresponding to the result marking signals without faults in the test results to obtain classification results.
[0141] The chip binning device provided by the embodiment of the present application, the acquisition module acquires the test signals of multiple single modules in the chip to be tested, the marking module performs marking processing on the test signals of the single modules, and obtains the result marking signal of the test signal. Since the result marking signal is used to identify whether the single module has a fault signal, and each single module has a corresponding result marking signal, when the chip is tested, the determination module only needs to determine the test result of the chip to be tested based on the result marking signal of the test signals of multiple single modules, and the classification module classifies the chip based on the test result to obtain the classification result, and no longer directly based on the test signal, which reduces the difficulty of analysis, thereby reducing the difficulty of binning and improving the efficiency of binning; and, since the chip test is only based on the result marking signal of the single module, even if the binning scheme and / or the test vector change, the result marking signal is not affected, and the efficiency of binning is not affected. In addition, since each single module has a corresponding result marking signal, even if there are many modules including mirror modules, the single modules can be distinguished, the single module test results can be quickly identified, and the module positioning can be achieved.
[0142] In some embodiments, the chip binning device further includes: a shielding module, which is used to shield the test signal of the single module marked as faulty, that is, to shield the test signal of the single module with fault for retesting.
[0143] Figure 3 A schematic diagram of the principle of automatic identification and shielding of a memory built-in self-test (MBIST) provided in an embodiment of the present application. Figure 3 As shown, a plurality of single modules 20, an acquisition module 21, a marking module 22, a module controller 26, and a shielding module 25 are provided in the chip, and each single module 20 corresponds to an acquisition module 21, a marking module 22, a shielding module 25, and a module controller 26, wherein the acquisition module 21 may be an MBIST unit, which is used to obtain the test signal of the single module 21. A marking module 22 is also provided in the chip, and each memory 21 corresponds to a marking module 22, and the marking module 22 is used to mark the test signal to obtain a result marking signal. The module controller 26 is used to control the path of the marking module 22 and the shielding module 25, and control the flow direction of data.
[0144] In some embodiments, the acquisition module includes an MBIST unit, and the logic of the marking module 22 is to perform marking processing on the test signal output by the MBIST unit to obtain a result marking signal.
[0145] In some embodiments, the test signal output by the MBIST unit includes a ready state bit signal (ready_sms) and a failure state bit signal (sms_fail), and the marking module 22 performs an inversion process on the ready state bit signal to obtain the ready state bit inversion signal; and, performs an OR process on the ready state bit inversion signal and the failure state bit signal to obtain a result marking signal of the test signal.
[0146] Specifically, the ready_sms signal is inverted to obtain the inverted signal of ready_sms, and then the inverted signal of ready_sms is ORed with the sms_fail signal to obtain a result mark signal of the test signal.
[0147] The marking module 22 sends the result marking signal to the shielding module 25, and the shielding module 25 shields the test signal based on the result marking signal to shield the test signal of the faulty single module to prevent the faulty single module from outputting a signal.
[0148] Specifically, the shielding module 25 inverts the result mark signal and then ANDs it with the memory built-in self-test (MBIST) signal. If the single module has no fault, the result mark signal is 0, and the test signal of the single module will not be shielded, that is, the MBIST test signal will not be changed; if the single module has a fault, the result mark signal is 1, then the test signal of the single module is shielded, and the test signal of the single module is always set to 0.
[0149] Figure 4 The schematic diagram of the principle of performing mask logic on the test signal in the embodiment of the present application. In some embodiments, the test signal can be a key output signal of a single module, such as bira_mode_r, current_error, current_error_int and clr_err_reg signals. For example, the bira_mode_r signal is ANDed with the negated signal of the result mark signal (it does not mean that these signals are fault-free). If the result mark signal is 0, the bira_mode_r signal will not be masked, that is, the output of the bira_mode_r signal will not be changed; if the result mark signal is 1, the bira_mode_r signal is masked, and the bira_mode_r signal is always set to zero.
[0150] In some embodiments, after obtaining the result mark signal, the result mark signal can also be stored in the yield design one-time programmable memory (DFY_efuse module) 27. When the shielding module 25 needs to obtain the result mark signal of the test signal of a single module, it can be obtained from the DFY_efuse module 27.
[0151] In some embodiments, the chip further includes a controller 28 and a central processing unit 29. The controller 28 is used to control the single module 20, the acquisition module 21, the marking module 22, and the module controller 26. The central processing unit 29 is used to process some data in the chip.
[0152] In some embodiments, the acquisition module includes a scanning unit. Figure 5 Schematic diagram of the structure of the scanning unit of the present application embodiment. Figure 5 As shown, the scanning unit includes:
[0153] The test response subunit 51 is used to obtain a scan test signal.
[0154] The test response subunit 51 responds to the test signal sent by the control circuit 54 to obtain a scan test signal. The scan test signal is to input the test vector edt-in into the circuit under test 56 through the test stimulus module 55. When the circuit under test 56 runs the test vector edt-in, the test response subunit 51 obtains the scan test signal edt-out from the circuit under test 56.
[0155] The feature compression subunit 52 is used to compress the scan test signal to obtain a test compression feature vector.
[0156] The processing method of the feature compression subunit 52 for compressing the scan test signal is the same as the compression processing method in the chip binning method, which will not be repeated here.
[0157] In some embodiments, the test compressed feature vector may be stored in the DFY_efuse module 57 .
[0158] The comparison circuit subunit 53 is used to compare the test compression feature vector with the preset ideal feature vector to obtain a result mark signal of the test signal.
[0159] The ideal feature vector is stored in a storage module, such as the DFY_efuse module 57. The result flag signal includes no fault (PASS) and fault (FAIL).
[0160] Figure 6 A circuit diagram of a scanning unit and a shielding module provided in an embodiment of the present application. Figure 6 As shown, the scan test signal dcc_dft_edt_out output by the test response module is input into the feature compression subunit 51 beat by beat for feature compression, wherein the feature compression subunit 51 can be a multi-input feature register (MISR), and the feature compression subunit 51 calculates the test compression feature vector sig_out, and the test compression feature vector sig_out is transmitted to the comparison circuit subunit 53.
[0161] In some embodiments, the scanning unit further includes: a link subunit 58 , which is disposed between the feature compression subunit 52 and the comparison circuit subunit 53 and is used to transmit the test compression feature vector to the comparison circuit subunit 53 .
[0162] like Figure 6 As shown, the link subunit 58 inputs the test compression feature vector sig_out into the first input terminal of the XOR in the comparison circuit subunit 53, and the ideal feature vector Golden_sig is input into the second input terminal of the XOR via the link subunit 58. The test compression feature vector sig_out and the ideal feature vector Golden_sig are compared at the bit level (exclusive OR processing) via XOR, and OR processing is performed on the input to output the bit comparison result.
[0163] When the test compressed feature vector sig_out is compared with the ideal feature vector Golden_sig, if the feature values of the bits are the same, "0" is output, that is, a PASS signal is output; if the feature values of the bits are different, "1" is output, that is, a FAIL signal is output.
[0164] When the number of bits of the test compressed feature vector sig_out and the ideal feature vector Golden_sig is 8 bits, the number of bits of the bit comparison result is also 8 bits.
[0165] In the embodiment of the present application, a comparison enable (comp_en) signal may be input into the comparison circuit subunit 53 through the link subunit 58. The comp_en signal may be used as a switch signal to control the output of the result mark signal, that is, to control the output of the bit comparison result.
[0166] It should be noted that the result mark signal output by the comparison circuit sub-unit 53 can also be shielded by the selection signal.
[0167] In some embodiments, the scanning unit further includes an EDT module 59 for implementing EDT compression logic.
[0168] In some embodiments, the scan test signal includes n groups of scan test vectors, each group of scan test vectors includes k cycles, where n and k are integers and are greater than or equal to 1. Therefore, the feature compression subunit 52 includes a plurality of linear feedback shift registers, and the plurality of linear feedback shift registers are sequentially signal-connected.
[0169] Figure 7 This is a schematic diagram of the structure of the feature compression subunit provided in the embodiment of the present application. Figure 7 As shown, the feature compression subunit includes a plurality of registers DFF 0 、DFF 1 、DFF2 , ...DFF n-1 The characteristic value output by the characteristic register is the state of the register. The characteristic value output by the characteristic register is not only related to the current state, but also related to the characteristic value of the real-time input.
[0170] As before, for the i-th cycle, the i-th set of test compressed feature vectors Y i It is expressed as:
[0171]
[0172] For the i+1th cycle, the i+1th group of test compressed feature vectors Y i+1 The feature vector Y can be compressed by the i-th group test i and the i+1th group of scan test vectors D i+1 get:
[0173] Y i+1 =MISR(Y i ,D i+1 )
[0174] g n is the MISR feedback coefficient. Each feedback coefficient corresponds to the connection relationship between the register and the XOR gate. The feedback coefficient determines the difference in the algorithm for generating the eigenvalue.
[0175] In some embodiments, the apparatus further comprises a data transfer network, the data transfer network comprising:
[0176] The control (sub_tap) module is used to transfer the input and output test signals; the yield improvement module (DFY_sub_tap), the control (sub_tap) module and the yield improvement module (DFY_sub_tap) jointly realize the transfer of the test mark signal.
[0177] Figure 8 This is a schematic diagram of the structure of the data transfer network provided in the embodiment of the present application. Figure 8 As shown, the test result of the chip to be tested is written into the DFY_efuse module through the gating module.
[0178] Specifically, the main control module 81 simultaneously turns on the enable signal tap_en of the control module 82 and the DFY control module 83 through dedicate_dr_chain, and configures the yield mode (DFY_mode) to 01, and configures mux_1, mux_2 and mux_3 to 1, thereby realizing the upper and lower cascade relationship between the control module 82 and the DFY control module 83, thereby forming a loop from the main control module 81 to the control module 82, and then to the DFY_efuse_tap module 83.
[0179] Table 2 shows the corresponding relationship between DFY_mode and mux, where mux indicates the gating of the link.
[0180] Table 2
[0181] DFY_mode mux_1 mux_2 mux_3 01 1 1 1 10 0 0 0
[0182] Fig. 9 Schematic diagram of the DFY control module writing and reading compressed information in efuse in the embodiment of the present application. Fig. 9 As shown, the control module 91 includes a yield_up_DR_chain module 911 , and the DFY control module 92 includes a DFY_efuse module 921 , an ef_ctrl_DR_chain 922 , an ef_w_DR_chain 923 , and an ef_r_DR_chain 924 .
[0183] The data register chain (DR_chain, i.e. ef_w_DR_chain) of the yield_up_DR_chain module 911 and the DFY_efuse module 921 is selected through JTAG_IRLOAD. The obs_pi data in the yield_up_DR_chain module can be shifted to the ef_w_DR_chain 923 of the DFY_efuse module. At the same time, the ef_w_DR_chain 923 is connected to the corresponding write bit of DFY_efuse. After enabling the ef_ctrl_DR_chain in the DFY_efuse module, the ef_atuo_mode automatic data write mode is turned on to burn the ef_w_DR_chain data into the DFY_efuse module 921.
[0184] Figure 8 The main control module 81 turns on the tap_en enable signal of the control module and the DFY control module at the same time through dedicate_dr_chain (sub_tap select_DR), configures DFY_mode to 10, and configures mux_1, mux_2 and mux_3 to 0, thereby realizing the upper and lower cascade relationship between the DFY control module 83 and the control module 82, forming a loop from the main control module 81 to the DFY_efuse_tap module 83 and then to the control module 82.
[0185] like Fig. 9As shown, the read data register chain DR_chain (ef_r_DR_chain) and yield_up_DR_chain module 911 in DFY_efuse921 are selected by JTAG_IRLOAD; the corresponding read bit of the DFY_efuse module is connected to the ef_r_DR_chain, so that the obs_pi data of the ef_r_DR_chain can be transferred to the yield_up_DR_chain module 911. At the same time, the ef_ctrl_DR_chain in the DFY_efuse module is configured, and the ef_atuo_mode is enabled to enter the read mode, so that data can be read from the DFY_efuse module 921.
[0186] It should be noted that in the chip binning method and device provided in the embodiments of the present application, data is transmitted inside the chip during the identification, storage, downloading and retesting processes, and no auxiliary information processing outside the chip is required. It is a closed-loop process. Therefore, in addition to reducing the difficulty of binning and improving the efficiency of binning, it is also highly automated, fast and efficient.
[0187] Thirdly, refer to Fig.10 , an embodiment of the present application provides an electronic device, comprising:
[0188] One or more processors 1001;
[0189] A memory 1002, on which one or more programs are stored. When the one or more programs are executed by one or more processors, the one or more processors implement any one of the above chip binning methods;
[0190] One or more I / O interfaces 1003 are connected between the processor and the memory and are configured to implement information exchange between the processor and the memory.
[0191] Among them, the processor 1001 is a device with data processing capabilities, including but not limited to a central processing unit (CPU); the memory 1002 is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH); the I / O interface (read-write interface) 1003 is connected between the processor 1001 and the memory 1002, and can realize information interaction between the processor 1001 and the memory 1002, including but not limited to a data bus (Bus), etc.
[0192] In some embodiments, the processor 1001 , the memory 1002 , and the I / O interface 1003 are connected to each other through a bus, and further connected to other components of the computing device.
[0193] In a fourth aspect, an embodiment of the present application provides a computer-readable medium having a computer program stored thereon, which implements any of the above-mentioned chip binning methods when the program is executed by a processor.
[0194] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods applied for above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.
[0195] Example embodiments have been claimed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly noted, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present application as set forth in the appended claims.
Claims
1. A chip binning method, characterized in that: include: Obtain test signals of multiple single modules in the chip under test; Marking the test signal of the single module to obtain a result marking signal of the test signal; the result marking signal is used to identify whether the single module has a fault; Determining a test result of the chip to be tested based on result marking signals of the test signals of the multiple single modules; The chip is classified based on the test result to obtain a classification result.
2. The method according to claim 1, characterized in that Before determining the test result of the chip to be tested based on the result mark signal of the test signals of the multiple single modules, the method further includes: The test signal of the single module marked as faulty is shielded, and then the chip to be tested is retested.
3. The method according to claim 1 or 2, characterized in that: Described test signal comprises memory built-in self test MBIST signal, and described MBIST test signal comprises ready state bit signal and failure state bit signal; The step of performing marking processing on the test signal of the single module to obtain a result marking signal of the test signal includes: Performing an inversion process on the ready state bit signal to obtain an inverted ready state bit signal; A result mark signal of the test signal is obtained based on the ready state bit negation signal and the fail state bit signal.
4. The method according to claim 1 or 2, characterized in that: The test signal includes a scanning test signal; The step of performing marking processing on the test signal of the single module to obtain a result marking signal of the test signal includes: Performing compression processing on the scanning test signal of the single module to obtain a test compression feature vector; Based on the comparison between the test compression feature vector and a preset ideal feature vector, a result marking signal of the test signal is obtained.
5. The method according to claim 4, characterized in that The scan test signal of the single module includes n groups of scan test vectors, each group of the scan test vectors includes k cycles, wherein: n and k are integers greater than or equal to 1; For the i-th cycle, compression processing is performed based on the i-th group of scan test signals, the i-1-th group of test compression feature vectors and feedback coefficients to obtain the i-th group of test compression feature vectors.
6. The method according to claim 5, characterized in that The step of obtaining a result marking signal of the test signal based on comparing the test compression feature vector with a preset ideal feature vector includes: Comparing the test compressed feature vector with a preset ideal feature vector to obtain a vector comparison result; A result flag signal of the test signal is obtained based on the vector comparison result.
7. The method according to claim 6, characterized in that The test compressed feature vector, the ideal feature vector and the vector comparison result have the same number of bits; The step of comparing the test compression feature vector with a preset ideal feature vector to obtain a vector comparison result includes: Comparing the eigenvalues at the same bit position in the test compressed eigenvector and the ideal eigenvector to obtain a bit position comparison result; When the characteristic values are different, the bit comparison result is a first preset value; When the characteristic values are the same, the bit comparison result is a second preset value; The vector comparison result is determined based on the bit comparison results of the plurality of bits.
8. The method according to claim 7, characterized in that The step of obtaining a result marking signal of the test signal based on the vector comparison result comprises: In the vector comparison results, if there is a bit comparison result that is the first preset value, then the result mark signal of the test signal is a fault signal; In the vector comparison result, if all the bit comparison results are the second preset value, the result mark signal of the test signal is a fault-free signal.
9. The method according to claim 5, characterized in that Before compressing the scan test signal of the single module to obtain the test compression feature vector, the method further includes: The scan test vector is processed with a circuit unknown state value to remove or mask the unknown state of the circuit to be tested.
10. The method according to claim 1, characterized in that After obtaining the result mark signal of the test signal, the method further includes: The result marking signal of the test signal is transferred, stored and downloaded via a data transfer network.
11. The method according to claim 10, characterized in that The step of classifying the chip based on the test result to obtain a classification result includes: The chip is classified based on the function of the single module corresponding to the result marking signal without fault in the test result to obtain the classification result.
12. A chip binning device, characterized in that: include: An acquisition module is used to acquire test signals of multiple single modules in the chip to be tested; A marking module, used for marking the test signal of the single module to obtain a result marking signal of the test signal; the result marking signal is used to identify whether the single module test is fault-free; A determination module, configured to determine a test result of the chip to be tested based on result marking signals of the test signals of the multiple single modules; The classification module is used to classify the chip based on the test result to obtain a classification result.
13. The device according to claim 12, characterized in that The device also includes: The shielding module is used to shield the test signal of a single module marked as having a fault.
14. The device according to claim 12 or 13, characterized in that The acquisition module comprises an MBIST unit, and the test signal output by the MBIST unit comprises a ready state bit signal and a failure state bit signal; The marking module is used to perform an inversion process on the ready state bit signal to obtain an inverted ready state bit signal; And, the preparation state bit negation signal and the failure state bit signal are ORed together to obtain a result mark signal of the test signal.
15. The device according to claim 12 or 13, characterized in that The acquisition module includes a scanning unit, and the scanning unit includes: A test response subunit, used for obtaining a scanning test signal; A feature compression subunit, used for compressing the scan test signal to obtain a test compression feature vector; The comparison circuit subunit is used to compare the test compression feature vector with a preset ideal feature vector to obtain a result marking signal of the test signal.
16. The device according to claim 15, characterized in that The scanning unit also includes: A link subunit is provided between the feature compression subunit and the comparison circuit subunit, and is used for transmitting the test compression feature vector to the comparison circuit subunit.
17. The device according to claim 15, characterized in that The feature compression subunit includes a plurality of linear feedback shift registers, and the plurality of linear feedback shift registers are signal-connected in sequence.
18. The device according to claim 12, characterized in that The classification module is used to classify the chip based on the function of the single module corresponding to the result marking signal without fault in the test result to obtain the classification result.
19. An electronic device, characterized in that: include: one or more processors; A storage device having one or more programs stored thereon, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 1 to 11; One or more I / O interfaces are connected between the processor and the memory and are configured to implement information interaction between the processor and the memory.
20. A computer readable medium having a computer program stored thereon, wherein the program, when executed by a processor, implements the method according to any one of claims 1 to 11.