Flash memory optimization design method, chip, electronic device and storage medium
By configuring a charge pump circuit in the memory chip, the current supply multiple factor α is used to optimize the charge pump design, which solves the contradiction between charge pump capability and write operation efficiency, and realizes efficient write operation and low-power chip design.
Patent Information
- Application Number
- CN202411807495.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-10
- Publication Date
- 2025-04-04
AI Technical Summary
When designing a memory chip that adopts a thermal electron injection mechanism, there is a contradiction between the ability of the charge pump and the efficiency of the write operation. The higher the capacity of the charge pump, the higher the write operation efficiency, but the chip area increases. Conversely, the write operation efficiency is reduced, resulting in unusable in application scenarios that require write operation efficiency.
By simulating a binary data unit that randomly generates a preset number of bits, counts the number of 0 in each data unit, generates a series reference probability Pm, maps the preset write operation one-time completion probability PT into the series reference probability Pm, obtains the current supply multiple factor α, and configures the charge pump circuit based on the single memory cell write operation support current Is and supply multiple factor α.
On the premise of ensuring write operation efficiency, the chip area is reduced, the charge pump capacity is avoided, the chip cost and power consumption is reduced, and the power consumption and efficiency optimization of the memory circuit is achieved.
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Figure CN119761272A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of circuit design, and in particular to a flash memory optimization design method, a chip, an electronic device and a storage medium. Background Art
[0002] Existing memories are divided into volatile memories and non-volatile memories according to whether data is retained after power failure. Among non-volatile memories, the most common is flash memory, and the storage unit of flash memory is mainly a floating gate structure. According to the connection relationship of the storage unit, flash memory is divided into NOR flash memory and NAND flash memory.
[0003] The basic principle of flash memory for storing data is to change the number of carriers in the floating gate to change the threshold voltage of the storage unit. Storage units with different threshold voltages show data 0 (hereinafter, high threshold voltage is defined as data 0) or 1 (hereinafter, low threshold voltage is defined as data 1) when reading. The write operation of flash memory is to increase the threshold voltage of the storage unit by injecting electrons in the channel into the floating gate. A common write operation mechanism is through hot electron injection, which requires a large voltage difference between the drain and source ends of the storage unit to generate hot electron current, and injects hot electrons into the floating gate by applying a high voltage to the control gate end. The write operation of the hot electron injection mechanism requires not only the internal charge pump of the memory chip to provide a high voltage at the drain end, but also a large current, and the current is proportional to the amount of data written 0 at the same time.
[0004] Therefore, when designing a memory chip that uses a hot electron injection mechanism, the capacity of the charge pump and the efficiency of the write operation are in conflict. The greater the capacity of the charge pump, the more data that can be written as 0 at the same time, thereby improving the efficiency of the write operation, but the chip area will increase, and when there is less data that needs to be written as 0, the utilization rate of the charge pump will decrease. If the capacity of the charge pump is designed to be too small in order to reduce the chip area, too little data can be written as 0 at the same time, and the efficiency of the write operation is reduced, which will make the memory unusable in application scenarios that require write operation efficiency. Summary of the invention
[0005] In view of the deficiencies in the prior art, the present invention provides a flash memory optimization design method, chip, electronic device and storage medium, which effectively reduces the chip area and achieves optimization of power consumption and efficiency while effectively ensuring the efficiency of write operations.
[0006] The present invention solves the technical problem by adopting the following technical solution:
[0007] The present invention provides a flash memory optimization design method, the method comprising:
[0008] Simulate the random generation of a binary data unit with a preset number of bits;
[0009] Count the number of 0s in each data unit respectively;
[0010] Generate a series of reference probabilities P based on statistical results m , the reference probability P m is the probability of occurrence of data units containing no more than m zeros;
[0011] The probability P of completing the preset write operation at one time T Mapped to the series reference probability P m In the above, the current supply multiplication factor α is obtained and output;
[0012] The charge pump circuit is configured based on the single memory cell write operation support current Is and the supply multiplication factor α.
[0013] Preferably, the data unit is the maximum single-write data amount that is read once and sent to the storage unit.
[0014] Preferably, the preset bit number of the data unit includes one of 32 bits, 64 bits and 128 bits.
[0015] Preferably, the probability P of completing the preset write operation at one time is T Mapped to the series reference probability P m The current supply multiplier factor α is obtained and output as follows:
[0016] Let P m =P T , reverse deduction to get the value of m;
[0017] At this time, the value of m is the value of the current supply multiplication factor α.
[0018] Preferably, the single memory cell write operation support current Is includes a drain capacitance charging current of the single memory cell during a write operation and a write operation voltage application current.
[0019] Preferably, the configuration of the charge pump circuit based on the single storage unit write operation support current Is and the supply multiplication factor α specifically includes:
[0020] Generate the charge pump minimum output current Iout based on the single memory cell write operation support current Is and the supply multiplier factor α; substitute the minimum output current Iout into the formula
[0021]
[0022] The configuration parameter value of the boost capacitor C is obtained, where f is the clock flip frequency, V DD is the power supply voltage, N is the number of charge pump stages, C s is the parasitic capacitance, Vout is the output voltage.
[0023] Preferably, a programming language including Python is used to simulate the random generation of binary data units with a preset number of bits, wherein the number of generated data units is not less than 100,000.
[0024] The present invention also provides a chip, including a flash memory, wherein the flash memory is configured using the flash memory optimization design method as described above.
[0025] The present invention also provides an electronic device, comprising:
[0026] at least one processor; and
[0027] a memory communicatively connected to the at least one processor; wherein,
[0028] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the flash memory optimization design method as described above.
[0029] The present invention also provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable the computer to execute the flash memory optimization design method as described above.
[0030] Compared with the prior art, the present invention has the following beneficial effects:
[0031] The memory circuit designed by the flash memory optimization design method of the present invention can basically ensure that a write operation is fully completed, effectively improving the efficiency of the write operation. On this premise, it can also minimize the area of the charge pump, avoid wasting the charge pump capacity, reduce chip costs, and reduce power consumption at the same time, so that the memory circuit can achieve the optimal result of power consumption and efficiency.
[0032] Other outstanding essential features and significant improvements of the present invention compared to the prior art are further described in detail in the embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:
[0034] Figure 1 A schematic diagram of a specific source code for simulating random generation of a binary data unit with a preset number of bits in Example 1;
[0035] Figure 2 This is a probability distribution diagram of the number of 0s in the data unit (64 bits) of Example 1;
[0036] Figure 3 This is a diagram showing the cumulative ratio of the number of 0s in the data unit (64 bits) of Example 1. DETAILED DESCRIPTION
[0037] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0038] It should be noted that certain names are used in the specification and claims to refer to specific components. It should be understood that a person of ordinary skill in the art may use different names to refer to the same component. The specification and claims of this application do not use differences in names as a way to distinguish components, but use substantial differences in the functions of components as the criterion for distinguishing components. As used in the specification and claims of this application, "including" or "comprising" is an open term, which should be interpreted as "including but not limited to" or "including but not limited to". The embodiments described in the specific implementation section are preferred embodiments of the present invention and are not intended to limit the scope of the present invention.
[0039] In addition, it is known to those skilled in the art that various aspects of the present invention may be implemented as a system, method or computer program product. Therefore, various aspects of the present invention may be specifically implemented in the form of a combination of software and hardware, which may be collectively referred to herein as a "circuit", "module" or "system". In addition, in some embodiments, various aspects of the present invention may also be implemented in the form of a computer program product in one or more microcontroller-readable media, which contains program code readable by the microcontroller.
[0040] Example 1
[0041] This embodiment provides a flash memory optimization design method, the method comprising:
[0042] Simulate and randomly generate a binary data unit with a preset number of bits; in this embodiment, the data unit is the maximum single write data amount read and sent to the storage unit at one time, and the content of setting the data unit is specifically described here:
[0043] Since the write operation instruction of NOR flash memory is defined as page write instruction, that is, one instruction can write a page of data at most, and the page size is generally defined as 256 bytes. Various restrictions determine that a page of data cannot be written to the storage unit at the same time, such as:
[0044] Determine whether the circuit area for writing 0 is too large and whether there are too many wires between the circuit and the storage unit, and one bit of data requires one wire;
[0045] The current required by the charge pump is too large, resulting in an excessively large area; the chip write current is too large;
[0046] Therefore, in this embodiment, when executing a page write instruction, the data input from the port is first stored in a cache inside the chip, the cache size is consistent with the page size, and then read in batches into a circuit that determines whether to write 0 and sent to a storage unit.
[0047] In this embodiment, the preset bit number of the data unit includes one of 32 bits, 64 bits and 128 bits.
[0048] Continue to count the number of 0s in each data unit;
[0049] Generate a series of reference probabilities P based on statistical results m , the reference probability P m is the probability of occurrence of data units containing no more than m zeros;
[0050] The probability P of completing the preset write operation at one time T Mapped to the series reference probability P m In the embodiment, the current supply multiplication factor α is obtained and output, which is specifically:
[0051] Let P m =P T , reverse deduction is used to obtain the value of m; at this time, the value of m is the value of the current supply multiplication factor α;
[0052] Based on single memory cell write operation support current I s and the supply multiplication factor α configures the charge pump circuit. In this embodiment, the single memory cell write operation supports the current I s Including the drain capacitance charging current of a single storage unit during a write operation and the voltage application current of a write operation, which are specifically described as follows:
[0053] The number of data cells that need to undergo hot electron injection operations to change the storage cells from a low threshold voltage state to a high threshold voltage state is determined by the input data. In extreme cases, all data may need to undergo a write-0 operation, or only a very small number (such as 1 bit) may need to undergo a write-0 operation. When performing a write-0 operation, since the charge pump not only needs to charge the storage cell drain capacitance, but also needs to support the current brought by the application of the write-0 operation voltage to the storage cell, the number of storage cells that need to undergo a write-0 operation at one time depends on the number of storage cells that need to be supported by the current.
[0054] In this embodiment, based on a single memory cell write operation, the support current I s and supply multiplication factor α to configure the charge pump circuit, specifically including:
[0055] Based on single memory cell write operation support current I s and the supply multiplication factor α to generate the charge pump minimum output current I out ; Set the minimum output current I out Substitute into the formula
[0056]
[0057] The configuration parameter value of the boost capacitor C is obtained, where f is the clock flip frequency, V DD is the power supply voltage, N is the number of charge pump stages, C s is the parasitic capacitance, V out is the output voltage.
[0058] Generally, when the clock flip frequency, power supply voltage, charge pump stage number and output voltage are fixed values, the greater the output current capacity of the charge pump, the larger the internal boost capacitor required. The area of the charge pump is mainly determined by the boost capacitor, so the optimized charge pump area parameters are configured.
[0059] In order to further explain the specific optimization design method steps of this embodiment in detail, taking a data unit of 64 bits as an example, the Python programming language is used to generate 100,000 groups of 64-bit 0 / 1 random sequences. Of course, other programming languages can also be used, which will not be described in detail here:
[0060] Specific code such as Figure 1 As shown, the programming software simulates the random data units input by the user and counts the number of 0s in the random data units. Except for extreme special cases, the user's data can be regarded as a random 0 / 1 sequence. Therefore, a large number of 0 / 1 random sequences of the same size as the data unit are first generated, and then the number of 0s in each group of random sequences is counted.
[0061] The statistical results are as follows Figure 2 and Figure 3 As shown, Figure 2 The horizontal axis represents the number of 0s in the data unit, and the vertical axis represents the probability of the number of 0s shown on the horizontal axis appearing. Figure 3 The horizontal axis represents the number of 0s in the data unit, and the vertical axis represents the proportion of the data units whose number is less than the number of 0s shown on the horizontal axis to the total number of data units.
[0062] The charge pump capacity and write operation time under different maximum numbers of single write 0s are compared, where each parameter is normalized according to the value of the maximum number of write 0s being 64 (the size of the data unit), as shown in Table 1. Assuming that the gate voltage of each storage cell is 10V and the drain voltage is 5V when performing a write 0 operation, the current generated by the storage cell under this voltage condition is 100uA.
[0063]
[0064] Table 1
[0065] As shown in the table above, when the maximum number of single write 0s is 41, that is, the current supply multiplier factor α is 41, the charge pump is designed. At this time, the charge pump output capacity is 5V / 4.1mA, which is 35.94% less than when the maximum number of write 0s is 64 (5V / 6.4mA), and the average write operation time is only increased by 1.56%;
[0066] When the maximum number of single write zeros is 46, that is, the current supply multiplier factor α is 46, the charge pump capacity (5V / 4.6mA) is reduced by 28.125% compared to the maximum number of write zeros of 64 (5V / 6.4mA) without almost increasing the average time of the write operation (increase of 0.013%).
[0067] From the above data, it can be seen that the flash memory optimization design method provided in this embodiment has the following performance effects:
[0068] It can realize that data with a preset probability can be overwritten by a write-0 operation, improve the efficiency of the write operation, and ensure that the write operation meets the product parameter requirements;
[0069] The area of the charge pump can be constrained not to be too large, thereby avoiding waste of area, reducing chip cost, and reducing power consumption.
[0070] Example 2
[0071] This embodiment provides a chip including a flash memory, wherein the flash memory is configured using the flash memory optimization design method described in Embodiment 1.
[0072] Example 3
[0073] This embodiment provides an electronic device, including:
[0074] at least one processor; and
[0075] a memory communicatively connected to the at least one processor; wherein,
[0076] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the flash memory optimization design method described in Example 1.
[0077] Example 4
[0078] This embodiment provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable the computer to execute the flash memory optimization design method as described in Embodiment 1.
[0079] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.
[0080] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.
Claims
1. A flash memory optimization design method, characterized in that: The method comprises: Simulate the random generation of a binary data unit with a preset number of bits; Count the number of 0s in each data unit respectively; Generate a series of reference probabilities P based on statistical results m , the reference probability P m is the probability of occurrence of data units containing no more than m zeros; The probability P of completing the preset write operation at one time T Mapped to the series reference probability P m In the above, the current supply multiplication factor α is obtained and output; Based on single memory cell write operation support current I s and the supply multiplication factor α configures the charge pump circuit.
2. A flash memory optimization design method according to claim 1, characterized in that: The data unit is the maximum single-write data amount that is read once and sent to the storage unit.
3. A flash memory optimization design method according to claim 2, characterized in that: The preset number of bits of the data unit includes one of 32 bits, 64 bits and 128 bits.
4. The flash memory optimization design method according to claim 1, characterized in that: The probability P of completing the preset write operation at one time T Mapped to the series reference probability P m The current supply multiplier factor α is obtained and output as follows: Let P m =P T , reverse deduction to get the value of m; At this time, the value of m is the value of the current supply multiplication factor α.
5. A flash memory optimization design method according to claim 4, characterized in that: The single memory cell write operation supports current I s It includes the drain capacitance charging current of a single storage unit during a write operation and the voltage application current of the write operation.
6. A flash memory optimization design method according to claim 5, characterized in that: The single memory cell write operation supports current I s and supply multiplication factor α to configure the charge pump circuit, specifically including: Based on single memory cell write operation support current I s and the supply multiplication factor α to generate the charge pump minimum output current I out ; The minimum output current I out Substitute into the formula The configuration parameter value of the boost capacitor C is obtained, where f is the clock flip frequency, V DD is the power supply voltage, N is the number of charge pump stages, C s is the parasitic capacitance, V out is the output voltage.
7. A flash memory optimization design method according to claim 1, characterized in that: Programming languages including Python are used to simulate the random generation of binary data units with a preset number of bits, where the number of data units generated is no less than 100,000.
8. A chip, characterized in that: It comprises a flash memory, and the flash memory is configured by using the flash memory optimization design method according to any one of claims 1 to 7.
9. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the flash memory optimization design method according to any one of claims 1 to 7.
10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to enable the computer to execute the flash memory optimization design method according to any one of claims 1 to 7.