A gate-controlled field sequential circuit and method

Abstract

The application discloses a gate-controlled field sequential circuit and method, including M rows of sub-circuits, the sub-circuit includes a compensation unit, the compensation unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a pre-storage capacitor;The first source-drain electrode of the first transistor is coupled to the reference signal line, the second source-drate electrode of the first transistor is coupled to one end of the pre-storage capacitor and the first source-drain electrode of the third transistor, the first source-drain electrode of the second transistor is coupled to the data signal line;The gate of the third transistor is coupled to the second reset signal line, and the first source-drain electrode of the third transistor is also coupled to the gate of the fourth transistor, and the gate of the fifth transistor is coupled to the second reset signal line;The first source-drain electrode of the fourth transistor is coupled to the positive power supply line.The beneficial effects achieved by the application are: the threshold voltage is removed by utilizing the conduction characteristics of the transistor, so that the abnormal phenomenon of the picture caused by the threshold voltage drift is avoided.

Description

Technical Field

[0001] The present invention relates to the field of pixel display technology, and in particular to a field sequential circuit and method for gate control. Background Art

[0002] Field-sequential or color-sequential display driver technology exploits the residual effect of human visual pauses to directly mix the RGB light sources to achieve full-color display. This eliminates the need for color filters, improving light source utilization while reducing power consumption. The backlight can only be activated after all screen data has been written and the liquid crystal deflection has reached a stable state. Otherwise, the image will be distorted, requiring a significant amount of time for the liquid crystal deflection to complete before the backlight is activated. This makes it difficult to achieve high brightness and high-frequency display over an average timeframe, while also increasing backlight brightness specifications and lifespan requirements, driving up costs.

[0003] Due to the influence of transistor manufacturing processes, the threshold voltage of driver transistors at different spatial locations is likely to be different. For hydrogenated amorphous silicon, low-temperature polysilicon, and oxide transistors, the threshold voltage can also vary with operating conditions, a phenomenon known as threshold voltage drift. Because the potential ultimately written to the pixel electrode under gate control is related to the threshold voltage, variations or inconsistencies in the threshold voltage of the driver transistors can cause uneven display in LCDs.

[0004] Therefore, the present invention proposes a gate-controlled field sequential circuit and method to eliminate the influence of the threshold voltage, thereby avoiding the influence of abnormal image display. Summary of the Invention

[0005] The purpose of the present invention is to provide a gate-controlled field sequence circuit and method, which eliminates the influence of threshold voltage.

[0006] The object of the present invention is to realize a gate-controlled field sequential circuit through the following technical solution, comprising M rows of sub-circuits, wherein the sub-circuits include a compensation unit and a driving unit;

[0007] The compensation unit includes a first circuit structure;

[0008] The first circuit structure includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a pre-storage capacitor;

[0009] The gate of the first transistor of the sub-circuit in the Nth row is coupled to the reset signal line, the first source and drain of the first transistor are coupled to the reference signal line, the second source and drain of the first transistor are coupled to one end of the pre-storage capacitor and the first source and drain of the third transistor, the other end of the pre-storage capacitor is coupled to the second source and drain of the second transistor, the gate of the second transistor is coupled to the row gate signal line of the Nth row, and the first source and drain of the second transistor are coupled to the data signal line;

[0010] The gate of the third transistor is coupled to the second reset signal line, the first source and drain of the third transistor are also coupled to the gate of the fourth transistor, the second source and drain of the third transistor are coupled to the first source and drain of the fifth transistor, the gate of the fifth transistor is coupled to the second reset signal line, and the second source and drain of the fifth transistor are coupled to the second source and drain of the fourth transistor and the driving unit;

[0011] The gate of the fourth transistor is coupled to one end of the pre-storage capacitor, and the first source and drain of the fourth transistor are coupled to a positive power supply line.

[0012] Furthermore, the first circuit structure further includes: a sixth transistor and an eighth transistor;

[0013] The first source and drain of the fourth transistor are coupled to the driving unit and the first source and drain of the eighth transistor, the second source and drain of the eighth transistor are coupled to the common signal line, and the gate of the eighth transistor is coupled to the second reset signal line;

[0014] The first source and drain of the fifth transistor are coupled to the second source and drain of the sixth transistor. The first source and drain of the sixth transistor are coupled to a positive power supply line. The gate of the sixth transistor is coupled to a transfer signal line.

[0015] Furthermore, the first circuit structure may be replaced with a second circuit structure, wherein the second circuit structure includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a sixth transistor and a pre-storage capacitor;

[0016] The gate of the first transistor of the sub-circuit in the Nth row is coupled to the row gate signal line in the N-1th row, the first source and drain of the first transistor are coupled to the reference signal line, the second source and drain of the first transistor are coupled to one end of the pre-storage capacitor and the first source and drain of the third transistor, the gate of the third transistor is coupled to the row gate signal line in the Nth row, the second source and drain of the third transistor are coupled to the second source and drain of the fourth transistor; the gate of the fourth transistor is coupled to one end of the pre-storage capacitor, and the other end of the pre-storage capacitor is coupled to the positive power line;

[0017] The first source and drain of the fourth transistor are coupled to the first source and drain of the second transistor and the second source and drain of the sixth transistor;

[0018] The gate of the second transistor is coupled to the row gate signal line of the Nth row, and the second source and drain of the second transistor are coupled to the data signal line; the gate of the sixth transistor is coupled to the transfer signal line, and the first source and drain of the sixth transistor are coupled to the positive power supply line;

[0019] The second source and drain electrodes of the fourth transistor and the third transistor are both coupled to the driving unit.

[0020] Further, the driving unit includes a seventh transistor and a pixel electrode;

[0021] The gate of the seventh transistor is coupled to the transfer signal line, the first source and drain of the seventh transistor are coupled to the compensation unit (the second source and drain of the fourth transistor), the second source and drain of the seventh transistor are coupled to the pixel electrode, and the other end of the pixel electrode is coupled to the common signal line.

[0022] Further, the driving unit includes a seventh transistor and a pixel electrode;

[0023] The gate of the seventh transistor is coupled to the transfer signal line, the first source and drain of the seventh transistor are coupled to the second source and drain of the fourth transistor, the second source and drain of the seventh transistor are coupled to the pixel electrode, and the other end of the pixel electrode is coupled to the common signal line.

[0024] Furthermore, the driving unit further includes a storage capacitor, one end of the storage capacitor is coupled to the second source and drain of the seventh transistor, and the other end of the storage capacitor is coupled to the common signal line.

[0025] Furthermore, the field sequential circuit further includes a reset unit, the reset unit including a ninth transistor, a first source and a drain of the ninth transistor coupled to the driving unit, and a second source and a drain of the ninth transistor coupled to the second reference signal line.

[0026] The present invention also provides a gate-controlled field sequence circuit control method, comprising:

[0027] During the backlight-on phase of the sub-circuit in row N:

[0028] The row gate signal line of the Nth row jumps to a high level, and the second transistor is turned on;

[0029] The data signal line writes a data signal voltage to the pre-storage capacitor through the second transistor, and makes the potential of the second node the data signal voltage; the pre-storage capacitor has a threshold voltage written in the previous frame, and the pre-storage capacitor currently stores the sum of the data signal voltage and the threshold voltage;

[0030] The row gate signal line jumps to a normal level, which is a common level, the second transistor is turned off, the first node is maintained at a high potential by the pre-storage capacitor, and the fourth transistor is turned on;

[0031] During the backlight off phase of the sub-circuit in row N:

[0032] The transfer signal line jumps to a high potential, and the sixth transistor is turned on;

[0033] The positive power line jumps to a low potential, and the positive power line writes a low potential to the pixel electrode through the fourth transistor and the sixth transistor to reset;

[0034] After the reset is completed, the positive power line jumps to a high potential, the pre-storage capacitor maintains the first node at the sum of the data signal voltage and the threshold voltage, and the fourth transistor is turned on until it reaches saturation. At this time, the voltage of the third node is the data signal voltage, and the data signal voltage is written into the pixel electrode through the seventh transistor.

[0035] Furthermore, before the backlight-on phase of the sub-circuit in the Nth row, a pre-extraction phase is also included;

[0036] The pre-extraction stage includes:

[0037] The reset signal line and the second reset signal line jump to a high level, and the first transistor, the third transistor and the fifth transistor are turned on;

[0038] The reset signal line writes a high potential to the pre-storage capacitor;

[0039] The reset signal line jumps to a normal level, and the first transistor is turned off;

[0040] The positive power line is at a normal level. At this time, the pre-storage capacitor maintains the potential of the first node at a high potential, and at the same time, the second node and the third node are at a high potential through the third transistor and the fifth transistor;

[0041] The fourth transistor is turned on, and the potentials of the first node and the third node are continuously discharged to the threshold voltage of the fourth transistor. At this time, the voltage in the pre-storage capacitor is the threshold voltage of the fourth transistor.

[0042] The present invention also provides a gate-controlled field sequence circuit control method, comprising:

[0043] During the backlight-on phase of the sub-circuit in row N:

[0044] The row gate signal line of the N-1th row jumps to a high level, and the first transistor is turned on; the reference signal line writes a high potential into the pre-storage capacitor through the first transistor;

[0045] The row gate signal line of the N-1th row jumps to a normal level, the first transistor is turned off, and the pre-storage capacitor maintains the first node at a high potential;

[0046] The row gate signal line of the Nth row jumps to a high level, the second transistor and the third transistor are turned on, so that the second node is at a high potential;

[0047] The data signal voltage is continuously written to the fourth transistor through the second transistor. The fourth transistor is turned on until it reaches saturation. The first node and the second node are discharged to the sum of the data signal voltage and the threshold voltage. At this time, the amount of electricity in the pre-storage capacitor is the sum of the data signal voltage and the threshold voltage.

[0048] The row gate signal line of the Nth row jumps to a normal level, and the second transistor and the third transistor are turned off;

[0049] During the backlight off phase of the sub-circuit in row N:

[0050] The reset signal line jumps to a high level, the ninth transistor is turned on, and the second reference signal line writes a low potential into the pixel electrode through the ninth transistor, so that the pixel electrode is reset;

[0051] After the reset is completed, the reset signal line jumps to the normal level and the ninth transistor is turned off;

[0052] The transfer signal line jumps to a high potential, the sixth transistor is turned on, and the positive power line jumps to a high level; the positive power line inputs a high potential signal to the source and drain of the fourth transistor through the sixth transistor, and the high level is a level greater than the data signal voltage;

[0053] The pre-storage capacitor maintains the potential of the first node as the sum of the data signal line and the threshold voltage. The fourth transistor is saturated and discharged, so that the potential of the second node is the data signal voltage when cut off. The data signal voltage is written into the pixel electrode through the seventh transistor.

[0054] The present invention has the following advantages:

[0055] The present invention provides a compensation unit, which includes a variety of circuit structures, and can obtain a threshold voltage in advance and store it in a pre-storage capacitor; a high potential is pre-stored in the pre-storage capacitor, so that the gate of the fourth transistor is at a high potential; and the potential of the source and drain of the fourth transistor is simultaneously changed, and the transistor conduction characteristics are utilized to make the potential difference between the first node and the source and drain (the second source and drain) of the fourth transistor connected to one end of the driving unit equal to the threshold voltage of the fourth transistor;

[0056] During the backlight-on stage, the potential of the first node is the sum of the data signal voltage and the threshold voltage; during writing, the conduction characteristics of the transistor are used again to make the potential of the second source and drain of the fourth transistor the data signal voltage. Since the threshold voltage is pre-compensated in the pre-storage capacitor, the influence of the threshold voltage can be eliminated after conduction, reducing the influence of the data signal writing into the pixel electrode, thereby avoiding abnormal screen display caused by uneven in-plane process and threshold voltage drift of the transistor over time. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 A circuit diagram of embodiment 1 of the present invention;

[0058] Figure 2 This is a timing diagram of the first embodiment of the present invention;

[0059] Figure 3 This is a circuit diagram of embodiment 2 of the present invention;

[0060] Figure 4 This is a circuit diagram of embodiment 3 of the present invention;

[0061] Figure 5 This is a timing diagram of embodiment 3 of the present invention. DETAILED DESCRIPTION

[0062] The present invention will be further described below in conjunction with the accompanying drawings, but the protection scope of the present invention is not limited to the following description.

[0063] It should be noted that the directions or positional relationships indicated by "left" and "right" are based on the directions or positional relationships shown in the accompanying drawings, or are the directions or positional relationships in which the inventive product is typically placed when in use, or are directions or positional relationships commonly understood by those skilled in the art. Such terms are intended only to facilitate the description of the present invention and simplify the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operate in a specific direction. Therefore, they should not be understood as limiting the present invention. It should be noted that the embodiments of the present invention and the features and technical solutions in the embodiments can be combined with each other unless there is a conflict.

[0064] Example 1

[0065] See Figure 1 The present invention provides a gate-controlled field sequential circuit, comprising M rows of sub-circuits, the sub-circuits comprising a compensation unit and a driving unit; the compensation unit comprising a first circuit structure, the first circuit structure comprising a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5 and a pre-storage capacitor Cst1;

[0066] The gate of the first transistor M1 of the sub-circuit in the Nth row is coupled to the reset signal line Reset, the first source and drain of the first transistor M1 are coupled to the reference signal line Vref, the second source and drain of the first transistor M1 are coupled to one end of the pre-storage capacitor Cst1 and the first source and drain of the third transistor M3, the other end of the pre-storage capacitor Cst1 is coupled to the second source and drain of the second transistor M2, the gate of the second transistor M2 is coupled to the row gate signal line ScanN of the Nth row, and the first source and drain of the second transistor M2 are coupled to the data signal line Data;

[0067] The gate of the third transistor M3 is coupled to the second reset signal line Reset2, the first source and drain of the third transistor M3 are also coupled to the gate of the fourth transistor M4, the second source and drain of the third transistor M3 are coupled to the first source and drain of the fifth transistor M5, the gate of the fifth transistor M5 is coupled to the second reset signal line Reset2, and the second source and drain of the fifth transistor M5 are coupled to the second source and drain of the fourth transistor M4 and the driving unit;

[0068] A gate of the fourth transistor M4 is coupled to one end of the pre-storage capacitor Cst1 , and a first source and drain of the fourth transistor M4 is coupled to the positive power supply line Vdd. M and N are positive integers, and N≤M.

[0069] In some specific embodiments, the data signal line Data and the reference signal line Vref can be multiplexed into one signal line, and the first transistor M1 and the second transistor M2 use the same transistor; by multiplexing the signal lines, the number of transistors is reduced, thereby improving the aperture ratio.

[0070] Furthermore, the driving unit includes a seventh transistor M7, a pixel electrode Clc, and a storage capacitor Cst2; the gate of the seventh transistor M7 is coupled to the transfer signal line Tran, the first source and drain of the seventh transistor M7 are coupled to the second source and drain of the second transistor M2, the second source and drain of the seventh transistor M7 are coupled to the pixel electrode Clc, and the other end of the pixel electrode Clc is coupled to the common signal line Com; one end of the storage capacitor Cst2 is coupled to the second source and drain of the seventh transistor M7, and the other end of the storage capacitor Cst2 is coupled to the common signal line Com.

[0071] like Figure 2 As shown, before the backlight-on stage of the sub-circuit in row N, a pre-extraction stage is also included;

[0072] The pre-extraction stage includes: the reset signal line Reset and the second reset signal line Reset2 jump to a high level, and the first transistor M1, the third transistor M3 and the fifth transistor M5 are turned on;

[0073] The reset signal line Vref writes a high potential to the pre-storage capacitor Cst1;

[0074] The reset signal line Reset jumps to a normal level, and the first transistor M1 is turned off;

[0075] The positive power line Vdd is at a normal level. At this time, the pre-storage capacitor Cst1 maintains the potential of the first node A at a high potential, and at the same time, the second node B and the third node C are at a high potential through the third transistor M3 and the fifth transistor M5.

[0076] The fourth transistor M4 is turned on, and the potentials of the first node A and the third node C are continuously discharged to the threshold voltage of the fourth transistor M4. At this time, the voltage in the pre-storage capacitor Cst1 is the threshold voltage of the fourth transistor M4.

[0077] In the pre-extraction stage, the threshold voltage of the fourth transistor M4 is written into the pre-storage capacitor Cst1 in advance, and the threshold voltage Vth is written into the pre-storage capacitor Cst1 through the first transistor M1, the third transistor M3, and the fifth transistor M5. In the subsequent stage, after the fourth transistor M4 can enter the preset on-off state, the influence of the difference in the threshold voltage Vth when reaching the saturation state on the written data signal voltage Vdata can be offset.

[0078] During the backlight-on phase of the sub-circuit in row N:

[0079] The row gate signal line ScanN of the Nth row jumps to a high level, and the second transistor M2 is turned on;

[0080] The data signal line Data writes the data signal voltage Vdata to the pre-storage capacitor Cst1 through the second transistor M5, and makes the potential of the second node B the data signal voltage Vdata. At this time, the pre-storage capacitor Cst1 now stores the sum of the data signal voltage Vdata and the threshold voltage Vth.

[0081] The row gate signal line ScanN jumps to a normal level, which is the common level Vcom. The second transistor M2 is turned off. The first node A is maintained at a high potential by the pre-storage capacitor Cst1, and VA=Vdata+Vth.

[0082] In the backlight-on stage, the fourth transistor M4 is used to cooperate with the pre-storage capacitor Cst1, the second transistor M2 and the fifth transistor M6 to store the data signal voltage in the pre-storage capacitor Cst1, so that the potential of the first node A is the sum of the data signal voltage Vdata and the threshold voltage Vth, which is used to pre-compensate the threshold voltage Vth.

[0083] During the backlight off phase of the sub-circuit in row N:

[0084] The transfer signal line Tran jumps to a high potential, and the sixth transistor M6 is turned on;

[0085] The positive power line Vdd jumps to a low potential, and the positive power line Vdd writes a low potential to the pixel electrode Clc through the fourth transistor M4 and the sixth transistor M6 to reset;

[0086] After the reset is completed, the positive power line Vdd jumps to a high potential, the pre-storage capacitor Cst1 maintains the first node A at the sum of the data signal voltage Vdata and the threshold voltage Vth, and the fourth transistor M4 is turned on until it reaches a saturation state;

[0087] At this time, the potential of the first node A is VA=Vdata+Vth, so that the voltage of the third node C is the data signal voltage Vdata, that is, VC=Vdata, and the data signal voltage Vdata is written into the pixel electrode Clc through the seventh transistor M7.

[0088] The reset signal line Reset jumps to a high level, and the seventh transistor M7 is turned on, so that the pixel electrode Clc is reset through the seventh transistor M7;

[0089] At this stage, the accurate data signal voltage Vdata is written into the pixel electrode Clc through the fourth transistor M4 and the pre-storage capacitor Cst1, so that the pixel voltage Vpixel = Vdata; by utilizing the saturation state characteristics of the fourth transistor M4, it can offset the pre-compensated threshold voltage Vth, thereby avoiding the impact of the change in the threshold voltage Vth.

[0090] The present invention sets a compensation unit to pre-write the threshold voltage Vth into the pre-storage capacitor Cst1. The data signal line Data then continues to write Vdata into the pre-storage capacitor Cst1 through the second transistor M2, so that the charge in the pre-storage capacitor Cst1 is the sum of the data signal voltage Vdata and the threshold voltage Vth, which offsets the threshold voltage Vth when the voltage of the pixel electrode Clc is subsequently written.

[0091] Through the on-off and cut-off voltage characteristics of the fourth transistor M4, when the fourth transistor M4 reaches saturation, the potential of the first node A is maintained stable by the pre-storage capacitor Cst1, and the third node C is discharged. When the transistor is stable in the saturation state, VA = Vdata + Vth, VC = Vdata, thereby eliminating the influence of the threshold voltage Vth on the writing of the data signal into the pixel electrode, thereby avoiding the abnormal display of the picture caused by the unevenness of the in-plane process and the drift of the threshold voltage Vth of the transistor over time.

[0092] Example 2

[0093] like Figure 3As shown, this embodiment is a gate-controlled field sequential circuit. In this embodiment 2, the sub-circuit includes a selection unit, a compensation unit and a driving unit;

[0094] The first circuit structure further includes: a sixth transistor M6 and an eighth transistor M8;

[0095] A first source and drain of the fourth transistor M4 is coupled to the driving unit and a first source and drain of the eighth transistor M8. A second source and drain of the eighth transistor M8 is coupled to the common signal line Com. A gate of the eighth transistor M8 is coupled to the second reset signal line Reset2. A first source and drain of the fifth transistor M5 is coupled to the second source and drain of the sixth transistor M6. A first source and drain of the sixth transistor M6 is coupled to the positive power supply line Vdd. A gate of the sixth transistor M6 is coupled to the transfer signal line Tran.

[0096] like Figure 4 As shown, before the backlight-on stage of the sub-circuit in row N, a pre-extraction stage is also included;

[0097] The pre-extraction stage includes: the reset signal line Reset and the second reset signal line Reset2 jump to a high level, and the first transistor M1, the third transistor M3, the fifth transistor M5 and the eighth transistor M8 are turned on;

[0098] The reset signal line Vref writes a high potential to the pre-storage capacitor Cst1;

[0099] The reset signal line Reset jumps to a normal level, and the first transistor M1 is turned off;

[0100] Because the third transistor M3 and the fifth transistor M5 are turned on, the pre-storage capacitor Cst1 maintains the potentials of the first node A, the second node B, and the third node C at a high potential; the eighth transistor M8 is turned on, and the second source and drain of the fourth transistor M4 are at the normal potential Vcom. At this time, the fourth transistor M4 is turned on and is saturated. The potentials of the first node A and the third node C are continuously discharged to the threshold voltage of the fourth transistor M4. At this time, the voltage in the pre-storage capacitor Cst1 is the threshold voltage of the fourth transistor M4.

[0101] In the pre-extraction stage, the threshold voltage of the fourth transistor M4 is written into the pre-storage capacitor Cst1 in advance, and the threshold voltage Vth is written into the pre-storage capacitor Cst1 through the first transistor M1, the third transistor M3, the fifth transistor M5 and the eighth transistor M8; in the subsequent stage, after the fourth transistor M4 can enter the preset on-off state, the influence of the difference in the threshold voltage Vth when reaching the saturation state on the written data signal voltage Vdata can be offset.

[0102] The difference between this embodiment and the first embodiment is that the position of the source-drain compensation of the fourth transistor M4 is changed; this embodiment provides a circuit structure for achieving threshold voltage Vth compensation through the common signal line Com.

[0103] Example 3

[0104] like Figure 4 As shown, embodiment 3 provides a gate-controlled field sequence circuit, including a compensation unit, a driving unit and a reset unit;

[0105] The compensation unit includes a second circuit structure, which includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a sixth transistor M6 and a pre-storage capacitor Cst1;

[0106] The gate of the first transistor M1 of the sub-circuit in the Nth row is coupled to the row gate signal line ScanN-1 in the N-1th row, the first source and drain of the first transistor M1 are coupled to the reference signal line Vref, the second source and drain of the first transistor M1 are coupled to one end of the pre-storage capacitor Cst1 and the first source and drain of the third transistor M3, the gate of the third transistor M3 is coupled to the row gate signal line ScanN in the Nth row, the second source and drain of the third transistor M3 are coupled to the second source and drain of the fourth transistor M4; the gate of the fourth transistor M4 is coupled to one end of the pre-storage capacitor Cst1, and the other end of the pre-storage capacitor Cst1 is coupled to the positive power supply line Vdd;

[0107] The first source and drain of the fourth transistor M4 are coupled to the first source and drain of the second transistor M2 and the second source and drain of the sixth transistor M6; the gate of the second transistor M2 is coupled to the row gate signal line Scan N of the Nth row, and the second source and drain of the second transistor M2 are coupled to the data signal line Data; the gate of the sixth transistor M6 is coupled to the transfer signal line Tran, and the first source and drain of the sixth transistor M6 are coupled to the positive power supply line Vdd; the second source and drain of the fourth transistor M4 and the third transistor M3 are both coupled to the driving unit.

[0108] Furthermore, the driving unit includes a seventh transistor M7, a pixel electrode Clc, and a storage capacitor Cst2; the gate of the seventh transistor M7 is coupled to the transfer signal line Tran, the first source and drain of the seventh transistor M7 are coupled to the second source and drain of the fourth transistor M4, the second source and drain of the seventh transistor M7 are coupled to the pixel electrode Clc, and the other end of the pixel electrode Clc is coupled to the common signal line Com; one end of the storage capacitor Cst2 is coupled to the second source and drain of the seventh transistor M7, and the other end of the storage capacitor Cst2 is coupled to the common signal line Com.

[0109] Furthermore, the reset unit includes a ninth transistor M9 , a first source and a drain of the ninth transistor M9 are coupled to the driving unit, and a second source and a drain of the ninth transistor M9 are coupled to the second reference signal line Vref2 .

[0110] like Figure 5 As shown, in the backlight-on stage of the sub-circuit in row N:

[0111] The row gate signal line ScanN-1 of the N-1th row jumps to a high level, and the first transistor M1 is turned on; the reference signal line Vref writes a high potential into the pre-storage capacitor Cst1 through the first transistor M1;

[0112] The row gate signal line ScanN-1 of the N-1th row jumps to the normal level, the first transistor M1 is turned off, and the pre-storage capacitor Cst1 maintains the first node A at a high potential;

[0113] The row gate signal line ScanN of the Nth row jumps to a high level, the second transistor M2 and the third transistor M3 are turned on, so that the second node B is at a high potential;

[0114] The data signal voltage Data is continuously written to the fourth transistor M4 through the second transistor M2. The fourth transistor M4 is turned on until it reaches a saturated state. The first node A and the second node B are discharged from a high potential to the sum of the data signal voltage Vdaat and the threshold voltage Vth, that is, VA=VC=Vdata+Vth. At this time, the amount of electricity in the pre-storage capacitor Cst1 is the sum of the data signal voltage Vdata and the threshold voltage Vth.

[0115] The row gate signal line ScanN of the Nth row jumps to the normal level, and the second transistor M2 and the third transistor M3 are turned off;

[0116] The data signal voltage Vdata and the threshold voltage Vth are pre-stored in the pre-storage capacitor Cst1 through the cooperation of the first transistor M1 , the second transistor M2 , the third transistor M3 and the fourth transistor M4 , so as to offset the threshold voltage Vth in the subsequent stage.

[0117] During the backlight off phase of the sub-circuit in row N:

[0118] The reset signal line Reset jumps to a high level, the ninth transistor M9 is turned on, and the second reference signal line Vref2 writes a low potential into the pixel electrode Clc through the ninth transistor M9, so that the pixel electrode Clc is reset;

[0119] After the reset is completed, the reset signal line Reset jumps to the normal level, and the ninth transistor M9 is turned off;

[0120] The transfer signal line Tran jumps to a high potential, the sixth transistor M6 is turned on, and the positive power line Vdd jumps to a high level; the positive power line Vdd inputs a high potential signal to the source and drain of the fourth transistor M4 through the sixth transistor M6, and the high potential is a level greater than the data signal voltage;

[0121] The pre-storage capacitor Cst1 maintains the potential of the first node A at the sum of the data signal voltage Vdata and the threshold voltage Vth, and the fourth transistor M4 is saturated discharged, so that the potential of the second node B is the data signal voltage Vdata when it is cut off, and the data signal voltage Vdata is written into the pixel electrode Clc through the seventh transistor M7.

[0122] Compared with the first and second embodiments, the present embodiment does not require a pre-extraction stage. In the backlight-on stage, the threshold voltage Vth and the data signal voltage Vdata of the present embodiment are turned on row by row through the characteristic that multiple rows of row gate signal lines are turned on row by row. The change of the row gate signal line of the previous row is used to control the on and off of the first transistor M1, and the high potential is first written into the pre-storage capacitor Cst1. The present embodiment can simplify the control of the signal line timing and reduce the control difficulty.

[0123] Example 4

[0124] This embodiment is a gate-controlled field sequence circuit control method.

[0125] In the fourth embodiment, before the backlight-on phase of the sub-circuit in the Nth row, a pre-extraction phase is further included;

[0126] The pre-extraction stage includes: the reset signal line Reset and the second reset signal line Reset2 jump to a high level, and the first transistor M1, the third transistor M3 and the fifth transistor M5 are turned on;

[0127] The reset signal line Vref writes a high potential to the pre-storage capacitor Cst1;

[0128] The reset signal line Reset jumps to a normal level, and the first transistor M1 is turned off;

[0129] The positive power line Vdd is at a normal level. At this time, the pre-storage capacitor Cst1 maintains the potential of the first node A at a high potential, and at the same time, the second node B and the third node C are at a high potential through the third transistor M3 and the fifth transistor M5.

[0130] The fourth transistor M4 is turned on, and the potentials of the first node A and the third node C are continuously discharged to the threshold voltage of the fourth transistor M4. At this time, the voltage in the pre-storage capacitor Cst1 is the threshold voltage of the fourth transistor M4.

[0131] In the pre-extraction stage, the threshold voltage of the fourth transistor M4 is written into the pre-storage capacitor Cst1 in advance, and the threshold voltage Vth is written into the pre-storage capacitor Cst1 through the first transistor M1, the third transistor M3, and the fifth transistor M5. In the subsequent stage, after the fourth transistor M4 can enter the preset on-off state, the influence of the difference in the threshold voltage Vth when reaching the saturation state on the written data signal voltage Vdata can be offset.

[0132] During the backlight-on phase of the sub-circuit in row N:

[0133] The row gate signal line ScanN of the Nth row jumps to a high level, and the second transistor M2 is turned on;

[0134] The data signal line Data writes the data signal voltage Vdata to the pre-storage capacitor Cst1 through the second transistor M5, and makes the potential of the second node B the data signal voltage Vdata. At this time, the pre-storage capacitor Cst1 now stores the sum of the data signal voltage Vdata and the threshold voltage Vth.

[0135] The row gate signal line ScanN jumps to a normal level, which is the common level Vcom. The second transistor M2 is turned off. The first node A is maintained at a high potential by the pre-storage capacitor Cst1, and VA=Vdata+Vth.

[0136] In the backlight-on stage, the fourth transistor M4 is used to cooperate with the pre-storage capacitor Cst1, the second transistor M2 and the fifth transistor M6 to store the data signal voltage in the pre-storage capacitor Cst1, so that the potential of the first node A is the sum of the data signal voltage Vdata and the threshold voltage Vth, which is used to pre-compensate the threshold voltage Vth.

[0137] During the backlight off phase of the sub-circuit in row N:

[0138] The transfer signal line Tran jumps to a high potential, and the sixth transistor M6 is turned on;

[0139] The positive power line Vdd jumps to a low potential, and the positive power line Vdd writes a low potential to the pixel electrode Clc through the fourth transistor M4 and the sixth transistor M6 to reset;

[0140] After the reset is completed, the positive power line Vdd jumps to a high potential, the pre-storage capacitor Cst1 maintains the first node A at the sum of the data signal voltage Vdata and the threshold voltage Vth, and the fourth transistor M4 is turned on until it reaches a saturation state;

[0141] At this time, the potential of the first node A is VA=Vdata+Vth, so that the voltage of the third node C is the data signal voltage Vdata, that is, VC=Vdata, and the data signal voltage Vdata is written into the pixel electrode Clc through the seventh transistor M7.

[0142] The reset signal line Reset jumps to a high level, and the seventh transistor M7 is turned on, so that the pixel electrode Clc is reset through the seventh transistor M7;

[0143] At this stage, the accurate data signal voltage Vdata is written into the pixel electrode Clc through the fourth transistor M4 and the pre-storage capacitor Cst1, so that the pixel voltage Vpixel = Vdata; by utilizing the saturation state characteristics of the fourth transistor M4, it can offset the pre-compensated threshold voltage Vth, thereby avoiding the impact of the change in the threshold voltage Vth.

[0144] The present invention sets a compensation unit to pre-write the threshold voltage Vth into the pre-storage capacitor Cst1, and the data signal line Data continues to write Vdata into the pre-storage capacitor Cst1 through the second transistor M2, so that the amount of charge in the pre-storage capacitor Cst1 is the sum of the data signal voltage Vdata and the threshold voltage Vth, which offsets the threshold voltage Vth when the voltage of the pixel electrode Clc is subsequently written.

[0145] This embodiment is used in the first embodiment, the second embodiment, and the deformation circuits of the first embodiment and the second embodiment, and its beneficial effects are the same as those of the first embodiment.

[0146] Example 5

[0147] The fifth embodiment is a gate-controlled field sequence circuit control method.

[0148] During the backlight-on phase of the sub-circuit in row N:

[0149] The row gate signal line ScanN-1 of the N-1th row jumps to a high level, and the first transistor M1 is turned on; the reference signal line Vref writes a high potential into the pre-storage capacitor Cst1 through the first transistor M1;

[0150] The row gate signal line ScanN-1 of the N-1th row jumps to the normal level, the first transistor M1 is turned off, and the pre-storage capacitor Cst1 maintains the first node A at a high potential;

[0151] The row gate signal line ScanN of the Nth row jumps to a high level, the second transistor M2 and the third transistor M3 are turned on, so that the second node B is at a high potential;

[0152] Data signal voltage Data continuously writes through the second transistor M2 to the fourth transistor M4, the fourth transistor M4 is turned on until saturation, the first node A and the second node B discharge from high potential to the sum of the data signal voltage Vdata and the threshold voltage Vth, that is, VA=VC=Vdata+Vth, at this time, the amount of electricity in the pre-storage capacitor Cst1 is the sum of the data signal voltage Vdata and the threshold voltage Vth;

[0153] The row gate signal line ScanN of the Nth row jumps to a normal level, and the second transistor M2 and the third transistor M3 are turned off;

[0154] The data signal voltage Vdata and the threshold voltage Vth are pre-stored in the pre-storage capacitor Cst1 through the cooperation of the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4, which is used for the threshold voltage Vth offset in the subsequent stage.

[0155] In the backlight-off stage of the sub-circuit of the Nth row:

[0156] The reset signal line Reset jumps to a high level, the ninth transistor M9 is turned on, and the second reference signal line Vref2 writes a low potential into the pixel electrode Clc through the ninth transistor M9, so that the pixel electrode Clc is reset;

[0157] After the reset is completed, the reset signal line Reset jumps to a normal level, and the ninth transistor M9 is turned off;

[0158] The transfer signal line Tran jumps to a high level, the sixth transistor M6 is turned on, and the positive power supply line Vdd jumps to a high level; the positive power supply line Vdd inputs a high potential signal to the source-drain electrode of the fourth transistor M4 through the sixth transistor M6, and the high potential is a level greater than the data signal voltage;

[0159] The pre-storage capacitor Cst1 maintains the potential of the first node A as the sum of the data signal voltage Vdata and the threshold voltage Vth, the fourth transistor M4 is saturated and discharged, so that the potential of the second node B is the data signal voltage Vdata when it is cut off, and the seventh transistor M7 writes the data signal voltage Vdata into the pixel electrode Clc.

[0160] The embodiment is used to provide a control method different from the fourth embodiment, which is suitable for the third embodiment and the variant circuit of the third embodiment, and has the same beneficial effects as the third embodiment.

[0161] The above embodiments merely represent preferred implementations, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art will be able to make various modifications and improvements without departing from the present invention, and these modifications and improvements are all within the scope of protection of the present invention.

Claims

1. A gate-controlled field-sequential circuit, characterized in that: comprising M rows of sub-circuits, each of which comprises a compensation unit and a driving unit; The compensation unit includes a first circuit structure; The first circuit structure includes a first transistor (M1), a second transistor (M2), a third transistor (M3), a fourth transistor (M4), a fifth transistor (M5) and a pre-storage capacitor (Cst1); The gate of the first transistor (M1) of the sub-circuit of the Nth row is coupled to the reset signal line (Reset), the first source and drain of the first transistor (M1) are coupled to the reference signal line (Vref), the second source and drain of the first transistor (M1) are coupled to one end of the pre-storage capacitor (Cst1) and the first source and drain of the third transistor (M3), the other end of the pre-storage capacitor (Cst1) is coupled to the second source and drain of the second transistor (M2), the gate of the second transistor (M2) is coupled to the row gate signal line (ScanN) of the Nth row, and the first source and drain of the second transistor (M2) are coupled to the data signal line (Data); The gate of the third transistor (M3) is coupled to the second reset signal line (Reset2), the first source and drain of the third transistor (M3) are also coupled to the gate of the fourth transistor (M4), the second source and drain of the third transistor (M3) are coupled to the first source and drain of the fifth transistor (M5), the gate of the fifth transistor (M5) is coupled to the second reset signal line (Reset2), and the second source and drain of the fifth transistor (M5) are coupled to the second source and drain of the fourth transistor (M4) and the driving unit; The gate of the fourth transistor (M4) is coupled to one end of the pre-storage capacitor (Cst1), and the first source and drain of the fourth transistor (M4) are coupled to a positive power supply line (Vdd); The first circuit structure further includes: a sixth transistor (M6) and an eighth transistor (M8); A first source and drain of the fourth transistor (M4) is coupled to the driving unit and a first source and drain of the eighth transistor (M8), a second source and drain of the eighth transistor (M8) is coupled to a common signal line (Com), and a gate of the eighth transistor (M8) is coupled to a second reset signal line (Reset2); The first source and drain of the fifth transistor (M5) are coupled to the second source and drain of the sixth transistor (M6), the first source and drain of the sixth transistor (M6) are coupled to the positive power supply line (Vdd), and the gate of the sixth transistor (M6) is coupled to the transfer signal line (Tran).

2. The gate-controlled field sequence circuit according to claim 1, characterized in that: The driving unit includes a seventh transistor (M7) and a pixel electrode (Clc); The gate of the seventh transistor (M7) is coupled to the transfer signal line (Tran), the first source and drain of the seventh transistor (M7) are coupled to the second source and drain of the fourth transistor (M4), the second source and drain of the seventh transistor (M7) are coupled to the pixel electrode (Clc), and the other end of the pixel electrode (Clc) is coupled to the common signal line (Com).

3. The gate-controlled field sequence circuit according to claim 2, characterized in that: The driving unit further includes a storage capacitor (Cst2), one end of the storage capacitor (Cst2) is coupled to the second source and drain of the seventh transistor (M7), and the other end of the storage capacitor (Cst2) is coupled to the common signal line (Com).

4. A gate-controlled field-sequential circuit control method, applied to the field-sequential circuit according to claim 3, characterized in that: include: During the backlight-on phase of the sub-circuit in row N: The row gate signal line (ScanN) of the Nth row jumps to a high level, and the second transistor (M2) is turned on; The data signal line (Data) writes a data signal voltage to the pre-storage capacitor (Cst1) through the second transistor (M5), and causes the potential of the second node (B) to be the data signal voltage; the pre-storage capacitor (Cst1) has a threshold voltage written in the previous frame, and the pre-storage capacitor (Cst1) currently stores the sum of the data signal voltage and the threshold voltage; The row gate signal line (ScanN) jumps to a normal level, which is a common level, the second transistor (M2) is turned off, and the first node (A) is maintained at a high potential by the pre-storage capacitor (Cst1); During the backlight off phase of the sub-circuit in row N: The transfer signal line (Tran) jumps to a high potential, and the sixth transistor (M6) is turned on; The positive power line (Vdd) jumps to a low potential, and the positive power line (Vdd) writes a low potential to the pixel electrode (Clc) through the fourth transistor (M4) and the sixth transistor (M6) to reset; After the reset is completed, the positive power line (Vdd) jumps to a high potential, the pre-storage capacitor (Cst1) maintains the first node (A) at the sum of the data signal voltage and the threshold voltage, and the fourth transistor (M4) is turned on until it reaches a saturation state. At this time, the voltage of the third node (C) is the data signal voltage, and the data signal voltage is written into the pixel electrode (Clc) through the seventh transistor (M7).

5. The gate-controlled field sequence circuit control method according to claim 4, characterized in that: Before the backlight-on phase of the sub-circuit in row N, a pre-extraction phase is also included; The pre-extraction stage includes: The reset signal line (Reset) and the second reset signal line (Reset2) jump to a high level, and the first transistor (M1), the third transistor (M3) and the fifth transistor (M5) are turned on; The reset signal line (Vref) writes a high potential to the pre-storage capacitor (Cst1); The reset signal line (Reset) jumps to a normal level, and the first transistor (M1) is turned off; The positive power line (Vdd) is at a normal level. At this time, the pre-storage capacitor (Cst1) maintains the potential of the first node (A) at a high potential, and simultaneously makes the second node (B) and the third node (C) at a high potential through the third transistor (M3) and the fifth transistor (M5); The fourth transistor (M4) is turned on, and the potentials of the first node (A) and the third node (C) are continuously discharged to the threshold voltage of the fourth transistor (M4). At this time, the voltage in the pre-storage capacitor (Cst1) is the threshold voltage of the fourth transistor (M4).

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