An evaluation method and system for the charge and discharge effect of the space of a volatile interlock storage circuit

Abstract

The present invention discloses a method and system for evaluating the charge and discharge effect of the space of a volatile interlocked memory circuit, belonging to the technical field of space charge and discharge effect. The method includes: successively obtaining the positive SESD pulse core threshold, the first SESD core threshold, and the second SESD core threshold according to the volatile interlocked memory circuit; substituting the positive SESD pulse core threshold, the first SESD core threshold, and the second SESD core threshold into the lowest SESD threshold expression to calculate the lowest SESD threshold; substituting the lowest SESD threshold into the SESD pulse flip threshold expression to calculate the SESD pulse flip threshold, so as to evaluate the space charge and discharge induced flip effect of the volatile interlocked memory circuit. The present invention provides a brand-new and effective method to quickly evaluate the ability of the volatile interlocked memory circuit to resist the space charge and discharge effect, which has important value.

Description

Technical Field

[0001] The present invention belongs to the technical field of space charge and discharge effects, and particularly relates to a method and system for evaluating the space charge and discharge effects of a volatile interlock memory circuit. Background Art

[0002] Space charge and discharge effects and single particle effects are the main factors inducing data inversion in spaceborne memory circuits. At present, the test of the space charge and discharge induced inversion effect on memory circuits is an important process for developing space charge and discharge effect resistant devices and their safe and reliable application in space missions.

[0003] However, there are many problems when using high-energy electron accelerators and proton accelerators to evaluate the space charge and discharge effect resistance level of spaceborne components. Due to the complex operation and operation of large test devices, the test cycle and cost are often greatly increased. In some cases, these problems even hinder the normal development of devices and the successful delivery of space missions, seriously affecting the progress and efficiency of space projects. Summary of the Invention

[0004] To solve the above technical problems, the present invention proposes a method and system for evaluating the space charge and discharge effects of a volatile interlock memory circuit to solve the problems existing in the above prior art.

[0005] To achieve the above object, in a first aspect, the present invention provides a method for evaluating the space charge and discharge effects of a volatile interlock memory circuit, including:

[0006] According to the volatile interlock memory circuit, obtain the SESD pulse inversion threshold expression corresponding to the lowest voltage inducing data inversion in the core memory circuit;

[0007] Obtain the path of the SESD induced data inversion in the circuit, and obtain the lowest SESD threshold expression for inducing data inversion through each path; where each path includes a first path injected from the gate of the MOS transistor and a second path injected from the source of the MOS transistor;

[0008] Obtain the positive SESD pulse core threshold for the storage node to change from low level to high level caused by injecting into the storage circuit from the gate of the MOS transistor;

[0009] According to the core power supply voltage and noise tolerance of the storage circuit, calculate the first SESD core threshold for inducing output inversion by injecting SESD pulses from the storage circuit transistors;

[0010] According to the offset voltage of the latch structure of the storage circuit, calculate the second SESD core threshold for inducing storage data errors by injecting SESD pulses from the storage circuit transistors;

[0011] Substitute the positive SESD pulse kernel threshold, the first SESD kernel threshold, and the second SESD kernel threshold into the lowest SESD threshold expression to calculate the lowest SESD threshold;

[0012] Substitute the lowest SESD threshold into the SESD pulse flip threshold expression to calculate the SESD pulse flip threshold, so as to evaluate the spatial charge and discharge induced flip effect of the volatile interlocked storage circuit.

[0013] Preferably, the SESD pulse flip threshold expression corresponding to the lowest voltage that induces data flip in the kernel storage circuit includes:

[0014] According to the volatile interlocked storage circuit, determine the relationship expression between the SESD pulse voltage acting on the power input terminal of the storage circuit and the kernel related voltage of the storage circuit;

[0015] Through the relationship expression, obtain the SESD pulse flip threshold expression corresponding to the lowest voltage that induces data flip in the kernel storage circuit.

[0016] Preferably, determining the relationship expression between the SESD pulse voltage acting on the power input terminal of the storage circuit and the kernel related voltage of the storage circuit includes:

[0017] According to the volatile interlocked storage circuit, obtain the power supply rejection ratio expression of the low dropout regulator;

[0018] According to the power supply rejection ratio expression, obtain the relationship expression between the SESD pulse voltage acting on the power input terminal of the storage circuit and the kernel related voltage of the storage circuit.

[0019] Preferably, the volatile interlocked storage circuit is a complementary metal oxide CMOS semiconductor circuit and a digital logic circuit.

[0020] Preferably, the expression for calculating the SESD pulse flip threshold is:

[0021] ;

[0022] where PSRR is the power supply rejection ratio, is the kernel power supply voltage, is the offset voltage, V IH is the upper limit of the noise margin, V IL is the lower limit of the noise margin.

[0023] Preferably, dielectric discharge pulses are coupled to each pin of the volatile interlocked storage circuit.

[0024] In a second aspect, the present invention also provides an evaluation system for the spatial charge and discharge effect of a volatile interlocked storage circuit, including:

[0025] A first derivation module, configured to obtain an SESD pulse flip threshold expression corresponding to the lowest voltage that induces data flipping in the kernel storage circuit according to the volatile interlock storage circuit;

[0026] A second derivation module, configured to obtain the path of data flipping induced by the SESD induction circuit, and obtain the lowest SESD threshold expression for inducing data flipping through each path; wherein each path includes a first path injected from the gate of the MOS transistor and a second path injected from the source of the MOS transistor;

[0027] A first calculation module, configured to obtain a positive SESD pulse kernel threshold for the storage node to change from a low level to a high level due to injection into the storage circuit from the gate of the MOS transistor;

[0028] A second calculation module, configured to calculate a first SESD kernel threshold for inducing output flipping by injecting an SESD pulse from the transistor of the storage circuit according to the kernel power supply voltage and noise tolerance of the storage circuit;

[0029] A third calculation module, configured to calculate a second SESD kernel threshold for inducing storage data errors by injecting an SESD pulse from the transistor of the storage circuit according to the offset voltage of the latch structure of the storage circuit;

[0030] A first substitution module, configured to substitute the positive SESD pulse kernel threshold, the first SESD kernel threshold, and the second SESD kernel threshold into the lowest SESD threshold expression to calculate the lowest SESD threshold;

[0031] A second substitution module, configured to substitute the lowest SESD threshold into the SESD pulse flip threshold expression to calculate the SESD pulse flip threshold, so as to evaluate the spatial charge and discharge induced flip effect of the volatile interlock storage circuit.

[0032] In a third aspect, the present invention also discloses a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the method described in the first aspect are implemented.

[0033] In a fourth aspect, the present invention also discloses a computer program product, including a computer program, and when the computer program is executed by a processor, the steps of the method described in the first aspect are implemented.

[0034] Compared with the prior art, the present invention has the following advantages and technical effects:

[0035] The present invention provides a method for evaluating the space charge and discharge effect of a volatile interlocked storage circuit, including: First, according to the volatile interlocked storage circuit, obtain the SESD pulse flip threshold expression corresponding to the lowest voltage that induces data flip in the kernel storage circuit; Second, obtain the path of data flip induced by the SESD in the circuit, and obtain the lowest SESD threshold expression for inducing data flip through each path; where each path includes a first path injected from the gate of the MOS transistor and a second path injected from the source of the MOS transistor; Then, obtain the positive SESD pulse kernel threshold for the storage node to change from low level to high level due to the injection of the storage circuit from the gate of the MOS transistor; Further, according to the kernel power supply voltage and noise tolerance of the storage circuit, calculate the first SESD kernel threshold for inducing output flip by injecting the SESD pulse into the storage circuit transistor; Again, according to the offset voltage of the latch structure of the storage circuit, calculate the second SESD kernel threshold for inducing storage data error by injecting the SESD pulse into the storage circuit transistor; Finally, substitute the positive SESD pulse kernel threshold, the first SESD kernel threshold, and the second SESD kernel threshold into the lowest SESD threshold expression to calculate the lowest SESD threshold; Then substitute the lowest SESD threshold into the SESD pulse flip threshold expression to calculate the SESD pulse flip threshold, so as to evaluate the space charge and discharge induced flip effect of the volatile interlocked storage circuit.

[0036] Based on the mechanism of inducing data flip in a volatile storage circuit by the space charge and discharge effect, the present invention proposes a calculation method that can effectively calculate the discharge pulse threshold. This method can quickly calculate the discharge pulse voltage threshold of the circuit pin that can induce storage data error by inputting the electrical parameters of the circuit under test.

[0037] Compared with the method of measuring the threshold through a large particle accelerator for discharge tests, the present invention has great potential for quickly and economically evaluating the anti-space charge and discharge effect of components, and can provide accurate, efficient and inexpensive space charge and discharge effect evaluation technologies for aerospace engineering, promote the development of domestic aerospace components, and ensure the long-life and high-reliability operation of spacecraft. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The drawings constituting a part of this application are used to provide a further understanding of this application. The schematic embodiments of this application and their descriptions are used to explain this application and do not constitute an improper limitation of this application. In the drawings:

[0039] Figure 1 is a schematic diagram of a volatile interlocked storage circuit according to an embodiment of the present invention;

[0040] Figure 2 is a schematic diagram of the space environment effect test of a volatile interlocked storage circuit according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0041] It should be noted that, without conflict, the embodiments in this application and the features in the embodiments can be combined with each other. The following will detail this application with reference to the accompanying drawings and in combination with the embodiments.

[0042] It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here.

[0043] First, the technical terms involved in the following embodiments will be described below.

[0044] 1. A volatile interlocked storage circuit is a storage circuit based on a volatile memory (such as SRAM), mainly used to keep data unchanged when the device is powered on and the data is lost after power-off. SRAM (Static Random Access Memory) is a typical volatile memory, and its storage unit is built by transistors. Common structures include 6-transistor (6T) and 8-transistor (8T) structures. SRAM stores data through two inverters forming an interlocked structure, keeps the stored data unchanged when the device is powered on, and the stored data is lost after power-off.

[0045] The working principle of SRAM: The basic storage unit of SRAM consists of two inverters, forming an interlocked structure. When the output of one inverter is high, the output of the other inverter is low, and vice versa. This interlocked structure ensures that the data remains stable when the device is powered on. When the device is powered off, the data is lost.

[0046] The characteristics of SRAM:

[0047] Fast read and write speed: Since the read and write operations of SRAM mainly involve the switching operations of transistors, the read and write speed is very fast.

[0048] No limit on the number of read and write times: The read and write operations of SRAM will not cause data damage, so there is no limit on the number of read and write times.

[0049] Mature process: The manufacturing process of SRAM is relatively mature, and the device consistency and stability are good.

[0050] High cost and low density: Since SRAM needs to be powered on to keep data, the power consumption is high, and the storage density is low under the multi-transistor unit structure, resulting in a high cost.

[0051] Application scenarios: SRAM is often used for CPU cache, especially in high-speed cache. Due to its fast read and write speed, mature process, good device consistency and stability, it is suitable for scenarios that require high-speed data access.

[0052] 2. A low dropout regulator (LDO) is a linear DC regulator that is mainly used to provide a stable DC voltage supply. Compared with a general linear regulator, a low dropout regulator can operate at a smaller input and output voltage difference, and its dropout voltage is usually within 200mV.

[0053] Working principle: The working principle of the low-dropout regulator is based on negative feedback regulation. Its internal structure mainly includes a voltage-dividing sampling circuit, a reference voltage, an error amplifier circuit, and a transistor adjustment circuit. The voltage-dividing sampling circuit collects the output voltage through resistors R1 and R2; the reference voltage is usually generated by a bandgap (bandgap voltage reference) to reduce the impact of temperature changes; the error amplifier circuit compares the collected voltage with the desired output voltage and amplifies the comparison result; the transistor adjustment circuit outputs the amplified signal to the control electrode of the transistor, thereby controlling the on-voltage of the transistor.

[0054] Main features and applications:

[0055] ‌Low Noise‌: Low dropout regulators contain a small voltage drop between input and output, allowing them to operate normally even when the output voltage is very close to the input voltage, unlike linear regulators which require a huge voltage drop to operate properly, thus having lower noise.

[0056] ‌High Efficiency‌: Due to their miniature system-on-chip design with extremely low self-consumption, low-dropout regulators excel in current main channel control and are suitable for applications requiring high-efficiency power management.

[0057] ‌Protection function‌: Usually has over-current protection, over-temperature protection and other functions to ensure stable operation of the equipment.

[0058] ‌Widely used‌: Commonly used in mobile and IoT devices, especially in lithium battery applications. It is the best choice for analog circuits that require high precision and low noise.

[0059] Embodiment 1

[0060] This embodiment provides a method for evaluating the spatial charge and discharge effect of a volatile interlock storage circuit, including:

[0061] S1. According to the volatile interlock storage circuit, the SESD pulse flip threshold expression corresponding to the lowest voltage that induces the data flip of the core storage circuit is obtained;

[0062] Further, the expression for the SESD pulse flip threshold corresponding to the lowest voltage that induces data flipping in the kernel storage circuit includes:

[0063] According to the volatile interlocked storage circuit, determine the relationship expression between the SESD pulse voltage applied to the power input terminal of the storage circuit and the kernel-related voltage of the storage circuit;

[0064] Through the relationship expression, obtain the expression for the SESD pulse flip threshold corresponding to the lowest voltage that induces data flipping in the kernel storage circuit.

[0065] Further, determining the relationship expression between the SESD pulse voltage applied to the power input terminal of the storage circuit and the kernel-related voltage of the storage circuit includes:

[0066] According to the volatile interlocked storage circuit, obtain the expression for the power supply rejection ratio of the low-dropout regulator;

[0067] According to the power supply rejection ratio expression, obtain the relationship expression between the SESD pulse voltage applied to the power input terminal of the storage circuit and the kernel-related voltage of the storage circuit.

[0068] Further, the volatile interlocked storage circuit is a complementary metal-oxide semiconductor (CMOS) circuit and a digital logic circuit.

[0069] Further, dielectric discharge pulses are coupled to each pin of the volatile interlocked storage circuit.

[0070] As Figure 1 shown, for the volatile interlocked storage circuit, the storage unit of the circuit consists of two cross-coupled inverters and a conduction control NMOS transistor, where P11 and P12 are PMOS, and N11, N12, N13, and N14 are NMOS. When the six-transistor storage unit stores data '1', P11 and N12 are conducting, and N11, P12, P13, and P14 are cutoff; when the six-transistor storage unit stores data '0', P12 and N11 are conducting, and N12, P11, P13, and P14 are cutoff.

[0071] Specifically, according to the definition formula of the power supply rejection ratio of the low-dropout regulator (LDO) of the volatile interlocked storage circuit , the relationship between the SESD pulse voltage applied to the LDO power input and the pulse voltage at the LDO output is:

[0072] (1)

[0073] If The lowest voltage for inducing data inversion in the kernel storage circuit , then the SESD pulse inversion threshold is:

[0074] (2)

[0075] In the formula, is the SESD pulse inversion threshold of the kernel circuit, is the kernel power supply voltage, is the offset voltage, VIH is the upper limit of the noise margin and VIL is the lower limit of the noise margin.

[0076] S2. Obtain the path for the SESD-induced circuit data inversion, and obtain the expression of the lowest SESD threshold for inducing data inversion through each path; where each path includes a first path injected from the gate of the MOS transistor and a second path injected from the source of the MOS transistor;

[0077] Specifically, for the discharge pulse generated by the space charge and discharge effect, there are two paths for the SESD discharge pulse to induce circuit data inversion, including two paths injected from the input terminal gate and the input terminal source of the CMOS transistor. The kernel SESD threshold is the lowest SESD threshold for inducing data inversion through the two paths. Therefore The expression is as follows:

[0078] (3)

[0079] Where is the positive SESD pulse kernel threshold for the storage node to change from low level to high level caused by injecting into the storage circuit from the gate of the MOS transistor, is the negative SESD pulse kernel threshold for the storage node to change from high level to low level caused by injecting into the storage circuit from the gate of the MOS transistor, is the SESD kernel threshold injected from the source of the MOS transistor.

[0080] S3. Obtain the positive SESD pulse kernel threshold for the storage node to change from low level to high level caused by injecting into the storage circuit from the gate of the MOS transistor;

[0081] Specifically, then calculate the SESD kernel threshold for the SESD pulse injected from the gate of the CMOS transistor to induce output inversion according to the kernel power supply voltage and noise margin of the CMOS circuit forming an inverter.

[0082] If the storage circuit node is at low level '0', after the space charge and discharge pulse acts on the input terminal gate voltage V gate = 0 V, it makes V gate+V SESD >V IH , which causes the CMOS node voltage to flip from low level to high level. Thus, the threshold voltage for the spatial charge and discharge pulse injection into the gate to induce low-level flip can be obtained. is:

[0083] (4)

[0084] S4. Calculate the first SESD core threshold for the output flip induced by injecting the SESD pulse through the storage circuit transistor according to the core power supply voltage and noise tolerance of the storage circuit;

[0085] Specifically, if the storage circuit node is at high level '1', when the amplitude of the charge and discharge pulse V SESD acts on the gate voltage V gate =V DD of the CMOS circuit input end, making V gate +V SESD <V IL , which causes the storage node voltage to flip from high level to low level. Thus, the threshold voltage for the spatial charge and discharge pulse injection into the gate to induce the flip of data '0' can be obtained. is:

[0086] (5)

[0087] S5. Calculate the second SESD core threshold for the storage data error induced by injecting the SESD pulse through the storage circuit transistor according to the offset voltage of the latch structure of the storage circuit;

[0088] Specifically, calculate the SESD core threshold for the storage data error induced by injecting the SESD pulse from the source of the CMOS transistor according to the offset voltage Voff of the latch structure formed by the CMOS circuit as the storage circuit. .

[0089] When the negative SESD pulse is injected into the latch structure of the storage circuit through the source of the CMOS transistor (the circuit power input terminal VDD), it will cause the output voltage at both ends of the circuit to change. When the voltage difference at both ends is less than the offset voltage Voff, it will cause storage data error. is:

[0090] (6)

[0091] S6. Substitute the positive SESD pulse core threshold, the first SESD core threshold, and the second SESD core threshold into the lowest SESD threshold expression to calculate the lowest SESD threshold;

[0092] Specifically, the lowest SESD threshold expression can be expressed as:

[0093] (7)

[0094] S7. Substitute the lowest SESD threshold into the SESD pulse flip threshold expression, and calculate the SESD pulse flip threshold to evaluate the spatial charge and discharge induced flip effect of the volatile interlock memory circuit.

[0095] Specifically, the expression for the finally calculated SESD pulse flip threshold is:

[0096] (8)

[0097] where PSRR is the power supply rejection ratio, is the core power supply voltage, is the offset voltage, V IH is the upper limit of the noise margin, V IL is the lower limit of the noise margin.

[0098] As Figure 2 shown, for the spatial environment effect test of the volatile interlock memory circuit, during the test, an electrostatic generator is used to perform contact discharge on a grounded metal plate on the table to simulate the spatial charge and discharge environment. The circuit under test is placed on an insulating material about 200 mm away from the electrostatic generator. When the ESD generator generates an excitation, the discharge transient is coupled to the pins of the device through the electromagnetic field and generates an SESD transient on the pins.

[0099] After testing the basic parameters of the memory circuit under test, the noise margin and core voltage in the model are based on the data in the chip data sheet, and the offset voltage is less than 0.1 V. The result comparison table of the specific embodiment is shown in Table 1.

[0100] Table 1

[0101] It can be seen from Table 1 that by using the evaluation method for the spatial charge and discharge effect of the volatile interlock memory circuit proposed in the present invention, the obtained charge and discharge effect flip threshold is basically the same as the measured SESD threshold of the pins of three SRAM devices irradiated by the electrostatic generator. Especially for the state of storing data '1', the error between the two is less than 20%. Considering the uncertainty of the test, the data is completely consistent.

[0102] An evaluation method for the charge and discharge effect of the space of a volatile interlock memory circuit mentioned in the present invention. Compared with the method of obtaining the flip threshold of the charge and discharge effect of the space of the volatile interlock memory circuit through experimental measurement and the methods reported in existing literature and patents, the advantages are mainly reflected in that the anti-charge and discharge effect ability of the memory circuit can be quickly evaluated through the basic parameters of the circuit under test, and the flip threshold of its space charge and discharge effect can be calculated. The popularization of this evaluation method has important value. The flip threshold of the space charge and discharge effect obtained by using this calculation method tends to be consistent with the experimental measurement threshold.

[0103] In summary, the evaluation method for the charge and discharge effect of the space of the volatile interlock memory circuit involved in the present invention can calculate the data flip threshold of the volatile interlock memory circuit induced by the electrical pulse generated by the charge and discharge effect of the space on the device pin on the premise of accurately determining each calculation parameter.

[0104] Embodiment 2

[0105] Based on the same inventive concept, this embodiment also provides an evaluation system for the charge and discharge effect of the space of a volatile interlock memory circuit, including:

[0106] A first derivation module, configured to obtain an expression of the SESD pulse flip threshold corresponding to the lowest voltage that induces data flip in the kernel memory circuit according to the volatile interlock memory circuit;

[0107] A second derivation module, configured to obtain the path of the SESD-induced circuit data flip, and obtain an expression of the lowest SESD threshold for inducing data flip through each path; where each path includes a first path injected from the gate of the MOS transistor and a second path injected from the source of the MOS transistor;

[0108] A first calculation module, configured to obtain the positive SESD pulse kernel threshold for the storage node to change from a low level to a high level caused by injecting into the storage circuit from the gate of the MOS transistor;

[0109] A second calculation module, configured to calculate the first SESD kernel threshold for inducing output flip by injecting an SESD pulse from the transistor of the storage circuit according to the kernel power supply voltage and noise tolerance of the storage circuit;

[0110] A third calculation module, configured to calculate the second SESD kernel threshold for inducing storage data error by injecting an SESD pulse from the transistor of the storage circuit according to the offset voltage of the latch structure of the storage circuit;

[0111] A first substitution module, configured to substitute the positive SESD pulse kernel threshold, the first SESD kernel threshold, and the second SESD kernel threshold into the lowest SESD threshold expression, and calculate the lowest SESD threshold;

[0112] The second substitution module is used to substitute the lowest SESD threshold into the SESD pulse flip threshold expression to calculate the SESD pulse flip threshold, so as to evaluate the spatial charge and discharge induced flip effect of the volatile interlock storage circuit.

[0113] The evaluation system for the spatial charge and discharge effect of the volatile interlock storage circuit provided in this embodiment has all the advantages of the evaluation method for the spatial charge and discharge effect of the volatile interlock storage circuit provided in Embodiment 1.

[0114] Embodiment 3

[0115] This embodiment also discloses a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method described in Embodiment 1 are implemented.

[0116] Embodiment 4

[0117] This embodiment also discloses a computer program product, including a computer program. When the computer program is executed by a processor, the steps of the method described in Embodiment 1 are implemented.

[0118] The above is only the preferred specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for evaluating the spatial charge-discharge effect of a volatile interlocking memory circuit, characterized in that: The following steps are involved: According to the volatile interlock storage circuit, the SESD pulse flip threshold expression corresponding to the lowest voltage that induces the data flip of the core storage circuit is obtained; Obtain the paths of SESD-induced circuit data flipping, and obtain the lowest SESD threshold expression for inducing data flipping through each path; wherein each of the paths comprises a first path injected from a gate of a MOS transistor and a second path injected from a source of the MOS transistor; Obtaining a positive SESD pulse core threshold injected into a storage circuit by a MOS transistor gate causing a storage node to change from a low level to a high level; Calculating a first SESD core threshold value for output flipping induced by SESD pulse injected into a transistor of the storage circuit according to the core power supply voltage and noise margin of the storage circuit; Calculating a second SESD core threshold for causing a storage data error induced by a SESD pulse injected by a storage circuit transistor according to an offset voltage of a latch structure of the storage circuit; Substituting the positive SESD pulse kernel threshold, the first SESD kernel threshold and the second SESD kernel threshold into the minimum SESD threshold expression to calculate the minimum SESD threshold; The lowest SESD threshold is substituted into the SESD pulse inversion threshold expression to calculate the SESD pulse inversion threshold so as to evaluate the spatial charge-discharge induced inversion effect of the volatile interlock storage circuit.

2. The method according to claim 1, characterized in that: The SESD pulse flip threshold expression corresponding to the lowest voltage that induces data flipping in the core storage circuit includes: According to the volatile interlock storage circuit, a relationship expression between the SESD pulse voltage acting on the power input terminal of the storage circuit and the voltage related to the core of the storage circuit is determined; Through the relational expression, the SESD pulse flip threshold expression corresponding to the lowest voltage that induces data flipping in the core storage circuit is obtained.

3. The method according to claim 2, characterized in that The expressions for determining the relationship between the SESD pulse voltage acting on the power input terminal of the storage circuit and the voltage related to the core of the storage circuit include: According to the volatile interlock storage circuit, the power supply rejection ratio expression of the low dropout regulator is obtained; According to the power supply rejection ratio expression, an expression for the relationship between the SESD pulse voltage acting on the power input terminal of the storage circuit and the core-related voltage of the storage circuit is obtained.

4. The method according to claim 1, characterized in that The volatile interlocking storage circuit is a complementary metal oxide semiconductor (CMOS) circuit and a digital logic circuit.

5. The method according to claim 1, characterized in that The expression of SESD pulse flip threshold is calculated as: ； Where PSRR is the power supply rejection ratio, is the core supply voltage, is the offset voltage, V IH is the upper limit of noise tolerance, V IL is the lower limit of noise tolerance.

6. The method according to claim 1, characterized in that A dielectric discharge pulse is coupled to each pin of the volatile interlock storage circuit.

7. A system for evaluating spatial charge and discharge effects of a volatile interlocking storage circuit, characterized in that: include: The first derivation module is used to obtain a SESD pulse flip threshold expression corresponding to the lowest voltage that induces data flipping in the core storage circuit according to the volatile interlock storage circuit; The second derivation module is used to obtain the paths of SESD-induced circuit data flipping and obtain the lowest SESD threshold expression for inducing data flipping through each path; wherein each of the paths comprises a first path injected from a gate of a MOS transistor and a second path injected from a source of the MOS transistor; The first calculation module is used to obtain a positive SESD pulse core threshold value injected into the storage circuit by the MOS transistor gate causing the storage node to change from a low level to a high level; A second calculation module is used to calculate a first SESD core threshold value for inducing output flipping by injecting SESD pulses into the storage circuit transistor according to the core power supply voltage and noise margin of the storage circuit; A third calculation module is used to calculate a second SESD core threshold value for causing a storage data error induced by a SESD pulse injected by a storage circuit transistor according to an offset voltage of a latch structure of the storage circuit; A first substitution module is used to substitute the positive SESD pulse kernel threshold, the first SESD kernel threshold and the second SESD kernel threshold into the minimum SESD threshold expression to calculate the minimum SESD threshold; The second substitution module is used to substitute the minimum SESD threshold into the SESD pulse flip threshold expression to calculate the SESD pulse flip threshold so as to evaluate the spatial charge-discharge induced flip effect of the volatile interlock storage circuit.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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