Structure and method for improving apparent qualified rate of chromium-silicon thin-film resistor

Abstract

The invention discloses a structure and a method for improving the apparent qualification rate of a chromium-silicon thin-film resistor, and silicon-based substrate cleaning, in order to ensure the realizability and rationality of a process, a dielectric layer below the chromium-silicon thin-film resistor is usually realized by a chemical vapor deposition method, and the topmost thin film generated by the manufacturing method has the characteristics of low cost and high efficiency. The method is formed in a time period between a growth equipment deposition environment and deposition ending, and is unstable in property. Through verification, the appearance of the chromium-silicon thin-film resistor is affected absolutely due to the thermal property and the plastic instability in the subsequent manufacturing process of the thin-film resistor due to the existence of the topmost thin film, and the removal before the chromium-silicon thin-film resistor is an effective method for improving the appearance qualification rate of the chromium-silicon thin-film resistor. In the manufacturing process of the resistor, after the chemical vapor deposition of the insulating dielectric layer, a step of fluorine-containing chemical liquid treatment is added, and the surface film finally formed in the chemical vapor deposition process is removed, so that the apparent qualified rate of the chromium-silicon film resistor can be effectively improved through the treatment.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor integrated circuit manufacturing, and relates to a structure and method for improving the apparent qualified rate of chromium silicon thin film resistors. Background Art

[0002] In today's electronic components field, resistors are basic and indispensable components, with various types, each with unique performance characteristics and applicable scenarios. Among them, compared with common relative injection resistors, polycrystalline resistors, etc., chromium silicon thin film resistors stand out with their excellent performance and become the darling of high-precision analog integrated circuits.

[0003] Compared with injection resistors, there are often certain limitations in precision control. They are greatly affected by process fluctuations, and the resistance value is prone to obvious deviations during the production process, making it difficult to maintain a high-precision level. Although polycrystalline resistors have made some progress compared to some traditional resistors, their temperature drift characteristics are still not ideal. When the temperature environment changes, the resistance value will fluctuate significantly, which will affect the overall performance stability of the circuit. Chrome silicon thin film resistors are completely different. They are naturally endowed with the significant advantages of high precision, high and low temperature drift. In high-precision analog integrated circuits, the accuracy requirements for the resistance value of resistors are almost harsh. Small resistance deviations may cause error accumulation in key functions such as signal amplification and filtering, seriously affecting the accuracy of circuit output. Thanks to advanced manufacturing processes, chrome silicon thin film resistors can achieve laser burn-in (Trim) operations, just like finely "carving" the resistance value, successfully controlling the absolute accuracy at an amazing 0.01%, greatly meeting the urgent needs of high-precision analog integrated circuits for precision resistors, so they are widely used in such circuits.

[0004] However, in the production process of chromium silicon thin film resistors, there is currently a thorny problem - there are problems with the apparent pass rate, and this problem is closely related to the lack of understanding of the properties of the underlying film. Chromium silicon thin film resistors do not exist in isolation, and their underlying films play a key supporting and synergistic role. In past research and production practices, because scientific researchers and industry practitioners have not fully and deeply understood the mechanism of the influence of the properties of the underlying film on the integrity of chromium silicon thin film resistors, a series of adverse conditions have occurred frequently, seriously dragging down the apparent pass rate.

[0005] Specifically, if there are tiny impurities mixed into the material composition of the lower film, even if it is a trace amount of foreign atoms doped, it may change its lattice structure or electrical properties, and then interfere with the uniformity of the film formation of the upper chromium silicon thin film resistor, causing the resistor to have abnormal resistance in local areas, exceeding the standard tolerance range, and causing the product to be judged as unqualified. From the perspective of the physical structure of the film, if the density of the lower film is inconsistent, there are loose areas or microcracks, and in the subsequent deposition, etching and other process steps, the stress distribution will be unbalanced, which is easy to cause physical defects such as cracking and peeling of the chromium silicon film, destroying the integrity of the resistor, causing defects in the appearance, and failing to meet the quality acceptance standards. In terms of thermal performance, when the thermal expansion coefficient of the lower film does not match that of the chromium silicon film, when undergoing the heating and cooling processes in the production process, different materials will produce internal stress due to the difference in the degree of thermal expansion and contraction, which will not only distort the film morphology and cause poor appearance, but also indirectly change the resistance value of the resistor, which greatly reduces the product qualification rate. Due to the influence of various factors, the apparent pass rate of existing chromium silicon thin film resistors is in trouble. It is urgent to optimize the process and material formulation in a targeted manner to improve the overall product quality through in-depth research on the interaction between the properties of the underlying film and the chromium silicon film. Summary of the invention

[0006] The purpose of the present invention is to solve the problems in the prior art and to provide a structure and method for improving the apparent qualified rate of chromium silicon thin film resistors.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions:

[0008] The present invention proposes a structure for improving the apparent qualified rate of chromium silicon thin film resistors, comprising a substrate, a chromium silicon conductive film, a tungsten titanium conductive film and a low-resistance conductive film;

[0009] An insulating dielectric layer is provided above the substrate, the chromium silicon conductive film is located above the insulating dielectric layer, and the tungsten titanium conductive film is located above the chromium silicon conductive film; the low resistance conductive film is located above the insulating dielectric layer and the tungsten titanium conductive film.

[0010] The present invention provides a method for improving the apparent qualified rate of chromium silicon thin film resistors, comprising:

[0011] Depositing an insulating dielectric layer on the surface of the substrate, and removing the deposited film on the surface of the insulating dielectric layer;

[0012] depositing a chromium silicon conductive film and a tungsten titanium conductive film on the insulating dielectric layer;

[0013] After the chromium silicon conductive film and the tungsten titanium conductive film are subjected to photolithography and etching treatment, a low-resistance conductive film is deposited on the chromium silicon conductive film and the tungsten titanium conductive film;

[0014] After the low-resistance conductive film is subjected to photolithography and etching, the tungsten-titanium conductive film is self-alignedly etched to improve the apparent qualified rate of chromium silicon thin film resistors.

[0015] Preferably, the step of depositing an insulating dielectric layer on the surface of the substrate comprises:

[0016] The substrate is cleaned by RCA and then centrifuged or dried by IPA;

[0017] Depositing an insulating dielectric layer on the surface of the substrate by using normal pressure chemical vapor deposition, low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition;

[0018] Wherein, the thickness of the substrate is 400 microns to 1500 microns;

[0019] The deposition temperature is 350° C. to 500° C., the pressure is 2 Torr to 1 atm, and the thickness of the deposited film deposited on the insulating dielectric layer is 5000 angstroms to 20000 angstroms.

[0020] Preferably, the removing of the deposited film on the surface of the insulating dielectric layer comprises:

[0021] The deposited film is silicon dioxide, silicon nitride or silicon oxynitride;

[0022] When the deposited film is silicon dioxide or silicon oxynitride, a fluorine-containing etching solution with a high fluorine content is used as a cleaning solution to remove the deposited film on the surface of the insulating dielectric layer;

[0023] When the deposited film is silicon nitride, hot phosphoric acid or fluorine-containing etching solution is used as a cleaning solution to remove the deposited film on the surface of the insulating dielectric layer;

[0024] The thickness of the removed deposited film is greater than 100 angstroms.

[0025] Preferably, the step of depositing a chromium silicon conductive film and a tungsten titanium conductive film on the insulating dielectric layer is specifically as follows:

[0026] Depositing a chromium silicon conductive film on the insulating dielectric layer by magnetron sputtering, wherein the thickness of the deposited chromium silicon conductive film is 30 angstroms to 500 angstroms;

[0027] A tungsten-titanium conductive film is deposited on the chromium-silicon conductive film by magnetron sputtering, and the thickness of the tungsten-titanium conductive film is 500 angstroms to 2000 angstroms.

[0028] Preferably, during the deposition process, the sputtering temperature of the silicon conductive film is 20°C to 300°C; the sputtering argon flow rate is 30sccm to 200sccm, the sputtering nitrogen flow rate is 5sccm to 100sccm, and the sputtering power is 100W to 1000W; the sputtering temperature of the tungsten-titanium conductive film is 20°C to 300°C, the sputtering argon flow rate is 50sccm to 200sccm, and the sputtering power is 1000W to 6000W.

[0029] Preferably, the step of depositing a low-resistance conductive film on the chromium-silicon conductive film and the tungsten-titanium conductive film comprises:

[0030] When a low-resistance conductive film is deposited on a chromium-silicon conductive film and a tungsten-titanium conductive film, the sputtering temperature is 20° C. to 500° C.; the sputtering argon gas flow rate is 30 sccm to 200 sccm; and the sputtering power is 6000W to 12000W.

[0031] Preferably, photolithography is achieved by means of coating, exposure and development.

[0032] Preferably, after the chromium silicon conductive film and the tungsten titanium conductive film are subjected to photolithography and etching, the following steps are specifically performed:

[0033] After photolithography, tungsten titanium is etched with hydrogen peroxide at a temperature of 60°C to 80°C and a time of about 30s to 3min.

[0034] Then, the chromium silicon is etched by RIE dry etcher, the etching time is about 30s to 3min, the etching gas is trichlorosilane and oxygen, and the etching power is 100W to 600W.

[0035] Preferably, after the low-resistance conductive film is subjected to photolithography and etching, the tungsten-titanium conductive film is subjected to self-aligned etching to improve the apparent qualified rate of the chromium-silicon thin film resistor, specifically:

[0036] After photolithography, the low-resistance conductive film is corroded by aluminum etching solution at a temperature of 40°C to 50°C for 3min to 20min; the tungsten-titanium conductive film is then corroded by hydrogen peroxide at a temperature of 60°C to 80°C for about 30s to 3min.

[0037] Compared with the prior art, the present invention has the following beneficial effects:

[0038] The structure of the apparent qualified rate of a chromium silicon thin film resistor proposed by the present invention, first, the substrate provides a stable basic support for the entire structure, ensuring the flatness and uniformity of the subsequent film growth. The insulating dielectric layer is on the substrate, which plays a role of isolation and protection. On the one hand, it prevents impurities in the substrate from diffusing into the chromium silicon conductive film, avoids the abnormal local conductive performance caused by the introduction of impurities, thereby improving the quality and performance stability of the chromium silicon conductive film, and helps to improve the qualified rate. On the other hand, it provides a good interface for the growth of the chromium silicon conductive film, so that the chromium silicon conductive film can be deposited more evenly, reducing film defects, and thus improving the apparent qualified rate. The chromium silicon conductive film is the core resistor functional layer, and its performance directly affects the overall performance of the resistor. By growing on the insulating dielectric layer, a higher quality film can be obtained, and the subsequent tungsten titanium conductive film is covered on it, forming a good contact and synergy between the two, optimizing the current transmission path, reducing the resistance value deviation or instability caused by interface problems, and improving the consistency and qualified rate of the product. The tungsten titanium conductive film not only improves the contact performance with the chromium silicon conductive film, but also protects and enhances the chromium silicon conductive film to a certain extent. It can prevent the direct impact of external factors on the chromium silicon conductive film, such as oxidation and corrosion, thereby maintaining the stable performance of the chromium silicon conductive film and helping to improve the apparent pass rate of the entire resistor. The low-resistance conductive film is located above the insulating dielectric layer and the tungsten titanium conductive film, and it plays several important roles. First, as a surface protective coating, it prevents external mechanical damage, chemical pollution, etc. from damaging the underlying film during subsequent processing, testing or use, thereby reducing the number of unqualified products caused by surface damage. Second, its low-resistance characteristics help to further optimize the electrical performance of the entire resistor structure, allowing the resistor to work more stably under different working conditions, improving the reliability and pass rate of the product.

[0039] Furthermore, to ensure the feasibility and rationality of the process, the dielectric layer below the chrome silicon thin film resistor is usually realized by chemical vapor deposition. The top film generated by this type of manufacturing method is formed between the deposition environment of the growth equipment and the end of the deposition, and its properties are unstable. It has been verified that the existence of the top film will have an absolute impact on the appearance of the chrome silicon thin film resistor due to the thermal and plastic instability of its properties during the subsequent thin film resistor manufacturing process. Removing it before the chrome silicon thin film resistor is an effective way to improve the apparent pass rate of the chrome silicon thin film resistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0041] Figure 1 It is a schematic diagram of the dielectric layer deposition of the present invention.

[0042] Figure 2 It is a schematic diagram of the surface removal of the dielectric layer of the present invention.

[0043] Figure 3 It is a schematic diagram of the structure of the chromium silicon thin film resistor device of the present invention.

[0044] Among them: 1-substrate, 2-insulating dielectric layer, 3-chromium silicon conductive film, 4-tungsten titanium conductive film, 5-low resistance conductor film, 6-deposited film. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0046] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0047] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0048] In the description of the embodiments of the present invention, it should be noted that if the terms "upper", "lower", "horizontal", "inner", etc. indicate an orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the invention is usually placed when in use, it is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0049] In addition, if the term "horizontal" appears, it does not mean that the component is required to be absolutely horizontal, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", which does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0050] In the description of the embodiments of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0051] The present invention is further described in detail below in conjunction with the accompanying drawings:

[0052] The present invention proposes a structure for improving the apparent qualified rate of chromium silicon thin film resistors, such as Figures 1 to 3 As shown, it includes a substrate 1, a chromium silicon conductive film 3, a tungsten titanium conductive film 4 and a low resistance conductive film 5;

[0053] An insulating dielectric layer 2 is provided above the substrate 1, the chromium silicon conductive film 3 is located above the insulating dielectric layer 2, and the tungsten titanium conductive film 4 is located above the chromium silicon conductive film 3; the low-resistance conductive film 5 is located above the insulating dielectric layer 2 and the tungsten titanium conductive film 4.

[0054] The present invention provides a method for improving the apparent qualified rate of chromium silicon thin film resistors, comprising the following steps:

[0055] Step 1, depositing an insulating dielectric layer 2 on the surface of a substrate 1;

[0056] 1.1. Pretreatment of substrate 1:

[0057] The thickness of the substrate 1 is between 400 micrometers and 1500 micrometers. The substrate 1 is cleaned by RCA cleaning and then centrifugally dried or IPA dried.

[0058] 1.2. Deposition of dielectric layer 2:

[0059] The insulating dielectric layer 2 is deposited on the surface of the substrate 1 by normal pressure chemical vapor deposition, low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition;

[0060] The deposition temperature is 350°C to 500°C, the pressure is 2 Torr to 1 atm, the RF power is 80W to 1000W, and the thickness of the deposited film 6 is 5000 angstroms to 20000 angstroms. The substrate 1 can be a ceramic sheet. <100> Crystalline silicon wafer or <111> Crystalline silicon wafer.

[0061] Step 2, removing the deposited film 6 on the surface of the dielectric layer 2; the deposited film 6 is silicon dioxide, silicon nitride or silicon oxynitride;

[0062] When the deposited film 6 is silicon dioxide or silicon oxynitride, the cleaning liquid for removing the deposited film 6 on the surface of the dielectric layer 2 is a fluorine-containing etching liquid containing a certain proportion of fluorine;

[0063] When the deposited film 6 is silicon nitride, the cleaning liquid for removing the deposited film 6 on the surface of the dielectric layer 2 is hot phosphoric acid or a fluorine-containing etching solution.

[0064] When removing the deposited film 6 on the surface of the dielectric layer 2, the amount of the deposited film 6 removed from the surface of the dielectric layer 2 needs to be greater than 100 angstroms, and the removal method needs to be wet liquid treatment removal. The concentration of the cleaning solution can be adjusted, but it is necessary to ensure that the etching time of 10 seconds to 10 minutes can achieve a removal amount of more than 100 angstroms.

[0065] Step 3, depositing a chromium silicon conductive film 3 and a tungsten titanium conductive film 4 on the insulating dielectric layer 2, performing photolithography, and then etching the tungsten titanium first, and then etching the chromium silicon;

[0066] A chromium silicon conductive film 3 is deposited on the insulating dielectric layer 2 by magnetron sputtering, wherein the thickness of the chromium silicon conductive film 3 is 30 angstroms to 500 angstroms. The parameters involved in the deposition process are mainly sputtering temperature, sputtering gas flow rate and sputtering power. The sputtering temperature is from 20°C to 300°C; the sputtering gas flow rate includes argon flow rate of 30sccm to 200sccm and nitrogen flow rate of 5sccm to 100sccm; the sputtering power is 100W to 1000W.

[0067] A tungsten-titanium conductive film 4 is deposited on the chromium-silicon conductive film 3 by magnetron sputtering, wherein the thickness of the tungsten-titanium conductive film 4 is 500 angstroms to 2000 angstroms; the sputtering temperature of the tungsten-titanium conductive film 4 is from 20°C to 300°C; the sputtering gas flow rate includes an argon gas flow rate of 50sccm to 200sccm; and the sputtering power is 1000W to 6000W.

[0068] Photolithography is achieved by coating, exposing and developing. The final pattern of the photoresist is the pattern of the resistor. After photolithography, tungsten titanium is etched by 100% hydrogen peroxide, the corrosion temperature is 60℃~80℃, and the corrosion time is about 30s~3min. Then, chromium silicon is etched by RIE dry etcher, the corrosion time is about 30 seconds to 3 minutes, the corrosion gas is trichlorosilane and oxygen, and the power is 100W to 600W. After completion, the photoresist is removed.

[0069] The chromium silicon conductive film 3 is a chromium silicon group metal. The tungsten titanium conductive film 4 is a tungsten titanium metal.

[0070] Step 4, depositing a low-resistance conductive film 5 on the chrome silicon conductive film 3 and the tungsten titanium conductive film 4; after photolithography and etching of the low-resistance conductive film 5, self-aligned etching of the tungsten titanium conductive film 4 is performed to improve the apparent qualified rate of the chrome silicon thin film resistor;

[0071] The low-resistance conductive film 5 is an aluminum alloy or pure aluminum, and is deposited using a metal magnetron sputtering device. The parameters involved in the deposition process are mainly sputtering temperature, sputtering gas flow rate, and sputtering power. The sputtering temperature is from 20°C to 500°C; the sputtering gas flow rate includes an argon gas flow rate of 30sccm to 200sccm, and the sputtering power is 6000W to 12000W. The thickness of the low-resistance conductive film 5 is 5000 angstroms to 40000 angstroms.

[0072] The photolithography of the resistor is realized by coating, exposure and development. After photolithography, the low-resistance conductive film 5 is corroded by a common aluminum etching solution at a temperature of 40°C to 50°C, and the etching time is about 3min to 20min depending on the composition and thickness of the aluminum. After completion, the photoresist is removed. Then, the tungsten-titanium conductive film 4 is corroded by 100% hydrogen peroxide at a temperature of 60°C to 80°C, and the etching time is about 30s to 3min.

[0073] Example 1

[0074] Step 1: After RCA cleaning of a 1500 micron substrate 1, a 20,000 angstrom plasma enhanced chemical vapor deposition silicon nitride layer is deposited on the surface by centrifugal drying. The deposition temperature is 390° C., the pressure is 2 Torr, and the RF power is 350W.

[0075] Step 2: Use 10:1 hydrofluoric acid at 30°C for 10 minutes to remove about 150 angstroms of silicon nitride;

[0076] Step 3, depositing a chromium silicon conductive film 3 and a tungsten titanium conductive film 4 on the insulating dielectric layer 2;

[0077] A 500 angstrom chromium silicon conductive film 3 and a 2000 angstrom tungsten titanium conductive film 4 are deposited on the insulating dielectric layer 2 by magnetron sputtering. The sputtering temperature of the chromium silicon conductive film 3 is 20°C; the argon flow rate is 200 sccm, the nitrogen flow rate is 5 sccm; and the sputtering power is 1000 W. The sputtering temperature of the tungsten titanium conductive film 4 is 20°C; the argon flow rate is 200 sccm in the sputtering gas flow rate, and the sputtering power is 6000 W.

[0078] Step 4: Resistor photolithography and etching;

[0079] The photolithography of the resistor is achieved by coating, exposure and development. After photolithography, tungsten titanium is etched by 100% hydrogen peroxide at a temperature of 80°C for about 1 minute. Then, chromium silicon is etched by RIE dry etcher for about 3 minutes. The etching gas is trichlorosilane and oxygen at a power of 300 watts. After completion, the photoresist is removed.

[0080] Step 5, low resistance conductive film 5 is deposited;

[0081] The low-resistance conductive film 5 used is pure aluminum with a thickness of 40,000 angstroms, and is deposited using a metal magnetron sputtering device. The sputtering temperature is 25° C., the sputtering argon gas flow rate is 200 sccm, and the sputtering power is 6000W.

[0082] Step 6: Photolithography and etching of the low-resistance conductive film 5.

[0083] The photolithography of metal wiring is achieved by coating, exposure and development; after photolithography, it is etched by common aluminum etching solution, the etching temperature is 42℃, and the etching time is 20 minutes. After completion, the photoresist is removed. Tungsten titanium is etched by 100% hydrogen peroxide for cleaning, the etching temperature is 80℃, and the etching time is about 1 minute.

[0084] Example 2

[0085] Step 1: 675 micron thick <100> 8~13Ω.cm 6-inch substrate 1 is cleaned by RCA and dried by IPA. A layer of 5000 angstroms of plasma enhanced chemical vapor deposition silicon dioxide is deposited on the surface at a deposition temperature of 400°C and a pressure of 3.2 Torr.

[0086] Step 2: Use 25°C 50:1 HF for 3 minutes to remove about 300 angstroms of silicon dioxide;

[0087] Step 3, depositing a chromium silicon conductive film 3 and a tungsten titanium conductive film 4 on the insulating dielectric layer 2;

[0088] A 100 angstrom chromium silicon conductive film 3 and a 1000 angstrom tungsten titanium conductive film 4 are deposited on the insulating dielectric layer 2 by magnetron sputtering. The sputtering temperature of the chromium silicon conductive film 3 is 200°C; the argon flow rate is 50 sccm, the nitrogen flow rate is 10 sccm; and the sputtering power is 300W. The sputtering temperature of the tungsten titanium conductive film 4 is 90°C; the sputtering gas flow rate is 75 sccm, and the sputtering power is 3000W.

[0089] Step 4: Resistor photolithography and etching;

[0090] The photolithography of the resistor is achieved by coating, exposure and development. After photolithography, tungsten titanium is etched by 100% hydrogen peroxide at a temperature of 60°C for about 2 minutes. Then, chromium silicon is etched by RIE dry etcher for about 3 minutes. The etching gas is trichlorosilane and oxygen at a power of 150 watts. After completion, the photoresist is removed.

[0091] Step 5, low resistance conductive film 5 is deposited;

[0092] The low-resistance conductive film 5 used is an aluminum-silicon-copper alloy with a thickness of 15,000 angstroms, and is deposited using a metal magnetron sputtering device with a sputtering temperature of 300° C., a sputtering argon gas flow rate of 44 sccm, and a sputtering power of 9,000 W.

[0093] Step 6: Photolithography and etching of metal connections.

[0094] The photolithography of metal wiring is achieved by coating, exposure and development. After photolithography, it is etched by common aluminum etching solution at a temperature of 42°C and a corrosion time of 5 minutes. After completion, the photoresist is removed. Tungsten titanium is cleaned by etching with 100% hydrogen peroxide at a temperature of 60°C and a corrosion time of about 2 minutes.

[0095] Example 3

[0096] Step 1: 400 micron thick <111> 8~13Ω.cm The 6-inch substrate 1 is cleaned by RCA and then dried by IPA. A layer of 20,000 angstroms of plasma enhanced chemical vapor deposition silicon oxynitride is deposited on the surface at a deposition temperature of 500°C and a pressure of 5 Torr.

[0097] Step 2: Use 25°C 50:1 HF for 8 minutes to remove about 300 angstroms of silicon dioxide;

[0098] Step 3, depositing a chromium silicon conductive film 3 and a tungsten titanium conductive film 4 on the insulating dielectric layer 2;

[0099] A 30 angstrom chromium silicon conductive film 3 and a 1500 angstrom tungsten titanium conductive film 4 are deposited on the insulating dielectric layer 2 by magnetron sputtering. The sputtering temperature of the chromium silicon conductive film 3 is 150°C; the argon flow rate is 50 sccm, the nitrogen flow rate is 4 sccm; and the sputtering power is 200W. The sputtering temperature of the tungsten titanium conductive film 4 is 65°C; the sputtering gas flow rate is 1000 sccm, and the sputtering power is 6000W.

[0100] Step 4: Resistor photolithography and etching;

[0101] The photolithography of the resistor is achieved by coating, exposure and development. After photolithography, tungsten titanium is etched by 100% hydrogen peroxide at a temperature of 60°C for about 1.5 minutes. Then, chromium silicon is etched by RIE dry etcher for about 0.5 minutes. The etching gas is trichlorosilane and oxygen at a power of 100 watts. After completion, the photoresist is removed.

[0102] Step 5, low resistance conductive film 5 is deposited;

[0103] The low-resistance conductive film 5 used is an aluminum-silicon-copper alloy with a thickness of 5000 angstroms, and is deposited using a metal magnetron sputtering device with a sputtering temperature of 300° C., a sputtering argon gas flow rate of 70 sccm, and a sputtering power of 6000W.

[0104] Step 6: Photolithography and etching of metal connections.

[0105] The photolithography of metal wiring is achieved by coating, exposure and development. After photolithography, it is etched by common aluminum etching solution at a temperature of 42°C and a etching time of 2 minutes. After completion, the photoresist is removed. Tungsten titanium is cleaned by etching with 100% hydrogen peroxide at a temperature of 60°C and a etching time of about 1.5 minutes.

[0106] The present invention proposes a method for improving the apparent qualified rate of chromium silicon thin film resistors. In order to ensure the feasibility and rationality of the process, the dielectric layer below the chromium silicon thin film resistor is usually realized by a chemical vapor deposition method. The top-layer film generated by this type of manufacturing method is formed in the period between the deposition environment of the growth equipment and the end of the deposition, and its properties are unstable. It has been verified that the existence of the top-layer film will have an absolute impact on the appearance of the chromium silicon thin film resistor due to the thermal and plastic instability of the properties in the subsequent thin film resistor manufacturing process. Removing it before the chromium silicon thin film resistor is an effective method to improve the apparent qualified rate of the chromium silicon thin film resistor. The present invention removes the unstable layer that inevitably grows when the deposition of the insulating medium finally stops, so that the unstable dielectric layer will not affect the subsequent quality of the chromium silicon thin film resistor, and the improvement of the surface qualified rate is unique and effective. This treatment does not add unnecessary lithography and degumming processes, and does not increase the complexity of the manufacturing process.

[0107] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A structure for improving the apparent qualified rate of chromium silicon thin film resistors, characterized in that: It comprises a substrate (1), a chromium silicon conductive film (3), a tungsten titanium conductive film (4) and a low resistance conductive film (5); An insulating dielectric layer (2) is provided above the substrate (1); the chromium silicon conductive film (3) is located above the insulating dielectric layer (2); the tungsten titanium conductive film (4) is located above the chromium silicon conductive film (3); and the low-resistance conductive film (5) is located above the insulating dielectric layer (2) and the tungsten titanium conductive film (4).

2. A method for improving the apparent qualified rate of chromium silicon thin film resistors, characterized in that: The structure for improving the apparent qualified rate of chromium silicon thin film resistors according to claim 1 comprises: Depositing an insulating dielectric layer (2) on the surface of a substrate (1), and removing a deposited thin film (6) on the surface of the insulating dielectric layer (2); Depositing a chromium silicon conductive film (3) and a tungsten titanium conductive film (4) on the insulating dielectric layer (2); After photolithography and etching are performed on the chromium silicon conductive film (3) and the tungsten titanium conductive film (4), a low-resistance conductive film (5) is deposited on the chromium silicon conductive film (3) and the tungsten titanium conductive film (4); After the low-resistance conductive film (5) is subjected to photolithography and etching, the tungsten-titanium conductive film (4) is subjected to self-alignment etching, thereby achieving an improvement in the apparent qualified rate of the chromium silicon thin film resistor.

3. The method for improving the apparent qualified rate of chromium silicon thin film resistors according to claim 2, characterized in that: The step of depositing an insulating dielectric layer (2) on the surface of the substrate (1) specifically comprises: The substrate (1) is cleaned by RCA and then dried by centrifugation or IPA; Depositing an insulating dielectric layer (2) on the surface of a substrate (1) by using normal pressure chemical vapor deposition, low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition; Wherein, the thickness of the substrate (1) is 400 micrometers to 1500 micrometers; The deposition temperature is 350° C. to 500° C., the pressure is 2 Torr to 1 atm, and the thickness of the deposited film (6) deposited on the insulating dielectric layer (2) is 5000 angstroms to 20000 angstroms.

4. The method for improving the apparent qualified rate of chromium silicon thin film resistors according to claim 2, characterized in that: The step of removing the deposited film (6) on the surface of the insulating dielectric layer (2) is specifically: The deposited film (6) is silicon dioxide, silicon nitride or silicon oxynitride; When the deposited film (6) is silicon dioxide or silicon oxynitride, a fluorine-containing etching solution with a high fluorine content is used as a cleaning solution to remove the deposited film (6) on the surface of the insulating dielectric layer (2); When the deposited film (6) is silicon nitride, hot phosphoric acid or a fluorine-containing etching solution is used as a cleaning solution to remove the deposited film (6) on the surface of the insulating dielectric layer (2); The thickness of the removed deposited film (6) is greater than 100 angstroms.

5. The method for improving the apparent qualified rate of chromium silicon thin film resistors according to claim 2, characterized in that: The step of depositing a chromium silicon conductive film (3) and a tungsten titanium conductive film (4) on the insulating dielectric layer (2) is specifically as follows: Depositing a chromium silicon conductive film (3) on the insulating dielectric layer (2) by magnetron sputtering, wherein the thickness of the deposited chromium silicon conductive film (3) is 30 angstroms to 500 angstroms; A tungsten-titanium conductive film (4) is deposited on a chromium-silicon conductive film (3) by magnetron sputtering, and the thickness of the tungsten-titanium conductive film (4) is 500 angstroms to 2000 angstroms.

6. The method for improving the apparent qualified rate of chromium silicon thin film resistors according to claim 5, characterized in that: During the deposition process, the sputtering temperature of the silicon conductive film (3) is 20°C to 300°C; the sputtering argon gas flow rate is 30sccm to 200sccm, the sputtering nitrogen gas flow rate is 5sccm to 100sccm, and the sputtering power is 100W to 1000W; the sputtering temperature of the tungsten titanium conductive film (4) is 20°C to 300°C, the sputtering argon gas flow rate is 50sccm to 200sccm, and the sputtering power is 1000W to 6000W.

7. The method for improving the apparent qualified rate of chromium silicon thin film resistors according to claim 2, characterized in that: The step of depositing a low-resistance conductive film (5) on the chromium-silicon conductive film (3) and the tungsten-titanium conductive film (4) is specifically as follows: When a low-resistance conductive film (5) is deposited on a chromium silicon conductive film (3) and a tungsten titanium conductive film (4), the sputtering temperature is 20°C to 500°C; the sputtering argon gas flow rate is 30sccm to 200sccm, and the sputtering power is 6000W to 12000W.

8. The method for improving the apparent qualified rate of chromium silicon thin film resistors according to claim 2, characterized in that: Photolithography is achieved through coating, exposure and development.

9. The method for improving the apparent qualified rate of chromium silicon thin film resistors according to claim 2, characterized in that: After the chromium silicon conductive film (3) and the tungsten titanium conductive film (4) are subjected to photolithography and etching, the following steps are specifically performed: After photolithography, tungsten titanium is etched with hydrogen peroxide at a temperature of 60°C to 80°C and a time of about 30s to 3min. Then, the chromium silicon is etched by RIE dry etcher, the etching time is about 30s to 3min, the etching gas is trichlorosilane and oxygen, and the etching power is 100W to 600W.

10. The method for improving the apparent qualified rate of chromium silicon thin film resistors according to claim 2, characterized in that: After the low-resistance conductive film (5) is subjected to photolithography and etching, the tungsten-titanium conductive film (4) is subjected to self-aligned etching to improve the apparent qualified rate of the chromium-silicon thin film resistor, specifically: After photolithography, the low-resistance conductive film (5) is etched by aluminum etching solution at a temperature of 40°C to 50°C for 3 minutes to 20 minutes; and the tungsten-titanium conductive film (4) is then etched by hydrogen peroxide at a temperature of 60°C to 80°C for about 30 seconds to 3 minutes.

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