Preparation method of semiconductor film

Abstract

The invention provides a preparation method of a semiconductor film, and the method comprises the steps: limiting the range of a porous structure formed on the surface of a transfer substrate in a graphical doped region of a second semiconductor layer when an epitaxial semiconductor layer is formed through the combination of a homoepitaxial technology and a heteroepitaxial technology; the second semiconductor layer is provided with a patterned doped region, so that defects in the porous structure are effectively prevented from expanding into a lattice structure of the epitaxial semiconductor layer, meanwhile, except the patterned doped region, other undoped regions of the second semiconductor layer still keep an original single-crystal structure, and when the epitaxial semiconductor layer is formed above the second semiconductor layer, the epitaxial quality is relatively high, and the yield is relatively high. In addition, thermal stress mismatch does not exist in the preparation process, the probability that the semiconductor film is damaged and lattice defects are generated is reduced, and the quality of the prepared semiconductor film is further improved.

Description

Technical Field

[0001] The invention relates to the technical field of thin film preparation, and in particular to a method for preparing a semiconductor thin film. Background Art

[0002] As the semiconductor industry pursues increasingly higher data transmission speed, integration density, power consumption, etc. of devices / chips, researchers need to provide new chip integration solutions to achieve high performance, high integration, low power consumption, high power and other chip technologies. Material quality is the guarantee of chip performance improvement, so the development of high-quality semiconductor film preparation technology is particularly critical.

[0003] At present, semiconductor devices are often prepared on epitaxial semiconductor films, and the epitaxial process, as an important semiconductor film material preparation technology, can be widely used in the preparation of SOI substrates, III-V semiconductor films, and II-VI semiconductor films. After the epitaxial growth of the semiconductor film is completed, the ion stripping method can be used to peel and transfer it, but this method has a large thermal budget. When preparing some semiconductor films, such as GaN, AlN and other materials, it faces poor process compatibility and high process costs. There is also a thermal stress mismatch between the heterogeneous epitaxial layer and the heterogeneous substrate, which can easily cause substrate warping, damage to the semiconductor film, and lattice defects. The quality of the formed semiconductor film is greatly deteriorated, thereby reducing the life of the semiconductor device prepared with the semiconductor film and affecting the reliability of the semiconductor device. In addition, the method of grinding the wafer substrate after bonding can also be used to prepare and transfer semiconductor films, but this method has high process costs and poor uniformity of semiconductor film thickness.

[0004] Therefore, it is necessary to develop a method for preparing semiconductor thin films with low process cost and higher process reliability. Summary of the invention

[0005] In view of the shortcomings of the prior art mentioned above, the object of the present invention is to provide a method for preparing a semiconductor thin film, which is used to solve the problems existing in the existing transfer technology, such as high manufacturing cost, great process difficulty, and substrate warping easily caused by thermal stress mismatch, which causes damage to the semiconductor film and lattice defects, making it difficult to prepare high-quality semiconductor films.

[0006] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a semiconductor thin film, the method for preparing a semiconductor thin film comprising the following steps:

[0007] Providing a transfer substrate, the transfer substrate having a first surface and a second surface arranged opposite to each other, and forming a first semiconductor layer on the first surface of the transfer substrate;

[0008] forming a patterned second semiconductor layer on the surface of the first semiconductor layer;

[0009] Performing an electrochemical etching process on the first semiconductor layer and the second semiconductor layer to form a porous structure in the first semiconductor layer and the second semiconductor layer;

[0010] forming an epitaxial semiconductor layer on the second semiconductor layer, wherein the epitaxial semiconductor layer includes a homoepitaxial layer and / or a heteroepitaxial layer;

[0011] Providing a supporting substrate, and performing a bonding process on the supporting substrate and the epitaxial semiconductor layer to form a temporary bonding substrate;

[0012] Using a cracking process on the temporary bonding substrate, so that the temporary bonding substrate is cracked laterally along the first semiconductor layer to obtain a bonding substrate containing the epitaxial semiconductor layer and the second semiconductor layer;

[0013] The bonded substrate is subjected to a surface treatment process to remove the second semiconductor layer, and the epitaxial semiconductor layer is subjected to a thinning, polishing and specific atmosphere annealing process to obtain the semiconductor film.

[0014] Optionally, the specific steps of forming the patterned second semiconductor layer include: forming a patterned mask on the surface of the first semiconductor layer, the patterned mask exposing a portion of the first semiconductor layer, performing selective epitaxy on the exposed portion of the surface of the first semiconductor layer, and then removing the patterned mask to form a patterned second semiconductor layer exposing a portion of the surface of the first semiconductor layer; or, forming a patterned mask on the surface of the second semiconductor layer, performing an etching process along the patterned mask to remove a portion of the second semiconductor layer, and further removing the patterned mask to form a patterned second semiconductor layer; or, A patterned mask is formed on the surface of the body layer, and a doping process is performed on the second semiconductor layer along the patterned mask to form a patterned doped region in the second semiconductor layer, and the patterned doped region and the undoped region together constitute the patterned second semiconductor layer; or, a patterned mask structure is formed on the surface of the second semiconductor layer, and an electrochemical etching process is performed on the second semiconductor layer, and the patterned mask structure can protect the second semiconductor layer located below the patterned mask structure from being corroded by the electrochemical etching process, and the electrochemically corroded region and the non-electrochemically corroded region together constitute the patterned second semiconductor layer.

[0015] Optionally, the ion doping concentration in the first semiconductor layer and in the patterned doped regions of the second semiconductor layer is at least 10 times the ion doping concentration in the unpatterned doped regions of the second semiconductor layer.

[0016] Optionally, when the first semiconductor layer is P-type doped, the doping type of the unpatterned doped area in the second semiconductor layer is N-type doping, P-type doping or undoped; when the first semiconductor layer is N-type doped, the doping type of the unpatterned doped area in the second semiconductor layer is only N-type doping or undoped.

[0017] Optionally, the process of forming the first semiconductor layer includes at least one of a diffusion process, an ion implantation process, and an in-situ doping epitaxial process.

[0018] Optionally, before the support substrate is bonded to the epitaxial semiconductor layer, the method further includes forming a bonding intercalation layer on the first surface of the support substrate or on the epitaxial semiconductor layer.

[0019] Optionally, the bonding intercalation layer includes at least one of a single crystal semiconductor layer, a polycrystalline semiconductor layer, an amorphous material layer, an insulating dielectric layer, a piezoelectric material layer, a metal layer, and a compound conductive layer.

[0020] Optionally, before forming a temporary bonding substrate, a step of forming a patterned cavity structure is also included, wherein the patterned cavity structure can be completely located in the bonding intercalation layer in the depth direction, or span the interface between the bonding intercalation layer and the supporting substrate, or span the interface between the bonding intercalation layer and the semiconductor thin film layer, or be completely located in the supporting substrate and connected to the bonding intercalation layer.

[0021] Optionally, the bonding process for forming the temporary bonding substrate includes at least one of a hydrophilic bonding process, a thermal compression bonding process, a surface plasma activation bonding process or an anodic bonding process.

[0022] Optionally, the cracking process includes at least one of a thermal stress cracking process, a crystal stress cracking process, an ultrasonic energy cracking process, a laser cracking process, a water flow impact cracking process, and a cleaver insertion cracking process.

[0023] Optionally, the specific steps of forming the epitaxial semiconductor layer include: performing a homoepitaxial process on the surface of the second semiconductor layer to form a homoepitaxial layer, performing surface smoothing on the homoepitaxial layer, and then performing a heteroepitaxial process on the surface of the homoepitaxial layer to form a heteroepitaxial layer, wherein the heteroepitaxial layer covers the homoepitaxial layer.

[0024] Optionally, after the temporary bonding substrate is laterally cleaved along the first semiconductor layer, the step further includes performing at least one of thinning, polishing, homoepitaxial growth or heteroepitaxial growth on the epitaxial semiconductor layer.

[0025] As described above, the method for preparing a semiconductor film of the present invention has the following beneficial effects: when forming an epitaxial semiconductor layer, by limiting the range of the porous structure formed on the surface of the transfer substrate to the patterned doped region of the second semiconductor layer, the defects in the porous structure can be effectively suppressed from extending to the lattice structure of the epitaxial semiconductor layer. At the same time, except for the patterned doped region, other undoped regions of the second semiconductor layer still maintain the original single crystal structure. When an epitaxial semiconductor layer is formed above the second semiconductor layer, the quality of the epitaxy is high, thereby obtaining a high-quality semiconductor film. In addition, the preparation method combines a homoepitaxial process with a heteroepitaxial process, so that there is no thermal stress mismatch in the preparation process of the semiconductor film, reducing the probability of semiconductor film damage and lattice defects, and further improving the quality of the prepared semiconductor film. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Shown is a process flow chart of the method for preparing the semiconductor thin film provided by the present invention.

[0027] Figures 2 to 12 Shown is a schematic diagram of the cross-sectional structure corresponding to each step in the method for preparing a semiconductor thin film provided by the present invention.

[0028] Component number description

[0029] 10. Transfer substrate; 101. First surface; 102. Second surface; 11. First semiconductor layer; 12. Second semiconductor layer; 13. Epitaxial semiconductor layer; 131. Homoepitaxial layer; 132. Heteroepitaxial layer; 14. Support substrate; 15. Bonding intercalation layer; 16. Patterned cavity structure; 17. Temporary bonding substrate; S1~S7: steps. DETAILED DESCRIPTION

[0030] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0031] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the schematic diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0032] For convenience of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings.

[0033] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0034] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0035] The present invention provides a method for preparing a semiconductor thin film, such as Figure 1 As shown, it is a process flow chart of the method for preparing the semiconductor thin film, which includes the following steps:

[0036] S1: providing a transfer substrate 10, wherein the transfer substrate 10 has a first surface 101 and a second surface 102 arranged opposite to each other, and forming a first semiconductor layer 11 on the first surface 101 of the transfer substrate 10;

[0037] S2: forming a patterned second semiconductor layer 12 on the surface of the first semiconductor layer 11;

[0038] S3: performing an electrochemical etching process on the first semiconductor layer 11 and the second semiconductor layer 12 to form a porous structure in the first semiconductor layer 11 and the second semiconductor layer 12;

[0039] S4: forming an epitaxial semiconductor layer 13 on the second semiconductor layer 12, wherein the epitaxial semiconductor layer 13 includes a homoepitaxial layer 131 and / or a heteroepitaxial layer 132;

[0040] S5: providing a support substrate 14, and performing a bonding process on the support substrate 14 and the epitaxial semiconductor layer 13 to form a temporary bonding substrate 17;

[0041] S6: using a cracking process on the temporary bonding substrate 17, so that the temporary bonding substrate 17 is cracked laterally along the first semiconductor layer 11, to obtain a bonding substrate containing the epitaxial semiconductor layer 13 and the second semiconductor layer 12;

[0042] S7: performing a surface treatment process on the bonded substrate to remove the second semiconductor layer 12 .

[0043] The following is a further introduction to the method for preparing the semiconductor thin film in conjunction with the accompanying drawings. It should be noted that the above sequence does not strictly represent the sequence of the method for preparing the semiconductor thin film protected by the present invention, and those skilled in the art may change it according to the actual preparation steps. The following is a further introduction to the method for preparing the semiconductor thin film in conjunction with the accompanying drawings, as follows:

[0044] In step S1, see Figure 1 and Figure 2 , a transfer substrate 10 is provided, wherein the transfer substrate 10 has a first surface 101 and a second surface 102 which are opposite to each other, and a first semiconductor layer 11 is formed on the first surface 101 of the transfer substrate 10 .

[0045] As an example, Figure 2 As shown in FIG. 1 , the transfer substrate 10 has a first surface 101 and a second surface 102 that are arranged opposite to each other. Optionally, the transfer substrate 10 is a wafer-type substrate, and its size specification can be set to be the same as a 6-inch, 8-inch or 12-inch wafer commonly used in integrated circuit manufacturing, so that the semiconductor thin film preparation method of the present invention can be integrated into an existing integrated circuit production line and realize mass production of related devices.

[0046] Optionally, the material of the transfer substrate 10 may be a silicon-based material, such as a silicon wafer, silicon carbide or silicon oxide. In addition, the material of the transfer substrate 10 may also include any one of single crystal sapphire, aluminum nitride, gallium nitride, gallium arsenide, indium arsenide, indium phosphide and quartz or a combination of multiple materials, which are not particularly limited herein. In this embodiment, the transfer substrate 10 is a wafer substrate formed of single crystal silicon carbide.

[0047] As an example, the process of forming the first semiconductor layer 11 includes at least one of a diffusion process, an ion implantation process, and an in-situ doping epitaxial process.

[0048] Specifically, Figure 2As shown in b, the arrow indicates the direction of ion implantation. Single-type ion implantation is performed from the first surface 101 of the transfer substrate 10, which may include phosphorus ion implantation or boron ion implantation. This embodiment takes boron ion implantation as an example to explain in detail the formation process of the first semiconductor layer 11: when the implanted ions are boron ions, the boron ions can destroy the lattice of the transfer substrate 10 at the first preset depth, and the doped boron ions are activated by annealing, so that the area where the doped boron ions are concentrated forms a P-type doped first semiconductor layer 11, and the part of the transfer substrate 10 above the first semiconductor layer 11 forms a second semiconductor layer 12. In the subsequent cracking process, the transfer substrate 10 can be cracked at the first semiconductor layer 11, wherein the depth of forming the first semiconductor layer 11 is determined by the energy of the ion implantation, and whether it can be cracked is determined by the dose of the ion implantation. In other embodiments, the first semiconductor layer 11 can also be formed on the surface of the transfer substrate 10 by a diffusion process, which specifically includes: first doping the surface of the transfer substrate 10 to form a first layer, forming a functional film layer on the first layer by a deposition process, and the solubility of the doped ions in the functional film layer is greater than that in the first layer, and through a subsequent high-temperature annealing step, the doped ions on the surface of the first layer are enriched in the functional film layer, thereby reducing the doping concentration on the surface of the first layer, and the first layer with reduced doping concentration is formed as the second semiconductor layer 12, and the functional film layer enriched with doped ions is formed as the first semiconductor layer 11.

[0049] In step S2, see Figure 1 , Figure 3 and Figure 4 , a patterned second semiconductor layer 12 is formed on the surface of the first semiconductor layer 11.

[0050] As an example, the specific steps of forming the patterned second semiconductor layer 12 include: forming the patterned second semiconductor layer 12 includes: forming a patterned mask on the surface of the first semiconductor layer 11, the patterned mask exposing a portion of the first semiconductor layer 11, performing selective epitaxy on the exposed portion of the surface of the first semiconductor layer 11, and then removing the patterned mask to form a patterned second semiconductor layer 12 exposing the portion of the surface of the first semiconductor layer 11; or, forming a patterned mask on the surface of the second semiconductor layer 12, performing an etching process along the patterned mask to remove a portion of the second semiconductor layer 12, and further removing the patterned mask to form a patterned second semiconductor layer 12; or, a patterned mask is formed on the surface of the second semiconductor layer 12, and a doping process is performed on the second semiconductor layer 12 along the patterned mask to form a patterned doped region in the second semiconductor layer 12, and the patterned doped region and the undoped region together constitute the patterned second semiconductor layer 12; or, a patterned mask structure is formed on the surface of the second semiconductor layer 12, and an electrochemical etching process is performed on the second semiconductor layer 12, and the patterned mask structure can protect the second semiconductor layer 12 located below the patterned mask structure from being corroded by the electrochemical etching process, and the electrochemically corroded region and the non-electrochemically corroded region together constitute the patterned second semiconductor layer 12.

[0051] In one embodiment, a method for forming a patterned second semiconductor layer 12 includes: forming a patterned mask structure on the surface of the second semiconductor layer 12, and then performing an electrochemical etching process on the second semiconductor layer 12, wherein the patterned mask structure can protect the second semiconductor layer 12 located below the patterned mask structure from being corroded by the electrochemical etching process, and the electrochemically corroded area and the non-electrochemically corroded area together constitute the patterned second semiconductor layer 12.

[0052] In another embodiment, if Figure 3 As shown, the method for forming the patterned second semiconductor layer 12 includes: forming a photoresist mask layer on the second semiconductor layer 12, exposing and developing the photoresist mask layer to form a patterned photoresist mask layer, etching the second semiconductor layer 12 through the patterned photoresist mask layer, thereby forming a plurality of etching grooves on the second semiconductor layer 12, and then removing the photoresist mask layer. Figure 4As shown, a patterned doping mask is formed on the second semiconductor layer 12 again, and a single type of ion implantation is performed on the second semiconductor layer 12 through the patterned doping mask to form a patterned doped region, and then the patterned doping mask is removed and a CMP process is performed on the second semiconductor layer 12 so that the formed second semiconductor layer 121 has a flat surface, thereby improving the quality of the subsequently formed epitaxial semiconductor layer 13. That is, the second semiconductor layer 12 is composed of a patterned doped region and an undoped region.

[0053] In step S3, see Figure 1 and Figure 5 , an electrochemical etching process is performed on the first semiconductor layer 11 and the second semiconductor layer 12 to form a porous structure in the first semiconductor layer 11 and the second semiconductor layer 12.

[0054] As an example, the ion doping concentration in the first semiconductor layer 11 and in the patterned doped regions of the second semiconductor layer 12 is at least 10 times the ion doping concentration in the unpatterned doped regions of the second semiconductor layer 12 .

[0055] Generally speaking, the priority of electrochemical corrosion is: P+ region>N+ region>P- region>N- region>intrinsic silicon. Optionally, when a P-type doped first semiconductor layer 11 is formed, the first semiconductor layer 11 is a P+ region, and the doping type of the unpatterned doped region in the second semiconductor layer 12 is N-type doping, P-type doping or no doping, and can also be co-doping of N-type doping and P-type doping. Since the ion doping concentration in the first semiconductor layer 11 is much greater than the ion doping concentration in the unpatterned doped region in the second semiconductor layer 12, it is ensured that the electrochemical corrosion of the first semiconductor layer 11 occurs first before the second semiconductor layer 12, so that a porous structure is formed in both the first semiconductor layer 11 and the second semiconductor layer 12, and the porosity of the first semiconductor layer 11 is much higher than the porosity of the second semiconductor layer 12. In another embodiment, when the first semiconductor layer 11 is N-type doped, the first semiconductor layer 11 is an N+ region, the doping type of the unpatterned doped region in the second semiconductor layer 12 can only be N-type doping or undoped, and the second semiconductor layer 12 is an N- region to ensure that the electrochemical corrosion of the first semiconductor layer 11 occurs preferentially before the second semiconductor layer 12.

[0056] Specifically, an electrochemical corrosion process is used for the first semiconductor layer 11 and the second semiconductor layer 12. The corrosion depth of the first semiconductor layer 11 and the second semiconductor layer 12 is regulated by adjusting parameters such as the type of current signal, current intensity, solution composition ratio, lighting conditions, and corrosion time. After the electrochemical corrosion process is completed to form a composite porous structure layer, the second semiconductor layer 12 needs to be oxidized to form an oxide film layer that completely covers or partially covers the surface of the micro-nano structure inside the second semiconductor layer 12, thereby enhancing the strength of the second semiconductor layer 12.

[0057] In step S4, see Figure 1 and Figure 6 , an epitaxial semiconductor layer 13 is formed on the second semiconductor layer 12 , and the epitaxial semiconductor layer 13 includes a homoepitaxial layer 131 and / or a heteroepitaxial layer 132 .

[0058] Before forming the epitaxial semiconductor layer 13 on the second semiconductor layer 12, it is also necessary to remove the oxide layer on the surface of the composite porous structure layer. Specifically, the oxide film layer covering the composite porous structure layer is selectively removed by extending downward from the surface of the composite porous structure layer to a depth of 5 nm to 1 μm. Then, the transfer substrate 10 and the composite porous structure layer are annealed in a hydrogen atmosphere or a mixed atmosphere of hydrogen and an inert gas. The annealing temperature may be 300 to 1400° C., thereby further repairing the surface defects of the composite porous structure layer and partially or completely healing the corrosion holes on the surface of the composite porous structure layer, which is more conducive to forming a high-quality semiconductor film layer.

[0059] Specifically, Figure 6 As shown, the specific steps of forming the epitaxial semiconductor layer 13 include: performing a homoepitaxial process on the surface of the second semiconductor layer 12 to form a homoepitaxial layer 131, performing a surface smoothing process on the homoepitaxial layer 131, and then performing a heteroepitaxial process on the surface of the homoepitaxial layer 131 to form a heteroepitaxial layer 132, wherein the heteroepitaxial layer 132 covers the homoepitaxial layer 131. The epitaxial semiconductor layer 13 is formed by combining the homoepitaxial process with the heteroepitaxial process, so that the defects in the second semiconductor layer 12 will not extend to the lattice structure of the heteroepitaxial layer 132, so that there is no lattice mismatch in the epitaxial semiconductor layer 13.

[0060] In a specific embodiment, the transfer substrate 10 is a SiC substrate, a first semiconductor layer 11 and a second semiconductor layer 12 are formed on the SiC substrate, a homoepitaxial process is performed on the second semiconductor layer 12 to form a SiC epitaxial layer, the SiC epitaxial layer is surface-smoothed, and then a heteroepitaxial process is performed on the surface of the SiC epitaxial layer to form a single-crystal AlN epitaxial layer, so that defects in the second semiconductor layer 12 will not extend to the lattice structure of the single-crystal AlN epitaxial layer, and a bonded substrate containing a high-quality single-crystal AlN thin film layer is obtained through subsequent bonding processes, cracking processes, and surface treatment processes. Furthermore, power devices and radio frequency devices can also be prepared based on the bonded substrate with a single-crystal AlN thin film layer.

[0061] In step S5, refer to Figure 1 , Figures 7 to 9 , providing a supporting substrate 14 , and performing a bonding process on the supporting substrate 14 and the epitaxial semiconductor layer 13 to form a temporary bonding substrate 17 .

[0062] The supporting substrate 14, as a substrate for subsequent bonding and supporting the semiconductor film, needs to have a certain thickness and structural strength. Therefore, when selecting the material of the supporting substrate 14, its compatibility with the transfer substrate 10 must also be considered. It is necessary to select a material with better bonding performance during bonding as the supporting substrate 14.

[0063] Optionally, the material of the support substrate 14 includes at least one or more of silicon, silicon oxide, sapphire, diamond, aluminum nitride, gallium nitride or silicon carbide. The material of the support substrate 14 can be selected according to the material of the transfer substrate 10 to obtain a better bonding effect.

[0064] Optionally, before the support substrate 14 is bonded to the epitaxial semiconductor layer 13 , the method further includes forming a bonding intercalation layer 15 on the first surface of the support substrate 14 or on the epitaxial semiconductor layer 13 .

[0065] Specifically, Figure 7As shown, the support substrate 14 is bonded to the epitaxial semiconductor layer 13. Before bonding, a bonding intercalation layer 15 is epitaxially grown on the bonding interface of the support substrate 14 through an epitaxial process. The bonding intercalation layer 15 is formed on the first surface of the support substrate 14 or on the epitaxial semiconductor layer 13. The bonding intercalation layer 15 is subjected to a CMP process, thereby ensuring the subsequent bonding quality of the support substrate 14 and the transfer substrate 10. Optionally, the bonding intercalation layer 15 includes at least one of a single crystal semiconductor layer, a polycrystalline semiconductor layer, an amorphous material layer, an insulating dielectric layer, a piezoelectric material layer, a metal layer, and a compound conductive layer, that is, the bonding intercalation layer 15 can be composed of one of the above materials, or can be composed of multiple of the above materials, and there is no special limitation here. Preferably, in this embodiment, the bonding intercalation layer 15 is formed on the first surface of the support substrate 14.

[0066] In one embodiment, before forming the temporary bonding substrate 17, a step of forming a patterned cavity structure 16 is also included, wherein: Figure 8 As shown in a, the patterned cavity structure 16 can be completely located in the functional material layer in the depth direction; or Figure 8 As shown in FIG. 2 , the patterned cavity structure 16 spans the interface between the functional material layer and the supporting substrate 14; or as shown in FIG. Figure 8 As shown in c, the patterned cavity structure 16 spans the interface between the functional material layer and the semiconductor thin film layer; or Figure 8 d, the patterned cavity structure 16 is completely located in the support substrate 14 and connected to the functional material layer. The arrangement of the patterned cavity structure 16 makes it easier to tape out the subsequently formed device. Preferably, in this embodiment, the patterned cavity structure 16 is completely located in the support substrate 14 and connected to the functional material layer.

[0067] like Fig. 9 As shown, after forming the bonding intercalation layer 15, the support substrate 14 is bonded to the epitaxial semiconductor layer 13 to form a temporary bonding substrate 17. Optionally, the bonding process includes at least one of a hydrophilic bonding process, a hot compression bonding process, a surface plasma activation bonding process or an anodic bonding process. Preferably, in this embodiment, the bonding process is a hot compression bonding process. After the support substrate 14 is bonded to the epitaxial semiconductor layer 13, the temporary bonding substrate 17 is subjected to a high temperature hot compression process, so as to enhance the bonding interface strength between the support substrate 14 and the epitaxial semiconductor layer 13.

[0068] In step S6, refer to Figure 1 , Fig.10 and Fig.11A cracking process is applied to the temporary bonding substrate 17 so that the temporary bonding substrate 17 is cracked laterally along the first semiconductor layer 11 to obtain a bonding substrate containing the epitaxial semiconductor layer 13 and the second semiconductor layer 12 .

[0069] Specifically, a fastening fixture is first used to clamp the front and back sides of the temporary bonding substrate 17. The fastening fixture can limit the warping of the temporary bonding substrate 17 to a certain extent, thereby avoiding irreversible deformation of the temporary bonding substrate 17 under greater stress and improving production yield.

[0070] Optionally, the cracking process includes at least one of a thermal stress cracking process, a crystal stress cracking process, an ultrasonic energy cracking process, a laser cracking process, a water flow impact cracking process, and a splitter insertion cracking process. Preferably, in this embodiment, the cracking process is a thermal stress cracking process. Specifically, different temperatures are applied to the front and back sides of the temporary bonding substrate 17, respectively, so that a temperature gradient is formed inside the temporary bonding substrate 17. The direction of change of the temperature gradient is perpendicular to the front side of the temporary bonding substrate 17. As a high-porosity layer, the first semiconductor layer 11 has a lower thermal conductivity and weaker mechanical strength. The existence of the temperature gradient will cause a higher thermal stress accumulation in the first semiconductor layer 11, such as Fig.10 As shown, the temporary bonding substrate 17 is cleaved laterally along the first semiconductor layer 11, and cleavage occurs between the transfer substrate 10 and the support substrate 14, completing the transfer of the epitaxial semiconductor layer 13 to the support substrate 14, as shown in FIG. Fig.11 As shown, a bonded substrate containing the epitaxial semiconductor layer 13 and the second semiconductor layer 12 is obtained.

[0071] In step S7, refer to Figure 1 and Fig.12 , performing a surface treatment process on the bonded substrate to remove the second semiconductor layer 12 .

[0072] Specifically, Fig.11 As shown, after the cleavage occurs between the transfer substrate 10 and the support substrate 14, the support substrate 14 is subjected to a surface treatment process to remove the second semiconductor layer 12 to obtain a planarized surface of the epitaxial semiconductor layer 13. Furthermore, the surface treatment may be performed by one or more of a thinning process, a polishing process, a homoepitaxial process or a heteroepitaxial process to improve the surface flatness and roughness of the epitaxial semiconductor layer 13, reduce the surface defects of the epitaxial semiconductor layer 13, and finally obtain a bonded substrate with a semiconductor thin film that meets the semiconductor process requirements.

[0073] In summary, the present invention provides a method for preparing a semiconductor thin film. When forming an epitaxial semiconductor layer by combining a homoepitaxial process and a heteroepitaxial process, the scope of the porous structure formed on the surface of the transfer substrate is limited to the patterned doped region of the second semiconductor layer, so as to effectively inhibit the defects in the porous structure from extending to the lattice structure of the epitaxial semiconductor layer. At the same time, except for the patterned doped region, other undoped regions of the second semiconductor layer still maintain the original single crystal structure. When an epitaxial semiconductor layer is formed above the second semiconductor layer, the quality of the epitaxy is high, thereby obtaining a high-quality semiconductor thin film. In addition, there is no thermal stress mismatch in the preparation process, which reduces the probability of semiconductor film damage and lattice defects, thereby further improving the quality of the prepared semiconductor film.

[0074] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a semiconductor thin film, characterized in that: The method for preparing the semiconductor thin film comprises the following steps: Providing a transfer substrate, the transfer substrate having a first surface and a second surface arranged opposite to each other, and forming a first semiconductor layer on the first surface of the transfer substrate; forming a patterned second semiconductor layer on the surface of the first semiconductor layer; Performing an electrochemical etching process on the first semiconductor layer and the second semiconductor layer to form a porous structure in the first semiconductor layer and the second semiconductor layer; forming an epitaxial semiconductor layer on the second semiconductor layer, wherein the epitaxial semiconductor layer includes a homoepitaxial layer and / or a heteroepitaxial layer; Providing a supporting substrate, and performing a bonding process on the supporting substrate and the epitaxial semiconductor layer to form a temporary bonding substrate; Using a cracking process on the temporary bonding substrate, so that the temporary bonding substrate is cracked laterally along the first semiconductor layer to obtain a bonding substrate containing the epitaxial semiconductor layer and the second semiconductor layer; A surface treatment process is performed on the bonded substrate to remove the second semiconductor layer.

2. The method for preparing a semiconductor thin film according to claim 1, characterized in that: The specific steps of forming the patterned second semiconductor layer include: forming a patterned mask on the surface of the first semiconductor layer, the patterned mask exposing a portion of the first semiconductor layer, performing selective epitaxy on the exposed portion of the first semiconductor layer surface, and then removing the patterned mask to form a patterned second semiconductor layer exposing a portion of the first semiconductor layer surface; or, forming a patterned mask on the surface of the second semiconductor layer, performing an etching process along the patterned mask to remove a portion of the second semiconductor layer, and further removing the patterned mask to form a patterned second semiconductor layer; or, A patterned mask is formed on the surface of the second semiconductor layer, and a doping process is performed on the second semiconductor layer along the patterned mask to form a patterned doped region in the second semiconductor layer, and the patterned doped region and the undoped region together constitute the patterned second semiconductor layer; or, a patterned mask structure is formed on the surface of the second semiconductor layer, and an electrochemical etching process is performed on the second semiconductor layer, and the patterned mask structure can protect the second semiconductor layer located below the patterned mask structure from being corroded by the electrochemical etching process, and the electrochemically corroded region and the non-electrochemically corroded region together constitute the patterned second semiconductor layer.

3. The method for preparing a semiconductor thin film according to claim 2, characterized in that: The ion doping concentration in the first semiconductor layer and in the patterned doped regions of the second semiconductor layer is at least 10 times the ion doping concentration in the unpatterned doped regions of the second semiconductor layer.

4. The method for preparing a semiconductor thin film according to claim 3, characterized in that: When the first semiconductor layer is P-type doped, the doping type of the unpatterned doped area in the second semiconductor layer is N-type doping, P-type doping or undoped; when the first semiconductor layer is N-type doped, the doping type of the unpatterned doped area in the second semiconductor layer is only N-type doping or undoped.

5. The method for preparing a semiconductor thin film on a substrate according to claim 2, characterized in that: The process of forming the first semiconductor layer includes at least one of a diffusion process, an ion implantation process, and an in-situ doping epitaxial process.

6. The method for preparing a semiconductor thin film according to claim 1, characterized in that: Before the support substrate is bonded to the epitaxial semiconductor layer, the method further includes forming a bonding intercalation layer on the first surface of the support substrate or on the epitaxial semiconductor layer.

7. The method for preparing a semiconductor thin film according to claim 6, characterized in that: The bonding intercalation layer includes at least one of a single crystal semiconductor layer, a polycrystalline semiconductor layer, an amorphous material layer, an insulating dielectric layer, a piezoelectric material layer, a metal layer, and a compound conductive layer.

8. The method for preparing a semiconductor thin film according to claim 6, characterized in that: Before forming a temporary bonding substrate, a step of forming a patterned cavity structure is also included, wherein the patterned cavity structure can be completely located in the bonding intercalation layer in the depth direction, or span the interface between the bonding intercalation layer and the supporting substrate, or span the interface between the bonding intercalation layer and the semiconductor thin film layer, or be completely located in the supporting substrate and connected to the bonding intercalation layer.

9. The method for preparing a semiconductor thin film according to claim 1, characterized in that: The bonding process for forming the temporary bonding substrate includes at least one of a hydrophilic bonding process, a thermal compression bonding process, a surface plasma activation bonding process or an anodic bonding process.

10. The method for preparing a semiconductor thin film according to claim 1, characterized in that: The cracking process includes at least one of a thermal stress cracking process, a crystal stress cracking process, an ultrasonic energy cracking process, a laser cracking process, a water flow impact cracking process, and a cleaver insertion cracking process.

11. The method for preparing a semiconductor thin film according to claim 1, characterized in that: The specific steps of forming the epitaxial semiconductor layer include: performing a homoepitaxial process on the surface of the second semiconductor layer to form a homoepitaxial layer, performing surface smoothing treatment on the homoepitaxial layer, and then performing a heteroepitaxial process on the surface of the homoepitaxial layer to form a heteroepitaxial layer, wherein the heteroepitaxial layer covers the homoepitaxial layer.

12. The method for preparing a semiconductor thin film layer according to claim 1, characterized in that: After the temporary bonding substrate is laterally cleaved along the first semiconductor layer, the method further includes performing at least one of thinning, polishing, homoepitaxial growth or heteroepitaxial growth on the epitaxial semiconductor layer.

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