Wafer crack-based partition cutting method and chip unit

Abstract

The application provides a wafer dark crack-based partition cutting method and a chip unit, and the wafer dark crack-based partition cutting method comprises the following steps: providing a glass stage and a CCD, and setting a light source; acquiring a gray-scale image of a wafer to be cut through the CCD; judging whether the wafer to be cut has a dark crack; acquiring a personnel instruction, if the personnel instruction is a first instruction, acquiring a plurality of cutting tracks; dividing the wafer to be cut into a plurality of regions based on the dark crack line segment and the plurality of cutting tracks; and cutting the interiors of the plurality of regions in sequence. The CCD is used to recognize an image, and the image is processed into a gray-scale image; whether there is a dark crack is detected through a gray-scale difference; in the case that there is a dark crack, the wafer to be cut is divided into a plurality of regions, and the plurality of regions are cut respectively, so that the plurality of chip units which are misaligned due to the dark crack are prevented from being damaged.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a wafer partitioning method and chip unit based on dark cracks. Background Technology

[0002] Today's LED chip products are developing towards miniaturization and densification, and the requirements for wafer dicing in the LED chip production process are becoming increasingly stringent.

[0003] Currently, the most common LED chip cutting equipment is the picosecond laser scribing machine, which uses a fixed wavelength laser to cut sapphire. Before the cutting operation, a wide-angle CCD (Charge Coupled Device) is used to detect the wafer contour, thereby determining the size and shape of the wafer. The picosecond laser scribing machine then cuts the wafer based on the contour identified by the wide-angle CCD.

[0004] However, dark cracks are prone to occur during wafer cleaning, transfer and other processing. Current technology cannot detect dark cracks, which cause slight misalignment of the LED chips on the wafer. If the wafer is cut according to the originally planned automatic cutting route, the misaligned LED chips will be damaged. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the purpose of this invention is to provide a wafer partitioning and dicing method and chip unit based on wafer dark cracks, which aims to solve the problem that dark cracks are difficult to detect and easily lead to chip damage in the prior art.

[0006] To achieve the above objectives, the present invention is implemented through the following technical solution:

[0007] A method for partitioning and dicing wafers based on dark cracks includes the following steps:

[0008] A glass stage and a CCD are provided, and a light source is disposed within the glass stage;

[0009] The wafer to be cut is placed on the glass stage, and a grayscale image of the wafer to be cut is obtained by the CCD. The wafer to be cut includes several chip units.

[0010] Based on the grayscale image, determine whether there are dark cracks in the wafer to be cut. If there are, then establish one or more dark crack line segments from the grayscale image.

[0011] Obtain personnel instructions, determine the instruction type of the personnel instructions, and the instruction type includes a first instruction and a second instruction;

[0012] If the personnel instruction is the first instruction, then based on the positions of the chip units, a plurality of cutting channels are obtained, and the cutting channels are located between adjacent chip units;

[0013] Based on the dark crack segments and several cutting paths, regional boundary lines are established to divide the wafer to be cut into several regions.

[0014] The area of ​​the region is extracted, and several regions to be cut are determined based on the area. The several regions to be cut are sorted according to the area size corresponding to the region to be cut, so as to cut the interior of the several regions in turn to obtain several chip units after segmentation.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: the image is identified by the CCD and processed into a grayscale image. The presence of dark cracks is detected by the grayscale difference. In the case of dark cracks, the wafer to be cut is divided into several regions and cut separately. This prevents the straight cutting path originally intended for the entire wafer from passing through the inside of the chip unit, thereby preventing the machine from cutting several chip units that are misaligned due to dark cracks.

[0016] Furthermore, the wafer to be cut includes a DBR layer.

[0017] Furthermore, prior to the steps of placing the wafer to be diced on the glass stage and acquiring a grayscale image of the wafer to be diced via the CCD, wherein the wafer to be diced comprises several chip units, the following steps are included:

[0018] A reference wafer with dark cracks is provided, and a reference grayscale image of the reference wafer is acquired by the CCD.

[0019] Based on the location and morphology of the dark crack in the reference wafer, the grayscale value of the dark crack is obtained from the reference grayscale image;

[0020] A first maximum gray value is obtained from the reference gray image, and a gray difference threshold is established based on the dark crack gray value and the first maximum gray value.

[0021] Furthermore, the step of determining whether the wafer to be cut has dark cracks based on the grayscale image includes:

[0022] Obtain the second maximum gray value from the grayscale image;

[0023] Based on the second maximum gray value and the gray difference threshold, it is determined whether the wafer to be cut has a dark crack.

[0024] Furthermore, after the step of determining whether the wafer to be cut has dark cracks based on the grayscale image, the method further includes:

[0025] If no dark cracks are present, the wafer to be cut is cut along an S-shaped path to obtain several chip units after division.

[0026] Furthermore, after the steps of obtaining personnel instructions and determining the instruction type of the personnel instructions, wherein the instruction type includes a first instruction and a second instruction, the method further includes:

[0027] If the personnel instruction is the second instruction, then the wafer to be cut is cut along an S-shaped route to obtain several chip units after division.

[0028] Furthermore, the step of establishing the region boundary line based on the dark crack segment and several of the cutting paths includes:

[0029] Determine whether the dark crack segment intersects with any of the cutting channels;

[0030] If there is an intersection, then a number of cutting paths to be connected are established from the number of cutting paths that intersect with the dark crack line segment;

[0031] Several of the cut channels to be connected and the hidden crack segments are combined to form a region boundary line.

[0032] Furthermore, the step of establishing several regions to be cut based on the area of ​​the region includes:

[0033] Extract the total area of ​​the wafer to determine an area threshold based on the total area;

[0034] The areas of several regions are compared with the area threshold to select the region to be cut from the several regions.

[0035] Furthermore, the ratio of the area threshold to the total area is 0.2:1.

[0036] This invention also provides a chip unit, which is formed by cutting based on the wafer dark crack partitioning method described above. Attached Figure Description

[0037] Figure 1 This is a flowchart of the wafer partitioning method based on dark cracks in the first embodiment of the present invention;

[0038] Figure 2 This is a schematic diagram of the glass stage and CCD structure in the wafer cleaving method based on dark cracks in the first embodiment of the present invention.

[0039] Figure 3 This is a schematic diagram of the chip arrangement of the wafer to be cut in the wafer partitioning method based on wafer dark cracks in the first embodiment of the present invention;

[0040] Figure 4 This is a partial schematic diagram of the wafer to be cut in the wafer partitioning method based on wafer dark cracks in the first embodiment of the present invention;

[0041] Figure 5 This is a schematic diagram illustrating the division of several regions in the wafer partitioning method based on dark cracks in the first embodiment of the present invention;

[0042] Figure 6 This is another schematic diagram illustrating the division of several regions in the wafer partitioning method based on dark cracks in the first embodiment of the present invention;

[0043] Explanation of key component symbols:

[0044] glass stage 100 light source 110 CCD 200 Fixture 210 Wafer to be cut 300 First District 301 Second Zone 302 Chip unit 310 First sub-chip 311 Second sub-chip 312 Cutting channel 320 First dividing line 410 Second dividing line 420 Third dividing line 430

[0045] The following detailed description, in conjunction with the accompanying drawings, will further illustrate the present invention. Detailed Implementation

[0046] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of the invention are illustrated in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0047] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0049] Please see Figures 1 to 6 The wafer dicing method based on dark cracks in this embodiment of the invention includes the following steps:

[0050] Step S10: Provide a glass stage and a CCD, and place a light source inside the glass stage;

[0051] Preferably, please refer to Figure 2 The CCD 200 is a wide-angle CCD, connected to the mounting bracket 210, located directly above the wafer placement area in the glass stage 100, and corresponding to the position of the light source 110. The light source 110 illuminates the wafer, which can enhance the grayscale difference of the image acquired by the CCD 200 and make the dark cracks more obvious.

[0052] Step S20: Place the wafer to be cut on the glass stage and acquire a grayscale image of the wafer to be cut using the CCD. The wafer to be cut includes several chip units.

[0053] Preferably, please refer to Figure 3 The wafer 300 to be cut has several chip units 320, and there are gaps between adjacent chip units 320. The gaps can form dicing channels for cutting. The cutting path is planned according to the gaps, and is usually an S-shaped reciprocating cutting path, which is divided into horizontal and vertical S-shaped paths, that is, reciprocating from left to right and reciprocating from top to bottom, and finally dividing the wafer 300 to be cut into several rectangular chip units 320.

[0054] Specifically, the wafer to be cut includes a DBR layer.

[0055] Preferably, the DBR layer is located on the back side of the wafer 300 to be cut. When the wafer 300 to be cut is placed on the glass stage 100, the light source 110 illuminates the wafer 300 to be cut. The DBR layer prevents light from passing through, and displays black when recognizing grayscale images. If there is a crack, light passes through, and a white line will be formed in the cracked area. Understandably, the DBR layer is beneficial for more accurate identification and detection of dark cracks on the wafer.

[0056] Prior to step S20, the following is included:

[0057] S210: Provide a reference wafer with dark cracks, and acquire a reference grayscale image of the reference wafer through the CCD;

[0058] Preferably, a computer with judgment software is used to communicate with the CCD200 to judge the results of the CCD200 recognition. Therefore, it is necessary to provide cases that conform to the actual situation to provide a basis for the software to judge whether there is a dark crack and prevent misjudgment or omission.

[0059] S220: Obtain the grayscale value of the dark crack from the reference grayscale image based on the location and morphology of the dark crack in the reference wafer;

[0060] Understandably, this involves acquiring and recording data associated with actual dark cracks.

[0061] S230: Obtain a first maximum gray value from the reference gray image, and establish a gray difference threshold based on the dark crack gray value and the first maximum gray value.

[0062] Preferably, since the region with the first maximum gray value in the DBR layer is the crack-free black region in the reference wafer, the width of the dark crack varies in reality, resulting in different brightness of transmitted light. If the width of the dark crack to be determined is large, greater than that of the dark crack in the reference wafer, the gray value in the formed image will be smaller than that of the dark crack, and the gray value difference with the crack-free region will be large. Similarly, if the width of the dark crack to be determined is small, smaller than that of the dark crack in the reference wafer, it will still affect the wafer quality and cutting accuracy, and less light will be transmitted. In this case, the gray value in the formed image will be larger than that of the dark crack, and the gray value difference with the crack-free region will be small. Therefore, setting the gray value difference threshold helps to identify more types of dark cracks. The gray value difference threshold can be continuously adjusted manually to the optimal value during actual detection.

[0063] Step S30: Determine whether there are dark cracks in the wafer to be cut based on the grayscale image. If there are, identify one or more dark crack segments from the grayscale image.

[0064] By recognizing the grayscale image and reading the grayscale difference values ​​of areas with inconsistent grayscale, dark cracks can be identified, and the distribution pattern and location of the dark cracks can be specifically identified, which can be used as a basis for cutting in subsequent processes. Preferably, the computer used to recognize the grayscale image can sound an alarm to remind the operator of the existence of dark cracks.

[0065] Specifically, step S30 includes:

[0066] S310: Obtain the second maximum gray value from the grayscale image;

[0067] Understandably, the area with the second maximum gray value is a crack-free area, and the second maximum gray value is used to provide a standard for judging whether there are hidden cracks in areas with inconsistent gray values.

[0068] S320: Based on the second maximum gray value and the gray difference threshold, determine whether the wafer to be cut has a dark crack;

[0069] Understandably, due to material and processing errors, the maximum grayscale value of each wafer is not completely consistent. Therefore, using the grayscale difference threshold to determine the presence of dark cracks is more accurate and has wider applicability.

[0070] S330: If there are no dark cracks, the wafer to be cut is cut along an S-shaped route to obtain several chip units after division.

[0071] Please see Figure 3 and Figure 4 If the wafer 300 to be cut does not have dark cracks, all the cutting paths 320 are arranged in straight lines. The wafer 300 to be cut is reciprocated in the horizontal and vertical directions according to the S-shaped route in the figure. The cutting path is directly determined by the specifications, parameters, chip array arrangement and other factors of the wafer 300 to be cut, so as to divide the wafer 300 to be cut into a number of rectangular chip units 310.

[0072] Step S40: Obtain personnel instructions, determine the instruction type of the personnel instructions, the instruction type includes a first instruction and a second instruction;

[0073] Preferably, when the software indicates the presence of a hidden crack, the operator is given an operation option to ask whether to enable the partition cutting mode. If the operator selects to enable partition cutting, the first instruction is transmitted; if the operator selects not to enable partition cutting, the second instruction is transmitted.

[0074] Specifically, after step S40, the following is also included:

[0075] S410: If the personnel instruction is the second instruction, then the wafer to be cut is cut along an S-shaped route to obtain a plurality of the chip units after division.

[0076] Preferably, if the staff chooses not to enable partitioned cutting, the wafer 300 to be cut is directly cut according to the original S-shaped route.

[0077] Step S50: If the personnel instruction is the first instruction, then based on the positions of the chip units, a plurality of cutting channels are obtained, the cutting channels being located between adjacent chip units;

[0078] Preferably, if partitioning is enabled, the position and shape of the dark crack and the dicing path 320 around the dark crack are extracted to partition the wafer 300 to be cut.

[0079] Step S60: Based on the dark crack segment and several cutting paths, establish a region boundary line to divide the wafer to be cut into several regions;

[0080] Preferably, please refer to Figure 4 and Figure 5When the wafer 300 to be cut has a dark crack, the chip unit 310 with the dark crack is divided into a first sub-chip 311 and a second sub-chip 312. Because the dark crack has a certain width, the first sub-chip 311 and the second sub-chip 312 are misaligned, causing the chip unit 310 with the dark crack to no longer present a complete rectangle. The dicing path 320 around the chip unit 310 with the dark crack is also misaligned. If the wafer 300 to be cut is cut according to the original S-shaped route, refer to... Figure 4 From end B to end C, and from end D to end E, the cutting will cut into the interior of the second sub-chip 312. Affected by the dark crack, the misalignment of the cutting path 320 will affect the units around the chip unit 310 with the dark crack. Cutting according to the original S-shaped route will also damage the surrounding units, causing a lot of losses.

[0081] Specifically, step S60 includes:

[0082] S610: Determine whether the dark crack segment intersects with the plurality of cutting channels;

[0083] S620: If there is an intersection, then a number of cutting paths to be connected are established from the number of cutting paths that intersect with the dark crack line segment;

[0084] S630: Combine several of the cut channels to be connected and the dark crack segments into a region boundary line.

[0085] Preferably, S610 to S630, please refer to Figure 5 When a dark crack exists in the wafer 300 to be cut, the upper portion of the chip unit 310 on the wafer 300 is obliquely misaligned. The planned region boundary lines divide the wafer 300 into a first region 301 and a second region 302. The region boundary lines include a first boundary line 410, a second boundary line 420, and a third boundary line 430. The first boundary line 410 is the dark crack segment, which is planned as part of the region boundary lines by software through grayscale image recognition. The second boundary line 420 and the... The third dividing line 430 is connected to the first dividing line 410 and is taken from several cutting channels 320 around the chip unit 310 with dark cracks, thus overcoming the phenomenon of cutting channel misalignment. The end of the second dividing line 420 away from the first dividing line 410 and the end of the third dividing line 430 away from the first dividing line 410 are extended according to the chip unit array arrangement on the wafer 300 to be cut. Specifically, they are planned according to the other cutting channels 320 arranged in a straight line until the edge of the wafer 300 to be cut.

[0086] Step S70: Extract the area of ​​the region, establish several regions to be cut based on the area, sort the several regions to be cut according to the area size corresponding to the region to be cut, and cut the interior of the several regions in turn to obtain several chip units after segmentation.

[0087] Preferably, please refer to Figure 5 The area of ​​the first region 301 is larger than that of the second region 302. The first region 301 contains a larger number of intact chip units 310. Therefore, the first region 301 is cut first to ensure the cutting quality of the chips within this region. After partitioning, each region is cut separately, specifically following an S-shaped cutting path. For example, in the first region 301, the cutting proceeds horizontally from left to right, stopping at the region boundary line. The direction is then reversed, and the cutting continues from right to left. Further, when cutting to the first sub-chip 311, the cutting path stops at the connection between the first boundary line 410 and the third boundary line 430. The direction is then reversed, and the cutting continues to the left from the connection between the first boundary line 410 and the second boundary line 420. This prevents damage to the second sub-chip 312 and the units adjacent to it. Please refer to [link to relevant documentation]. Figure 6 This provides a partitioning method for situations where two dark cracks exist. Understandably, in the partitioning and cutting method based on wafer dark cracks, several regions are cut separately to prevent several straight cutting paths in the original S-shaped general route for the entire wafer from passing through the interior of the chip unit 310, thereby preventing the machine from damaging several chip units 310 that are misaligned due to dark cracks.

[0088] Specifically, step S70 includes:

[0089] S710: Extract the total area of ​​the wafer to determine an area threshold based on the total area;

[0090] S720: Compare the areas of several regions with the area threshold respectively to select the region to be cut from the several regions.

[0091] S730: The ratio of the area threshold to the total area is 0.2:1.

[0092] Preferably, in steps S710 to S730, if there is an area smaller than 20% of the total area, it will not be cut. After the cutting of the wafer 300 to be cut is completed, the material is automatically unloaded, and the cutting of the next wafer continues automatically.

[0093] The second embodiment of the present invention provides a chip unit, which is formed by cutting based on the wafer dark crack partitioning method as described in the above embodiments.

[0094] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0095] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A wafer crack-based zoning cutting method, characterized by, The method comprises the following steps: providing a glass stage and a CCD, and setting a light source in the glass stage; placing a wafer to be cut on the glass stage, and acquiring a gray-scale image of the wafer to be cut by the CCD, the wafer to be cut comprising a plurality of chip units; judging whether the wafer to be cut has a dark crack based on the gray-scale image, and if so, establishing one or a plurality of dark crack line segments from the gray-scale image; acquiring a personnel instruction, judging the instruction type of the personnel instruction, the instruction type comprising a first instruction and a second instruction, and if the partition cutting is selected to be enabled, the first instruction is delivered, and if the partition cutting is selected not to be enabled, the second instruction is delivered; if the personnel instruction is the first instruction, a plurality of cutting paths are acquired based on the positions of the plurality of chip units, the cutting paths being located between adjacent chip units; based on the dark crack line segments and the plurality of cutting paths, a region boundary line is established to divide the wafer to be cut into a plurality of regions; the step of establishing the region boundary line based on the dark crack line segments and the plurality of cutting paths comprises: judging whether the dark crack line segments intersect with the plurality of cutting paths; if there is an intersection, a plurality of to-be-connected cutting paths are established from the plurality of cutting paths intersecting with the dark crack line segments; combining the plurality of to-be-connected cutting paths and the dark crack line segments into a region boundary line; extracting the region area of the region, establishing a plurality of to-be-cut regions based on the region area, sorting the plurality of to-be-cut regions according to the region area corresponding to the to-be-cut region, and cutting the inside of the plurality of regions in sequence to obtain a plurality of chip units after cutting; the step of establishing a plurality of to-be-cut regions based on the region area comprises: extracting the total area of the wafer to determine an area threshold according to the total area; comparing the plurality of region areas with the area threshold respectively to select to-be-cut regions from the plurality of regions, and if the region area is smaller than the area threshold, the region is not cut.

2. The wafer crack-based zoning cutting method according to claim 1, wherein, The wafer to be cut comprises a DBR layer.

3. The wafer crack-based zoning cutting method according to claim 1, wherein, Before the step of placing the wafer to be cut on the glass stage and acquiring a gray-scale image of the wafer to be cut by the CCD, the wafer to be cut comprises a plurality of chip units, the step comprises: providing a reference wafer with a dark crack, and acquiring a reference gray-scale image of the reference wafer by the CCD; acquiring a dark crack gray-scale value from the reference gray-scale image according to the position and shape of the dark crack in the reference wafer; acquiring a first maximum gray-scale value from the reference gray-scale image, and establishing a gray-scale difference threshold based on the dark crack gray-scale value and the first maximum gray-scale value.

4. The wafer crack-based zoning cutting method according to claim 3, wherein, The step of judging whether the wafer to be cut has a dark crack based on the gray-scale image comprises: acquiring a second maximum gray-scale value from the gray-scale image; judging whether the wafer to be cut has a dark crack based on the second maximum gray-scale value and the gray-scale difference threshold.

5. The wafer crack-based zoning dicing method according to claim 1, wherein After the step of judging whether the wafer to be cut has a dark crack based on the gray-scale image, the method further comprises: If there is no dark crack, the wafer to be cut is cut according to an S-shaped route to obtain a plurality of chip units after segmentation.

6. The wafer crack-based zoning dicing method according to claim 1, wherein, After the step of obtaining the personnel instruction, judging the instruction type of the personnel instruction, the instruction type includes the first instruction and the second instruction, further comprising: If the personnel instruction is the second instruction, the wafer to be cut is cut according to an S-shaped route to obtain a plurality of chip units after segmentation.

7. The wafer-based crack-partitioning dicing method of claim 1, wherein, The ratio of the area threshold value to the total area is 0.2:

1.

8. A chip unit, characterized by The chip unit is cut based on the wafer dark crack segmentation cutting method based on any one of claims 1-7.

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