Semiconductor packaging structure and manufacturing method thereof

Abstract

The embodiment of the invention provides a semiconductor packaging structure and a manufacturing method thereof. The semiconductor packaging structure comprises a substrate; a plurality of semiconductor chips stacked on the substrate; the microelectrode is positioned at the top of the at least one semiconductor chip and is used for receiving a micro electric field; the microchannel is positioned at the top of at least one semiconductor chip, is arranged above or below the microelectrode and is isolated from the microelectrode to form a circulation loop; microfluid is contained in the microchannel; wherein under the action of the micro electric field, the microelectrode is used for driving the microfluid to circularly flow in the circulation loop, so that heat transfer and heat transfer of the semiconductor chip are realized.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a semiconductor packaging structure and a method for manufacturing the same. Background Art

[0002] As Moore's Law slows down, in order to continue to improve device performance, three-dimensional (3D) chip stacking interconnect technology can both increase the bandwidth between chips and improve computing performance. Chip stacking poses a great challenge to heat dissipation, because multiple chips in a chip stack cause heat accumulation, and the heat flux density per unit area is greatly increased. Effective means are needed to dissipate heat to prevent problems with chip thermal reliability. Summary of the invention

[0003] In view of this, an embodiment of the present application provides a semiconductor packaging structure and a manufacturing method thereof.

[0004] In a first aspect, an embodiment of the present application provides a semiconductor packaging structure, which includes: a substrate; a plurality of semiconductor chips stacked on the substrate; a microelectrode located on the top of at least one semiconductor chip and used to receive a micro-electric field; a microchannel located on the top of at least one semiconductor chip, arranged on or under the microelectrode and isolated from the microelectrode to form a circulation loop; the microchannel includes a microfluid; wherein, under the action of the microelectric field, the microelectrode is used to drive the microfluid to circulate in the circulation loop to achieve heat transfer and heat transfer to the semiconductor chip.

[0005] In some embodiments, at least one semiconductor chip also includes a first electrode and a second electrode staggered from the microchannel; the first electrode and the second electrode are connected to the microelectrode for receiving a microelectric field; the circulation loop includes a first path located in the middle of the semiconductor chip and a second path located at the edge of the semiconductor chip that are first connected; the microelectric field received by the microelectrode located under the first path has a first electric field direction, and the first electric field direction is a direction from the first end of the microelectrode to the second end of the microelectrode along the first path; the microelectric field received by the microelectrode located under the second path has a second electric field direction, and the second electric field direction is a direction from the second end of the microelectrode to the first end of the microelectrode along the second path; wherein, under the action of the microelectric field, the circulating flow includes flowing from the first electrode to the second electrode along the first path and flowing from the second electrode to the first electrode along the second path, or, flowing from the second electrode to the first electrode along the first path and flowing from the first electrode to the second electrode along the second path.

[0006] In some embodiments, the top of each semiconductor chip includes a microelectrode and a microchannel; each semiconductor chip also includes a first dummy silicon through via, a first electrode, and a second electrode that are staggered from the microchannel; the first electrode of each semiconductor chip is connected through the first dummy silicon through via; the second electrode of each semiconductor chip is connected through the first dummy silicon through via; the first electrode is connected to the first end of the microelectrode; the second electrode is connected to the second end of the microelectrode; the first electrode and the second electrode of a semiconductor chip located at the top of multiple semiconductor chips are used to receive a micro-electric field, or the first electrode and the second electrode of a semiconductor chip located at the bottom of multiple semiconductor chips are used to receive a micro-electric field via a substrate, so as to power the first electrode and the second electrode of each semiconductor chip to provide a micro-electric field to the microelectrode.

[0007] In some embodiments, the first electrode and the second electrode package of a semiconductor chip located on top of multiple semiconductor chips are led out to the lead pad; the lead pad is used for externally connecting a DC electric field; the DC electric field ranges from 30V to 90V.

[0008] In some embodiments, the microelectrode includes a comb electrode; the comb electrode includes multiple electrode pairs, an electrode pair consists of a pair of emitters and collectors; multiple emitters are led to the first electrode through emitter leads, and multiple collectors are led to the second electrode through collector leads.

[0009] In some embodiments, the first path includes a main channel and multiple branch channels; at a position near the first end of the microchannel, the first end of the main channel is connected to the multiple branch channels, and the multiple branch channels extend to the second end of the main channel; at a position near the second end of the microchannel, the multiple branch channels are connected to the second end of the main channel; wherein the cross-sectional area of ​​the main channel is greater than the cross-sectional area of ​​the branch channels.

[0010] In some embodiments, the planar shape of the first path includes a honeycomb shape, a snowflake shape, a spider web shape, or a straight shape.

[0011] In some embodiments, at least one semiconductor chip further includes a second dummy TSV staggered from the microchannel; the second dummy TSV is at least located outside the second path and is used to dissipate heat for the microfluid in the second path.

[0012] In some embodiments, the microelectrodes extend at least partially into the substrate of the semiconductor chip, and / or the microchannels extend at least partially into the substrate of the semiconductor chip.

[0013] In some embodiments, the material of the microelectrode includes gold, silver, platinum or aluminum; the material forming the microchannel includes silicon carbide or tetraethyl orthosilicate; and the material of the microfluid includes a thermally conductive nanofluid containing copper, carbon or graphene.

[0014] In some embodiments, the width of the cross section of the microchannel ranges less than or equal to 10 μm, and the depth of the cross section of the microchannel ranges less than or equal to 20 μm.

[0015] In a second aspect, an embodiment of the present application provides a method for manufacturing a semiconductor packaging structure, the manufacturing method comprising: providing a substrate; stacking a plurality of semiconductor chips in sequence on the substrate; forming a microelectrode on top of at least one semiconductor chip; the microelectrode is used to receive a micro-electric field; forming a microchannel on top of at least one semiconductor chip, which is arranged on or under the microelectrode and isolated from the microelectrode; the microchannel constitutes a circulation loop; the microchannel includes a microfluid; wherein, under the action of the microelectric field, the microelectrode is used to drive the microfluid to circulate in the circulation loop to achieve heat transfer and heat transfer to the semiconductor chip.

[0016] In some embodiments, a microelectrode is formed on the top of at least one semiconductor chip, including: forming a first back groove on the back side of at least one semiconductor chip; the planar shape of the first back groove includes a circulation loop; forming a microelectrode at the bottom of the first back groove; forming a microchannel on the top of at least one semiconductor chip, which is arranged on or under the microelectrode and isolated from the microelectrode, including: depositing a first dielectric barrier layer in the first back groove where the microelectrode is formed; depositing a first sealing layer on the first dielectric barrier layer; the first sealing layer and the first dielectric barrier layer have a first space; injecting microfluid into the first space to form a microchannel constituting a circulation loop.

[0017] In some embodiments, a microelectrode is formed on the top of at least one semiconductor chip, including: forming a second back groove on the back side of at least one semiconductor chip; the planar shape of the second back groove includes a circulation loop; forming a microelectrode in the second back groove; forming a microchannel disposed on or under the microelectrode and isolated from the microelectrode on the top of at least one semiconductor chip, including: depositing a dielectric layer on at least one semiconductor chip on which the microelectrode is formed; forming a third back groove in the dielectric layer; depositing a second dielectric barrier layer in the third back groove; depositing a second sealing layer on the second dielectric barrier layer; the second sealing layer and the second dielectric barrier layer have a second space; injecting microfluid into the second space to form a microchannel constituting a circulation loop.

[0018] In some embodiments, a microelectrode is formed on the top of at least one semiconductor chip, including: providing a glass substrate; forming a fourth back groove on the back of the glass substrate; the planar shape of the fourth back groove includes a circulation loop; forming a microelectrode at the bottom of the fourth back groove; forming a microchannel disposed on or under the microelectrode and isolated from the microelectrode on the top of at least one semiconductor chip, including: depositing a third dielectric barrier layer in the fourth back groove where the microelectrode is formed; bonding the glass substrate where the third dielectric barrier layer is formed to the top surface of the semiconductor chip; the back of the semiconductor chip and the third dielectric barrier layer have a third space; injecting microfluid into the third space to form a microchannel constituting a circulation loop.

[0019] In each embodiment of the present application, a microelectrode and a microchannel on or under the microelectrode and isolated from the microelectrode are arranged on the top of at least one semiconductor chip among the stacked multiple semiconductor chips, so that the microchannel constitutes a circulation loop, and the microchannel includes a microfluid; wherein, under the action of a microelectric field, the microelectrode is used to drive the microfluid to circulate in the circulation loop to achieve heat transfer and heat transfer to the semiconductor chip, effectively improve the heat dissipation of the stacked multiple semiconductor chips, and improve the thermal reliability of the stacked multiple semiconductor chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic cross-sectional view of a first semiconductor packaging structure provided in an embodiment of the present application;

[0021] Figure 2 for Figure 1 A schematic top view of a microchannel of a semiconductor chip;

[0022] Figure 3 for Figure 1 An enlarged schematic diagram of a region P;

[0023] Figure 4A A schematic top view of a microelectrode located under a first path provided in an embodiment of the present application;

[0024] Figure 4B A schematic top view of a microelectrode located under the second path provided in an embodiment of the present application;

[0025] Figure 5A One of the schematic top views of a microchannel of a semiconductor chip provided in an embodiment of the present application;

[0026] Figure 5B A second schematic top view of a microchannel of a semiconductor chip provided in an embodiment of the present application;

[0027] Figure 6 A third schematic top view of a microchannel of a semiconductor chip provided in an embodiment of the present application;

[0028] Figure 7 A schematic diagram of a process for manufacturing a semiconductor packaging structure provided by an embodiment of the present application;

[0029] FIG. 8A to FIG. 8E A schematic cross-sectional view of a method for manufacturing a first semiconductor packaging structure provided by an embodiment of the present application;

[0030] 9A to 9F A schematic cross-sectional view of a method for manufacturing a second semiconductor packaging structure provided by an embodiment of the present application;

[0031] FIG. 10A to FIG. 10F A schematic cross-sectional view of a method for manufacturing a third semiconductor packaging structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] The following will combine the implementation methods and drawings of this application to clearly and completely describe the technical solutions in the implementation methods of this application. The described implementation methods are only part of the implementation methods of this application, not all of the implementation methods. Based on the implementation methods in this application, all other implementation methods obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0033] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0034] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0035] The vertically stacked 3D stacked memory generates a lot of heat when working. If the heat cannot be effectively dissipated, it will affect the device yield and reliability.

[0036] In view of this, an embodiment of the present application provides a semiconductor packaging structure and a manufacturing method thereof.

[0037] Figure 1 A cross-sectional schematic diagram of a first semiconductor packaging structure provided in an embodiment of the present application. Figure 2 for Figure 1 A schematic top view of a microchannel of a semiconductor chip. Figure 3 for Figure 1 An enlarged schematic diagram of area P.

[0038] In a first aspect, the present invention provides a semiconductor packaging structure, referring to Figure 1 , Figure 2 and Figure 3 The semiconductor packaging structure includes: a substrate; a plurality of semiconductor chips stacked on the substrate; a microelectrode located on the top of at least one semiconductor chip and used to receive a micro-electric field; a microchannel located on the top of at least one semiconductor chip, arranged on or under the microelectrode and isolated from the microelectrode to form a circulation loop; the microchannel includes a microfluid; wherein, under the action of the microelectric field, the microelectrode is used to drive the microfluid to circulate in the circulation loop to achieve heat transfer and heat transmission to the semiconductor chip.

[0039] For the convenience of describing the embodiments of the present application, the first direction and the second direction are represented as two intersecting directions parallel to the top surface / bottom surface of the semiconductor chip, for example, the first direction and the second direction are orthogonal; the third direction is a direction perpendicular to the top surface / bottom surface of the semiconductor chip or the third direction is a stacking direction of multiple semiconductor chips. For example, the first direction can be represented as the X direction in the drawings; the second direction can be represented as the Y direction in the drawings; and the third direction can be represented as the Z direction in the drawings.

[0040] refer to Figure 1, the substrate 100 is used as the substrate of the semiconductor packaging structure, which may be a printed circuit board (PCB), a glass substrate, a ceramic substrate or a board with wiring. The semiconductor chip may be a memory chip or a logic chip. The logic chip may be, for example, a central processing unit (CPU), a digital signal processor (DSP), a field programmable gate array (FPGA), a microcontroller unit (MCU), or an application specific integrated circuit (ASIC). The memory chip may be a volatile memory chip, such as a dynamic random access memory (DRAM) chip and a static random access memory (SRAM) chip, or may be a non-volatile memory chip, such as a resistive random access memory (RRAM) chip.

[0041] In some embodiments, the semiconductor package structure includes a plurality of semiconductor chips stacked on a substrate, the plurality of semiconductor chips including a first semiconductor chip 102 and a plurality of second semiconductor chips 202 stacked in sequence, the first semiconductor chip 102 including a logic chip, and the second semiconductor chip 202 including a memory chip. The first semiconductor chip 102 and the plurality of second semiconductor chips 202 on the first semiconductor chip 102 may constitute a high bandwidth memory (HBM) DRAM. Although a semiconductor package structure (such as a semiconductor package structure in which one first semiconductor chip 102 and four second semiconductor chips 202 are stacked in sequence on a substrate) is shown in this exemplary embodiment, Figure 1 The number of the second semiconductor chips 202 that can be stacked on the first semiconductor chip 102 is not limited thereto. For example, two, three, or more than four second semiconductor chips 202 or chips similar to the second semiconductor chip 202 (e.g., 8 chips) can be stacked on the first semiconductor chip 102.

[0042] In some embodiments, the circuit of the first semiconductor chip 102 and / or the circuit of the second semiconductor chip 202 is connected to the functional circuit ( Figure 1(not shown). The functional circuit may include a variety of active and passive devices (e.g., capacitors, resistors, inductors, and the like) that meet the desired structural and functional requirements of the design. The functional circuit may include an NMOS device or a PMOS device. The material of the insulating layer includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The material of the interconnect layer includes, but is not limited to, tungsten, cobalt, nickel, copper, aluminum, polysilicon, doped silicon, silicide, nitride, or any combination thereof.

[0043] In some embodiments, the connection structure 302 between two adjacent semiconductor chips and between the semiconductor chip and the substrate, each semiconductor chip also includes a through silicon via (TSV) 104; the two adjacent semiconductor chips and the chip and the substrate can be connected through the connection structure and the through silicon via. Exemplarily, the material of the connection structure 302 and / or the through silicon via 104 includes doped polysilicon, tungsten, carbon or copper.

[0044] refer to Figure 1 and Figure 3 , the microchannel region MR includes a microelectrode 106 and a microchannel 108; the microelectrode 106 and the microchannel 108 are stacked on top of at least one semiconductor chip, the microelectrode 106 can be arranged at the top of the microchannel 108 or at the bottom of the microchannel, and at least follow the circulation loop, and the microelectrode is spaced from the microfluid 109 in the microchannel. In the case of receiving an external micro-electric field, the microelectrode 106 is used to drive the microfluid 109 to circulate in the circulation loop to achieve heat transfer and heat transfer to the semiconductor chip. Exemplarily, the microelectrode is composed of a plurality of paired emitters and collectors. Under the action of the electric field between the electrode pairs, the interaction between the ions, dipoles and particles in the microfluid and the electric field drives the flow of the microfluid.

[0045] refer to Figure 1 and Figure 3 In some embodiments, the microelectrode 106 at least partially extends into the substrate of the semiconductor chip, and / or the microchannel 108 at least partially extends into the substrate of the semiconductor chip. In this way, the size of the plurality of semiconductor chips along the stacking direction can be reduced. Figure 1 and Figure 3 The microelectrode 106 and the microchannel 108 are both located in the substrate of the second semiconductor chip 202 , but this is not intended to limit the embodiments of the present application.

[0046] refer to Figure 1 and Figure 3In some embodiments, the material of the microelectrode 106 includes gold, silver, platinum or aluminum; the material forming the microchannel 108 includes silicon carbide or tetraethyl orthosilicate; and the material of the microfluid 109 includes a thermally conductive nanofluid containing copper, carbon or graphene.

[0047] It should be noted that Figure 2 A partial structure is shown in perspective, for example, a microelectrode and a microchannel are shown in perspective, but since the microelectrode is arranged below the microchannel, only a part of the microelectrode is shown; Figure 2 Some structures are not shown, for example, the microchannel forming material located on the top surface of a semiconductor chip is not shown. Figure 5A , Figure 5B and Figure 6 for Figure 2 For some variant embodiments, the perspective display situation can also be similarly referred to Figure 2 To understand.

[0048] refer to Figure 1 and Figure 2 In some embodiments, at least one semiconductor chip further includes a first electrode 110 and a second electrode 112 staggered from the microchannel 108; the first electrode 110 and the second electrode 112 are connected to the microelectrode 106 for receiving a micro-electric field; the circulation loop includes a first path 114 located in the middle of the semiconductor chip and a second path 116 located at the edge of the semiconductor chip which are connected first; the micro-electric field received by the microelectrode located under the first path has a first electric field direction 118, and the first electric field direction 118 is a direction from the first end of the microelectrode to the second end of the microelectrode along the first path; the micro-electric field received by the microelectrode located under the second path has a second electric field direction 120, and the second electric field direction 120 is a direction from the second end of the microelectrode to the first end of the microelectrode along the second path; wherein, under the action of the micro-electric field, the circulation flow includes flowing from the first electrode 110 to the second electrode 112 along the first path 114 and flowing from the second electrode 112 to the first electrode 110 along the second path 116, or, flowing from the second electrode to the first electrode along the first path and flowing from the first electrode to the second electrode along the second path.

[0049] The first electrode 110 and the second electrode 112 may be located at opposite ends of the semiconductor chip, and the first electric field direction 118 and the second electric field direction 120 may be two directions pointing relatively to each other between the first electrode and the second electrode, and are used to drive the microfluid to circulate in the circulation loop, for example, to drive the microfluid to flow along the first electric field direction 118 in the first path 114 and along the second electric field direction 120 in the second path 116, so as to realize the circulation in the circulation loop from the first path 114 to the second path 116 and then from the second path 116 to the first path 114. Figure 2The relative positions of the first electrode 110 and the second electrode 112 shown can be interchanged, and the relative directions of the first electric field direction 118 and the second electric field direction 120 can also be interchanged.

[0050] The heat transfer path of the semiconductor chip may include: the heat generated by the functional circuit of the semiconductor chip (which may be located in the middle of the semiconductor chip) is transferred to the first path 114 or transferred to the first path 114 via the through silicon via 104, the first path 114 is transferred to the second path 116, and the second path 116 is transferred to the heat dissipation component (such as a heat conductive block) at the edge of the semiconductor chip, and the heat is dissipated to the outside of the semiconductor chip by the heat dissipation component. The first path can be understood as a heat source concentration area generated by the functional circuit of the semiconductor chip. For example, the first path can be close to the TSV dense area and the functional circuit dense area of ​​the semiconductor chip, and the heat of the TSV and the functional circuit can be heat transferred and heat transferred through the first path. The second path can be understood as a heat dissipation area through the semiconductor chip. For example, the second path can be close to the heat dissipation component at the edge of the semiconductor chip to transfer the heat to the heat dissipation component at the edge of the semiconductor chip. The heat dissipation component at the edge of the semiconductor chip can be close to the edge of the semiconductor chip to dissipate heat to the outside of the semiconductor chip.

[0051] In each embodiment of the present application, the term "closely attached" can be understood as the distance between the two components being greater than zero and less than or equal to a preset value, for example, there is a distance between the first path and the TSV of the semiconductor chip, and the distance is less than or equal to a preset value. While ensuring the stability of the first path and the TSV structure of the semiconductor chip, the heat transfer distance between the first path and the TSV of the semiconductor chip is minimized as much as possible to improve the heat transfer efficiency.

[0052] refer to Figure 1 In some embodiments, the heat dissipation component may be a heat conductive block 122 extending into the semiconductor chip, or a heat conductive hole ( Figure 1 (not shown). The heat conducting block 122 and the heat conducting hole are used for heat dissipation, and are not used to realize the functional circuit of the semiconductor chip. The material of the heat conducting block 122 and the heat conducting hole may include copper or copper alloy. In an optional embodiment, the planar shape of the heat conducting block 122 includes a honeycomb shape, a snowflake shape, a spider web shape or a straight shape, which can release stress and improve heat dissipation capacity.

[0053] refer to Figure 1 and Figure 2 In some embodiments, at least one semiconductor chip further includes a second dummy silicon via 124 staggered from the microchannel; the second dummy silicon via 124 is at least located outside the second path 116 and is used to dissipate heat for the microfluid in the second path 116. Figure 2As shown, the second dummy silicon through vias 124 can be located on both sides of the second path 116, and the second dummy silicon through vias 124 located outside the second path 116 are more conducive to heat transfer to the outside of the semiconductor chip. The second dummy silicon through vias 124 are used for heat dissipation and are not used to implement the functional circuit of the semiconductor chip. The material of the second dummy silicon through vias 124 may include copper or copper alloy.

[0054] refer to Figure 4A and Figure 4B In some embodiments, the microelectrode 106 includes a comb electrode; the comb electrode includes a plurality of electrode pairs, one electrode pair is composed of a pair of emitters 1061 and collectors 1062; the plurality of emitters are led to the first electrode 110 through an emitter lead 1063, and the plurality of collectors 1062 are led to the second electrode 112 through a collector lead 1064. The comb electrode has good driving microfluidic performance and stable performance. Exemplarily, the plurality of electrode pairs can be arranged at the bottom of the microchannel 108 and follow the circulation loop arrangement, refer to Figure 4A , the electric field between the electrode pair of the comb-shaped electrodes located under the first path has a first electric field direction 118, and the first electric field direction 118 is a direction from the first end of the microelectrode to the second end of the microelectrode along the first path; Figure 4B The electric field between the electrode pairs of the comb electrodes located under the second path has a second electric field direction 120, and the second electric field direction 120 is a direction pointing from the second end of the microelectrode to the first end of the microelectrode along the second path, which is used to drive the microfluid in the microchannel 108 to flow along the first electric field direction in the first path and along the second electric field direction in the second path, so as to realize a circulation flow in a circulation loop from the first path to the second path and then from the second path to the first path.

[0055] It should be noted that although Figure 1 The top of each semiconductor chip includes a microelectrode and a microchannel. The top of at least one semiconductor chip does not have a microelectrode and a microchannel. Figure 1 For example, the first semiconductor chip 102 is not provided with microelectrodes and microchannels, and the plurality of second semiconductor chips 202 are provided with microelectrodes and microchannels. The second semiconductor chips 202 provided with microelectrodes and microchannels can be connected to the substrate 100 through the first dummy silicon vias provided in the first semiconductor chip 102 .

[0056] In some embodiments, the top of a portion of the semiconductor chips in the plurality of semiconductor chips includes a microelectrode and a microchannel; each semiconductor chip also includes a first dummy silicon through-hole, a first electrode, and a second electrode staggered from the microchannel; the first electrode of a portion of the semiconductor chips is connected through the first dummy silicon through-hole, the second electrode is connected through the first dummy silicon through-hole, the first electrode is connected to the first end of the microelectrode, and the second electrode is connected to the second end of the microelectrode; the first electrode and the second electrode of a semiconductor chip located at the top of the plurality of semiconductor chips are used to receive the microelectric field, or the first electrode and the second electrode of a semiconductor chip located at the bottom of the plurality of semiconductor chips are used to receive the microelectric field via the substrate, so as to realize power supply to the first electrode and the second electrode of a portion of the semiconductor chips to provide the microelectric field to the microelectrode. A portion of the semiconductor chips in the plurality of semiconductor chips (for example, a semiconductor chip in the middle of the plurality of semiconductor chips) all have a heat transfer path composed of a microelectrode and a microchannel, and a microelectrode and a microchannel, and the heat dissipation component dissipates heat to the outside of the corresponding semiconductor chip, thereby improving the heat dissipation capacity.

[0057] For example, the top of a semiconductor chip located in the middle of a plurality of semiconductor chips includes a microelectrode and a microchannel, and the first electrode and the second electrode of a semiconductor chip located in the middle of the plurality of semiconductor chips can be connected to the first electrode and the second electrode of a semiconductor chip located at the top of the plurality of semiconductor chips through a first dummy silicon through hole, or connected to the first electrode and the second electrode of a semiconductor chip located at the bottom of the plurality of semiconductor chips through a first dummy silicon through hole. For another example, the top of a semiconductor chip located at the top of the plurality of semiconductor chips includes a microelectrode and a microchannel, and the first electrode and the second electrode of a semiconductor chip located at the top of the plurality of semiconductor chips can be connected to the first electrode and the second electrode of a semiconductor chip located at the bottom of the plurality of semiconductor chips through a first dummy silicon through hole. For another example, the top of a semiconductor chip located at the bottom of the plurality of semiconductor chips includes a microelectrode and a microchannel, and the first electrode and the second electrode of a semiconductor chip located at the bottom of the plurality of semiconductor chips can be connected to the first electrode and the second electrode of a semiconductor chip located at the top of the plurality of semiconductor chips through a first dummy silicon through hole.

[0058] refer to Figure 1 , Figure 2 and Figure 3In some embodiments, the top of each semiconductor chip includes a microelectrode and a microchannel; each semiconductor chip also includes a first dummy silicon through-hole, a first electrode and a second electrode staggered from the microchannel; the first electrode of each semiconductor chip is connected through the first dummy silicon through-hole; the second electrode of each semiconductor chip is connected through the first dummy silicon through-hole; the first electrode is connected to the first end of the microelectrode; the second electrode is connected to the second end of the microelectrode; the first electrode and the second electrode of a semiconductor chip located at the top of the plurality of semiconductor chips are used to receive the micro-electric field, or the first electrode and the second electrode of a semiconductor chip located at the bottom of the plurality of semiconductor chips are used to receive the micro-electric field via the substrate, so as to realize power supply to the first electrode and the second electrode of each semiconductor chip to provide the micro-electric field to the microelectrode. Each semiconductor chip has a heat transfer path composed of microelectrodes and microchannels, and the heat transfer path dissipates heat to the outside of each semiconductor chip to improve the heat dissipation capacity. The specific situation that each semiconductor chip has a microelectrode and a microchannel can refer to the above specific description, which will not be repeated here.

[0059] refer to Figure 1 In some embodiments, the first electrode and the second electrode package of a semiconductor chip located on top of the plurality of semiconductor chips are led out to the lead pad ( Figure 1 Alternatively, the first electrode and the second electrode of a semiconductor chip located at the bottom of the plurality of semiconductor chips are used to be led out to the lead pads ( Figure 1 The lead pad is used to connect an external DC electric field; the DC electric field ranges from 30 V to 90 V. In some embodiments, the potential difference between the first electrode and the second electrode can be adjusted, the potential of the first electrode is higher than the potential of the second electrode, or the potential of the first electrode is lower than the potential of the second electrode, so as to regulate the different directions of the electric field provided to the microelectrode.

[0060] refer to Figure 2 In some embodiments, the first path includes a main channel 1141 and multiple branch channels 1142; at a position close to the first end of the microchannel (for example, close to the first electrode 110), the first end of the main channel 1141 is connected to the multiple branch channels 1142, and the multiple branch channels 1142 extend to the second end of the main channel 1141 (for example, close to the second electrode 112); at a position close to the second end of the microchannel (for example, close to the second electrode 112), the multiple branch channels 1142 are connected to the second end of the main channel 1141; wherein the cross-sectional area of ​​the main channel 1141 is greater than the cross-sectional area of ​​the branch channels 1142.

[0061] In some embodiments, the planar shape of the first path includes a honeycomb shape (refer to Figure 5A ), snowflake, spider web (reference Figure 5B) or a straight shape. The first paths with different plane shapes can release stress and improve heat dissipation capacity.

[0062] refer to Figure 6 In some embodiments, the second path includes a plurality of channels 1161, 1162 surrounding the edge of the semiconductor chip. The second path flows through the edges of each semiconductor chip, and the heat dissipation components located on the edges of each semiconductor chip dissipate heat to the outside of each semiconductor chip, thereby improving the heat dissipation capacity. In an optional embodiment, Figure 6 The planar shape of the first path shown is replaced by Figure 5A The honeycomb-shaped first path shown or Figure 5B The spider web-like first path is shown.

[0063] refer to Figure 1 and Figure 3 In some embodiments, the width W1 of the cross section of the microchannel 108 is less than or equal to 10 μm, and the depth H1 of the cross section of the microchannel is less than or equal to 20 μm. When the microchannel 108 is structurally stable, the driving capability range of the microelectrode is met, and the resistance of the microfluid 109 circulating in the microchannel 108 is reduced as much as possible, which is beneficial to the circulation of the microfluid 109 and can improve the heat transfer efficiency.

[0064] In each embodiment of the present application, a microelectrode and a microchannel on or under the microelectrode and isolated from the microelectrode are arranged on the top of at least one semiconductor chip among the stacked multiple semiconductor chips, so that the microchannel constitutes a circulation loop, and the microchannel includes a microfluid; wherein, under the action of a microelectric field, the microelectrode is used to drive the microfluid to circulate in the circulation loop to achieve heat transfer and heat transfer to the semiconductor chip, effectively improve the heat dissipation of the stacked multiple semiconductor chips, and improve the thermal reliability of the stacked multiple semiconductor chips.

[0065] In a second aspect, the present application provides a method for manufacturing a semiconductor packaging structure, referring to Figure 7 , the manufacturing method comprises the following steps:

[0066] S101, providing a substrate;

[0067] S102, stacking a plurality of semiconductor chips in sequence on a substrate; forming a microelectrode on top of at least one semiconductor chip; the microelectrode is used to receive a micro-electric field;

[0068] S103. A microchannel is formed on the top of at least one semiconductor chip, which is arranged on or under the microelectrode and isolated from the microelectrode; the microchannel constitutes a circulation loop; the microchannel includes a microfluid; wherein, under the action of a microelectric field, the microelectrode is used to drive the microfluid to circulate in the circulation loop to achieve heat transfer and heat transmission to the semiconductor chip.

[0069] Step S101 is executed to provide a substrate. The substrate can refer to the description of the substrate 100 in the first aspect above, which will not be repeated here.

[0070] Steps S102 and S103 are executed to form a micro-electric field and micro-electrodes, and the specific process is integrated into the process of forming a plurality of semiconductor chips stacked.

[0071] The specific process of executing steps S102 and S103 to form the micro-electric field and the micro-electrode is described in detail below.

[0072] In some embodiments, a microelectrode is formed on the top of at least one semiconductor chip, including: forming a first back groove on the back side of at least one semiconductor chip; the planar shape of the first back groove includes a circulation loop; forming a microelectrode at the bottom of the first back groove; forming a microchannel on the top of at least one semiconductor chip, which is arranged on or under the microelectrode and isolated from the microelectrode, including: depositing a first dielectric barrier layer in the first back groove where the microelectrode is formed; depositing a first sealing layer on the first dielectric barrier layer; the first sealing layer and the first dielectric barrier layer have a first space; injecting microfluid into the first space to form a microchannel constituting a circulation loop.

[0073] refer to Fig. 8A , a first back groove T1 is formed on the back side of the second semiconductor chip 202 by using a photolithography and etching process. The planar shape of the first back groove T1 includes a loop. For example, the planar shape of the first back groove T1 can refer to Figure 2 , Figure 5B or Figure 6 The planar shape of the microchannel is used to form a microchannel in the first back trench T1 in the subsequent process.

[0074] refer to Figure 8B , a deposition and etching process is used to form a microelectrode 106 at the bottom of the first back groove T1. The plane shape of the microelectrode depends on the first back groove T1, and the microelectrode 106 can be composed of a comb-shaped electrode. The composition of the comb-shaped electrode can refer to the relevant description of the first aspect above, which will not be repeated here.

[0075] refer to Figure 8C, a first dielectric barrier layer 1081 is deposited in the first back groove T1 where the microelectrode 106 is formed by a deposition process; and a first sealing layer 1082 is deposited on the first dielectric barrier layer 1081. The first dielectric barrier layer 1081 and the first sealing layer 1082 may be the same or different. Here, taking the first dielectric barrier layer 1081 and the first sealing layer 1082 as the same as an example, the materials of the first dielectric barrier layer 1081 and the first sealing layer 1082 include silicon carbide or tetraethyl orthosilicate. The first dielectric barrier layer 1081 and the first sealing layer 1082 constitute a microchannel 108, and the microchannel 108 has a closed first space AP1.

[0076] refer to Fig.8D , injecting microfluid into the first space AP1 of the microchannel 108. The material of the microfluid 109 includes a thermally conductive nanofluid containing copper, carbon or graphene.

[0077] refer to Fig. 8E , a photolithography and etching process is used to form a through silicon via 104 staggered with the microchannel 108. The structure of the through silicon via 104 can refer to the related description of the first aspect above, which will not be repeated here.

[0078] In some embodiments, a microelectrode is formed on the top of at least one semiconductor chip, including: forming a second back groove on the back side of at least one semiconductor chip; the planar shape of the second back groove includes a circulation loop; forming a microelectrode in the second back groove; forming a microchannel disposed on or under the microelectrode and isolated from the microelectrode on the top of at least one semiconductor chip, including: depositing a dielectric layer on at least one semiconductor chip on which the microelectrode is formed; forming a third back groove in the dielectric layer; depositing a second dielectric barrier layer in the third back groove; depositing a second sealing layer on the second dielectric barrier layer; the second sealing layer and the second dielectric barrier layer have a second space; injecting microfluid into the second space to form a microchannel constituting a circulation loop.

[0079] refer to Fig.9A , a second back groove T2 is formed on the back side of the second semiconductor chip 202 by using a photolithography and etching process. The planar shape of the second back groove T2 includes a loop. For example, the planar shape of the second back groove T2 can refer to Figure 2 , Figure 5B or Figure 6 The planar shape of the microchannel is used to form a microelectrode in the second back groove T2 in the subsequent process.

[0080] refer to Fig. 9B , a deposition and etching process is used to form a microelectrode 106 at the bottom of the second back groove T2. The plane shape of the microelectrode depends on the second back groove T2, and the microelectrode 106 can be composed of a comb-shaped electrode. The composition of the comb-shaped electrode can refer to the relevant description of the first aspect above, which will not be repeated here.

[0081] refer to Fig. 9C , a dielectric layer 111 is deposited on the microelectrode 106 by a deposition process; a third back groove T3 is formed in the dielectric layer 111 by a photolithography etching process. In some embodiments, before depositing the dielectric layer 111, a deposition process may be further used to form a liner layer 113 covering the microelectrode 106. The materials of the dielectric layer 111 and the liner layer 113 may include silicon oxide.

[0082] refer to Fig.9D , a second dielectric barrier layer 1083 is deposited in the third back trench T3 by a deposition process; and a second sealing layer 1084 is deposited on the second dielectric barrier layer 1083. The second dielectric barrier layer 1083 and the second sealing layer 1084 may be the same or different. Here, taking the second dielectric barrier layer 1083 and the second sealing layer 1084 as an example, the materials of the second dielectric barrier layer 1083 and the second sealing layer 1084 include silicon carbide or tetraethyl orthosilicate. The second dielectric barrier layer 1083 and the second sealing layer 1084 constitute a microchannel 108, and the microchannel 108 has a closed second space AP2.

[0083] refer to Fig.9E , injecting microfluid into the second space AP2 of the microchannel 108. The material of the microfluid 109 includes a thermally conductive nanofluid containing copper, carbon or graphene.

[0084] refer to Fig.9F , a photolithography and etching process is used to form a through silicon via 104 staggered with the microchannel 108. The structure of the through silicon via 104 can refer to the related description of the first aspect above, which will not be repeated here.

[0085] In some embodiments, a microelectrode is formed on the top of at least one semiconductor chip, including: providing a glass substrate; forming a fourth back groove on the back of the glass substrate; the planar shape of the fourth back groove includes a circulation loop; forming a microelectrode at the bottom of the fourth back groove; forming a microchannel disposed on or under the microelectrode and isolated from the microelectrode on the top of at least one semiconductor chip, including: depositing a third dielectric barrier layer in the fourth back groove where the microelectrode is formed; bonding the glass substrate where the third dielectric barrier layer is formed to the top surface of the semiconductor chip; the back of the semiconductor chip and the third dielectric barrier layer have a third space; injecting microfluid into the third space to form a microchannel constituting a circulation loop.

[0086] Fig. 10A , Fig. 10B , Fig. 10C The X1 direction and the Y1 direction shown are two orthogonal directions parallel to the top surface / bottom surface of the glass substrate 200 , and the Z1 direction is a direction perpendicular to the top surface / bottom surface of the glass substrate 200 .

[0087] refer to Fig. 10A , a fourth back groove T4 is formed on the back of the glass substrate 200 by using a photolithography etching process. The plane shape of the fourth back groove T4 includes a loop. For example, the plane shape of the fourth back groove T4 can refer to Figure 2 , Figure 5B or Figure 6 The planar shape of the microchannel is used to form a microelectrode in the fourth back groove T4 in the subsequent process.

[0088] refer to Fig. 10B , a deposition and etching process is used to form a microelectrode 106 at the bottom of the fourth back groove T4. The plane shape of the microelectrode depends on the fourth back groove T4, and the microelectrode 106 can be composed of a comb-shaped electrode. The composition of the comb-shaped electrode can refer to the relevant description of the first aspect above, which will not be repeated here.

[0089] refer to Fig. 10C , using a deposition process, a third dielectric barrier layer 1085 is deposited in the fourth back trench T4 where the microelectrode 106 is formed. The material of the third dielectric barrier layer 1085 includes silicon carbide or tetraethyl orthosilicate.

[0090] refer to Fig. 10D A bonding process such as a hybrid bonding process is used to bond the surface S1 of the first wafer W102 having the third dielectric barrier layer 1085 to the top surface S2 of the second semiconductor chip 202. The top surface S2 of the semiconductor chip and the third dielectric barrier layer 1085 define a third space AP3.

[0091] refer to Fig. 10E , injecting microfluid into the third space AP3 of the microchannel 108. The material of the microfluid 109 includes a thermally conductive nanofluid containing copper, carbon or graphene.

[0092] refer to Fig.10F , a photolithography and etching process is used to form a through silicon via 104 that penetrates the glass substrate 200 and the second semiconductor chip 202 and is staggered with the microchannel 108. The composition of the through silicon via 104 can refer to the relevant description of the first aspect above, which will not be repeated here.

[0093] In some embodiments, a wafer-to-wafer (W2W) bonding packaging technology or a chip-to-wafer (D2W) bonding packaging technology may be used to obtain Figure 1 The semiconductor package structure shown.

[0094] In some embodiments, Figure 1 The semiconductor package structure shown is arranged along a scribe line (SL) 402 (refer to Figure 1) to cut the chips to obtain multiple independent semiconductor packaging structures.

[0095] The semiconductor packaging structure obtained by the manufacturing method of the semiconductor packaging structure provided in the second aspect of the embodiment of the present application is similar to the semiconductor packaging structure provided in the first aspect above. For the technical features not fully disclosed in the embodiment of the present application, please refer to the semiconductor packaging structure in the above embodiment for understanding, and no further details will be given here.

[0096] The above description is only a preferred implementation mode of the present application, and does not limit the protection scope of the present application. All equivalent structural changes made by using the contents of the present application specification and drawings under the inventive concept of the present application, or directly / indirectly applied in other related technical fields are included in the protection scope of the present application.

Claims

1. A semiconductor packaging structure, characterized in that: include: substrate; A plurality of semiconductor chips are stacked on the substrate; a microelectrode, located on top of at least one of the semiconductor chips, for receiving a micro-electric field; A microchannel is located on the top of at least one of the semiconductor chips, is arranged on or under the microelectrode and is isolated from the microelectrode to form a circulation loop; the microchannel includes a microfluid; wherein, under the action of the microelectric field, the microelectrode is used to drive the microfluid to circulate in the circulation loop to achieve heat transfer and heat transmission to the semiconductor chip.

2. The semiconductor package structure according to claim 1, wherein: At least one of the semiconductor chips further comprises a first electrode and a second electrode staggered from the microchannel; the first electrode and the second electrode are connected to the microelectrode for receiving the micro-electric field; the circulation loop comprises a first path located in the middle of the semiconductor chip and a second path located at the edge of the semiconductor chip which are connected first; The micro-electric field received by the micro-electrode located under the first path has a first electric field direction, and the first electric field direction is a direction from the first end of the micro-electrode to the second end of the micro-electrode along the first path; The micro-electric field received by the micro-electrode located under the second path has a second electric field direction, and the second electric field direction is a direction from the second end of the micro-electrode to the first end of the micro-electrode along the second path; Wherein, under the action of the micro-electric field, the circulating flow includes flowing from the first electrode to the second electrode along the first path and flowing from the second electrode to the first electrode along the second path, or flowing from the second electrode to the first electrode along the first path and flowing from the first electrode to the second electrode along the second path.

3. The semiconductor package structure according to claim 2, characterized in that: The top of each semiconductor chip includes the microelectrode and the microchannel; each semiconductor chip also includes a first dummy silicon through-hole, the first electrode and the second electrode staggered from the microchannel; the first electrode of each semiconductor chip is connected through the first dummy silicon through-hole; the second electrode of each semiconductor chip is connected through the first dummy silicon through-hole; The first electrode is connected to the first end of the microelectrode; the second electrode is connected to the second end of the microelectrode; The first electrode and the second electrode of a semiconductor chip located at the top of the multiple semiconductor chips are used to receive the micro-electric field, or the first electrode and the second electrode of a semiconductor chip located at the bottom of the multiple semiconductor chips are used to receive the micro-electric field via the substrate, so as to power the first electrode and the second electrode of each semiconductor chip to provide the micro-electric field to the microelectrode.

4. The semiconductor package structure according to claim 2 or 3, characterized in that: The first electrode and the second electrode package of a semiconductor chip located on the top of the multiple semiconductor chips are led out to the lead pad; the lead pad is used for externally connecting a DC electric field; the range of the DC electric field is 30V to 90V.

5. The semiconductor package structure according to claim 2 or 3, characterized in that: The microelectrode includes a comb-shaped electrode; the comb-shaped electrode includes a plurality of electrode pairs, one of the electrode pairs is composed of a pair of emitters and collectors; the plurality of emitters are led out to the first electrode through emitter leads, and the plurality of collectors are led out to the second electrode through collector leads.

6. The semiconductor package structure according to claim 2 or 3, characterized in that: The first path includes a main channel and a plurality of branch channels; At a position close to the first end of the microchannel, the first end of the main channel is connected to the plurality of branch channels, and the plurality of branch channels extend to the second end of the main channel; at a position close to the second end of the microchannel, the plurality of branch channels are connected to the second end of the main channel; Wherein, the cross-sectional area of ​​the main channel is larger than the cross-sectional area of ​​the branch channel.

7. The semiconductor package structure according to claim 6, characterized in that: The planar shape of the first path includes a honeycomb shape, a snowflake shape, a spider web shape or a straight shape.

8. The semiconductor package structure according to claim 2 or 3, characterized in that: At least one of the semiconductor chips further includes a second dummy through silicon via staggered from the microchannel; the second dummy through silicon via is at least located outside the second path and is used to dissipate heat for the microfluid in the second path.

9. The semiconductor package structure according to any one of claims 1 to 3, characterized in that: The microelectrode at least partially extends into the substrate of the semiconductor chip, and / or the microchannel at least partially extends into the substrate of the semiconductor chip.

10. The semiconductor package structure according to any one of claims 1 to 3, characterized in that: The material of the microelectrode includes gold, silver, platinum or aluminum; the material forming the microchannel includes silicon carbide or tetraethyl orthosilicate; the material of the microfluid includes a thermally conductive nanofluid containing copper, carbon or graphene.

11. The semiconductor package structure according to any one of claims 1 to 3, characterized in that: The width of the cross section of the microchannel is less than or equal to 10 μm, and the depth of the cross section of the microchannel is less than or equal to 20 μm.

12. A method for manufacturing a semiconductor packaging structure, characterized in that: include: providing a substrate; stacking a plurality of semiconductor chips in sequence on the substrate; forming microelectrodes on top of at least one of the semiconductor chips; The microelectrode is used to receive a micro electric field; A microchannel is formed on the top of at least one of the semiconductor chips, which is arranged on the microelectrode or under the microelectrode and isolated from the microelectrode; the microchannel constitutes a circulation loop; the microchannel includes a microfluid; wherein, under the action of the micro-electric field, the microelectrode is used to drive the microfluid to circulate in the circulation loop to achieve heat transfer and heat transmission to the semiconductor chip.

13. The manufacturing method according to claim 12, characterized in that: forming a microelectrode on top of at least one of the semiconductor chips, comprising: A first back groove is formed on the back side of at least one of the semiconductor chips; the planar shape of the first back groove includes a circulation loop; forming the microelectrode at the bottom of the first back groove; A microchannel is formed on the top of at least one of the semiconductor chips and is arranged on the microelectrode or under the microelectrode and isolated from the microelectrode, comprising: depositing a first dielectric barrier layer in the first back groove where the microelectrode is formed; Depositing a first sealing layer on the first dielectric barrier layer; the first sealing layer and the first dielectric barrier layer have a first space; The microfluid is injected into the first space to form the microchannel constituting a circulation loop.

14. The manufacturing method according to claim 12, characterized in that: forming a microelectrode on top of at least one of the semiconductor chips, comprising: A second back groove is formed on the back side of at least one of the semiconductor chips; the planar shape of the second back groove includes a circulation loop; forming the microelectrode in the second back groove; A microchannel is formed on the top of at least one of the semiconductor chips and is arranged on the microelectrode or under the microelectrode and isolated from the microelectrode, comprising: Depositing a dielectric layer on at least one of the semiconductor chips having the microelectrodes formed thereon; forming a third back trench in the dielectric layer; depositing a second dielectric barrier layer in the third back trench; Depositing a second sealing layer on the second dielectric barrier layer; the second sealing layer and the second dielectric barrier layer have a second space; The microfluid is injected into the second space to form the microchannel constituting a circulation loop.

15. The manufacturing method according to claim 12, characterized in that: forming a microelectrode on top of at least one of the semiconductor chips, comprising: providing a glass substrate; A fourth back groove is formed on the back side of the glass substrate; the plane shape of the fourth back groove includes a circulation loop; forming the microelectrode at the bottom of the fourth back groove; A microchannel is formed on the top of at least one of the semiconductor chips and is arranged on the microelectrode or under the microelectrode and isolated from the microelectrode, comprising: depositing a third dielectric barrier layer in the fourth back groove where the microelectrode is formed; The glass substrate on which the third dielectric barrier layer is formed is bonded to the top surface of the semiconductor chip; a third space is formed between the back surface of the semiconductor chip and the third dielectric barrier layer; The microfluid is injected into the third space to form the microchannel constituting a circulation loop.

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