Wafer structure and method of manufacturing the same

Abstract

The present disclosure provides a wafer structure and a manufacturing method thereof, and relates to the technical field of semiconductor, and is used to solve the technical problem of low chip yield. The wafer structure comprises a chip and a cutting channel surrounding the chip, the cutting channel has an adjacent blocking area and a filling area, the blocking area is adjacent to the chip; a buffer layer is arranged on the blocking area, at least two rows of blocking structures are arranged in the buffer layer and are spaced apart in a direction away from the chip, each row of blocking structures comprises a plurality of blocking holes penetrating through the buffer layer and being spaced apart, the blocking holes of the two adjacent rows of blocking structures are arranged in a staggered manner, and a filling layer is formed on the filling area and is located between at least two buffer layers. When the crack or the edge collapse extends in the buffer layer to the blocking hole, the crack or the edge collapse extends along the edge length direction of the blocking hole, so that the crack or the edge collapse is prevented from continuing to extend to the chip or the extending ability of the crack or the edge collapse to the chip is weakened, the chip is protected, the performance of the chip is ensured, and the chip yield is improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and in particular, to a wafer structure and a manufacturing method thereof. BACKGROUND

[0002] A wafer structure includes a plurality of dies and scribe lines isolating the dies, the dies are formed with integrated circuits, and the scribe lines are formed with test structures and the like for wafer acceptance test (WAT). The wafer is divided into individual dies by a cutting process in the scribe lines, and the dies are packaged. However, mechanical force of cutting can cause cracks or chipping in the scribe lines, and extend to the dies, affecting the use function and reliability of the dies, and the yield of the dies is low. SUMMARY

[0003] In view of the above problems, the present disclosure provides a wafer structure and a manufacturing method thereof to improve the yield of the dies.

[0004] According to some embodiments, the present disclosure provides a wafer structure including a die, and a scribe line surrounding the die, the scribe line has an adjacent blocking region and a filling region, and the blocking region is adjacent to the die;

[0005] A buffer layer is arranged on the blocking region, the buffer layer is arranged with at least two rows of blocking structures spaced apart in a direction away from the die, each row of the blocking structures includes a plurality of blocking holes penetrating through the buffer layer and spaced apart, the plurality of blocking holes of the blocking structures of adjacent two rows are arranged in a staggered manner, and a filling layer is formed on the filling region, the filling layer is located at least between the buffer layers.

[0006] In some possible examples, each row of the blocking structures surrounds a corresponding die, and at least two rows of the blocking structures are sequentially sleeved, in the adjacent two rows of the blocking structures, a gap between two adjacent blocking holes of one row of the blocking structures is opposite to the blocking holes of the other row of the blocking structures.

[0007] And / or, the material of the blocking layer includes metal.

[0008] In some possible examples, the filling region is further provided with a test structure and an alignment structure, and the filling layer covers the test structure and the alignment structure.

[0009] The buffer layer comprises a first region opposite to the test structure, and a second region opposite to the alignment structure, the arrangement density of the blocking holes in each row of the blocking structures in the first region is less than the arrangement density of the blocking holes in each row of the blocking structures in the second region.

[0010] In some possible examples, along the length direction of the chip, the length of the blocking holes in each row of the blocking structures in the first region is greater than the length of the blocking holes in each row of the blocking structures in the second region.

[0011] In some possible examples, along the length direction of the chip, the two ends of the second region protrude the two ends of the corresponding alignment structure respectively.

[0012] In some possible examples, the blocking holes in the first region are arranged at equal intervals, the blocking holes in the second region are arranged at equal intervals, and the interval between the blocking holes in the first region is equal to the interval between the blocking holes in the second region.

[0013] In some possible examples, the buffer layer comprises a third region corresponding to the corner of the chip, and a fourth region adjacent to the two ends of the third region;

[0014] The arrangement density of the blocking holes in each row of the blocking structures in the fourth region is less than the arrangement density of the blocking holes in each row of the blocking structures in the third region.

[0015] In some possible examples, the blocking holes in each row of the blocking structures in the third region are arc surfaces away from the surface of the chip, and the blocking holes in each row of the blocking structures are distributed radially.

[0016] In some possible examples, each blocking hole is filled with the filling layer or the medium layer, and the filling layer or the medium layer fills the corresponding blocking hole

[0017] The wafer structure provided by the embodiments of the present disclosure has at least the following advantages:

[0018] The wafer structure provided by the embodiments of the present disclosure includes a chip and a cutting path, the cutting path has an adjacent blocking area and a filling area, and the blocking area is adjacent to the chip. A buffer layer is arranged on the blocking area, at least two rows of blocking structures are arranged in the buffer layer in a direction away from the chip, each row of blocking structures includes a plurality of blocking holes penetrating through the buffer layer and arranged in a spaced manner, the blocking holes of the two adjacent rows of blocking structures are arranged in a staggered manner, and a filling layer is formed on the filling area and located between the buffer layers. By forming the blocking holes penetrating through the buffer layer in the buffer layer and forming the filling layer between the buffer layers, the cracks or chipping edges generated during cutting along the filling layer extend and expand in the filling layer and extend and expand to the buffer layer. When the cracks or chipping edges extend and expand to the blocking holes in the buffer layer, the cracks or chipping edges extend and expand along the edge length direction of the blocking holes, i.e., diffuse to the surrounding, thereby avoiding continuous extension and expansion to the chip or weakening the extension and expansion ability to the chip. The blocking holes can diffuse the crack effect or the chipping edge effect, so that the stress causing the cracks or the chipping edges is discontinuous and divergent, thereby protecting the chip, ensuring the performance of the chip, and improving the yield of the chip.

[0019] According to some embodiments, the present disclosure also provides a manufacturing method of a wafer structure, the wafer structure includes a chip and a cutting path surrounding the chip, the cutting path has an adjacent blocking area and a filling area, and the blocking area is adjacent to the chip.

[0020] The manufacturing method includes:

[0021] At least two rows of sacrificial structures are formed in the blocking area in a direction away from the chip, each row of the sacrificial structures includes a plurality of sacrificial blocks, and the plurality of sacrificial blocks of the two adjacent rows of the sacrificial structures are arranged in a staggered manner.

[0022] A buffer layer is formed in the blocking area, the buffer layer surrounds the chip and wraps the plurality of sacrificial blocks, and the top surface of the sacrificial block is exposed.

[0023] The sacrificial blocks are removed to form blocking holes.

[0024] A filling layer is formed in the filling area, and the filling layer is filled between at least the buffer layers.

[0025] The method for manufacturing the wafer structure in the embodiment of the present disclosure forms at least two rows of sacrificial structures in the blocking area, each row of sacrificial structures includes a plurality of sacrificial blocks, and the plurality of sacrificial blocks of the two adjacent rows of sacrificial structures are arranged in a staggered manner, forms a buffer layer in the blocking area, the buffer layer surrounds the chip and wraps the plurality of sacrificial blocks, and then removes the sacrificial blocks to form a blocking hole, and forms a filling layer in the filling area, the filling layer is filled between the buffer layers. The crack or the edge collapse generated when cutting along the filling layer extends and expands in the filling layer, and extends and expands to the buffer layer. When the crack or the edge collapse extends and expands to the blocking hole in the buffer layer, it extends and expands along the length direction of the edge of the blocking hole, that is, it spreads to the surrounding, thereby avoiding continuous extension and expansion to the chip, or weakening the expansion ability in the direction of the chip. The blocking hole can diffuse the crack effect or the edge collapse effect, so that the stress generated by the crack or the edge collapse is discontinuous and divergent, thereby protecting the chip, ensuring the performance of the chip, and improving the yield of the chip. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 A schematic diagram of a chip and a cutting path in a wafer structure in an embodiment of the present disclosure;

[0027] Figure 2 A schematic diagram of a buffer layer and a filling layer in a wafer structure in an embodiment of the present disclosure;

[0028] Figure 3 A schematic diagram of Figure 2 A structure schematic diagram at A in FIG. 1;

[0029] Figure 4 A schematic diagram of Figure 2 Another structure schematic diagram at A in FIG. 1;

[0030] Figure 5 A schematic diagram of Figure 2 A crack or edge collapse expansion schematic diagram at A in FIG. 1;

[0031] Figure 6 A schematic diagram of Figure 2 Another structure schematic diagram at A in FIG. 1;

[0032] Figure 7 A schematic diagram of Figure 2 Still another structure schematic diagram at A in FIG. 1;

[0033] Figure 8 Another schematic diagram of a buffer layer and a filling layer in a wafer structure in an embodiment of the present disclosure;

[0034] Figure 9 A schematic diagram of Figure 8 A structure schematic diagram at B in FIG. 1;

[0035] Figure 10 A flowchart of a method for manufacturing a wafer structure in an embodiment of the present disclosure;

[0036] Figure 11 A schematic view after forming a sacrificial structure in an embodiment of the present disclosure;

[0037] Figure 12 A schematic view after forming a buffer layer in an embodiment of the present disclosure;

[0038] Figure 13 A schematic view after removing the sacrificial structure in an embodiment of the present disclosure;

[0039] Figure 14 A schematic view after forming a filling layer in an embodiment of the present disclosure.

[0040] Explanation of reference signs:

[0041] 1-wafer structure; 10-die;

[0042] 20-dicing lane; 21-barrier region;

[0043] 22-filling region; 23-test structure;

[0044] 24-alignment structure; 30-buffer layer;

[0045] 31-barrier structure; 32-barrier hole;

[0046] 40-filling layer; 50-sacrificial structure;

[0047] 51-sacrificial block. DETAILED DESCRIPTION

[0048] The embodiment of the present disclosure provides a wafer structure, which comprises a die and a dicing lane, the dicing lane has a barrier region and a filling region which are adjacent to each other, and the barrier region is adjacent to the die. By arranging a buffer layer in the barrier region, arranging a barrier hole in the buffer layer, and forming a filling layer between the buffer layers, when the crack or the edge collapse generated by cutting the filling layer extends to the barrier hole, the crack or the edge collapse extends along the edge length direction of the barrier hole, so that the crack or the edge collapse does not continue to extend to the die, or the trend of extending to the die is weakened, the stress generated by the crack or the edge collapse is discontinuous and divergent, so that the die is protected, the performance of the die is ensured, and the yield of the die is improved.

[0049] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative labor fall within the protection scope of the present disclosure.

[0050] Referring to Figures 1 to 5 , the embodiments of the present disclosure provide a wafer structure 1, which comprises a chip 10 and a cutting path 20, the cutting path 20 is arranged around the chip 10. Wherein, the cutting path 20 can be circumferentially fully around the chip 10 and adjacent to the chip 10, that is, the cutting path 20 fully surrounds the chip 10, and the inner circumferential surface of the cutting path 20 is fitted with the outer circumferential surface of the chip 10.

[0051] The chip 10 is formed with a semiconductor device structure, such as a transistor, a capacitor, etc., to form an integrated circuit to realize a specific function. The cutting path 20 is formed with a test structure (test key) 23, etc., by performing a wafer acceptance test (WAT) to detect the working performance of the integrated circuit of the chip 10. The chip 10 can have multiple, and the multiple chips 10 are arranged at intervals, and the cutting path 20 surrounds each chip 10 to isolate each chip 10 from each other for cutting. As shown in Figure 1 , the chip 10 has four, and the cutting path 20 is arranged in a cross shape.

[0052] The cutting path 20 has an adjacent blocking area 21 and a filling area 22, and the blocking area 21 is adjacent to the chip 10. As shown in Figure 1 , the blocking area 21 corresponds to the chip 10, for example, each blocking area 21 circumferentially fully surrounds the corresponding chip 10 and is adjacent to the chip 10. The filling area 22 is adjacent to the blocking area 21. Exemplarily, the filling area 22 is located between each blocking area 21.

[0053] Continuing to refer to Figures 1 to 5 , the blocking area 21 is provided with a buffer layer 30, and the buffer layer 30 is provided with at least two rows of blocking structures 31 arranged at intervals in a direction away from the chip 10. The buffer layer 30 circumferentially fully surrounds the corresponding chip 10 and is adjacent to the corresponding chip 10. The buffer layer 30 is provided with at least two rows of blocking structures 31, each row of blocking structures 31 surrounds (for example, circumferentially fully surrounds) the corresponding chip 10, and the at least two rows of blocking structures 31 are sequentially arranged. By arranging at least two rows of blocking structures 31, the crack or edge collapse in the cutting process is blocked from extending to the chip 10, thereby ensuring the performance of the chip 10.

[0054] In order to protect the chip 10 all around, in some examples, as shown in Figure 2 and Figure 3 , the at least two rows of blocking structures 31 are sequentially arranged, and each row of blocking structures 31 circumferentially fully surrounds the chip 10. Exemplarily, as shown in Figure 2The two rows of blocking structures 31 are arranged on the buffer layer 30, the inner row of blocking structures 31 surrounds the chip 10, and the outer row of blocking structures 31 surrounds the inner row of blocking structures 31, so that the two rows of blocking structures 31 are arranged on the chip 10 in turn. The outer row of blocking structures 31 and the inner row of blocking structures 31 are equidistantly distributed to improve the symmetry of the two rows of blocking structures 31.

[0055] Referring back to Figures 1 to 5 , each row of blocking structures 31 includes a plurality of blocking holes 32 arranged in the buffer layer 30 and spaced apart, and the plurality of blocking holes 32 of the two adjacent rows of blocking structures 31 are arranged in a staggered manner, so that the plurality of blocking holes 32 form a grid structure. The plurality of blocking holes 32 in each row of blocking structures 31 are spaced apart, and the plurality of blocking holes 32 in each row of blocking structures 31 and the plurality of blocking holes 32 in the adjacent row of blocking structures 31 are spaced apart in a direction away from the chip 10. The blocking hole 32 can be a cylindrical hole, an elliptical cylindrical hole, a rectangular hole, or a square hole, etc.

[0056] As shown in Figure 2 and Figure 3 , in the two adjacent rows of blocking structures 31, the gap between the two adjacent blocking holes 32 of one row of blocking structures 31 is opposite to the blocking hole 32 of the other row of blocking structures 31, so that the blocking holes 32 of the two adjacent rows of blocking structures 31 are staggered, that is, the blocking holes 32 of different rows of blocking structures 31 are arranged in a staggered manner, so that as many blocking holes 32 as possible are arranged along the circumferential direction of the chip 10, thereby ensuring that the entire circumference of the chip 10 is protected.

[0057] In some possible examples, as shown in Figure 3 , in the two adjacent rows of blocking structures 31, the blocking hole 32 of one row of blocking structures 31 is opposite to the region between the two adjacent blocking holes 32 of the other row of blocking structures 31, and is opposite to the end portions of the two adjacent blocking holes 32 of the other row of blocking structures 31 that are close to each other. Along the circumferential direction of the chip 10, each blocking hole 32 spans the region between the two adjacent blocking holes 32 of the adjacent row, that is, the two end portions of each blocking hole 32 are opposite to the end portions of the two adjacent blocking holes 32 of the adjacent row that are close to each other.

[0058] Referring back to Figures 2 to 4 , the filling area 22 is provided with a filling layer 40, and the filling layer 40 is located between the buffer layers 30. The filling layer 40 is formed between the buffer layers 30 and does not contact the chip 10, and the buffer layer 30 is between the filling layer 40 and the chip 10. By forming the blocking hole 32 penetrating the buffer layer 30 in the buffer layer 30 and forming the filling layer 40 between the buffer layers 30, when the chip 10 is cut along the filling layer 40 (as shown by the dotted line in Figure 4 , the crack or edge collapse generated thereby extends in the filling layer 40 (as shown by the dotted line in Figure 4The crack or chipping extends in the buffer layer 30 (in the Y direction shown). Figure 4 Y direction as shown) to the blocking hole 32, along the side length direction of the blocking hole 32 ( Figure 4 The blocking holes 32 can diffuse the cracking or edge collapse effects, making the stress that causes the cracks or edge collapse discontinuous and divergent, thereby protecting the chip 10, ensuring the performance of the chip 10, and improving the yield of the chip 10.

[0059] For some examples, see Figure 3 The filling layer 40 fills the buffer layer 30, and the top surface of the filling layer 40 is flush with the top surface of the buffer layer 30. Each blocking hole 32 is filled with a dielectric layer, and the dielectric layer fills the corresponding blocking hole 32. In other examples, see Figure 6 The filling layer 40 fills the buffer layer 30 and the blocking hole 32, that is, the filling layer 40 fills between the buffer layers 30 and fills in the blocking hole 32, and the top surface of the filling layer 40 is flush with the top surface of the buffer layer 30. Each blocking hole 32 is filled with the filling layer 40, and the filling layer 40 fills the corresponding blocking hole 32. In some other examples, see Figure 7 The filling layer 40 is filled between the buffer layers 30, covers the buffer layers 30, and is also filled in the blocking holes 32. The top surface of the filling layer 40 is higher than the top surface of the buffer layer 30. The filling layer 40 is located in the filling area 22 (see FIG. Figure 1 ) and extends to the barrier area 21 (see Figure 1 ).

[0060] In some examples, the material of the barrier layer includes metal (e.g., pure metal), that is, the barrier layer is a metal layer. In this way, the barrier hole 32 in the buffer layer 30 can block the extension and expansion of small chipping or cracks. When a larger chipping or crack breaks through the barrier hole 32, the chipping or crack is weakened. The metal layer between the barrier hole 32 and the chip 10 (i.e., the part of the metal layer close to the chip 10) can increase the ability to resist chipping or cracks to block the weakened chipping or cracks. The metal layer between the barrier hole 32 and the chip 10 is narrower to achieve a blocking effect, that is, the distance between the barrier hole 32 and the chip 10 is smaller. In addition, the provision of the barrier hole 32 in the metal layer can also reduce the problem of excessive local stress caused by the metal layer being filled with metal.

[0061] Continue reading Figures 1 to 4A test structure 23 and an alignment structure 24 are also provided on the filling region 22. The filling layer 40 covers the test structure 23 and the alignment structure 24. The test structure 23 is used for testing the chip 10, and the alignment structure 24 is used for measurement and alignment in processes such as photolithography. The alignment structure 24 is fabricated simultaneously with the device structure. The alignment structure 24 and the device structure have the same film layer. The device structure has various sizes and shapes, while the alignment structure 24 has a standard size.

[0062] The test structure 23 is a metal structure with a certain degree of ductility, which can reduce the stress of cutting and is not prone to cracks or edge collapse during cutting. The alignment structure 24 is a combination of different materials, including silicon and other elements, which is prone to cracks or edge collapse during cutting. To this end, the buffer layer 30 includes a first area (such as Figure 4 M in FIG), and a second region opposite to the alignment structure 24 (as shown in FIG). Figure 4 As shown at N in the figure, the arrangement density of the blocking holes 32 in each row of the blocking structures 31 in the first region is less than the arrangement density of the blocking holes 32 in each row of the blocking structures 31 in the second region.

[0063] The blocking holes 32 in each row of blocking structures 31 opposite the test structures 23 are relatively sparse, while the blocking holes 32 in each row of blocking structures 31 opposite the alignment structures 24 are relatively dense. The arrangement density of the blocking holes 32 is determined based on the likelihood of cracks or edge collapse in different regions (the first region and the second region). The blocking holes 32 are denser in the second region, which is prone to cracks or edge collapse, to enhance the blocking effect. The arrangement of the blocking holes 32 is reasonable and has a high blocking efficiency.

[0064] Exemplarily, the arrangement density of the blocking holes 32 in each row of the blocking structures 31 in the first area is m, and the arrangement density of the blocking holes 32 in each row of the blocking structures 31 in the second area is greater than or equal to 2m, and the blocking effect of the blocking structure 31 is better.

[0065] In some possible implementations, such as Figure 4 As shown, along the length direction of the chip 10, the length of the blocking holes 32 in each row of the blocking structures 31 in the first region is greater than the length of the blocking holes 32 in each row of the blocking structures 31 in the second region. The blocking holes 32 in each row of the blocking structures 31 in the first region are longer, while the blocking holes 32 in each row of the blocking structures 31 in the second region are shorter, so as to achieve a dense arrangement of the blocking holes 32 in each row of the blocking structures 31 in the second region.

[0066] Continue reading Figure 4Along the length of the chip 10, the two ends of the second region protrude beyond the corresponding ends of the alignment structure 24. The second region is longer than the alignment structure 24, and the two ends of the second region protrude beyond the corresponding ends of the alignment structure 24, so that the second region can block cracks or chipping in the entire alignment structure 24, ensuring a blocking effect.

[0067] The blocking holes 32 in the first region are arranged at equal intervals, and the blocking holes 32 in the second region are arranged at equal intervals. The spacing between the blocking holes 32 in the first region is equal to the spacing between the blocking holes 32 in the second region. This arrangement ensures that the blocking holes 32 in the first and second regions are evenly spaced, and the spacing between adjacent blocking holes 32 is uniform, thereby better ensuring that the blocking holes 32 in two adjacent rows of blocking structures 31 are staggered.

[0068] See Figure 8 and Figure 9 , the buffer layer 30 further includes a third region (such as Figure 9 (As shown at E in the figure), the third area corresponds to the corner of the chip 10. During the cutting process, the cutting path 20 is cut twice in the vertical and horizontal directions, and the corner of the chip 10 is subjected to greater stress. The blocking holes 32 in the third area are arranged at a higher density to improve the ability to block cracks or edge collapse to protect the corner of the chip 10. The chip 10 can be rectangular and the third area can be fan-shaped. For example, the arc length of the third area can be greater than or equal to 1 / 10 of the side length of the chip 10.

[0069] The surfaces of the blocking holes 32 in each row of blocking structures 31 in the third region that are away from the chip 10 are curved. By forming the surfaces of the blocking holes 32 in each row of blocking structures 31 in the third region that are away from the chip 10 into curved surfaces (e.g., circular arc surfaces), stress that could cause cracks or chipping can be dispersed. The blocking holes 32 in each row of blocking structures 31 are radially distributed so that the blocking holes 32 are evenly arranged within the third region. For example, the curved surfaces of the blocking holes 32 in the same row of blocking structures 31 in the third region form a virtual curved surface.

[0070] In some examples, the buffer layer 30 further includes a fourth region (eg, Figure 9 (as shown at F in the figure), that is, the third region is connected to the fourth region at both ends. The arrangement density of the blocking holes 32 in each row of the blocking structures 31 in the fourth region is less than the arrangement density of the blocking holes 32 in each row of the blocking structures 31 in the third region. The arrangement density of the blocking holes 32 in each row of the blocking structures 31 in the fourth region can be the same as the arrangement density of the blocking holes 32 in each row of the blocking structures 31 in the first region. The arrangement density of the blocking holes 32 in each row of the blocking structures 31 in the third region can be the same as the arrangement density of the blocking holes 32 in each row of the blocking structures 31 in the second region.

[0071] For example, the arrangement density of the blocking holes 32 in each row of the blocking structures 31 in the first region is m, the arrangement density of the blocking holes 32 in each row of the blocking structures 31 in the fourth region is m, and the arrangement density of the blocking holes 32 in each row of the blocking structures 31 in the third region is greater than or equal to 2m.

[0072] In summary, the wafer structure 1 provided by the embodiment of the present disclosure includes the chip 10 and the cutting path 20. The cutting path 20 has the adjacent blocking region 21 and the filling region 22, and the blocking region 21 is adjacent to the chip 10. The blocking region 21 is provided with the buffer layer 30, and the buffer layer 30 is provided with at least two rows of blocking structures 31 arranged at intervals in the direction away from the chip 10. Each row of the blocking structures 31 includes a plurality of blocking holes 32 penetrating through the buffer layer 30 and arranged at intervals. The plurality of blocking holes 32 of the adjacent two rows of the blocking structures 31 are arranged at intervals. The filling region 22 is formed with the filling layer 40, and the filling layer 40 is located at least between the buffer layers 30. By forming the blocking holes 32 penetrating through the buffer layer 30 in the buffer layer 30 and forming the filling layer 40 between the buffer layers 30, the crack or the edge collapse generated when cutting along the filling layer 40 extends and expands in the filling layer 40 and extends and expands to the buffer layer 30. When the crack or the edge collapse extends and expands to the blocking holes 32 in the buffer layer 30, it extends and expands along the edge length direction of the blocking holes 32, that is, diffuses to the four directions, thereby avoiding the continuous extension and expansion to the chip 10 or weakening the expansion ability in the direction of the chip 10. The blocking holes 32 can diffuse the crack effect or the edge collapse effect, so that the stress generated by the crack or the edge collapse is discontinuous and divergent, thereby protecting the chip 10, ensuring the performance of the chip 10, and improving the yield of the chip 10.

[0073] The embodiment of the present disclosure also provides a manufacturing method of a wafer structure. Referring to Figures 1 to 9 , the wafer structure 1 includes the chip 10 and the cutting path 20, and the cutting path 20 is arranged around the chip 10. The cutting path 20 can circumferentially surround the chip 10 and be adjacent to the chip 10, that is, the cutting path 20 surrounds the chip 10 for a whole circumference, and the inner circumferential surface of the cutting path 20 is fitted with the outer circumferential surface of the chip 10.

[0074] The chip 10 is formed with a semiconductor device structure, such as a transistor, a capacitor, etc., to form an integrated circuit and realize a specific function. The cutting path 20 is formed with a test structure 23, etc., so that the wafer can be subjected to a wafer acceptance test to detect the working performance of the integrated circuit. The chip 10 can have a plurality of chips 10 arranged at intervals, and the cutting path 20 surrounds each chip 10 to isolate the chips 10 from each other, thereby facilitating cutting.

[0075] The cutting path 20 has the adjacent blocking region 21 and the filling region 22, and the blocking region 21 is adjacent to the chip 10. As Figure 1As shown, the blocking region 21 corresponds to the chip 10, each blocking region 21 circumferentially fully surrounds the corresponding chip 10, and the filling region 22 is adjacent to the blocking region 21. Exemplarily, the filling region 22 is located between the blocking regions 21.

[0076] Referring to Figure 10 , the method for manufacturing the wafer structure 1 can specifically include the following steps:

[0077] Step S100: In the blocking region, at least two rows of sacrificial structures are formed and arranged at intervals in a direction away from the chip, each row of sacrificial structures includes a plurality of sacrificial blocks, and the plurality of sacrificial blocks of the adjacent two rows of sacrificial structures are arranged in a staggered manner.

[0078] Referring to Figure 1 and Figure 11 , at least two rows of sacrificial structures 50 are formed in the blocking region 21, and the at least two rows of sacrificial structures 50 are arranged at intervals in a direction away from the chip 10. That is, the at least two rows of sacrificial structures 50 are sequentially arranged, and the innermost row of sacrificial structures 50 is arranged on the chip 10. Each row of sacrificial structures 50 is arranged at intervals and is arranged at intervals with the chip 10.

[0079] Each row of sacrificial structures 50 includes a plurality of sacrificial blocks 51, the plurality of sacrificial blocks 51 in the same row are arranged at intervals, and the plurality of sacrificial blocks 51 in the adjacent two rows are arranged in a staggered manner. When the position where the sacrificial block 51 is located forms the blocking hole 32 (see Figure 13 ), the plurality of blocking holes 32 of the adjacent two rows of blocking structures 31 are arranged in a staggered manner. The sacrificial block 51 can be a cylinder, an elliptical cylinder, a rectangular column or a square column, and the material of the sacrificial block 51 can be photoresist (resist). As Figure 11 shown, the blocking region 21 forms two rows of sacrificial structures 50, and the plurality of sacrificial blocks 51 in the same row are arranged at intervals, and the sacrificial block 51 is a rectangular column.

[0080] In some examples, in the adjacent two rows of sacrificial structures 50, the gap between the adjacent two sacrificial blocks 51 of one row of sacrificial structures 50 is opposite to the sacrificial block 51 of the other row of sacrificial structures 50, so that the sacrificial blocks 51 of the adjacent two rows of sacrificial structures 50 are staggered, so that as many sacrificial blocks 51 as possible are arranged along the circumference of the chip 10, thereby ensuring that the entire circumference of the chip 10 is protected.

[0081] In some examples, in the adjacent two rows of sacrificial structures 50, the gap between the adjacent two sacrificial blocks 51 of one row of sacrificial structures 50 is opposite to the sacrificial block 51 of the other row of sacrificial structures 50, so that the sacrificial blocks 51 of the adjacent two rows of sacrificial structures 50 are staggered, so that as many sacrificial blocks 51 as possible are arranged along the circumference of the chip 10, thereby ensuring that the entire circumference of the chip 10 is protected.

[0082] AsFigure 11 As shown, for the two adjacent rows of the sacrifice structures 50, the left end of any sacrifice block 51 is opposite to the right end of the sacrifice block 51 on the left side of the two adjacent sacrifice blocks 51 in the adjacent row, and the left and right of any sacrifice block 51 are opposite to the left end of the sacrifice block 51 on the right side of the two adjacent sacrifice blocks 51 in the adjacent row. In this way, the plurality of sacrifice blocks 51 in the two adjacent rows of the sacrifice structures 50 partially overlap along the circumference of the chip 10, so that the sacrifice blocks 51 are opposite to each other around the entire circumference of the chip 10, and the entire circumference of the chip 10 is provided with a barrier.

[0083] Step S200: forming a buffer layer in the barrier region, the buffer layer surrounds the chip and wraps the plurality of sacrifice blocks, and the top surface of the sacrifice block is exposed.

[0084] Referring to Figure 12 The buffer layer 30 wraps the plurality of sacrifice blocks 51 and forms a whole along the circumference of the chip 10, that is, the buffer layer 30 circumferentially surrounds the chip 10. The buffer layer 30 covers the side surface of the plurality of sacrifice blocks 51 to expose the top surface of the sacrifice block 51, facilitating the removal of the sacrifice layer. The buffer layer 30 can be metal, which has good ductility to block the extension of the crack or the edge collapse to the chip 10. Exemplarily, the buffer layer 30 can be formed in the remaining barrier region 21 by a sputtering process. The alignment structure 24 and / or the test structure 23 can be formed in the filling region 22.

[0085] Step S300: removing the sacrifice blocks to form barrier holes.

[0086] Referring to Figure 12 and Figure 13 The sacrifice blocks 51 are removed, for example, by a developing process to remove all the sacrifice blocks 51 to form barrier holes 32 in the buffer layer 30. When the crack or the edge collapse extends in the buffer layer 30 to the barrier holes 32, it extends along the edge length direction of the barrier holes 32, that is, diffuses to the four directions, thereby avoiding the continuous extension to the chip 10 or weakening the extension trend to the chip 10. The barrier holes 32 can diffuse the crack effect or the edge collapse effect, so that the stress causing the crack or the edge collapse is discontinuous and divergent, thereby protecting the chip 10 and ensuring the performance of the chip 10. In addition, the barrier holes 32 arranged in the buffer layer 30 can also reduce the problem of excessive local stress caused by the full coverage of the buffer layer 30.

[0087] Step S400: forming a filling layer in the filling region, the filling layer at least fills between the buffer layers.

[0088] Referring to Figure 14The filling layer 40 is located between the buffer layers 30 and does not contact the chip 10. The crack or the chipping generated when cutting along the filling layer 40 extends in the filling layer 40 and extends to the buffer layer 30. The crack or the chipping can also be blocked when the crack or the chipping breaks through the blocking hole 32 in the buffer layer 30 and extends to between the blocking hole 32 and the chip 10.

[0089] In some examples, the filling layer 40 fills the buffer layer 30, and the top surface of the filling layer 40 is flush with the top surface of the buffer layer 30. In other examples, the filling layer 40 fills the buffer layer 30 and the blocking hole 32, that is, the filling layer 40 fills between the buffer layers 30 and fills in the blocking layer, and the top surface of the filling layer 40 is flush with the top surface of the buffer layer 30. In yet other examples, the filling layer 40 fills the buffer layer 30 and the blocking hole 32 and covers the buffer layer 30, that is, the top surface of the filling layer 40 is higher than the top surface of the buffer layer 30, and the filling layer 40 is located in the filling area 22 and extends to the blocking area 21.

[0090] In summary, the manufacturing method of the wafer structure 1 in the embodiments of the present disclosure forms at least two rows of sacrificial structures 50 in the blocking area 21, each row of sacrificial structures 50 includes a plurality of sacrificial blocks 51, and the plurality of sacrificial blocks 51 of the two adjacent rows of sacrificial structures 50 are arranged in a staggered manner. The buffer layer 30 is formed in the blocking area 21, the buffer layer 30 surrounds the chip 10 and wraps the plurality of sacrificial blocks 51, and then the sacrificial blocks 51 are removed to form the blocking hole 32. The filling layer 40 is formed in the filling area 22, and the filling layer 40 is filled at least between the buffer layers 30. When cutting along the filling layer 40, the crack or the chipping extends in the filling layer 40 and extends to the buffer layer 30. When the crack or the chipping extends to the blocking hole 32 in the buffer layer 30, it extends along the length direction of the blocking hole 32, that is, it spreads to all directions, thereby avoiding further extending to the chip 10 or weakening the extending ability in the direction of the chip 10. The blocking hole 32 can diffuse the crack effect or the chipping effect, so that the stress generated by the crack or the chipping is discontinuous and divergent, thereby protecting the chip 10, ensuring the performance of the chip 10, and improving the yield of the chip 10.

[0091] The embodiments or examples in the specification are described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts between the embodiments can be mutually referred to. The description of the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In the specification, the exemplary description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0092] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present disclosure, but not to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand: the technical solutions recorded in the foregoing embodiments can still be modified, or some or all of the technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A wafer structure, characterized in that: The invention comprises a chip and a dicing street surrounding the chip, wherein the dicing street has a barrier area and a filling area adjacent to each other, and the barrier area is adjacent to the chip; A buffer layer is provided on the blocking area, and at least two rows of blocking structures are provided in the buffer layer and are spaced apart in a direction away from the chip. Each row of the blocking structures includes a plurality of blocking holes penetrating the buffer layer and spaced apart. The plurality of blocking holes in two adjacent rows of the blocking structures are staggered. A filling layer is formed on the filling area, and the filling layer is at least located between the buffer layers. A test structure and an alignment structure are further provided on the filling area, and the filling layer covers the test structure and the alignment structure; The buffer layer includes a first area opposite to the test structure and a second area opposite to the alignment structure, and an arrangement density of the blocking holes in each row of the blocking structures in the first area is less than an arrangement density of the blocking holes in each row of the blocking structures in the second area.

2. The wafer structure according to claim 1, wherein: Each row of the blocking structures surrounds the corresponding chip, and at least two rows of the blocking structures are nested in sequence. In two adjacent rows of the blocking structures, the gap between two adjacent blocking holes of one row of the blocking structures is opposite to the blocking holes of the other row of the blocking structures.

3. The wafer structure according to claim 1, wherein: Along the side length direction of the chip, the length of the blocking holes in each row of the blocking structures in the first region is greater than the length of the blocking holes in each row of the blocking structures in the second region.

4. The wafer structure according to claim 1, wherein: Along the length direction of the chip, two ends of the second region protrude from two ends of the corresponding alignment structure.

5. The wafer structure according to claim 1, wherein: The blocking holes in the first area are arranged at equal intervals, the blocking holes in the second area are arranged at equal intervals, and the spacing between the blocking holes in the first area is equal to the spacing between the blocking holes in the second area.

6. The wafer structure according to claim 1 or 2, characterized in that: The buffer layer includes a third region corresponding to a corner of the chip, and a fourth region adjacent to both ends of the third region; An arrangement density of the blocking holes in each row of the blocking structures in the fourth region is smaller than an arrangement density of the blocking holes in each row of the blocking structures in the third region.

7. The wafer structure according to claim 6, characterized in that: The surface of the blocking holes in each row of the blocking structures in the third region away from the chip is a curved surface, and the blocking holes in each row of the blocking structures are distributed radially.

8. The wafer structure according to claim 1 or 2, characterized in that: Each of the blocking holes is filled with the filling layer, and the filling layer fills up the corresponding blocking hole.

9. A method for manufacturing a wafer structure, characterized in that: The wafer structure includes a chip and a dicing street surrounding the chip, the dicing street having a barrier area and a filling area adjacent to each other, and the barrier area is adjacent to the chip; a buffer layer is provided on the barrier area, and at least two rows of barrier structures are provided in the buffer layer and are arranged in a direction away from the chip, each row of the barrier structures includes a plurality of barrier holes penetrating the buffer layer and arranged in a spaced-apart manner; The production method comprises: At least two rows of sacrificial structures are formed in the blocking area and arranged in a direction away from the chip, each row of the sacrificial structures includes a plurality of sacrificial blocks, and the plurality of sacrificial blocks of the sacrificial structures in two adjacent rows are staggered; forming a buffer layer in the barrier region, the buffer layer surrounding the chip and wrapping the plurality of sacrificial blocks, with top surfaces of the sacrificial blocks exposed; removing the sacrificial block to form a blocking hole; forming a filling layer in the filling area, wherein the filling layer is at least filled between the buffer layers; Wherein, a test structure and an alignment structure are further provided on the filling area, and the filling layer covers the test structure and the alignment structure; The buffer layer includes a first area opposite to the test structure and a second area opposite to the alignment structure, and an arrangement density of the blocking holes in each row of the blocking structures in the first area is less than an arrangement density of the blocking holes in each row of the blocking structures in the second area.

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