Chip module, self-testing method, preparation method of receiving chip and laser radar

Abstract

The embodiment of the invention relates to the field of laser radars, and discloses a chip module, a self-testing method, a preparation method of a receiving chip and a laser radar. The chip module comprises a packaging substrate; the system-on-chip is arranged on the surface of the packaging substrate; the at least two receiving chips comprise a first receiving chip and a second receiving chip which are arranged on the surface of the system-on-chip and are respectively used for receiving laser signals and visible light signals; the cover body is arranged on the packaging substrate, the cover body and the packaging substrate jointly define a mounting cavity, the system-on-chip, the first receiving chip and the second receiving chip are all located in the mounting cavity, and the cover body is provided with a first area and a second area through which laser signals and visible light signals pass. The chips for receiving the laser signals and the visible light signals are integrated on the system-level chip, so that the positions of observation points for receiving the laser signals and the visible light signals are approximately consistent, the error of unified calculation of point cloud data and image data coordinates is reduced, the accuracy of data fusion is improved, and the size of the laser radar is reduced.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of laser radar technology, and in particular to a chip module, a self-testing method, a method for preparing a receiving chip, and a laser radar. Background Art

[0002] LiDAR and camera are important sensors in vehicle-mounted systems. The fusion of LiDAR and camera data is an important development direction for vehicle-mounted / robot information sensing. At present, LiDAR and camera are usually two independent devices that need to be placed in different positions on the car / robot. Due to the inconsistency of the signal collection positions of the two devices, the unified coordinate calculation of their data is very complicated, and information mismatch is prone to occur during the data fusion process. In addition, LiDAR and camera are two independent devices, which will also result in a larger physical space occupied, which is not conducive to the integration and miniaturization of sensor equipment. Summary of the invention

[0003] The embodiments of the present application provide a chip module, a self-test method, a method for preparing a receiving chip, and a laser radar, which aim to improve the current situation where the laser radar and the camera, when used in combination, occupy a large physical space as a whole, which is not conducive to miniaturization.

[0004] In the first aspect, an embodiment of the present application provides a chip module, including a packaging substrate, a system-level chip, at least two receiving chips and a cover body. The system-level chip is arranged on the surface of the packaging substrate. At least two receiving chips are arranged on the surface of the system-level chip, and the at least two receiving chips include a first receiving chip and a second receiving chip, the first receiving chip is used to receive laser signals, and the second receiving chip is used to receive visible light signals. The cover body is arranged on the packaging substrate, and the cover body and the packaging substrate are together enclosed to form an installation cavity, the system-level chip, the first receiving chip and the second receiving chip are all located in the installation cavity, and the cover body is provided with a first area for the laser signal to pass through and a second area for the visible light signal to pass through. The chip module solves the problem of a single chip receiving laser signals and visible light signals at the same time, and reduces the size of the laser radar.

[0005] In some embodiments, the system-level chip is provided with a through silicon via, and a first material layer is provided in the through silicon via, and the thermal conductivity of the first material layer is higher than a preset threshold value; the first receiving chip covers at least one through silicon via and is electrically connected to the packaging substrate through the first material layer; the second receiving chip covers at least one through silicon via and is electrically connected to the packaging substrate through the first material layer. The first material layer in the through silicon via quickly conducts the heat generated by the first receiving chip and the second receiving chip after operation to the packaging substrate, greatly improving the heat dissipation efficiency and reducing the thermal resistance of the first receiving chip and the second receiving chip.

[0006] In some embodiments, the first receiving chip and the second receiving chip are both electrically connected to the system-level chip through hybrid bonding; the system-level chip and the packaging substrate are electrically connected through hybrid bonding. Hybrid bonding technology realizes high-density interconnection between chips, which not only improves the integration, response speed and performance of the system, but also improves the connection strength and stability between chips.

[0007] In some embodiments, the system-level chip is used to control the second receiving chip to be turned off when the first receiving chip is turned on; the system-level chip is used to control the second receiving chip to be turned on when the first receiving chip is turned off. The above settings can avoid mutual interference between laser signals and visible light signals, thereby improving the quality of received signals.

[0008] In some embodiments, the system-level chip is used to receive the laser signal processed by the first receiving chip, and obtain point cloud data based on the processed laser signal; the system-level chip is used to receive the visible light signal processed by the second receiving chip, and obtain image data based on the processed visible light signal.

[0009] In some embodiments, the system-level chip also includes a fusion unit; the fusion unit is used to perform coordinate unification calculation on the point cloud data and the image data, and obtain fused data, and the fused data includes the point cloud data and the image data after the coordinates are unified.

[0010] In some embodiments, the system-level chip further includes a communication interface; the communication interface is used to transmit the fused data from the chip module to a device outside the chip module.

[0011] In the second aspect, the embodiment of the present application provides a self-test method for a chip module, which is applied to the chip module in any of the above embodiments, and the method includes: receiving first excitation data output by a first receiving chip, wherein the first excitation data is point cloud data pre-stored by the first receiving chip and obtained based on a preset scene; receiving second excitation data output by a second receiving chip, wherein the second excitation data is point cloud data pre-stored by the second receiving chip and obtained based on a preset scene; fusing the first fusion data according to the first excitation data and the second excitation data, wherein the first fusion data includes information of the first excitation data and the second excitation data; obtaining a comparison result of the first fusion data and the expected data according to the first fusion data and the expected data, wherein the expected data is a result obtained by fusing the first excitation data and the second excitation data in advance; determining whether the signal path of the system-level chip, the first receiving chip, the second receiving chip and the package substrate is abnormal according to the comparison result; wherein the first excitation data and the second excitation data both correspond to the same preset scene. By adopting the above method to perform self-test on the chip, self-test can be realized inside the chip without investing in additional test equipment or devices, reducing the test cost, significantly shortening the test process and test time, and improving the test efficiency.

[0012] In a third aspect, an embodiment of the present application provides a method for preparing a receiving chip, which is applied to a chip module in any one of the above embodiments, wherein the receiving chip includes a device layer and a substrate layer, the device layer is connected to the system-level chip, and the substrate layer is located on a side of the device layer away from the system-level chip. The method for preparing the receiving chip includes: Step S1: photolithography is performed on the substrate layer using a mask of a preset width, so that the substrate layer forms a first boss and first recesses located on both sides of the first boss; Step S2: using a mask with a larger width than the mask used in the previous round, photolithography is performed on a part of the recessed groove formed in the previous round, so that the substrate layer forms a second boss supporting the boss formed in the previous round, and second recessed grooves located on both sides of the second boss; and, Step S3: Repeat step S2; The boss includes a first boss and a second boss, and the groove includes a first groove and a second groove. By directly performing photolithography on the substrate layer of the receiving chip, not only the integration of the receiving chip is improved, but also high-precision preparation of the receiving chip is achieved. In addition, by directly performing photolithography on the substrate layer of the receiving chip, the preparation of the entire process of the receiving chip from the device layer to the substrate layer can be completed at the same location, shortening the processing time of the receiving chip.

[0013] In some embodiments, a substrate layer is photolithographically processed using a mask of a preset width so that the substrate layer forms a first boss and a first groove located on both sides of the first boss, including: coating a photoresist on the surface of the substrate layer to obtain a first adhesive layer; exposing the first adhesive layer to ultraviolet light using a mask of a preset width; developing the exposed area of ​​the first adhesive layer so that the substrate layer forms a first area covered by the first adhesive layer and a second area is exposed; etching the second area to obtain a first groove; and removing the first adhesive layer so that the substrate layer forms a first boss and a first groove located on both sides of the first boss.

[0014] In some embodiments, a mask with a larger width than the mask used in the previous round is used to perform photolithography on a partial area of ​​the groove formed in the previous round, so that the substrate layer forms a second boss supporting the boss formed in the previous round, and a second groove located on both sides of the second boss, including: coating a photoresist on the surface of the substrate layer to obtain a second adhesive layer; using a mask with a larger width to expose the second adhesive layer to ultraviolet light, wherein the mask with a larger width blocks the boss formed in the previous round; developing the exposed area of ​​the second adhesive layer, so that the substrate layer forms a third area covered by the second adhesive layer, and a set fourth area is exposed; etching the fourth area to obtain a second groove; and removing the second adhesive layer, so that the substrate layer forms a second boss and second grooves located on both sides of the second boss.

[0015] In a fourth aspect, an embodiment of the present application provides a laser radar, comprising a shell and a chip module as in any of the above embodiments, wherein the chip module is disposed in the shell.

[0016] The technical solution provided by this application includes the following beneficial effects: The present invention discloses a chip module, a self-test method, a method for preparing a receiving chip and a laser radar. By integrating a chip for receiving laser signals and a chip for receiving visible light signals on a system-level chip, the observation point positions of the received laser signals and the visible light signals are made nearly consistent, thereby reducing the error in the unified calculation of the coordinates of point cloud data and image data, thereby improving the accuracy of data fusion and also reducing the size of the laser radar. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 is a schematic diagram of a side view of a chip module provided in an embodiment of the present application; Figure 2 is a schematic diagram of a top view of a chip module provided in an embodiment of the present application; Figure 3 It is a communication schematic diagram of a chip module provided in an embodiment of the present application; Figure 4 is a flow chart of a chip module self-test method provided in an embodiment of the present application; Figure 5 is a schematic diagram of a receiving chip provided in an embodiment of the present application; Figure 6 is a flow chart of a method for preparing a receiving chip provided in an embodiment of the present application; Figure 7 yes Figure 6 The manufacturing process flow chart corresponding to step S1; Figure 8 yes Figure 6 The production process flow chart corresponding to step S2 in FIG.

[0019] Wherein, each figure is marked as: 1. Chip module; 10. Packaging substrate; 11. System-level chip; 12. Receiving chip; 12a. First receiving chip; 12b. Second receiving chip; 13. Cover; 111. Through silicon via; 130. Dam; 131. Cover plate; 1311. First area; 1312. Second area; 110. Bus; 120. Main control unit; 140. First serial interface; 141. Second serial interface; 150. Control unit; 160. Storage unit; 170. Fusion unit; 180. Transmission unit; 190. Communication interface; 2. Equipment; 121. Device layer; 122. Substrate layer; 123. First glue layer; 124. Second glue layer; 1221. First boss; 1222. First groove; 1223. Second boss; 1224. Second groove. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical scheme and advantages of the present application clearer, the technical scheme in the embodiment of the present application will be described clearly and in detail below in conjunction with the drawings in the embodiment of the present application. Obviously, the described embodiment is a part of the embodiment of the present application, rather than all the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0021] The fusion of LiDAR point cloud data and traditional camera image data is an important development direction for vehicle / robot information sensing. At present, LiDAR and camera are usually two independent devices, placed in different positions of the vehicle / robot. Since the positions of LiDAR and camera information collection are inconsistent, the coordinate unification calculation when the point cloud data and image data are fused is very complicated, and information mismatch is prone to occur during the fusion process. In addition, LiDAR and camera are two independent devices, which will also cause them to occupy a larger physical space, which is not conducive to the integration and miniaturization of sensors.

[0022] Based on this, the embodiments of the present application aim to provide a chip module, a self-test method, a method for preparing a receiving chip, and a laser radar, aiming to improve the current situation in which the laser radar and the camera occupy a large physical space as a whole when used in conjunction, which is not conducive to miniaturization. In addition, the chip module can also reduce the error in the same calculation of the coordinates of the point cloud data and the image data, and improve the accuracy of the fusion of the point cloud data and the image data. The embodiments in this application are all described by taking the application of the chip module 1 to a laser radar as an example, but in other embodiments of the present application, the chip module 1 can also be applied to other products, such as robots, drones, etc.

[0023] like Figure 1 As shown, Figure 1 A schematic diagram of a side view of a chip module 1 provided in an embodiment of the present application. The chip module 1 includes a packaging substrate 10, a system-on-chip 11 (System on Chip, SOC), at least two receiving chips 12 and a cover 13. The system-on-chip 11 is arranged on the surface of the packaging substrate 10. The at least two receiving chips 12 include a first receiving chip 12a and a second receiving chip 12b, the first receiving chip 12a and the second receiving chip 12b are arranged on the surface of the system-on-chip 11, the first receiving chip 12a is used to receive laser signals, and the second receiving chip 12b is used to receive visible light signals. The cover 13 is arranged on the packaging substrate 10, and the cover 13 and the packaging substrate 10 are together surrounded to form an installation cavity, the system-on-chip 11, the first receiving chip 12a and the second receiving chip 12b are all located in the installation cavity, and the cover 13 is provided with a first area 1311 for the laser signal to pass through and a second area 1312 for the visible light signal to pass through.

[0024] The package substrate 10 is not only a base for mounting the system-level chip 11 and the cover 13, but also used to realize the electrical connection between the chip module 1 and the external device of the chip module 1. In one embodiment, the package substrate 10 includes a conductive structure, which is used to realize the electrical connection between the chip module 1 and the external circuit to ensure that the chip module 1 can work normally. Specifically, the package substrate 10 is used to supply power to the system-level chip 11, the first receiving chip 12a and the second receiving chip 12b.

[0025] The system-level chip 11 is arranged on the surface of the package substrate 10, and is used to support the first receiving chip 12a and the second receiving chip 12b. In some embodiments, the system-level chip 11 is provided with a through-silicon via 111 (TSV), and a first material layer is provided in the through-silicon via 111, and the thermal conductivity of the first material layer is higher than a preset threshold; the first receiving chip 12a covers at least one through-silicon via 111, and is electrically connected to the package substrate 10 through the first material layer; the second receiving chip 12b covers at least one through-silicon via 111, and is electrically connected to the package substrate 10 through the first material layer. In one embodiment, the preset threshold is 300 W / (m·K), and the first material layer includes copper or other medium with high thermal conductivity.

[0026] Specifically, the areas and positions of the first receiving chip 12 a and the second receiving chip 12 b need to be determined on the system-level chip 11 , and then through silicon vias 111 are provided at the positions of the first receiving chip 12 a and the second receiving chip 12 b on the system-level chip 11 .

[0027] Furthermore, the process of forming the through silicon via 111 includes etching, insulating layer deposition, barrier layer deposition, filling, annealing, chemical-mechanical planarization (CMP), and wafer thinning. In one embodiment, a hole is first formed on the system-level chip 11 by etching, and then an insulating layer and a barrier layer are deposited in the hole, and then copper is filled into the hole by electroplating. Finally, after chemical mechanical polishing and wafer thinning, the through silicon via 111 is formed on the system-level chip 11, and a bonding metal pad (pad), i.e., a copper pad, is formed on the through silicon via 111. In one embodiment, the first material layer in the through silicon via 111 is copper.

[0028] On the one hand, the through silicon via 111 is used to realize the electrical connection between the first receiving chip 12a and the second receiving chip 12b and the packaging substrate 10 respectively. Specifically, the packaging substrate 10 supplies power to the first receiving chip 12a and the second receiving chip 12b through the through silicon via 111. On the other hand, when the first receiving chip 12a and the second receiving chip 12b are working, the heat generated by the first receiving chip 12a and the second receiving chip 12b can be quickly conducted to the packaging substrate 10 through the first material layer in the through silicon via 111, which effectively improves the heat dissipation efficiency of the chip and reduces the thermal resistance of the chip.

[0029] The first receiving chip 12a and the second receiving chip 12b are respectively arranged on the surface of the system-level chip 11. The first receiving chip 12a is used to receive laser signals, and the second receiving chip 12b is used to receive visible light signals. In one embodiment, the laser signal received by the first receiving chip 12a is in the range of 850 nm to 1600 nm, and the visible light signal received by the second receiving chip 12b is in the range of 400 nm to 700 nm.

[0030] Specifically, the laser signal may refer to the echo laser formed by the laser emitted by the laser radar being reflected by the objects within the detection range. The laser signal may be used to obtain relevant information about the objects within the detection range, such as physical distance, speed, shape and other information; the visible light signal refers to the visible light reflected by the objects within the detection range. The visible light signal may be used to obtain relevant information about the objects within the detection range, such as brightness, color, shape and contour and other information.

[0031] In some embodiments, the first receiving chip 12a and the second receiving chip 12b are electrically connected to the system-level chip 11 through hybrid bonding (HyperBonding), and the system-level chip 11 and the packaging substrate 10 are electrically connected through hybrid bonding. In one embodiment, the first receiving chip 12a is a single photon avalanche diode (SPAD) chip, referred to as a SPAD chip. In one embodiment, the second receiving chip 12b is a CMOS image sensor (CIS) chip, referred to as a CIS chip.

[0032] Specifically, the first receiving chip 12a and the second receiving chip 12b are directly bonded to the copper pads of the system-level chip 11 through hybrid bonding technology to achieve copper-to-copper connection, thereby achieving electrical connection between the first receiving chip 12a and the second receiving chip 12b and the system-level chip 11 respectively. Hybrid bonding embeds metal pads in the bonding interface so that there is no signal interference between the pads, thereby improving the integrity and stability of the signal. Since hybrid bonding uses direct copper-to-copper connection, on the one hand, it reduces the signal transmission path between the chips in the chip module 1, thereby improving the data transmission speed; on the other hand, it reduces the need for physical connection between chips, reduces the mechanical stress and resistance inside the chip, and thus reduces power consumption.

[0033] Furthermore, the hybrid bonding technology integrates the first receiving chip 12a, the second receiving chip 12b, the system-level chip 11 and the packaging substrate 10 in a vertical stacking manner, which not only improves the integration of the chip module 1, realizes high-density interconnection between chips, reduces the volume of the laser radar, but also improves the connection strength and stability between chips. In addition, the hybrid bonding technology effectively reduces the thermal resistance of the chip module 1 and improves the heat dissipation performance through a compact structure and a direct conductive path.

[0034] In some embodiments, the cover body 13 includes a dam 130 and a cover plate 131, which are used to encapsulate the system-level chip 11, the first receiving chip 12a and the second receiving chip 12b. Among them, one end of the dam 130 is fixed to the first surface of the packaging substrate 10 provided with the system-level chip 11, and the other end extends away from the first surface. The cover plate 131 is fixed to the end of the dam 130 away from the first surface, so that the packaging substrate 10, the dam 130 and the cover plate 131 are surrounded to form an installation cavity, which is used to fix and protect the system-level chip 11, the first receiving chip 12a and the second receiving chip 12b, and prevent the chips in the cavity from being displaced or damaged during packaging or transportation. In one embodiment, the material of the dam 130 includes dual adhesive material (DMA), and the material of the cover plate 131 includes glass.

[0035] In one embodiment, the cover plate 131 is fixed to the end of the dam 130 away from the first surface, and is bonded to the dam 130 by glue, thereby achieving the packaging of the system-level chip 11, the first receiving chip 12a, and the second receiving chip 12b in the chamber, ensuring good air tightness and water tightness in the chamber. In addition, bonding the dam 130 and the cover plate 131 by glue also effectively prevents rain or dust from entering the chamber to damage the chip.

[0036] In some embodiments, the cover plate 131 includes a first area 1311 and a second area 1312, which are respectively used to refract the laser and the visible light into the closed chamber to obtain the refracted laser and the visible light, and focus the refracted laser onto the first receiving chip 12a, and the refracted visible light onto the second receiving chip 12b. In one embodiment, the first area 1311 and the second area 1312 both include convex lenses, which are used to focus the laser and the visible light outside the laser radar onto the first receiving chip 12a and the second receiving chip 12b, respectively. In another embodiment, the first area 1311 includes a microlens array, each microlens in the microlens array corresponds to a SPAD unit in the area array SPAD chip, and the microlens is used to improve the single photon detection efficiency of the first receiving chip 12a in a low-photon environment to ensure the accuracy of the point cloud data; the second area 1312 includes a microlens array and an infrared cutoff filter, and the microlens array and the infrared cutoff filter are respectively arranged on both sides of the cover 131, and the microlens array is used to focus visible light onto the second receiving chip 12b to improve the collection efficiency and imaging quality of visible light, and the infrared cutoff filter is used to transmit visible light and cut off or reflect infrared light to ensure the quality of image data and color accuracy.

[0037] The first receiving chip 12a processes the received refracted laser signal, and transmits it to the system-level chip 11 through the metal pad. After being processed by the system-level chip 11, point cloud data is finally obtained; the second receiving chip 12b processes the received refracted visible light signal, and transmits it to the system-level chip 11 through the metal pad. After being processed by the system-level chip 11, image data is finally obtained.

[0038] like Figure 2 As shown, Figure 2 A schematic diagram of a top view of a chip module 1 provided in an embodiment of the present application. In some embodiments, the first receiving chip 12a and the second receiving chip 12b are spaced apart along a first preset direction X. Specifically, the first preset direction X is the extension direction of the long side or the wide side of the surface of the system-level chip 11. In an embodiment of the present application, the first preset direction X is the extension direction of the long side of the surface of the system-level chip 11. Since the size of the system-level chip 11 is usually small, the first receiving chip 12a and the second receiving chip 12b are both arranged on the surface of the system-level chip 11, and the distance is relatively close, so the consistency of the signals received by the first receiving chip 12a and the second receiving chip 12b can be improved. It should be understood that the present invention does not impose any specific restrictions on the positions of the first receiving chip 12a and the second receiving chip 12b on the system-level chip 11.

[0039] In one embodiment, the through silicon vias 111 covered by the first receiving chip 12a and the second receiving chip 12b are distributed on the system-level chip 11 in the form of an M×N array, where M is the number of rows of the array, N is the number of columns of the array, and both M and N are integers greater than or equal to 1.

[0040] In addition, setting both the first receiving chip 12a and the second receiving chip 12b on the system-level chip 11 can not only reduce the volume and weight of the laser radar, but also reduce the cost of the laser radar system, and is also conducive to improving the integration of the laser radar.

[0041] like Figure 3 As shown, Figure 3 A communication schematic diagram of a chip module 1 provided in an embodiment of the present application. The chip module 1 includes a system-level chip 11, a first receiving chip 12a and a second receiving chip 12b. The first receiving chip 12a and the second receiving chip 12b are respectively connected to the system-level chip 11, and the system-level chip 11 is used to control the first receiving chip 12a and the second receiving chip 12b.

[0042] In some embodiments, the system-level chip 11 is used to control the second receiving chip 12b to be turned off when the first receiving chip 12a is turned on; the system-level chip 11 is used to control the second receiving chip 12b to be turned on when the first receiving chip 12a is turned off. The control method of the system-level chip 11 can avoid mutual interference between laser signals and visible light signals, and improve the quality of the signals received by the first receiving chip 12a and the second receiving chip 12b respectively.

[0043] In some embodiments, the system-level chip 11 is used to receive the laser signal processed by the first receiving chip 12a, and obtain point cloud data based on the processed laser signal; the system-level chip 11 is used to receive the visible light signal processed by the second receiving chip, and obtain image data based on the processed visible light signal.

[0044] In one embodiment, after the system-level chip 11 is powered on, the first receiving chip 12a and the second receiving chip 12b are first initialized. Specifically, the system-level chip 11 sets the detection threshold and other parameters of the first receiving chip 12a to improve the response capability to the laser signal; and sets the exposure time and other parameters of the second receiving chip 12b to ensure that high-quality image data can be obtained. In addition, the system-level chip 11 initializes the first receiving chip 12a and the second receiving chip 12b, and also includes error detection processing to ensure that the hardware devices of the first receiving chip 12a and the second receiving chip 12b work normally, and any problems will be identified by the system-level chip 11 and corresponding measures will be taken.

[0045] Further, after the system-level chip 11 initializes the first receiving chip 12a and the second receiving chip 12b, the first receiving chip 12a receives the laser signal within the detection range and transmits it to the system-level chip 11. After a series of processing by the system-level chip 11, point cloud data is finally obtained. After the first receiving chip 12a receives the laser signal within the detection range, the system-level chip 11 controls the first receiving chip 12a to turn off and the second receiving chip 12b to turn on, receive visible light within the detection range, and transmit it to the system-level chip 11. After a series of processing by the system-level chip 11, image data is finally obtained. The system-level chip 11 performs coordinate unified calculation and fusion on the point cloud data and the image data to obtain fused data, and transmits the fused data to the external device 2.

[0046] In some embodiments, the system-level chip 11 includes a bus 110, a main control unit 120, a first serial interface 140, a second serial interface 141, a control unit 150, a storage unit 160, a fusion unit 170, a transmission unit 180, and a communication interface 190. There are two communication interfaces 190, including a first communication interface and a second communication interface.

[0047] The bus 110 is a set of physical lines or electronic signals for transmitting data. The bus usually includes three parts: an address bus, a bus and a control bus, which are used to transmit addresses, data and control signals. The bus 110 connects the various units and interfaces in the system-level chip 11 so that they can communicate with each other and exchange data.

[0048] The main control unit 120 is the core part of the entire system-on-chip 11, connected to the bus 110, and is used to execute instructions, process data, and control other units. In one embodiment, the main control unit 120 includes a central processing unit (CPU).

[0049] The first serial interface 140 is connected to the first receiving chip 12a, and is used to transmit the electrical signal obtained by the first receiving chip 12a based on the laser signal conversion to the system-level chip 11. In one embodiment, the first receiving chip 12a converts the received laser signal into an electrical signal, and encodes and formats it through a serial communication protocol to ensure the integrity and reliability of the signal during the transmission process; the encoded and formatted signal is transmitted to the system-level chip 11 through the first serial interface 140, and the system-level chip 11 receives and decodes these signals, and then further processes and analyzes them to finally obtain point cloud data.

[0050] The second serial interface 141 is connected to the second receiving chip 12b, and is used to transmit the electrical signal obtained by the second receiving chip 12b based on the visible light signal conversion to the system-level chip 11. In one embodiment, the second receiving chip 12b converts the received visible light signal into an electrical signal, and encodes and formats it through a serial communication protocol to ensure the integrity and reliability of the signal during transmission; the encoded and formatted signal is transmitted to the system-level chip 11 through the second serial interface 141, and the system-level chip 11 receives and decodes these signals, and then further processes and analyzes them to finally obtain image data.

[0051] In one embodiment, the first serial interface 140 and the second serial interface 141 both include a MIPI CSI (Camera Serial Interface) interface. Specifically, the MIPI CSI interface is a high-speed serial interface designed specifically for mobile devices, mainly used for data transmission between cameras and processors, and has high bandwidth, low power consumption and high reliability. Furthermore, the MIPI CSI interface supports high-speed data transmission, meets the needs of high-resolution image and video transmission, and also supports multiple pixel formats, which enables it to adapt to different image processing requirements.

[0052] The control unit 150 is connected to the bus 110 and the second receiving chip 12b, and is used to control the opening and closing of the second receiving chip 12b. In one embodiment, the main control unit 120 controls the control unit 150 through the bus 110, and outputs a control instruction to the second receiving chip 12b. After receiving the control instruction, the second receiving chip 12b starts to receive visible light within the detection range, and transmits the visible light signal to the system-level chip 11 through the second serial interface 141. At the same time, the main control unit 120 controls the first receiving chip 12a to be turned off through the bus 110. Specifically, the main control unit 120 controls the control unit 150 through the bus 110, and outputs the control instruction after the first receiving chip 12a is turned off.

[0053] The storage unit 160 is connected to the bus 110 and is used to cache the point cloud data and image data in the same cycle. The same cycle includes when the first receiving chip 12a is turned on and the second receiving chip 12b is turned off, and when the first receiving chip 12a is turned off and the second receiving chip 12b is turned on. In one embodiment, the storage unit includes a frame buffer (frm buffer).

[0054] In some embodiments, the system-level chip 11 further includes a fusion unit 170, which is connected to the bus 110 and is used to perform coordinate unification calculation on the point cloud data and the image data and obtain fused data, which includes the point cloud data and the image data after the coordinates are unified. Further, the fusion unit 170 is also used to continue to transmit the fused data to the storage unit 160 for caching.

[0055] Specifically, when the fusion unit 170 fuses the point cloud data and the image data, since the spatial positions of the laser signal and the visible light signal received by the first receiving chip 12a and the second receiving chip 12b are almost consistent, the calculation of coordinate transformation can be simplified, and precise alignment of the point cloud data and the image data can be achieved when they are fused, thereby improving the accuracy and reliability of the fused data.

[0056] In one embodiment, the fusion unit 170 is used to map the color information in the image data to the point cloud data to generate point cloud data with color. This not only makes the point cloud data more vivid and intuitive, but also facilitates subsequent three-dimensional reconstruction and visualization analysis. Furthermore, after the fused data is filled with color, global optimization is performed to adjust the parameters of the image data and the point cloud data to ensure the consistency of the image data and the point cloud data in space, color and time. Among them, for the data obtained by multiple scans, splicing processing is also required to generate a complete scene panorama. By fusing point cloud data and image data, the fusion unit 170 can provide accurate three-dimensional spatial information, thereby improving the perception of the environment. Especially in fields such as autonomous driving, this fusion can significantly enhance the vehicle's understanding of the surrounding environment.

[0057] The transmission unit 180 is connected to the bus 110 and is used to transfer the fused data from the storage unit 160 to the communication interface 190. In one embodiment, the transmission unit 180 is a direct memory access (DMA). Specifically, direct memory access allows peripheral devices to directly access system memory without the control of the central processing unit, which can significantly increase the data transmission rate, reduce the burden on the central processing unit, and improve the overall system performance.

[0058] In some embodiments, the system-level chip 11 also includes a communication interface 190, which is connected to the bus 110 and is used to transmit the fused data from the chip module 1 to the device 2 outside the chip module. Among them, the communication interface 190 includes a first communication interface and a second communication interface, and the first communication interface is different from the second communication interface. Specifically, the fused data cached in the storage unit 160 is moved to the first communication interface or the second communication interface through the transmission unit 180, and is transmitted to the external device 2 through the first communication interface or the second communication interface, thereby realizing highly flexible data communication.

[0059] In one embodiment, the first communication interface includes a wired interface, and the second communication interface includes a wireless interface; or, the first communication interface includes a wireless interface, and the second communication interface includes a wired interface. The wired interface is used to transmit the fused data through a physical medium, and the wireless interface is used to transmit the fused data through radio waves. In one embodiment, the wired interface includes Ethernet, and the wireless interface includes WI-FI.

[0060] In one embodiment, when the chip module 1 is provided in an electrical device, such as a laser radar, an electric vehicle, an electric two-wheeled vehicle, an electric three-wheeled vehicle, a robot, etc., the external device 2 may include a memory or a processor in the electrical device. After the external device 2 receives the fused data, it uses the fused data for object detection and classification to identify and understand objects in the surrounding environment, such as vehicles, pedestrians, traffic signs, etc. In addition, the external device 2 is also responsible for tracking multiple frames of information, calculating and predicting the movement trajectory of obstacles, and semantic understanding of special scenes including traffic lights, road signs, construction areas, etc., and outputting the processed data to the decision-making system for path planning to achieve safe driving of the autonomous driving vehicle. In one embodiment, the external device 2 may also include a hard disk, a remote server or a cloud for storing and analyzing the fused data to facilitate further analysis and processing.

[0061] like Figure 4 As shown, Figure 4 A flowchart of a chip module 1 self-test method provided in an embodiment of the present application. It should be understood that the chip module 1 self-test method provided in the embodiment of the present application is applied to the above-mentioned chip module 1. Among them, the chip module 1 can be provided in any device, including but not limited to: a laser radar, a vehicle-mounted device, a handheld device, a wearable device or a computing device. The following embodiments of the present application are all described by taking the device executing the method as the system-level chip 11 in the chip module 1 as an example, and the specific steps of the method are as follows: S10 , receiving first excitation data output by the first receiving chip 12 a , wherein the first excitation data is point cloud data pre-stored in the first receiving chip 12 a and obtained based on a preset scenario.

[0062] In some embodiments, the system-level chip 11 receives the first excitation data through the first serial interface 140, and the first excitation data is pre-stored point cloud data obtained based on a preset scene. Specifically, before executing step S10, the preset scene is detected by a laser radar including a receiving chip of the same specification as the first receiving chip 12a to obtain corresponding point cloud data, and the point cloud data is stored in the first receiving chip 12a as reference data for the chip module 1 used in mass production.

[0063] S20, receiving second excitation data output by the second receiving chip 12b, wherein the second excitation data is image data pre-stored in the second receiving chip and obtained based on a preset scene.

[0064] In some embodiments, the system-level receiving chip 11 receives the second excitation data through the second serial interface 141, and the second excitation data is pre-stored image data obtained based on a preset scene. Specifically, before executing step S20, an image acquisition device including a receiving chip of the same specification as the second receiving chip 12b is used to acquire an image of the preset scene to obtain corresponding image data, and the image data is stored in the second receiving chip 12b as reference data for the chip module 1 used in mass production. The preset scene corresponding to the first excitation data and the second excitation data is the same scene.

[0065] S30 . Fusing the first excitation data and the second excitation data to obtain first fused data, wherein the first fused data includes information of the first excitation data and the second excitation data.

[0066] In some embodiments, the system-level chip 11 fuses the received first excitation data and the second excitation data through the fusion unit 170 to obtain first fused data. In one embodiment, the first fused data includes depth information of the point cloud and color information of the image in the same scene.

[0067] S40. Obtain a comparison result of the first fused data and the expected data according to the first fused data and the expected data, wherein the expected data is a result obtained in advance by fusing the first excitation data and the second excitation data.

[0068] In some embodiments, the expected data is the result obtained by the system-level chip 11 in advance based on the fusion of the first excitation data and the second excitation data. In one embodiment, the preset scene is detected by a laser radar to obtain point cloud data, and the preset scene is imaged by an image acquisition device to obtain image data, and then the point cloud data and the image data are fused by a processor or a microcontroller unit to obtain the expected data, and the expected data is stored in the system-level chip 11.

[0069] Specifically, the expected data is pre-stored in the system-level chip 11 as reference data, and the first fused data is the data actually fused by the system-level chip 11 based on the first excitation data output by the first receiving chip 12a and the second excitation data output by the second receiving chip 12b after the first receiving chip 12a and the second receiving chip 12b are set on the surface of the system-level chip 11. Therefore, by comparing the first fused data with the expected data, it can be determined whether the first receiving chip 12a and the second receiving chip 12b communicate with the system-level chip 11 normally.

[0070] In one embodiment, the first fused data and the expected data are both stored in the storage unit 160 in the system-level chip 11, and the first fused data and the expected data are transmitted to the main control unit 120 through the bus 110. The main control unit 120 compares the first fused data and the expected data to obtain a comparison result. In another embodiment, the expected data is pre-stored in the host computer, the first fused data is first transmitted to the storage unit 160 in the system-level chip 11 for caching, and then the transmission unit 180 moves the first fused data from the storage unit 160 to the communication interface 190, and finally the communication interface 190 transmits the first fused data to the host computer, and the host computer compares the first fused data and the expected data to obtain a comparison result.

[0071] S50, determining whether the signal paths of the system-level chip 11, the first receiving chip 12a, the second receiving chip 12b and the packaging substrate 10 are abnormal according to the comparison result; wherein the first excitation data and the second excitation data both correspond to the same preset scenario.

[0072] In one embodiment, if the comparison result of the first fusion data and the expected data is consistent or the difference is small, it means that the system-level chip, the first receiving chip, the second receiving chip and the package substrate signal path are normal; if the comparison result of the first fusion data and the expected data is significantly different, it means that the system-level chip, the first receiving chip, the second receiving chip and the package substrate signal path are abnormal. Through the self-test method of the above chip module 1, self-testing can be achieved inside the chip without investing in additional testing equipment or devices, reducing the testing cost, significantly shortening the testing process and testing time, and improving the testing efficiency.

[0073] like Figure 5 As shown, Figure 5 A schematic diagram of a receiving chip 12 provided in an embodiment of the present application. The receiving chip 12 includes a first receiving chip 12a and a second receiving chip 12b. In some embodiments, the receiving chip 12 includes a device layer 121 and a substrate layer 122, the device layer 121 is connected to the system-level chip 11, and the substrate layer 122 is located on the side of the device layer 121 away from the system-level chip 11.

[0074] In one embodiment, the material of the substrate layer 122 is silicon, which is prepared by a chemical vapor deposition process. The chemical vapor deposition process is a process that uses a gas to react chemically on a solid surface to produce solid deposition. Its basic principle is a gas phase reaction at high temperature, such as thermal decomposition of metal halides, organic metals, hydrocarbons, etc., hydrogen reduction or chemical reaction of its mixed gas at high temperature to precipitate inorganic materials such as metals, oxides, and carbides.

[0075] like Figures 6 to 8 As shown, Figure 6 A flowchart of a method for preparing a receiving chip 12 provided in an embodiment of the present application is provided. Figure 7 and Figure 8 1 is a flowchart of the manufacturing process corresponding to the method for manufacturing the receiving chip 12. It should be understood that the method for manufacturing the receiving chip 12 provided in the embodiment of the present application is applied to the above-mentioned chip module 1. The specific steps of the method are as follows: Step S1: photolithography is performed on the substrate layer 122 using a mask of a preset width, so that the substrate layer 122 forms a first boss 1221 and first grooves 1222 located on both sides of the first boss.

[0076] In some embodiments, Figure 7 As shown, the above-mentioned step S1 includes: coating a photoresist on the surface of the substrate layer 122 to obtain a first adhesive layer 123; using a mask of a preset width to expose the first adhesive layer 123 to ultraviolet rays; developing the exposed area of ​​the first adhesive layer to form a first area of ​​the substrate layer 122 covered by the first adhesive layer 123, and exposing a second area; etching the second area to obtain a first groove 1222; and removing the first adhesive layer 123 to form a first boss 1221 and first grooves 1222 located on both sides of the first boss on the substrate layer 122.

[0077] Step S2: Use a mask with a wider width than the mask used in the previous round to perform photolithography on a portion of the groove formed in the previous round, so that the substrate layer 122 forms a second boss 1223 that supports the boss formed in the previous round, and a second groove 1224 located on both sides of the second boss 1223.

[0078] In some embodiments, Figure 8 As shown, the above step S2 includes: coating photoresist on the surface of the substrate layer 122 to obtain a second adhesive layer 124; using a mask with a wider width to expose the second adhesive layer 124 to ultraviolet light, wherein the mask with a wider width blocks the boss formed in the previous round; developing the exposed area of ​​the second adhesive layer 124 so that the substrate layer 122 forms a third area covered by the second adhesive layer 124, and the set fourth area is exposed; etching the fourth area to obtain a second groove 1224; and removing the second adhesive layer so that the substrate layer 122 forms a second boss and second grooves located on both sides of the second boss.

[0079] Step S3: repeating step S2; wherein the boss includes a first boss 1221 and a second boss 1223 , and the sink includes a first sink 1222 and a second sink 1224 .

[0080] Specifically, the third area includes the bosses and part of the sink formed in the previous round, for example, part of the first boss and the first sink; the fourth area includes most of the sink formed in the previous step, for example, most of the first sink.

[0081] By continuously repeating step S2 , a curved shape with a thicker middle region and gradually decreasing thickness on both sides can be formed on the surface of the substrate layer 122 away from the device layer 121 , that is, a convex lens is finally obtained.

[0082] In one embodiment, the preset width of the mask in step S1 is the process limit of the mask, that is, the preset width of the mask is the minimum width that can be achieved under the current mask manufacturing process conditions, the mask width used for the first time in step S2 is greater than the mask width in step S1, and the mask width used in step S3 when step S2 is repeated is greater than the mask width used in the previous round, that is, the mask width gradually increases, but the maximum width of the mask is less than the width of the substrate layer 122. Specifically, the width of the mask in each step after the initial step is greater than the width of the boss formed in the previous step.

[0083] In one embodiment, the etching in the above steps is ion beam etching (IBE) or reactive ion etching (RIE). Ion beam etching is a dry etching technology that uses a physical or chemical reaction between an ion beam and the surface of a material to remove the material, thereby achieving precise transfer of the pattern. Reactive ion etching uses a high-energy ion beam to bombard the surface of the etched object, while introducing a reactive gas to generate chemically active groups and ions through the collision of the ion beam and the gas molecules. These high-energy ions and active groups react chemically with the surface of the etched material to remove unwanted materials.

[0084] like Figure 6 As shown, Figure 6 This is a flow chart of a method for preparing a receiving chip 12 provided in an embodiment of the present application. It should be understood that the method for preparing the receiving chip 12 provided in an embodiment of the present application is applied to the above-mentioned chip module 1. The specific steps of the method are as follows: In one embodiment, the substrate layer of the receiving chip 12 is prepared using the above method steps, so that the substrate layer 122 is finally prepared into an arc-shaped integrated lens, wherein the lens corresponds to the entire receiving chip 12. In another embodiment, the substrate layer of the receiving chip 12 is prepared using the above method steps, so that the substrate layer 122 is finally prepared into an arc-shaped microlens array. Specifically, the more times the above steps are repeated, the better the curvature and accuracy of the arc of the lens or microlens array will be optimized and improved.

[0085] In one embodiment, the receiving chip 12 also includes a pixel array and a microlens array, wherein the pixel array is arranged on the device layer 121, and the microlens array is prepared by the substrate layer 122. Specifically, each microlens in the microlens array corresponds one-to-one to each pixel in the pixel array, and the specific steps of the preparation method of the above-mentioned receiving chip 12 are to prepare a microlens on one pixel, so that the pixel and the microlens are integrally formed. By directly using a semiconductor preparation method to prepare a high-precision lens or microlens array on the substrate layer 122 on the receiving chip 12, not only the quality and performance of the signal received by the receiving chip 12 are improved, but also the integration of the receiving chip 12 is improved. In addition, the receiving chip 12 can be prepared at the same location from the device layer to the lens or microlens array, which shortens the processing time and reduces the production cost.

[0086] An embodiment of the present application also provides a laser radar, which includes a shell and a chip module 1 in any embodiment of the present application, and the chip module 1 is arranged in the shell.

[0087] In the description of the present application, it should be understood that, unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by technicians in the technical field of the present application. The terms used in the present specification are only for the purpose of describing specific embodiments and are not intended to limit the present application. The terms "and / or" and "and / or" used herein describe the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. The singular forms of "one" and "an" are also intended to include plural forms, unless the context clearly indicates otherwise. When the terms "comprising" and / or "including" are used in this specification, it indicates that the features, elements and / or components are present, but does not exclude the presence or addition of one or more other features, elements, components and / or their combinations, i.e., any and all combinations of one or more related listed items are included. The ordinal numbers such as "first" and "second" cited in the embodiments of the present application are merely identifiers and do not refer to other meanings such as a specific order or implying relative importance.

[0088] In the present application, unless otherwise clearly specified and limited, the first feature "above" or "below" the second feature may include the first and second features being in direct contact, or the first and second features being in contact not directly but through another feature between them. Moreover, the first feature "above", "above" and "above" the second feature include the first feature being directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. The first feature "below", "below" and "below" the second feature include the first feature being directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature. For those of ordinary skill in the art, the specific meanings of the above terms can be understood according to the specific circumstances. The "one or more embodiments" used herein do not refer to the same embodiment, but are based on any suitable combination of specific features, structures or characteristics. The above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A chip module, characterized in that: include: Package substrate; A system-level chip, arranged on the surface of the packaging substrate; At least two receiving chips are arranged on the surface of the system-level chip, the at least two receiving chips include a first receiving chip and a second receiving chip, the first receiving chip is used to receive laser signals, and the second receiving chip is used to receive visible light signals; as well as, A cover body is arranged on the packaging substrate, and the cover body and the packaging substrate together form an installation cavity. The system-level chip, the first receiving chip and the second receiving chip are all located in the installation cavity. The cover body is provided with a first area for the laser signal to pass through and a second area for the visible light signal to pass through.

2. The chip module according to claim 1, characterized in that: The system-level chip is provided with a through silicon via, a first material layer is provided in the through silicon via, and the thermal conductivity of the first material layer is higher than a preset threshold; The first receiving chip covers at least one of the through silicon vias and is electrically connected to the packaging substrate through the first material layer; The second receiving chip covers at least one of the through silicon vias and is electrically connected to the packaging substrate through the first material layer.

3. The chip module according to claim 1, characterized in that: The first receiving chip and the second receiving chip are both electrically connected to the system-on-chip through hybrid bonding; The system-level chip and the packaging substrate are electrically connected through hybrid bonding.

4. The chip module according to claim 3, characterized in that: The system-level chip is used to control the second receiving chip to be turned off when the first receiving chip is turned on; The system-level chip is used to control the second receiving chip to be turned on when the first receiving chip is turned off.

5. The chip module according to claim 4, characterized in that: The system-level chip is used to receive the laser signal processed by the first receiving chip, and obtain point cloud data according to the processed laser signal; The system-level chip is used to receive the visible light signal processed by the second receiving chip, and obtain image data according to the processed visible light signal.

6. The chip module according to claim 5, characterized in that: The system-level chip also includes a fusion unit; The fusion unit is used to perform coordinate unification calculation on the point cloud data and the image data, and obtain fused data, wherein the fused data includes the point cloud data and the image data after the coordinates are unified.

7. The chip module according to claim 6, characterized in that: The system-on-chip also includes a communication interface; The communication interface is used to transmit the fused data from the chip module to a device outside the chip module.

8. A chip module self-test method, characterized in that: Applied to the chip module according to any one of claims 1 to 7, the method comprises: Receiving first excitation data output by the first receiving chip, wherein the first excitation data is point cloud data pre-stored in the first receiving chip and obtained based on a preset scene; receiving second excitation data output by the second receiving chip, wherein the second excitation data is image data pre-stored in the second receiving chip and obtained based on a preset scene; fusing the first excitation data and the second excitation data to obtain first fused data, wherein the first fused data includes information of the first excitation data and the second excitation data; Obtaining a comparison result between the first fused data and the expected data according to the first fused data and the expected data, wherein the expected data is a result obtained in advance by fusing the first excitation data and the second excitation data; According to the comparison result, determining whether the system-level chip, the first receiving chip, the second receiving chip, and the signal path of the packaging substrate are abnormal; The first excitation data and the second excitation data both correspond to the same preset scenario.

9. A method for preparing a receiving chip, applied to the chip module according to any one of claims 1 to 7, characterized in that: The receiving chip includes a device layer and a substrate layer, the device layer is connected to the system-level chip, and the substrate layer is located on a side of the device layer away from the system-level chip. The preparation method of the receiving chip includes: Step S1: photolithography the substrate layer using a mask of a preset width to form a first boss and first recesses located on both sides of the first boss on the substrate layer; Step S2: using a mask with a larger width than the mask used in the previous round to perform photolithography on a portion of the recess formed in the previous round, so that the substrate layer forms a second boss supporting the boss formed in the previous round, and second recesses located on both sides of the second boss; and Step S3: Repeat step S2; Wherein, the boss includes the first boss and the second boss, and the sink includes the first sink and the second sink.

10. The method according to claim 9, characterized in that The method of photolithography the substrate layer using a mask of a preset width so as to form a first boss and first recesses on both sides of the first boss on the substrate layer comprises: Coating photoresist on the surface of the substrate layer to obtain a first resist layer; Using the mask with the preset width to expose the first adhesive layer to ultraviolet rays; Developing the exposed area of ​​the first glue layer so that the substrate layer forms a first area covered by the first glue layer and a second area is exposed; etching the second region to obtain the first sink; and, The first adhesive layer is removed so that the substrate layer forms the first boss and first recesses located on both sides of the first boss.

11. The method according to claim 9, characterized in that The method uses a mask with a larger width than the mask used in the previous round to perform photolithography on a portion of the recess formed in the previous round, so that the substrate layer forms a second boss supporting the boss formed in the previous round, and second recesses located on both sides of the second boss, including: Coating photoresist on the surface of the substrate layer to obtain a second resist layer; Using the mask with a larger width to expose the second adhesive layer to ultraviolet light, wherein the mask with a larger width covers the boss formed in the previous round; Developing the exposed area of ​​the second glue layer so that the substrate layer forms a third area covered by the second glue layer and a fourth area is exposed; Etching the fourth region to obtain the second sink; and, The second adhesive layer is removed so that the substrate layer forms the second boss and second recesses located on both sides of the second boss.

12. A laser radar, characterized in that: It comprises a shell and a chip module as described in any one of claims 1 to 7, wherein the chip module is arranged in the shell.

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