A latch and flip-flop resistant to single event upsets

Abstract

The application discloses a latch and a flip-flop resisting single event upset, and relates to the technical field of digital integrated circuit design, to solve the problem that the prior art cannot resist single event upset of multiple nodes in a digital circuit. The latch comprises at least a basic latch, a transmission gate and a detection circuit which are connected with each other, the basic latch is used for latching a storage level state of a corresponding hardened circuit of the latch, the latch uses a detection signal of the detection circuit to judge a level upset state of the basic latch, and generates a control signal of the latch based on the level upset state of the basic latch; further, a plurality of the above-mentioned latches can be used to form a flip-flop; thus, the latch and the flip-flop can be restored to a correct level after being subjected to multiple node single event upset, and the resistance of the latch and the flip-flop to single event upset is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of digital integrated circuit design, and in particular to a latch and flip-flop resisting single event upset. BACKGROUND

[0002] Digital circuit chips often work in space radiation environment. When high-energy particles are incident, energy is deposited through direct ionization and indirect ionization, thereby causing atoms in the material to ionize to generate electron-hole pairs. Part of the charges are collected by the sensitive nodes of the device under the action of the electric field, such as the off MOS tube drain, thereby causing the logic state of the device to change, which easily leads to single event upset. With the miniaturization of process feature size, node capacitance and power voltage are both decreasing, making single event upset more likely to occur. Due to the miniaturization of circuit size, the node spacing is reduced, which on the one hand aggravates the charge sharing effect, and on the other hand increases the probability of adjacent nodes being hit by single particles at the same time, making multi-node single event upset more likely to occur, which brings great challenges to how to improve the anti-radiation capability of digital circuits. In order to reduce the impact of single event upset on digital circuit chips, it is necessary to improve the anti-radiation capability of the flip-flop in the digital circuit.

[0003] In the prior art, the traditional digital circuit hardening scheme is to harden the master-slave latch of the flip-flop in the digital circuit. This hardening structure has good resistance to single node upset, but with the improvement of semiconductor process, the charge sharing effect becomes more and more significant due to the shortening of node spacing, which is very easy to cause the latch structure in the flip-flop circuit to occur multi-node upset at the same time. The traditional flip-flop hardening scheme cannot resist multi-node upset at the same time. And the interlocking structure increases the circuit delay and reduces the circuit speed.

[0004] Therefore, it is urgent to design a technical scheme that can resist multi-node single event upset to solve the problem that the prior art cannot resist single event upset of multiple nodes in the digital circuit. SUMMARY

[0005] The present application aims to provide a latch and flip-flop resisting single event upset, which designs a master-slave detection circuit independent of the master-slave latch of the flip-flop, uses the master-slave detection circuit to judge whether the corresponding latch circuit has single event upset, and generates a control signal for controlling the output of the latch circuit; thereby solving the problem that the prior art cannot resist single event upset of multiple nodes in the digital circuit.

[0006] In order to achieve the above-mentioned purpose, the present application provides the following technical scheme:

[0007] In a first aspect, the present application provides a latch resisting single event upset, which can at least include: a basic latch, a transmission gate and a detection circuit;

[0008] The input end of the basic latch is connected with the input end of the latch, the output end of the basic latch is connected with the input end of the transmission gate, the output end of the transmission gate is connected with the output end of the latch, the input end of the detection circuit is connected with the basic latch, and the output end of the detection circuit is connected with the transmission gate;

[0009] The basic latch is used for latching the storage level state of the corresponding hardened circuit of the latch;

[0010] The latch judges the level flip state of the basic latch by using the detection signal of the detection circuit, and generates a control signal for controlling the output of the latch based on the level flip state of the basic latch.

[0011] Preferably, the detection circuit can include an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, an eighth NMOS tube, a ninth NMOS tube, and a tenth NMOS tube.

[0012] The gate of the eighth PMOS tube is connected with a fourth signal end, the source of the eighth PMOS tube is connected with a power supply end, and the drain of the eighth PMOS tube is connected with a third signal end; the gate of the ninth PMOS tube is connected with a sixth signal end, the source of the ninth PMOS tube is connected with the power supply end, and the drain of the ninth PMOS tube is connected with a fifth signal end; the gate of the tenth PMOS tube is connected with a clock signal end, the source of the tenth PMOS tube is connected with the power supply end, and the drain of the tenth PMOS tube is connected with the third signal end; the gate of the eleventh PMOS tube is connected with the clock signal end, the source of the eleventh PMOS tube is connected with the power supply end, and the drain of the eleventh PMOS tube is connected with the fifth signal end; the gate of the twelfth PMOS tube is connected with a first signal end, the source of the twelfth PMOS tube is connected with the third signal end, and the drain of the twelfth PMOS tube is connected with the drain of a thirteenth PMOS tube; the gate of the thirteenth PMOS tube is connected with a second signal end, the source of the thirteenth PMOS tube is connected with the fifth signal end, and the drain of the thirteenth PMOS tube is connected with the drain of an eighth NMOS tube; the gate of the fourteenth PMOS tube is connected with the third signal end, the source of the fourteenth PMOS tube is connected with the power supply end, and the drain of the fourteenth PMOS tube is connected with the fourth signal end; the gate of the fifteenth PMOS tube is connected with the fifth signal end, the source of the fifteenth PMOS tube is connected with the power supply end, and the drain of the fifteenth PMOS tube is connected with a sixth signal end.

[0013] The gate of the eighth NMOS tube is connected with a clock signal end, and the source of the eighth NMOS tube is grounded; the drain of the ninth NMOS tube is connected with a fourth signal end, the gate of the ninth NMOS tube is connected with a third signal end, and the source of the ninth NMOS tube is grounded; the gate of the tenth NMOS tube is connected with a fifth signal end, the source of the tenth NMOS tube is grounded, and the drain of the tenth NMOS tube is connected with a sixth signal end.

[0014] Preferably, when the latch circuit is in a transparent state, the latch circuit can comprise:

[0015] The tenth PMOS tube and the eleventh PMOS tube in the detection circuit are turned on, the eighth NMOS tube is turned off, the third signal end and the fifth signal end node output a high level, and the fourth signal end and the sixth signal end node output a low level;

[0016] The fourth PMOS tube, the fourth NMOS tube, the fifth PMOS tube and the fifth NMOS tube in the basic latch are turned on, the sixth PMOS tube, the sixth NMOS tube, the seventh PMOS tube and the seventh NMOS tube are turned off, the sixteenth PMOS tube is turned on, and the eleventh NMOS tube is turned on.

[0017] Preferably, when the latch circuit is in a latch state, the latch circuit can comprise:

[0018] The tenth PMOS tube and the eleventh PMOS tube in the detection circuit are turned off, and the eighth NMOS tube is turned on;

[0019] When the first signal end is 1 and the second signal end is 0 in the basic latch; if a single event upset does not occur in the latch, the latch circuit outputs the second signal end; if a single event upset occurs in the first signal end and / or the second signal end node, the latch circuit outputs the first signal end;

[0020] When the first signal end is 0 and the second signal end is 1 in the basic latch; if a single event upset does not occur in the latch, the latch circuit outputs the second signal end; if a single event upset occurs in the first signal end and / or the second signal end node, the latch circuit outputs the first signal end corresponding electrical signal.

[0021] Preferably, the basic latch can comprise: a first PMOS tube, a second PMOS tube, a third PMOS tube, a sixteenth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube and an eleventh NMOS tube.

[0022] The gate of the sixteenth PMOS tube is connected with the clock signal end, the drain of the sixteenth PMOS tube is connected with the input end of the latch, and the source of the sixteenth PMOS tube is connected with the first signal end; the source of the first PMOS tube is connected with the source of the third PMOS tube, the drain of the first PMOS tube is connected with the second signal end, and the gate of the first PMOS tube is connected with the first signal end; the source of the second PMOS tube is connected with the drain of the third PMOS tube, the drain of the second PMOS tube is connected with the first signal end, and the gate of the second PMOS tube is connected with the second signal end; the gate of the third PMOS tube is connected with the clock inverse signal end.

[0023] The gate of the eleventh NMOS tube is connected with the clock inverse signal end, the drain of the eleventh NMOS tube is connected with the drain of the sixteenth PMOS tube, and the source of the eleventh NMOS tube is connected with the source of the sixteenth PMOS tube; the drain of the first NMOS tube is connected with the second signal end, the source of the first NMOS tube is connected with the source of the third NMOS tube, and the gate of the first NMOS tube is connected with the first signal end; the source of the second NMOS tube is connected with the drain of the third NMOS tube, the drain of the second NMOS tube is connected with the first signal end, and the gate of the second NMOS tube is connected with the second signal end; and the gate of the third NMOS tube is connected with the clock signal end.

[0024] Preferably, the transmission gate can comprise a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, and a seventh NMOS tube.

[0025] The gate of the fourth PMOS tube is connected with the sixth signal end, the drain of the fourth PMOS tube is connected with the second signal end, and the source of the fourth PMOS tube is connected with the output end of the latch; the gate of the fifth PMOS tube is connected with the fourth signal end, the drain of the fifth PMOS tube is connected with the second signal end, and the source of the fifth PMOS tube is connected with the source of the fourth PMOS tube; the gate of the sixth PMOS tube is connected with the third signal end, the drain of the sixth PMOS tube is connected with the first signal end, and the source of the sixth PMOS tube is connected with the drain of the seventh PMOS tube; the gate of the seventh PMOS tube is connected with the fifth signal end, and the source of the seventh PMOS tube is connected with the source of the fourth PMOS tube.

[0026] The gate of the fourth NMOS tube is connected with the fifth signal terminal, the drain of the fourth NMOS tube is connected with the second signal terminal, and the source of the fourth NMOS tube is connected with the source of the fourth PMOS tube; the gate of the fifth NMOS tube is connected with the third signal terminal, the drain of the fifth NMOS tube is connected with the second signal terminal, and the source of the fifth NMOS tube is connected with the source of the fifth PMOS tube; the gate of the sixth NMOS tube is connected with the fourth signal terminal, the drain of the sixth NMOS tube is connected with the first signal terminal, and the source of the sixth NMOS tube is connected with the source of the sixth PMOS tube; the gate of the seventh NMOS tube is connected with the sixth signal terminal, the drain of the seventh NMOS tube is connected with the drain of the seventh PMOS tube, and the source of the seventh NMOS tube is connected with the source of the seventh PMOS tube.

[0027] In a second aspect, the present application provides a flip-flop resistant to single event upset, which can include at least a latch and a slave latch;

[0028] The input of the latch is connected with the input of the flip-flop, the output of the latch is connected with the input of the slave latch, and the output of the slave latch is connected with the output of the flip-flop;

[0029] The latch includes at least a detection circuit and a basic latch; the flip-flop uses the detection signal of the detection circuit to judge the level upset state of the basic latch, and generates a control signal for controlling the output of the latch based on the level upset state of the basic latch;

[0030] The slave latch includes at least a slave detection circuit and a slave basic latch; the flip-flop uses the detection signal of the slave detection circuit to judge the level upset state of the slave basic latch, and generates a control signal for controlling the output of the slave latch based on the level upset state of the slave basic latch; the clock level of the detection circuit is opposite to that of the slave detection circuit.

[0031] Preferably, the latch further includes a transmission gate, and the slave latch can further include a slave transmission gate;

[0032] The input of the basic latch is connected with the input of the flip-flop, and the output of the basic latch is connected with the input of the transmission gate; the input of the slave basic latch is connected with the output of the transmission gate, the output of the slave basic latch is connected with the input of the slave transmission gate, and the output of the slave transmission gate is connected with the output of the flip-flop;

[0033] The basic latch is used for latching the storage level state of the latch, and the slave basic latch is used for latching the storage level state of the slave latch.

[0034] Preferably, the slave stage basic latch can comprise a seventeenth PMOS transistor, an eighteenth PMOS transistor, a nineteenth PMOS transistor, a twenty-fourth PMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor and a nineteenth NMOS transistor.

[0035] The gate of the twenty-fourth PMOS transistor is connected with the clock inverse signal end, the drain of the twenty-fourth PMOS transistor is connected with the output end of the transmission gate, and the source of the twenty-fourth PMOS transistor is connected with the seventh signal end; the source of the seventeenth PMOS transistor is connected with the source of the nineteenth PMOS transistor, the drain of the seventeenth PMOS transistor is connected with the eighth signal end, and the gate of the seventeenth PMOS transistor is connected with the seventh signal end; the source of the eighteenth PMOS transistor is connected with the drain of the nineteenth PMOS transistor, the drain of the eighteenth PMOS transistor is connected with the seventh signal end, and the gate of the eighteenth PMOS transistor is connected with the eighth signal end; the gate of the nineteenth PMOS transistor is connected with the clock signal end;

[0036] The gate of the nineteenth NMOS transistor is connected with the clock signal end, the drain of the nineteenth NMOS transistor is connected with the drain of the twenty-fourth PMOS transistor, and the source of the nineteenth NMOS transistor is connected with the seventh signal end; the drain of the twelfth NMOS transistor is connected with the eighth signal end, the source of the twelfth NMOS transistor is connected with the source of the fourteenth NMOS transistor, and the gate of the twelfth NMOS transistor is connected with the seventh signal end; the source of the thirteenth NMOS transistor is connected with the drain of the fourteenth NMOS transistor, the drain of the thirteenth NMOS transistor is connected with the seventh signal end, and the gate of the thirteenth NMOS transistor is connected with the eighth signal end; the gate of the fourteenth NMOS transistor is connected with the clock inverse signal end.

[0037] Preferably, the slave stage transmission gate can comprise a twentieth PMOS transistor, a twenty-first PMOS transistor, a twenty-second PMOS transistor, a twenty-third PMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor and an eighteenth NMOS transistor.

[0038] gate of the twentieth PMOS tube is connected with the twelfth signal terminal, the drain of the twentieth PMOS tube is connected with the eighth signal terminal, and the source of the twentieth PMOS tube is connected with the output terminal of the flip-flop; the gate of the twenty-first PMOS tube is connected with the tenth signal terminal, the drain of the twenty-first PMOS tube is connected with the eighth signal terminal, and the source of the twenty-first PMOS tube is connected with the output terminal of the flip-flop; the gate of the twenty-second PMOS tube is connected with the ninth signal terminal, the drain of the twenty-second PMOS tube is connected with the seventh signal terminal, and the source of the twenty-second PMOS tube is connected with the drain of the twenty-third PMOS tube; the gate of the twenty-third PMOS tube is connected with the eleventh signal terminal, and the source of the twenty-third PMOS tube is connected with the output terminal of the flip-flop;

[0039] the gate of the fifteenth NMOS tube is connected with the eleventh signal terminal, the drain of the fifteenth NMOS tube is connected with the eighth signal terminal, and the source of the fifteenth NMOS tube is connected with the source of the twentieth PMOS tube; the gate of the sixteenth NMOS tube is connected with the ninth signal terminal, the drain of the sixteenth NMOS tube is connected with the eighth signal terminal, and the source of the sixteenth NMOS tube is connected with the source of the twenty-first PMOS tube; the gate of the seventeenth NMOS tube is connected with the tenth signal terminal, the drain of the seventeenth NMOS tube is connected with the seventh signal terminal, and the source of the seventeenth NMOS tube is connected with the source of the twenty-second PMOS tube; the gate of the eighteenth NMOS tube is connected with the twelfth signal terminal, the drain of the eighteenth NMOS tube is connected with the drain of the twenty-third PMOS tube, and the source of the eighteenth NMOS tube is connected with the source of the twenty-third PMOS tube.

[0040] Compared with the prior art, the latch for resisting single event upset in a digital circuit provided by the application can at least include a basic latch, a transmission gate and a detection circuit; the input end of the basic latch is connected with the input end of the latch, the output end of the basic latch is connected with the input end of the transmission gate, the output end of the transmission gate is connected with the output end of the latch, the input end of the detection circuit is connected with the basic latch, and the output end of the detection circuit is connected with the transmission gate; wherein the basic latch is used for latching the storage level state of the corresponding hardened circuit of the latch; the latch uses the detection signal of the detection circuit to judge the level upset state of the basic latch, and generates a control signal for controlling the latch based on the level upset state of the basic latch; the output signal of the latch is used as the input signal of a slave latch; the clock level of the latch is opposite to that of the slave latch; based on this, if no single event upset occurs in the latch circuit, the latch can normally output data; if single event upset occurs, the inverted level is output after being inverted, so that the latch structure can still output correct logic level after multiple node single event upset occurs, the anti-single event radiation effect capability of the latch in the digital circuit is improved, and thus the problem that the multiple nodes in the digital circuit cannot resist single event upset in the prior art is solved. BRIEF DESCRIPTION OF DRAWINGS

[0041] The accompanying drawings, which are included to provide a further understanding of the application, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:

[0042] Figure 1 It is a first detection circuit structure schematic diagram in the prior art;

[0043] Figure 2 It is a second detection circuit structure schematic diagram in the prior art;

[0044] Figure 3 It is a main circuit structure schematic diagram of the latch and the flip-flop for resisting single event upset provided by the application;

[0045] Figure 4 It is a detection circuit structure schematic diagram of the latch and the flip-flop for resisting single event upset provided by the application.

[0046] Reference signs: 300 - flip-flop, 310 - latch, 320 - slave stage latch, 311 - basic latch, 312 - detection circuit, 313 - transmission gate, 321 - slave stage basic latch, 322 - slave stage detection circuit, 323 - slave stage transmission gate, clkb - clock inverse signal end, clkbb - clock signal end, b0 - first signal end, b1 - second signal end, E0 - third signal end, E0N - fourth signal end, E1 - fifth signal end, E1N - sixth signal end, b2 - seventh signal end, b3 - eighth signal end, E2 - ninth signal end, E2N - tenth signal end, E3 - eleventh signal end, E3N - twelfth signal end, IN - input end, OUT - output end. DETAILED DESCRIPTION

[0047] In order to clearly describe the technical solutions of the embodiments of the present application, in the embodiments of the present application, the words "first", "second" and the like are used to distinguish the same or similar items with basically the same function and effect. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and do not limit the order of time. Those skilled in the art can understand that the words "first", "second" and the like do not limit the number and execution order, and the words "first", "second" and the like do not necessarily mean different.

[0048] It should be noted that in the present application, the words "exemplary" or "for example" are used to represent an example, illustration or description. Any embodiment or design scheme described as "exemplary" or "for example" in the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the words "exemplary" or "for example" are intended to present the relevant concept in a specific manner.

[0049] In the present application, "at least one" means one or more, and "multiple" means two or more. The association relationship of the associated objects is described, which means that there can be three relationships, for example, A and / or B, which can represent the following cases: A exists alone, A and B exist together, and B exists alone, wherein A and B can be singular or plural. The character " / " generally represents that the previous associated objects have an "or" relationship. "At least one of the following" or similar expressions means any combination of these items, including single item or any combination of multiple items. For example, at least one of a, b or c can represent: a, b, c, a and b, a and c, b and c, or a, b and c, wherein a, b and c can be single or multiple.

[0050] In the prior art, the traditional flip-flop reinforcement scheme is to reinforce the master-slave stage latch of the flip-flop, and the reinforcement design structure is usually on the critical path of the circuit. Please refer toFigures 1 to 2 ; Figure 1 is a first kind of detection circuit structure in the prior art; Figure 2 is a second kind of detection circuit structure in the prior art.

[0051] In Figure 1 , a single event upset hardened latch structure of a dual inter-locked storage cell (DICE) is designed, which has four data storage nodes. When a single node is upset by an external high-energy particle, the temporary upset of the single node will not propagate the error level to other nodes and will not cause the logic state of other nodes to change, because the data stored in each node is controlled by another two nodes. Finally, the storage node that is upset by a single event can be restored to the original level through the feedback structure of the other nodes that are not affected. However, with the improvement of semiconductor process, the charge sharing effect becomes more and more significant due to the shortening of node spacing, which can easily trigger the latch structure in the flip-flop circuit to be upset by multiple nodes at the same time, and the DICE structure cannot resist the upset of multiple nodes at the same time. Moreover, the interlocking structure increases the circuit delay and reduces the data transmission rate.

[0052] In Figure 2 , a latch structure named Quatro is designed, which has four data storage nodes. The logic state of each node is controlled by another two nodes. When a single node is upset by an external high-energy particle, the temporary upset of the single node will not propagate the error level to other nodes and will not cause the logic state of other nodes to change, because the data stored in each node is controlled by another two nodes. The working principle is similar to that of the DICE structure. Finally, the storage node that is upset by a single event can be restored to the original level through the feedback structure of the other nodes that are not affected. However, one of the four nodes in this structure cannot completely resist the upset of a single node. When this node is upset, it may upset the logic state of the entire structure. Moreover, the latch structure is similar to the DICE structure, and also has the problem of being unable to resist the upset of multiple nodes at the same time. Moreover, the interlocking structure increases the circuit delay and reduces the data transmission rate.

[0053] In view of this, the present invention provides a latch and flip-flop resistant to single-event upsets. By strengthening the design of the latch and flip-flop circuit, the memory structure (latch) in the flip-flop can recover to the correct level after being bombarded by multiple single-event events, thereby improving the resistance of digital circuits to single-event radiation effects and enabling them to work normally in space irradiation environments. Furthermore, the detection circuit, which is part of the strengthening structure, is not on the critical path of the circuit and has a lower circuit delay, thus improving the data transmission rate of the circuit and making it suitable for high-speed, high-performance circuit design.

[0054] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings:

[0055] Please see Figure 3 , Figure 3 The latch circuit structure shown is a schematic diagram of the main circuit structure of a latch and flip-flop resistant to single-event upsets provided in the first aspect of this invention. It should be noted that this invention... Figure 3 The overall circuit structure shown is a flip-flop circuit structure, which is essentially a single-event upset (SEE) resistant flip-flop composed of a left-hand latch circuit structure and a right-hand slave latch circuit structure. The left-hand latch circuit is a SEE resistant latch provided by this invention. In the SEE resistant flip-flop provided by this invention, the latch uses the same circuit structure as the SEE resistant latch provided by this invention; the slave latch circuit structure is the same as the latch circuit structure, the difference being that the operating states of the latch and the slave latch are reversed. Therefore, for the sake of concise explanation of the technical solution of this invention, in specific embodiments, [the following is used as an example]. Figure 3 The flip-flop circuit structure shown is introduced as a whole, and the solution is described using the latch circuit structure as an example; in practical applications, Figure 3 The latch in the circuit can also be called the master-level latch. Similarly, the sub-circuit structure in the latch, the basic latch can also be called the master-level basic latch, the transmission gate can also be called the master-level transmission gate, and the probe circuit can also be called the master-level probe circuit.

[0056] exist Figure 3 In the latch circuit structure shown in the left half, the latch 310 includes at least a basic latch 311, a transmission gate 313, and a detection circuit 312.

[0057] The input terminal of the basic latch 311 is connected to the input terminal of the latch 310, the output terminal of the basic latch 311 is connected to the input terminal of the transmission gate 313, the output terminal of the transmission gate 313 is connected to the output terminal of the latch 310, the input terminal of the detection circuit 312 is connected to the basic latch 311, and the output terminal of the detection circuit 312 is connected to the transmission gate 313.

[0058] The basic latch 311 is used to latch the storage level state of the latch 310 circuit.

[0059] The latch 310 judges the level flip state of the basic latch 311 by using the detection signal of the detection circuit 312, and generates a control signal for controlling the latch 310 based on the level flip state of the basic latch 311; the output signal of the latch 310 is used as the input signal of the slave latch 320; the clock level of the latch 310 is opposite to that of the slave latch 320.

[0060] Based on this, the latch provided by the application can realize the following functions: if no single event upset occurs in the latch circuit, the latch normally outputs data; if a single event upset occurs, the flipped level is inverted and then output, so that the latch structure can still output correct logic level after multiple node single event upsets, thereby improving the single event radiation effect resistance of the latch in the digital circuit, and solving the problem that the prior art cannot resist single event upsets of multiple nodes in the digital circuit. In addition, the detection circuit in the latch circuit provided by the application is not on the critical path of the circuit, so that the circuit has low delay and can improve the data transmission rate of the circuit, and is suitable for high-speed and high-performance circuit design.

[0061] Preferably, refer to Figure 4 , Figure 4 The detection circuit structure of the latch and the flip-flop provided by the application is shown in the figure. It should be noted that the detection circuit in the flip-flop provided by the application and the slave detection circuit in the slave latch have the same circuit structure, and the difference lies in that the clock signals input into the detection circuit and the slave detection circuit are opposite; for example, when the first clock signal input end of the detection circuit inputs a clock signal, a clock inverse signal is input into the first clock signal input end of the slave detection circuit; when the second clock signal input end of the detection circuit inputs a clock inverse signal, a clock signal is input into the second clock signal input end of the slave detection circuit. In addition, the connection mode between the detection circuit and the latch is the same as the connection mode between the slave detection circuit and the slave latch, and the connection mode between the detection circuit and the transmission gate is the same as the connection mode between the slave detection circuit and the slave transmission gate. The detection circuit structure shown in the figure is only used for example in the application. Figure 4

[0062] In the Figure 4 , the detection circuit 312 can include an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, an eighth NMOS tube, a ninth NMOS tube, and a tenth NMOS tube.​

[0063] Specifically, the gate of the eighth PMOS is connected with the fourth signal terminal E0N, the source of the eighth PMOS is connected with the power terminal, and the drain of the eighth PMOS is connected with the third signal terminal E0; the gate of the ninth PMOS is connected with the sixth signal terminal E1N, the source of the ninth PMOS is connected with the power terminal, and the drain of the ninth PMOS is connected with the fifth signal terminal E1; the gate of the tenth PMOS is connected with the clock signal terminal clkbb, the source of the tenth PMOS is connected with the power terminal, and the drain of the tenth PMOS is connected with the third signal terminal E0; the gate of the eleventh PMOS is connected with the clock signal terminal clkbb, the source of the eleventh PMOS is connected with the power terminal, and the drain of the eleventh PMOS is connected with the fifth signal terminal E1; the gate of the twelfth PMOS is connected with the first signal terminal b0, the source of the twelfth PMOS is connected with the third signal terminal E0, and the drain of the twelfth PMOS is connected with the drain of the thirteenth PMOS; the gate of the thirteenth PMOS is connected with the second signal terminal b1, the source of the thirteenth PMOS is connected with the fifth signal terminal E1, and the drain of the thirteenth PMOS is connected with the drain of the eighth NMOS; the gate of the fourteenth PMOS is connected with the third signal terminal E0, the source of the fourteenth PMOS is connected with the power terminal, and the drain of the fourteenth PMOS is connected with the fourth signal terminal E0N; the gate of the fifteenth PMOS is connected with the fifth signal terminal E1, the source of the fifteenth PMOS is connected with the power terminal, and the drain of the fifteenth PMOS is connected with the sixth signal terminal E1N.

[0064] Further, the gate of the eighth NMOS is connected with the clock signal terminal clkbb, and the source of the eighth NMOS is grounded; the drain of the ninth NMOS is connected with the fourth signal terminal E0N, the gate of the ninth NMOS is connected with the third signal terminal E0, and the source of the ninth NMOS is grounded; the gate of the tenth NMOS is connected with the fifth signal terminal E1, the source of the tenth NMOS is grounded, and the drain of the tenth NMOS is connected with the sixth signal terminal E1N.

[0065] Based on this, the internal circuit structure of the detection circuit provided by the application can be obtained, so that the detection circuit can be used to detect whether a single event upset is sent in the latch, so that the latch can generate a control signal for controlling the latch through the output signal of the detection circuit, so that the latch can output a correct level; the latch provided by the application can output a correct level, and the anti-single particle radiation effect capability of the latch in the digital circuit is improved.

[0066] It should be noted that the detection circuit provided by the present application realizes the reinforcement of the latch by using relatively few MOS tubes, thereby saving cost; and the relatively few inverters used in the key transmission path of the latch have lower transmission delay of the latch than the reinforcement circuit in the prior art, thereby improving transmission efficiency; similarly, the slave latch provided by the present application also has the same technical effects as the latch.

[0067] Preferably, the basic latch 311 can include a first PMOS tube, a second PMOS tube, a third PMOS tube, a sixteenth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, and an eleventh NMOS tube.

[0068] Specifically, the gate of the sixteenth PMOS tube can be connected with the clock signal end clkbb, the drain of the sixteenth PMOS tube can be connected with the input end of the latch, and the source of the sixteenth PMOS tube can be connected with the first signal end b0; the source of the first PMOS tube can be connected with the source of the third PMOS tube, the drain of the first PMOS tube can be connected with the second signal end b1, and the gate of the first PMOS tube can be connected with the first signal end b0; the source of the second PMOS tube can be connected with the drain of the third PMOS tube, the drain of the second PMOS tube can be connected with the first signal end b0, and the gate of the second PMOS tube can be connected with the second signal end b1; and the gate of the third PMOS tube can be connected with the clock inverse signal end clkb.

[0069] Further, the gate of the eleventh NMOS tube can be connected with the clock inverse signal end clkb, the drain of the eleventh NMOS tube can be connected with the drain of the sixteenth PMOS tube, and the source of the eleventh NMOS tube can be connected with the source of the sixteenth PMOS tube; the drain of the first NMOS tube can be connected with the second signal end b1, the source of the first NMOS tube can be connected with the source of the third NMOS tube, and the gate of the first NMOS tube can be connected with the first signal end b0; the source of the second NMOS tube can be connected with the drain of the third NMOS tube, the drain of the second NMOS tube can be connected with the first signal end b0, and the gate of the second NMOS tube can be connected with the second signal end b1; and the gate of the third NMOS tube can be connected with the clock signal end clkbb.

[0070] Preferably, the transmission gate 313 can include a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, and a seventh NMOS tube.

[0071] Specifically, the gate of the fourth PMOS tube is connected with the sixth signal end E1N, the drain of the fourth PMOS tube is connected with the second signal end b1, and the source of the fourth PMOS tube is connected with the output end of the latch; the gate of the fifth PMOS tube is connected with the fourth signal end E0N, the drain of the fifth PMOS tube is connected with the second signal end b1, and the source of the fifth PMOS tube is connected with the source of the fourth PMOS tube; the gate of the sixth PMOS tube is connected with the third signal end E0, the drain of the sixth PMOS tube is connected with the first signal end b0, and the source of the sixth PMOS tube is connected with the drain of the seventh PMOS tube; the gate of the seventh PMOS tube is connected with the fifth signal end E1, and the source of the seventh PMOS tube is connected with the source of the fourth PMOS tube.

[0072] Further, the gate of the fourth NMOS tube is connected with the fifth signal end E1, the drain of the fourth NMOS tube is connected with the second signal end b1, and the source of the fourth NMOS tube is connected with the source of the fourth PMOS tube; the gate of the fifth NMOS tube is connected with the third signal end E0, the drain of the fifth NMOS tube is connected with the second signal end b1, and the source of the fifth NMOS tube is connected with the source of the fifth PMOS tube; the gate of the sixth NMOS tube is connected with the fourth signal end E0N, the drain of the sixth NMOS tube is connected with the first signal end b0, and the source of the sixth NMOS tube is connected with the source of the sixth PMOS tube; the gate of the seventh NMOS tube is connected with the sixth signal end E1N, the drain of the seventh NMOS tube is connected with the drain of the seventh PMOS tube, and the source of the seventh NMOS tube is connected with the source of the seventh PMOS tube.

[0073] In summary, the latch provided by the application can realize the following functions:

[0074] 1. When the latch is in a transparent state, the tenth PMOS tube and the eleventh PMOS tube in the detection circuit are opened, the eighth NMOS is closed, the third signal end E0 and the fifth signal end E1 node output high level, the fourth signal end E0N and the sixth signal end E1N node output low level; the fourth PMOS tube, the fourth NMOS tube, the fifth PMOS tube and the fifth NMOS tube in the basic latch are opened, the sixth PMOS tube, the sixth NMOS tube, the seventh PMOS tube and the seventh NMOS tube are closed, and the sixteenth PMOS tube and the eleventh NMOS tube are opened.

[0075] 2、When the latch is in the latch state, the tenth PMOS tube and the eleventh PMOS tube in the detection circuit are turned off, and the eighth NMOS tube is turned on; when the first signal end b0 in the basic latch is 1 and the second signal end b1 is 0; if a single event upset does not occur in the latch, the latch outputs the electrical signal corresponding to the second signal end b1; if a single event upset occurs at the first signal end b0 and / or the second signal end b1 node, the latch outputs the electrical signal corresponding to the first signal end b0.

[0076] When the first signal end b0 in the basic latch is 0 and the second signal end b1 is 1; if a single event upset does not occur in the latch, the latch outputs the electrical signal corresponding to the second signal end b1; if a single event upset occurs at the first signal end b0 and / or the second signal end b1 node, the latch outputs the electrical signal corresponding to the first signal end b0.

[0077] Specifically, the working principle of the latch for resisting single event upset provided by the application is explained as follows, wherein the output signals of the detection circuit are E0, E0N, E1 and E1N; E0 and E0N are inverse signals of each other, and E1 and E1N are inverse signals of each other. The input signals of the detection circuit are b0, b1, clkb and clkbb; b0 and b1 are inverse signals of each other, and clkb and clkbb are inverse signals of each other; wherein b0 and b1 are detection signals of the latch, and clkb and clkbb are clock signals.

[0078] (1) Transparent state (the clock clk is low)

[0079] When the main stage is in the transparent state, at this time, clkbb is low, MP10 and MP11 are opened, MN8 is turned off, E0 and E1 nodes are pulled up to high level, E0N and E1N outputs are low, therefore, MP4 and MN4, MP5 and MN5 are opened, MP6 and MN6, MP7 and MN7 are turned off, MP16 and MN11 are opened, at this time, the detection circuit has no any influence on the output, and the working state of the latch is equivalent to that of an ordinary latch, since clkbb is low, the reverse clock signal clkb is high, MP3 and MN3 are turned off, the input signal is transmitted to b0 through an inverter to reach the b1 node and serve as the output of the latch.

[0080] (2) Latch state (the clock clk is high)

[0081] When the main stage is in the latch state, at this time, clkbb is high. MP10 and MP11 are turned off, and MN8 is turned on.

[0082] ① When b0=1 and b1=0:

[0083] a) When no single event upset occurs, at this time because b1 = 0, MP13 is on, E1 is pulled to low level, E0 = 1, E0N = 0, E1 = 0, E1N = 1, therefore MP6 and MN6 are still off, and MP5 and MN5 are still on, therefore the detection circuit has no effect on the output, so in the case of no single event upset, the latch works as a normal latch, the output level is b1 = 0.

[0084] b) When a single event upset occurs on any node b0 and / or b1 of the latch unit, it will cause false latching, the irradiation particle will produce a low level pulse in NMOS and a high level pulse in PMOS, b0 and b1 nodes are connected to both NMOS and PMOS, therefore b0 and / or b1 nodes may occur from 0 to 1 flip or from 1 to 0 flip, when b0 = 1, b1 = 0, the circuit state flips, i.e. b0 = 0, b1 = 1, at this time MP12 is on, E0 is pulled to low level, E0 = 0, E0N = 1, E1 = 0, E1N = 1, therefore MP4 and MN4, MP5 and MN5 are off, MP6 and MN6, MP7 and MN7 are on, the output is b0 instead of b1, therefore the latch still outputs b0 = 0.

[0085] c) For the nodes in the detection circuit, E0 and E1 nodes are surrounded by PMOS, therefore they will only occur 0 to 1 pulse, so when b0 = 1, b1 = 0, E0 = 1, E1 = 0, only E1 node may flip to 1, but because MP13 is on, E1 will be pulled back to low level soon, finally the output of the circuit returns to normal.

[0086] ② When b0 = 0, b1 = 1:

[0087] a) When no single event upset occurs, at this time because b0 = 0, MP12 is on, E0 is pulled to low level, E0 = 0, E0N = 1, E1 = 1, E1N = 0, therefore MP7 and MN7 are still off, and MP4 and MN4 are still on, therefore the detection circuit has no effect on the output, so in the case of no single event upset, the latch works as a normal latch, the output level is b1 = 1.

[0088] b) When a single-event upset occurs at any node b0 and / or b1 of the latch unit, it will lead to an incorrect latch. Irradiated particles will generate a low-level pulse in the NMOS and a high-level pulse in the PMOS. Nodes b0 and b1 are connected to both NMOS and PMOS, so nodes b0 and / or b1 may flip from 0 to 1 or from 1 to 0. When b0 = 0 and b1 = 1, the circuit state flips, i.e., b0 = 1 and b1 = 0. At this time, MP13 is turned on, E1 is pulled low, E0 = 0, E0N = 1, E1 = 0, E1N = 1. Therefore, MP4 and MN4, MP5 and MN5 are turned off, MP6 and MN6, MP7 and MN7 are turned on, and the output is b0 instead of b1. Therefore, the latch still outputs b0 = 1.

[0089] c) For nodes in the probe circuit, nodes E0 and / or E1 are surrounded by PMOS, so they will only have 0 to 1 pulses. Therefore, when b0 = 1 and b1 = 0, E0 = 0 and E1 = 1. Only node E0 may flip to 1. However, since MP12 is on, E0 will be pulled back to low level quickly, and eventually the output of the latch will return to normal.

[0090] Secondly, the present invention provides a trigger that resists single-event upsets; please refer to further details. Figure 3 , Figure 3 The complete circuit diagram shown illustrates a single-event upset-resistant trigger provided by this invention. In practical applications, Figure 3 The latch shown in the left half can also be called the master latch. This flip-flop is a rising-edge master-slave latch structure, consisting of a latch circuit with cascaded transmission gates and a slave latch circuit. The two stages have the same structure. The output signal of the probe circuit (particle flip detection circuit) determines whether a particle flip has occurred in the latch circuit, and the output signal of the probe circuit determines the output signal of the master-slave latch; and the output signal of the slave probe circuit determines whether a particle flip has occurred in the corresponding circuit of the slave latch, and the output signal of the slave probe circuit determines the output signal of the master-slave latch.

[0091] exist Figure 3 In this context, the trigger 300 may include at least a latch 310 and a slave latch 320.

[0092] The input terminal of latch 310 is connected to the input terminal IN of flip-flop 300, and the output terminal of latch 310 is connected to the input terminal of slave latch 320. The output terminal of slave latch 320 is connected to the output terminal OUT of flip-flop 300. The operating states of latch 310 and slave latch 320 are opposite; that is, when latch 310 is in a transparent state, slave latch 320 is in a latched state; when latch 310 is in a latched state, slave latch 320 is in a transparent state.

[0093] The latch 310 at least includes a detection circuit 312 and a basic latch 311; the flip-flop 300 judges the level flip state of the basic latch 311 by using the detection signal of the detection circuit 312, and generates a control signal for controlling the output of the latch 310 based on the level flip state of the basic latch 311.

[0094] The slave latch 320 at least includes a slave detection circuit 322 and a slave basic latch 321; the flip-flop 300 judges the level flip state of the slave basic latch 321 by using the detection signal of the slave detection circuit 322, and generates a control signal for controlling the output of the slave latch 320 based on the level flip state of the slave basic latch 321; the clock level of the detection circuit 312 is opposite to that of the slave detection circuit 322.

[0095] Based on this, the application provides a flip-flop for resisting single event upset in a digital circuit, by reinforcing the design of the flip-flop circuit, the memory structure in the flip-flop can recover to the correct level after being bombarded by multi-node single particles, if single event upset does not occur in the master-slave latch, the latch can normally output data; if single event upset occurs, the flipped level is inverted and then output, so that the master-slave latch can still output the correct logic level after multi-node single event upset, the resistance of the digital circuit to the single particle radiation effect is improved, and the digital circuit can work normally in the space radiation environment; and the master-slave detection circuit proposed in the application is not in the critical path of the circuit, has low circuit delay, and thus the data transmission rate of the circuit is improved, and the anti-radiation reinforced circuit design of the advanced process can be applied.

[0096] It should be noted that the internal circuit structure of the slave detection circuit is the same as that of the detection circuit, and the difference lies in that the state of the input clock signal is opposite. Figure 3 and Figure 4 and the detailed introduction of the latch in the first aspect, the connection mode of the slave detection circuit in the slave latch can be obtained, and the description is not repeated in this specification. Therefore, whether the slave latch circuit sends single event upset can be detected by using the slave detection circuit, so that the flip-flop can generate a control signal for controlling the slave latch by using the output signal of the slave detection circuit, so that the slave latch can output the correct level, that is, no matter whether single event upset occurs in any node of the master or slave latch of the digital circuit, the flip-flop provided by the application can output the correct level, and the anti-single particle radiation effect capability of the flip-flop in the digital circuit is improved.

[0097] Preferably, the latch 310 further comprises a transfer gate 313, and the slave latch 320 further comprises a slave transfer gate 323; an input terminal of the basic latch 311 is connected with an input terminal of the flip-flop 300, an output terminal of the basic latch 311 is connected with an input terminal of the transfer gate 313; an input terminal of the slave basic latch 321 is connected with an output terminal of the transfer gate 313, an output terminal of the slave basic latch 321 is connected with an input terminal of the slave transfer gate 323, and an output terminal of the slave transfer gate 323 is connected with an output terminal of the flip-flop 300.

[0098] The basic latch 311 is used for latching a storage level state of the latch 310, and the slave basic latch 321 is used for latching a storage level state of the slave latch 320.

[0099] Preferably, the slave basic latch 321 can comprise a seventeenth PMOS tube, an eighteenth PMOS tube, a nineteenth PMOS tube, a twenty-fourth PMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube and a nineteenth NMOS tube.

[0100] Specifically, a gate of the twenty-fourth PMOS tube can be connected with a clock inverse signal terminal clkb, a drain of the twenty-fourth PMOS tube is connected with an output terminal of the transfer gate, and a source of the twenty-fourth PMOS tube is connected with a seventh signal terminal b2; a source of the seventeenth PMOS tube is connected with a source of the nineteenth PMOS tube, a drain of the seventeenth PMOS tube is connected with an eighth signal terminal b3, and a gate of the seventeenth PMOS tube is connected with the seventh signal terminal b2; a source of the eighteenth PMOS tube is connected with a drain of the nineteenth PMOS tube, a drain of the eighteenth PMOS tube is connected with the seventh signal terminal b2, and a gate of the eighteenth PMOS tube is connected with the eighth signal terminal b3; a gate of the nineteenth PMOS tube is connected with a clock signal terminal clkbb; wherein the drain of the twenty-fourth PMOS tube is an input terminal of the slave latch, and the source of the fourth PMOS tube is an output terminal of the transfer gate.

[0101] Further, a gate of the nineteenth NMOS tube is connected with the clock signal terminal clkbb, a drain of the nineteenth NMOS tube is connected with the drain of the twenty-fourth PMOS tube, and a source of the nineteenth NMOS tube is connected with the seventh signal terminal b2; a drain of the twelfth NMOS tube is connected with the eighth signal terminal b3, a source of the twelfth NMOS tube is connected with a source of the fourteenth NMOS tube, and a gate of the twelfth NMOS tube is connected with the seventh signal terminal b2; a source of the thirteenth NMOS tube is connected with a drain of the fourteenth NMOS tube, a drain of the thirteenth NMOS tube is connected with the seventh signal terminal b2, and a gate of the thirteenth NMOS tube is connected with the eighth signal terminal b3; a gate of the fourteenth NMOS tube is connected with the clock signal terminal clkbb.

[0102] Preferably, the transfer gate 323 can comprise a twentieth PMOS transistor, a twenty-first PMOS transistor, a twenty-second PMOS transistor, a twenty-third PMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor and an eighteenth NMOS transistor.

[0103] Specifically, the gate of the twentieth PMOS transistor can be connected with the twelfth signal terminal E3N, the drain of the twentieth PMOS transistor can be connected with the eighth signal terminal b3, and the source of the twentieth PMOS transistor can be connected with the output terminal of the flip-flop; the gate of the twenty-first PMOS transistor can be connected with the tenth signal terminal E2N, the drain of the twenty-first PMOS transistor can be connected with the eighth signal terminal b3, and the source of the twenty-first PMOS transistor can be connected with the output terminal of the flip-flop; the gate of the twenty-second PMOS transistor can be connected with the ninth signal terminal E2, the drain of the twenty-second PMOS transistor can be connected with the seventh signal terminal b2, and the source of the twenty-second PMOS transistor can be connected with the drain of the twenty-third PMOS transistor; the gate of the twenty-third PMOS transistor can be connected with the eleventh signal terminal E3, and the source of the twenty-third PMOS transistor can be connected with the output terminal of the flip-flop.

[0104] Further, the gate of the fifteenth NMOS transistor can be connected with the eleventh signal terminal E3, the drain of the fifteenth NMOS transistor can be connected with the eighth signal terminal b3, and the source of the fifteenth NMOS transistor can be connected with the source of the twentieth PMOS transistor; the gate of the sixteenth NMOS transistor can be connected with the ninth signal terminal E2, the drain of the sixteenth NMOS transistor can be connected with the eighth signal terminal b3, and the source of the sixteenth NMOS transistor can be connected with the source of the twenty-first PMOS transistor; the gate of the seventeenth NMOS transistor can be connected with the tenth signal terminal E2N, the drain of the seventeenth NMOS transistor can be connected with the seventh signal terminal b2, and the source of the seventeenth NMOS transistor can be connected with the source of the twenty-second PMOS transistor; the gate of the eighteenth NMOS transistor can be connected with the twelfth signal terminal E3N, the drain of the eighteenth NMOS transistor can be connected with the drain of the twenty-third PMOS transistor, and the source of the eighteenth NMOS transistor can be connected with the source of the twenty-third PMOS transistor.

[0105] For the latch, the working principle is the same as that of the latch described in the first aspect of the present application, which will not be described here.

[0106] For the slave latch, the output signals of the slave level detection circuit are E2, E2N, E3 and E3N; E2 and E2N are inverse signals of each other, and E3 and E3N are inverse signals of each other; the input signals of the slave level detection circuit are b2, b3, clkb and clkbb; b2 and b3 are inverse signals of each other, and clkb and clkbb are inverse signals of each other; wherein, b2 and b3 are detection signals of the slave latch, and clkb and clkbb are clock signals. In the slave latch, the high level corresponds to the transparent state, and the low level corresponds to the latch state, so that the clock signals of all MOS transistors connected with the clock signals of the MOS transistors in the latch are opposite to the clock signals of the MOS transistors in the latch, so as to improve the anti-single event upset capability of the slave level hardened circuit.

[0107] It should be noted that the detection circuit in the latch and the slave level detection circuit in the slave latch resist single event upset, the detection circuit (hardened circuit) is precharged in the transparent stage of the latch, and the latch state is evaluated; the detection circuit can identify whether single event upset occurs in the latch, and sends an alarm signal to provide conditions for architecture level hardening. The output level of the detection circuit determines the output value of the latch, when no single event upset is detected, the latch outputs normally, and when single event upset is detected, the current level of the latch is inverted and then output; and the hardened circuit in the present application is located outside the data transmission critical path, which realizes the characteristics of low delay and high transmission rate.

[0108] In summary, the flip-flop provided by the present application resists single event upset by setting a master-slave two-stage latch, each of which includes a detection circuit as a hardened structure to resist single event upset, and the signal of the detection circuit is used to determine whether the latch structure has a level state upset. If no single event upset occurs, the latch outputs data normally; if single event upset occurs, the inverted level is output; the flip-flop can still output correct logic level after single event upset, and has good resistance to single event upset; and the structure has fewer sensitive nodes, so it has good resistance to multiple node upset; at the same time, since the hardened structure is located outside the data transmission critical path, it has high transmission rate characteristics, and is suitable for advanced process radiation hardened circuit design. The problem that the prior art cannot resist single event upset of multiple nodes in a digital circuit is solved, and the transmission rate of the flip-flop is improved.

[0109] Although the application has been described in connection with various embodiments thereof, it will be understood that the application is capable of further modifications and that this application is intended to cover any and all such variations, using the scope of the claims. In the claims, the term comprising does not exclude the presence of other elements or steps than those listed in a claim. The term "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. A single processor or other unit can fulfil the functions of several items recited in the claims. The terms "first", "second" and the like in the description do not necessarily imply that there are two or more items. Embodiments of the application can relate to any of the specific features and combinations thereof without necessarily referring to the corresponding drawings.

[0110] Although the application has been described in connection with specific embodiments thereof, it will be understood that it is capable of further modifications and this application is intended to cover any and all such variations, using the scope of the claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense. It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Therefore, it is intended that the present application cover all such modifications and variations of the application that come within the scope of the appended claims and their equivalents.

Claims

1. A latch resistant to single event upsets, comprising: The latch comprises a basic latch, a transmission gate and a detection circuit; The input end of the basic latch is connected with the input end of the latch, the output end of the basic latch is connected with the input end of the transmission gate, the output end of the transmission gate is connected with the output end of the latch, the input end of the detection circuit is connected with the basic latch, and the output end of the detection circuit is connected with the transmission gate; The basic latch is used for latching the storage level state of the corresponding hardened circuit of the latch; The latch judges the level flip state of the basic latch by using the detection signal of the detection circuit, and generates a control signal for controlling the output of the latch based on the level flip state of the basic latch; The detection circuit comprises eighth to fifteenth PMOS tubes and eighth to tenth NMOS tubes; the gate of the eighth PMOS tube is connected with the fourth signal end, the source is connected with the power supply end, and the drain is connected with the third signal end; the gate of the ninth PMOS tube is connected with the sixth signal end, the source is connected with the power supply end, and the drain is connected with the fifth signal end; the gate of the tenth PMOS tube is connected with the clock signal end, the source is connected with the power supply end, and the drain is connected with the third signal end; the gate of the eleventh PMOS tube is connected with the clock signal end, the source is connected with the power supply end, and the drain is connected with the fifth signal end; the gate of the twelfth PMOS tube is connected with the first signal end, the source is connected with the third signal end, and the drain is connected with the drain of the thirteenth PMOS tube; the gate of the thirteenth PMOS tube is connected with the second signal end, the source is connected with the fifth signal end, and the drain is connected with the drain of the eighth NMOS tube; the gate of the fourteenth PMOS tube is connected with the third signal end, the source is connected with the power supply end, and the drain is connected with the fourth signal end; the gate of the fifteenth PMOS tube is connected with the fifth signal end, the source is connected with the power supply end, and the drain is connected with the sixth signal end; The gate of the eighth NMOS tube is connected with the clock signal end, and the source is grounded; the drain of the ninth NMOS tube is connected with the fourth signal end, the gate is connected with the third signal end, and the source is grounded; the gate of the tenth NMOS tube is connected with the fifth signal end, the source is grounded, and the drain is connected with the sixth signal end; When the latch circuit is in the transparent state, the tenth and eleventh PMOS tubes in the detection circuit are opened, the eighth NMOS tube is turned off, the third signal end and the fifth signal end are connected to output a high level, and the fourth signal end and the sixth signal end are connected to output a low level; when the latch circuit is in the latching state, the tenth and eleventh PMOS tubes in the detection circuit are turned off, and the eighth NMOS tube is turned on.

2. The latch of claim 1, wherein, When the latch circuit is in the transparent state, the fourth and fifth PMOS tubes and the fourth and fifth NMOS tubes in the basic latch are opened, the sixth and seventh PMOS tubes and the sixth and seventh NMOS tubes are turned off, and the sixteenth PMOS tube and the eleventh NMOS tube are opened. ​ 3. The latch of claim 1, wherein, When the latch circuit is in a latching state, further comprising: When the first signal end of the basic latch is 1 and the second signal end is 0; if a single event upset does not occur in the latch, the latch output is the electrical signal corresponding to the second signal end; if a single event upset occurs in the first signal end and / or the second signal end node, the latch output is the electrical signal corresponding to the first signal end; When the first signal end of the basic latch is 0 and the second signal end is 1; if a single event upset does not occur in the latch, the latch output is the electrical signal corresponding to the second signal end; if a single event upset occurs in the first signal end and / or the second signal end node, the latch output is the electrical signal corresponding to the first signal end.

4. The latch of claim 1, wherein, The basic latch comprises: a first PMOS tube, a second PMOS tube, a third PMOS tube, a sixteenth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, and an eleventh NMOS tube; The gate of the sixteenth PMOS tube is connected with the clock signal end, the drain of the sixteenth PMOS tube is connected with the input end of the latch, and the source of the sixteenth PMOS tube is connected with the first signal end; the source of the first PMOS tube is connected with the source of the third PMOS tube, the drain of the first PMOS tube is connected with the second signal end, and the gate of the first PMOS tube is connected with the first signal end; the source of the second PMOS tube is connected with the drain of the third PMOS tube, the drain of the second PMOS tube is connected with the first signal end, and the gate of the second PMOS tube is connected with the second signal end; the gate of the third PMOS tube is connected with the clock inverse signal end; The gate of the eleventh NMOS tube is connected with the clock inverse signal end, the drain of the eleventh NMOS tube is connected with the drain of the sixteenth PMOS tube, and the source of the eleventh NMOS tube is connected with the source of the sixteenth PMOS tube; the drain of the first NMOS tube is connected with the second signal end, the source of the first NMOS tube is connected with the source of the third NMOS tube, and the gate of the first NMOS tube is connected with the first signal end; the source of the second NMOS tube is connected with the drain of the third NMOS tube, the drain of the second NMOS tube is connected with the first signal end, and the gate of the second NMOS tube is connected with the second signal end; the gate of the third NMOS tube is connected with the clock signal end.

5. The latch of claim 1, wherein, The transmission gate comprises: a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, and a seventh NMOS tube; a gate of the fourth PMOS transistor is connected with the sixth signal terminal, a drain of the fourth PMOS transistor is connected with the second signal terminal, and a source of the fourth PMOS transistor is connected with an output terminal of the latch; a gate of the fifth PMOS transistor is connected with the fourth signal terminal, a drain of the fifth PMOS transistor is connected with the second signal terminal, and a source of the fifth PMOS transistor is connected with the source of the fourth PMOS transistor; a gate of the sixth PMOS transistor is connected with the third signal terminal, a drain of the sixth PMOS transistor is connected with the first signal terminal, and a source of the sixth PMOS transistor is connected with a drain of the seventh PMOS transistor; a gate of the seventh PMOS transistor is connected with the fifth signal terminal, and a source of the seventh PMOS transistor is connected with the source of the fourth PMOS transistor; a gate of the fourth NMOS transistor is connected with the fifth signal terminal, a drain of the fourth NMOS transistor is connected with the second signal terminal, and a source of the fourth NMOS transistor is connected with the source of the fourth PMOS transistor; a gate of the fifth NMOS transistor is connected with the third signal terminal, a drain of the fifth NMOS transistor is connected with the second signal terminal, and a source of the fifth NMOS transistor is connected with the source of the fifth PMOS transistor; a gate of the sixth NMOS transistor is connected with the fourth signal terminal, a drain of the sixth NMOS transistor is connected with the first signal terminal, and a source of the sixth NMOS transistor is connected with the source of the sixth PMOS transistor; a gate of the seventh NMOS transistor is connected with the sixth signal terminal, a drain of the seventh NMOS transistor is connected with the drain of the seventh PMOS transistor, and a source of the seventh NMOS transistor is connected with the source of the seventh PMOS transistor.

6. A flip-flop resistant to single event upsets, characterized by The flip-flop at least comprises a latch and a slave latch; the latch is the latch against single event upset according to any one of claims 1 to 5; an input terminal of the latch is connected with an input terminal of the flip-flop, an output terminal of the latch is connected with an input terminal of the slave latch, and an output terminal of the slave latch is connected with an output terminal of the flip-flop; the latch at least comprises a detection circuit and a basic latch; the flip-flop uses a detection signal of the detection circuit to judge a level flip state of the basic latch, and generates a control signal for controlling an output of the latch based on the level flip state of the basic latch; the slave latch at least comprises a slave detection circuit and a slave basic latch; the flip-flop uses a detection signal of the slave detection circuit to judge a level flip state of the slave basic latch, and generates a control signal for controlling an output of the slave latch based on the level flip state of the slave basic latch; the clock level of the detection circuit is opposite to that of the slave detection circuit.

7. The flip-flop as claimed in claim 6, wherein the first and second inverters are connected in series to each other, and the third and fourth inverters are connected in series to each other. the latch further comprises a pass gate, and the slave latch further comprises a slave pass gate; an input terminal of the basic latch is connected with the input terminal of the flip-flop, and an output terminal of the basic latch is connected with an input terminal of the pass gate; The input end of the slave stage basic latch is connected with the output end of the transmission gate, the output end of the slave stage basic latch is connected with the input end of the slave stage transmission gate, and the output end of the slave stage transmission gate is connected with the output end of the flip-flop; The basic latch is used for locking the storage level state of the latch; The slave stage basic latch is used for locking the storage level state of the slave stage latch.

8. The flip-flop as claimed in claim 6, wherein, The slave stage basic latch comprises a seventeenth PMOS tube, an eighteenth PMOS tube, a nineteenth PMOS tube, a twenty-fourth PMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube and a nineteenth NMOS tube; The gate of the twenty-fourth PMOS tube is connected with the clock inverse signal end, the drain of the twenty-fourth PMOS tube is connected with the output end of the transmission gate, and the source of the twenty-fourth PMOS tube is connected with the seventh signal end; the source of the seventeenth PMOS tube is connected with the source of the nineteenth PMOS tube, the drain of the seventeenth PMOS tube is connected with the eighth signal end, and the gate of the seventeenth PMOS tube is connected with the seventh signal end; the source of the eighteenth PMOS tube is connected with the drain of the nineteenth PMOS tube, the drain of the eighteenth PMOS tube is connected with the seventh signal end, and the gate of the eighteenth PMOS tube is connected with the eighth signal end; the gate of the nineteenth PMOS tube is connected with the clock signal end; The gate of the nineteenth NMOS tube is connected with the clock signal end, the drain of the nineteenth NMOS tube is connected with the drain of the twenty-fourth PMOS tube, and the source of the nineteenth NMOS tube is connected with the seventh signal end; the drain of the twelfth NMOS tube is connected with the eighth signal end, the source of the twelfth NMOS tube is connected with the source of the fourteenth NMOS tube, and the gate of the twelfth NMOS tube is connected with the seventh signal end; the source of the thirteenth NMOS tube is connected with the drain of the fourteenth NMOS tube, the drain of the thirteenth NMOS tube is connected with the seventh signal end, and the gate of the thirteenth NMOS tube is connected with the eighth signal end; and the gate of the fourteenth NMOS tube is connected with the clock inverse signal end.

9. The flip-flop as claimed in claim 7, wherein the first and second inverters are connected in series to each other, and the first and second inverters are connected in parallel to each other. The slave stage transmission gate comprises a twentieth PMOS tube, a twenty-first PMOS tube, a twenty-second PMOS tube, a twenty-third PMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a seventeenth NMOS tube and an eighteenth NMOS tube; The gate of the twentieth PMOS tube is connected with the twelfth signal end, the drain of the twentieth PMOS tube is connected with the eighth signal end, and the source of the twentieth PMOS tube is connected with the output end of the flip-flop; the gate of the twenty-first PMOS tube is connected with the tenth signal end, the drain of the twenty-first PMOS tube is connected with the eighth signal end, and the source of the twenty-first PMOS tube is connected with the output end of the flip-flop; the gate of the twenty-second PMOS tube is connected with the ninth signal end, the drain of the twenty-second PMOS tube is connected with the seventh signal end, and the source of the twenty-second PMOS tube is connected with the drain of the twenty-third PMOS tube; the gate of the twenty-third PMOS tube is connected with the eleventh signal end, and the source of the twenty-third PMOS tube is connected with the output end of the flip-flop; The gate of the fifteenth NMOS tube is connected with the eleventh signal end, the drain of the fifteenth NMOS tube is connected with the eighth signal end, and the source of the fifteenth NMOS tube is connected with the source of the twentieth PMOS tube; the gate of the sixteenth NMOS tube is connected with the ninth signal end, the drain of the sixteenth NMOS tube is connected with the eighth signal end, and the source of the sixteenth NMOS tube is connected with the source of the twenty-first PMOS tube; the gate of the seventeenth NMOS tube is connected with the tenth signal end, the drain of the seventeenth NMOS tube is connected with the seventh signal end, and the source of the seventeenth NMOS tube is connected with the source of the twenty-second PMOS tube; the gate of the eighteenth NMOS tube is connected with the twelfth signal end, the drain of the eighteenth NMOS tube is connected with the drain of the twenty-third PMOS tube, and the source of the eighteenth NMOS tube is connected with the source of the twenty-third PMOS tube.

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