Latch and trigger for resisting single event upset in digital circuit

Abstract

The invention discloses a latch and a trigger for resisting single event upset in a digital circuit, relates to the technical field of digital integrated circuit design, and aims to solve the problem that single event upset of a plurality of nodes in a latch structure of the digital circuit cannot be resisted in the prior art. The latch at least comprises a basic latch, a transmission gate and a detection circuit which are connected with one another; the latch judges the level flipping state of the basic latch by using the detection signal of the detection circuit, and generates a control signal for controlling the output of the latch based on the level flipping state of the basic latch; furthermore, a trigger can be formed by utilizing a plurality of latches with the structures; therefore, the latch and the trigger can recover to the correct level after being subjected to multi-node single-particle bombardment, and the resistance of the latch and the trigger to the single-particle radiation effect is improved.

Description

Technical Field

[0001] The invention relates to the technical field of digital integrated circuit design, in particular to a latch and a trigger capable of resisting single particle flip-flop in a digital circuit. Background Art

[0002] When high-energy particles are incident on digital circuit chips working in space radiation environments, they deposit energy through direct ionization and indirect ionization, eventually causing the atoms in the material to ionize and produce electron-hole pairs. Part of the charge is collected by the sensitive nodes of the device under the action of the electric field, such as the drain of the off MOS tube, which causes the logic state of the device to change and triggers a single-particle upset. In order to mitigate the impact of single-particle upsets on digital circuit chips, digital circuits need to be hardened against radiation.

[0003] As the process feature size of semiconductor devices shrinks, node capacitance and power supply voltage are decreasing, making single-particle flips more likely to occur. In addition, the reduction in node spacing due to size reduction exacerbates the charge sharing effect on the one hand, and on the other hand, the probability of adjacent nodes being hit by single particles at the same time increases, making multi-node single-particle flips more likely to occur, thus posing a great challenge to the reinforcement of advanced processes. In the prior art, the traditional latch reinforcement scheme is to reinforce the master-slave latch of the trigger. This reinforcement structure has good resistance to single-node flips. However, with the improvement of semiconductor process, the charge sharing effect becomes more and more significant due to the shortening of node spacing, which is very easy to cause the latch structure in the latch circuit to flip multiple nodes at the same time. The traditional latch reinforcement scheme cannot resist the simultaneous flipping of multiple nodes; and the interlocking structure will increase the circuit delay and reduce the circuit speed.

[0004] Therefore, it is urgent to design a technical solution that can resist the simultaneous flipping of multiple nodes in the latch structure of the circuit, so as to solve the problem that the prior art cannot resist the single particle flipping of multiple nodes in the latch structure of the digital circuit. Summary of the invention

[0005] The purpose of the present invention is to provide a latch and a trigger that can resist single-particle upsets in digital circuits. A detection circuit independent of the latch structure is designed. The latch uses the detection circuit to determine whether a single-particle upset occurs in a basic latch circuit, and generates a control signal for controlling the output of the latch circuit based on a detection signal of the detection circuit, thereby realizing that the memory structure of the latch can be restored to a correct level after being bombarded by single particles at multiple nodes; the problem in the prior art that the latch structure of a digital circuit cannot resist single-particle upsets at multiple nodes is solved.

[0006] In order to achieve the above object, the present invention provides the following technical solutions:

[0007] In a first aspect, the present invention provides a latch for resisting single-particle upset in a digital circuit, wherein the latch may at least include a basic latch, a transmission gate, and a detection circuit;

[0008] The input end of the basic latch is connected to the input end of the latch, the output end of the basic latch is connected to the input end of the transmission gate, the output end of the transmission gate is connected to the output end of the latch, the input end of the detection circuit is connected to the basic latch, and the output end of the detection circuit is connected to the transmission gate;

[0009] The latch determines the level inversion state of the basic latch by using the detection signal of the detection circuit, and generates a control signal for controlling the output of the latch based on the level inversion state of the basic latch.

[0010] Preferably, the detection circuit may include a first detection circuit, and the first detection circuit may include a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube and a thirteenth NMOS tube;

[0011] The drain of the seventh PMOS tube is connected to the third signal terminal, the gate of the seventh PMOS tube is connected to the clock anti-signal terminal, and the source of the seventh PMOS tube is connected to the drain of the eighth PMOS tube; the gate of the eighth PMOS tube is connected to the first signal terminal, and the source of the eighth PMOS tube is connected to the drain of the ninth PMOS tube; the gate of the ninth PMOS tube is connected to the clock anti-signal terminal, the source of the ninth PMOS tube is connected to the power supply terminal, and the drain of the ninth PMOS tube is connected to the seventh signal terminal; the gate of the tenth PMOS tube is connected to the first signal terminal, and the source of the eighth PMOS tube is connected to the drain of the ninth PMOS tube; the gate of the ninth PMOS tube is connected to the clock anti-signal terminal, the source of the ninth PMOS tube is connected to the power supply terminal, and the drain of the ninth PMOS tube is connected to the seventh signal terminal; the gate of the tenth PMOS tube is connected to the The first PMOS tube is connected to the clock signal terminal, the source of the tenth PMOS tube is connected to the power supply terminal, the drain of the tenth PMOS tube is connected to the drain of the eleventh PMOS tube and the fourth signal terminal; the gate of the eleventh PMOS tube is connected to the first signal terminal; the drain of the twelfth PMOS tube is connected to the fourth signal terminal, and the gate of the twelfth PMOS tube is connected to the seventh signal terminal; the gate of the thirteenth PMOS tube is connected to the fourth signal terminal, the source of the thirteenth PMOS tube is connected to the power supply terminal, and the drain of the thirteenth PMOS tube is connected to the fifth signal terminal;

[0012] The drain of the seventh NMOS tube is connected to the third signal terminal, the gate of the seventh NMOS tube is connected to the clock signal terminal, and the source of the seventh NMOS tube is connected to the source of the seventh PMOS tube; the drain of the eighth NMOS tube is connected to the drain of the eighth PMOS tube, the gate of the eighth NMOS tube is connected to the first signal terminal, and the source of the eighth NMOS tube is connected to the drain of the ninth NMOS tube; the gate of the ninth NMOS tube is connected to the clock signal terminal, the gate source of the ninth NMOS tube is grounded, and the drain of the ninth NMOS tube is connected to the sixth signal terminal; the gate of the tenth NMOS tube is connected to the clock signal terminal, and the gate of the tenth NMOS tube is connected to the clock signal terminal. The source of the NMOS tube is grounded, and the drain of the tenth NMOS tube is connected to the source of the eleventh NMOS tube; the gate of the eleventh NMOS tube is connected to the sixth signal terminal, and the drain of the eleventh NMOS tube is connected to the source of the eleventh PMOS tube; the source of the twelfth NMOS tube is connected to the drain of the tenth NMOS tube, the gate of the tenth NMOS tube is connected to the first signal terminal, and the drain of the tenth NMOS tube is connected to the source of the twelfth PMOS tube; the gate of the thirteenth NMOS tube is connected to the fourth signal terminal, the source of the thirteenth NMOS tube is grounded, and the drain of the thirteenth NMOS tube is connected to the fifth signal terminal.

[0013] Preferably, when the latch is in a transparent state, it may include:

[0014] In the first detection circuit, the tenth PMOS tube is turned on, the tenth NMOS tube is turned off, the level output to the fourth signal terminal node is a high level, and the level output to the fifth signal terminal node is a low level;

[0015] In the basic latch, the third PMOS tube and the third NMOS tube are turned off, the seventh PMOS tube and the seventh NMOS tube are turned off, the ninth PMOS tube and the ninth NMOS tube are turned on, the fourteenth PMOS tube and the fourteenth NMOS tube are turned on, the sixth signal terminal node is at a low level, and the seventh signal terminal node is at a high level.

[0016] Preferably, when the latch is in a latched state, it may include:

[0017] In the first detection circuit, the ninth PMOS tube and the ninth NMOS tube are turned off, the seventh PMOS tube and the seventh NMOS tube are turned on, the tenth PMOS tube is turned off, and the tenth NMOS tube is turned on;

[0018] When the first signal terminal in the basic latch is 1 and the second signal terminal is 0; if no single event upset occurs, the latch output is the third signal terminal; if a single event upset occurs at the first signal terminal and / or the second signal terminal node, the latch output is the second signal terminal;

[0019] When the first signal terminal in the basic latch is 1 and the second signal terminal is 0; if no single particle upset occurs, the latch output is the third signal terminal; if a single particle upset occurs at the first signal terminal and / or the second signal terminal node, the latch output is the second signal terminal.

[0020] Preferably, the detection circuit may include a second detection circuit, and the second detection circuit includes a twenty-ninth PMOS tube, a thirtieth PMOS tube, a thirty-first PMOS tube, a thirty-second PMOS tube, a thirty-third PMOS tube, a thirty-fourth PMOS tube, a thirty-fifth PMOS tube, a thirty-sixth PMOS tube, a thirty-seventh PMOS tube, a thirty-eighth PMOS tube, a thirty-ninth PMOS tube, a twenty-ninth NMOS tube, a 30th NMOS tube, a thirty-first NMOS tube, a thirty-second NMOS tube, a thirty-third NMOS tube, a thirty-fourth NMOS tube, a thirty-fifth NMOS tube, a thirty-sixth NMOS tube and a thirty-seventh NMOS tube;

[0021] The source of the 29th PMOS tube is connected to the power supply terminal, the gate of the 29th PMOS tube is connected to the clock signal terminal, and the drain of the 29th PMOS tube is connected to the source of the 30th PMOS tube; the gate of the 30th PMOS tube is connected to the first signal terminal, the drain of the 30th PMOS tube is connected to the drain of the 31st NMOS tube, and the source of the 30th PMOS tube is connected to the 13th signal terminal; the gate of the 31st NMOS tube is connected to the clock signal terminal, and the source of the 31st NMOS tube is grounded; the gate of the 32nd PMOS tube is connected to the 13th signal terminal, the source of the 32nd PMOS tube is connected to the power supply terminal, and the drain of the 32nd PMOS tube is connected to the 14th signal terminal; the drain of the 32nd NMOS tube is connected to the 14th signal terminal, the source of the 32nd NMOS tube is grounded, and the gate of the 32nd NMOS tube is connected to the 13th signal terminal; The source of the thirty-first PMOS tube is connected to the power supply terminal, the gate of the thirty-first PMOS tube is connected to the clock inverse signal terminal, and the drain of the thirty-first PMOS tube is connected to the drain of the thirtieth NMOS tube; the source of the thirtieth NMOS tube is connected to the fifteenth signal terminal, the gate of the thirtieth NMOS tube is connected to the first signal terminal, and the source of the thirtieth NMOS tube is connected to the drain of the twenty-ninth NMOS tube; the gate of the twenty-ninth NMOS tube is connected to the clock inverse signal terminal, and the source of the twenty-ninth NMOS tube is grounded; the source of the thirty-third PMOS tube is connected to the power supply terminal, the gate of the thirty-third PMOS tube is connected to the fifteenth signal terminal, and the drain of the thirty-third PMOS tube is connected to the sixteenth signal terminal; the source of the thirty-third NMOS tube is grounded, the gate of the thirty-third NMOS tube is connected to the fifteenth signal terminal, and the gate and drain of the thirty-third NMOS tube are connected to the sixteenth signal terminal;

[0022] The gate of the thirty-fourth PMOS tube is connected to the clock signal terminal, the source of the thirty-fourth PMOS tube is connected to the power supply terminal, and the drain of the thirty-fourth PMOS tube is connected to the fourth signal terminal; the source of the thirty-fifth PMOS tube is connected to the power supply terminal, the gate of the thirty-fifth PMOS tube is connected to the thirteenth signal terminal, and the drain of the thirty-fifth PMOS tube is connected to the source of the thirty-seventh PMOS tube; the gate of the thirty-seventh PMOS tube is connected to the fifteenth signal terminal, and the drain is connected to the fourth signal terminal; the source of the thirty-sixth PMOS tube is connected to the power supply terminal, the gate of the thirty-sixth PMOS tube is connected to the fourteenth signal terminal, and the drain of the thirty-sixth PMOS tube is connected to the source of the thirty-eighth PMOS tube; the gate of the thirty-eighth PMOS tube is connected to the sixteenth signal terminal, and the drain is connected to the fourth signal terminal; The source of the MOS tube is connected to the power supply terminal, the gate of the thirty-ninth PMOS tube is connected to the fourth signal terminal, and the drain of the thirty-ninth PMOS tube is connected to the fifth signal terminal; the drain of the thirty-fourth NMOS tube is connected to the source of the thirty-fifth NMOS tube, the gate of the thirty-fourth NMOS tube is connected to the clock signal terminal, and the source of the thirty-fourth NMOS tube is grounded; the drain of the thirty-fifth NMOS tube is connected to the source of the thirty-sixth NMOS tube, and the gate of the thirty-fifth NMOS tube is connected to the fourteenth signal terminal; the gate of the thirty-sixth NMOS tube is connected to the fifteenth signal terminal, and the drain of the thirty-sixth NMOS tube is connected to the fourth signal terminal; the drain of the thirty-seventh NMOS tube is connected to the fifth signal terminal, the source of the thirty-seventh NMOS tube is grounded, and the gate of the thirty-seventh NMOS tube is connected to the fourth signal terminal.

[0023] Preferably, when the latch is in a latched state, it may include:

[0024] The twenty-ninth PMOS tube and the twenty-ninth NMOS tube in the second detection circuit are turned off, and the thirty-first PMOS tube and the thirty-first NMOS tube are turned on;

[0025] When the first signal terminal in the basic latch is 1 and the second signal terminal is 0; if no single-particle upset occurs, the latch output is the third signal terminal; if a single-particle upset occurs at the first signal terminal and / or the second signal terminal node, the latch output is the electrical signal corresponding to the second signal terminal;

[0026] When the first signal terminal in the basic latch is 0 and the second signal terminal is 1; if no single particle upset occurs, the latch output is the third signal terminal; if a single particle upset occurs at the first signal terminal and / or the second signal terminal node, the latch output is the electrical signal corresponding to the second signal terminal.

[0027] Preferably, the basic latch may include: a first PMOS tube, a second PMOS tube, a third PMOS tube, a sixth PMOS tube, a fourteenth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a sixth NMOS tube and a fourteenth NMOS tube; the transmission gate includes: a fourth PMOS tube, a fifth PMOS tube, a fourth NMOS tube and a fifth NMOS tube;

[0028] The source of the first PMOS tube is connected to the source of the third PMOS tube, the drain of the first PMOS tube is connected to the second signal terminal, and the gate of the first PMOS tube is connected to the first signal terminal; the source of the second PMOS tube is connected to the drain of the third PMOS tube, the drain of the second PMOS tube is connected to the first signal terminal, and the gate of the second PMOS tube is connected to the second signal terminal; the gate of the third PMOS tube is connected to the clock anti-signal terminal; the gate of the sixth PMOS tube is connected to the second signal terminal, the source of the sixth PMOS tube is connected to the power supply terminal, and the drain of the sixth PMOS tube is connected to the third signal terminal; the gate of the fourteenth PMOS tube is connected to the clock signal terminal, the drain of the fourteenth PMOS tube is connected to the input terminal of the latch, and the source of the fourteenth PMOS tube is connected to the first signal terminal;

[0029] The drain of the first NMOS tube is connected to the second signal terminal, the source of the first NMOS tube is connected to the source of the third NMOS tube, and the gate of the first NMOS tube is connected to the first signal terminal; the source of the second NMOS tube is connected to the drain of the third NMOS tube, the drain of the second NMOS tube is connected to the first signal terminal, and the gate of the second NMOS tube is connected to the second signal terminal; the gate of the third NMOS tube is connected to the clock signal terminal; the gate of the sixth NMOS tube is connected to the second signal terminal, the source of the sixth NMOS tube is grounded, and the drain of the sixth NMOS tube is connected to the third signal terminal; the gate of the fourteenth NMOS tube is connected to the clock anti-signal terminal, the drain of the fourteenth NMOS tube is connected to the input terminal of the latch, and the source of the fourteenth NMOS tube is connected to the first signal terminal;

[0030] The gate of the fourth PMOS tube is connected to the fifth signal terminal, the drain of the fourth PMOS tube is connected to the third signal terminal, and the source of the fourth PMOS tube is connected to the input terminal of the slave-level latch; the gate of the fifth PMOS tube is connected to the fourth signal terminal, the drain of the fifth PMOS tube is connected to the second signal terminal, and the source of the fifth PMOS tube is connected to the input terminal of the slave-level latch; the gate of the fourth NMOS tube is connected to the fourth signal terminal, the drain of the fourth NMOS tube is connected to the third signal terminal, and the source of the fourth NMOS tube is connected to the input terminal of the slave-level latch; the gate of the fifth NMOS tube is connected to the fifth signal terminal, the drain of the fifth NMOS tube is connected to the second signal terminal, and the source of the fifth NMOS tube is connected to the input terminal of the slave-level latch.

[0031] In a second aspect, the present invention provides a trigger for resisting single-particle upset in a digital circuit, the trigger may at least include a latch and a slave latch;

[0032] The input end of the latch is connected to the input end of the trigger, the output end of the latch is connected to the input end of the slave latch, and the output end of the slave latch is connected to the output end of the trigger;

[0033] The latch may include at least a detection circuit and a basic latch; the trigger determines the level flip state of the basic latch using the detection signal of the detection circuit, and generates a control signal for controlling the output of the latch based on the level flip state of the basic latch;

[0034] The slave latch may include at least a slave detection circuit and a slave basic latch; the trigger uses the detection signal of the slave detection circuit to determine the level flip state of the slave basic latch, and generates a control signal for controlling the output of the slave latch based on the level flip state of the slave basic latch.

[0035] Preferably, the latch may further include a transmission gate, and the slave latch may further include a slave transmission gate;

[0036] The input end of the basic latch is connected to the input end of the trigger, and the output end of the basic latch is connected to the input end of the transmission gate; the output end of the transmission gate is connected to the input end of the slave basic latch, the output end of the slave basic latch is connected to the input end of the slave transmission gate, and the output end of the slave transmission gate is connected to the output end of the trigger;

[0037] The basic latch is used to latch the storage level state of the latch; the slave basic latch is used to latch the storage level state of the slave latch.

[0038] Preferably, the slave-level basic latch may include: a fifteenth PMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube, a twentieth PMOS tube, a twenty-eighth PMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a seventeenth NMOS tube, a twentieth NMOS tube and a twenty-eighth NMOS tube; the slave-level transmission gate includes: an eighteenth PMOS tube, a nineteenth PMOS tube, an eighteenth NMOS tube and a nineteenth NMOS tube;

[0039] The source of the fifteenth PMOS tube is connected to the source of the seventeenth PMOS tube, the drain of the fifteenth PMOS tube is connected to the ninth signal terminal, and the gate of the fifteenth PMOS tube is connected to the eighth signal terminal; the source of the sixteenth PMOS tube is connected to the drain of the seventeenth PMOS tube, the drain of the sixteenth PMOS tube is connected to the eighth signal terminal, and the gate of the sixteenth PMOS tube is connected to the ninth signal terminal; the gate of the seventeenth PMOS tube is connected to the clock signal terminal; the gate of the 20th PMOS tube is connected to the ninth signal terminal, the source of the 20th PMOS tube is connected to the power supply terminal, and the drain of the 20th PMOS tube is connected to the tenth signal terminal; the gate of the twenty-eighth PMOS tube is connected to the clock anti-signal terminal, the drain of the twenty-eighth PMOS tube is connected to the input terminal of the slave basic latch, and the source of the twenty-eighth PMOS tube is connected to the eighth signal terminal;

[0040] The drain of the fifteenth NMOS tube is connected to the ninth signal terminal, the source of the fifteenth NMOS tube is connected to the source of the seventeenth NMOS tube, and the gate of the fifteenth NMOS tube is connected to the eighth signal terminal; the source of the sixteenth NMOS tube is connected to the drain of the seventeenth NMOS tube, the drain of the sixteenth NMOS tube is connected to the eighth signal terminal, and the gate of the sixteenth NMOS tube is connected to the ninth signal terminal; the gate of the seventeenth NMOS tube is connected to the clock inverse signal terminal; the gate of the 20th NMOS tube is connected to the ninth signal terminal, the source of the 20th NMOS tube is grounded, and the drain of the 20th NMOS tube is connected to the tenth signal terminal; the gate of the 28th NMOS tube is connected to the clock signal terminal, the drain of the 28th NMOS tube is connected to the input terminal of the slave basic latch, and the source of the 28th NMOS tube is connected to the eighth signal terminal;

[0041] The gate of the eighteenth PMOS tube is connected to the twelfth signal terminal, the drain of the eighteenth PMOS tube is connected to the tenth signal terminal, and the source of the eighteenth PMOS tube is connected to the output terminal of the trigger; the gate of the nineteenth PMOS tube is connected to the eleventh signal terminal, the drain of the nineteenth PMOS tube is connected to the ninth signal terminal, and the source of the nineteenth PMOS tube is connected to the output terminal of the trigger; the gate of the eighteenth NMOS tube is connected to the eleventh signal terminal, the drain of the eighteenth NMOS tube is connected to the tenth signal terminal, and the source of the eighteenth NMOS tube is connected to the output terminal of the trigger; the gate of the nineteenth NMOS tube is connected to the twelfth signal terminal, the drain of the nineteenth NMOS tube is connected to the ninth signal terminal, and the source of the nineteenth NMOS tube is connected to the output terminal of the trigger.

[0042] Compared with the prior art, the present invention provides a latch for resisting single-particle upset in a digital circuit. The latch may at least include a basic latch, a transmission gate and a detection circuit. The input end of the basic latch is connected to the input end of the latch, the output end of the basic latch is connected to the input end of the transmission gate, the output end of the transmission gate is connected to the output end of the latch, the input end of the detection circuit is connected to the basic latch, and the output end of the detection circuit is connected to the transmission gate. The latch uses a detection signal of the detection circuit to judge the level flip state of the basic latch, and generates a control signal for controlling the output of the latch based on the level flip state of the basic latch. Based on this, if no single-particle upset occurs at any node in the latch circuit, the latch outputs data normally. If a single-particle upset occurs, the flip level is inverted and then output, ensuring that the latch can still output the correct logic level after a multi-node single-particle upset occurs, thereby improving the resistance of the latch structure to the single-particle radiation effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0044] Figure 1 It is a schematic diagram of the structure of the first detection circuit in the prior art;

[0045] Figure 2 It is a schematic diagram of the structure of the second detection circuit in the prior art;

[0046] Figure 3 A schematic diagram of the main circuit structure of a latch and a trigger for resisting single particle upset in a digital circuit provided by the present invention;

[0047] Figure 4A schematic diagram of the first detection circuit structure of a latch and a trigger for resisting single-particle upset in a digital circuit provided by the present invention;

[0048] Figure 5 A schematic diagram of the second detection circuit structure of a latch and a trigger for resisting single particle upset in a digital circuit provided by the present invention.

[0049] Reference numerals: 100 - trigger, 110 - latch, 120 - slave latch, 112 - detection circuit, 111 - basic latch, 113 - transmission gate, 122 - slave detection circuit, 121 - slave basic latch, 123 - slave transmission gate, 1121 - first detection circuit, 1122 - second detection circuit, clkb - clock inverted signal terminal, clkbb - clock signal terminal, b0 - first signal terminal, b1 - second signal terminal Terminal, b1N-third signal terminal, E1-fourth signal terminal, E1N-fifth signal terminal, A1-sixth signal terminal, C1-seventh signal terminal, b2-eighth signal terminal, b3-ninth signal terminal, b3N-tenth signal terminal, E2-eleventh signal terminal, E2N-twelfth signal terminal, A2-thirteenth signal terminal, A2N-fourteenth signal terminal, C2-fifteenth signal terminal, C2N-sixteenth signal terminal, IN-input terminal, OUT-output terminal. DETAILED DESCRIPTION

[0050] In order to facilitate the clear description of the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, the words "first", "second" and the like are used to distinguish the same items or similar items with substantially the same functions and effects. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and do not limit their order of precedence. Those skilled in the art can understand that the words "first", "second" and the like do not limit the quantity and execution order, and the words "first", "second" and the like do not necessarily limit them to be different.

[0051] It should be noted that, in the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0052] In the present invention, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects in the previous time are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b, c can be single or multiple.

[0053] At present, the traditional trigger reinforcement scheme is to reinforce the master and slave latches of the trigger; see Figure 1 to Figure 2 ; Figure 1 It is a schematic diagram of the structure of the first detection circuit in the prior art; Figure 2 This is a schematic diagram of the second detection circuit structure in the prior art.

[0054] Figure 1 The reinforcement design shown in the figure is a single-particle upset reinforcement structure of a dual inter-locked storage cell (DICE), which has four data storage nodes. When a node undergoes a single-particle upset due to external high-energy particles, since the data stored in each node is controlled by the other two nodes, the temporary upset of a single node will not propagate the error level to other nodes, and will not cause changes in the logical states of other nodes. Ultimately, through the feedback structure of the structure, other unaffected nodes can restore the storage node where the single-particle upset occurred to its original level.

[0055] The DICE reinforcement structure has good resistance to single-node flipping, but with the improvement of semiconductor process, the charge sharing effect becomes more and more significant due to the shortening of node spacing, which can easily cause multiple nodes in the latch structure in the trigger circuit to flip simultaneously, and the DICE structure cannot resist the simultaneous flipping of multiple nodes; and the interlocking structure will increase circuit delay and reduce data transmission rate.

[0056] Figure 2The reinforcement design shown in is a latch structure called Quatro, which has four data storage nodes. The logic state of each node is controlled by the other two nodes. When a node undergoes a single-particle flip due to external high-energy particles, since the data stored in each node is controlled by the other two nodes, similar to the DICE structure, when a node undergoes a single-particle flip due to external high-energy particles, since the data stored in each node is controlled by the other two nodes, the temporary flip of a single node will not propagate the error level to other nodes, and will not cause the logic state of other nodes to change. Ultimately, through the feedback structure of the structure, other unaffected nodes can restore the storage node that has undergone the single-particle flip to its original level.

[0057] This structure cannot completely resist the situation of single-node flipping. There are two nodes among the four nodes. When these two nodes flip, it is possible to flip the logical state of the entire structure. In addition, similar to the DICE structure, it is also unable to resist the simultaneous flipping of multiple nodes. The interlocking structure will increase circuit delay and reduce data transmission rate.

[0058] In view of this, the present invention provides a latch and trigger that resist single-particle upset in a digital circuit. By reinforcing the design of an ordinary trigger circuit, the memory structure in the trigger can be restored to the correct level after being bombarded by a single particle at multiple nodes, so that it has the ability to resist the single-particle radiation effect and can work normally in a space radiation environment. In addition, the reinforced latch circuit reinforcement structure provided by the present invention is not on the critical path of the circuit, has a lower circuit delay, and can thus improve the data transmission rate of the circuit, and is suitable for high-speed and high-performance circuit design.

[0059] Next, the technical solution of the present invention is described in detail with reference to the accompanying drawings:

[0060] See also Figure 3 , Figure 3 The main circuit structure diagram of a latch and a trigger for resisting single particle upset in a digital circuit provided by the present invention is shown in FIG. Figure 3The overall circuit structure shown in is a trigger circuit structure, which is essentially a trigger that resists single-particle upsets and is composed of a latch circuit structure in the left half and a slave latch circuit structure in the right half; wherein the latch circuit in the left half is a latch that resists single-particle upsets provided by the present invention. In a trigger that resists single-particle upsets provided by the present invention, the circuit structure adopted by its latch is the same as the circuit structure of a latch that resists single-particle upsets provided by the present invention; the circuit structure of the slave latch is the same as the circuit structure of the latch, except that the latch and the slave latch have opposite working states; therefore, in order to concisely illustrate the technical solution of the present invention, in a specific embodiment, Figure 3 The trigger circuit structure shown in the figure is introduced as a whole, and the circuit structure of the latch is used as an example to introduce the scheme; in practical applications, Figure 3 The latch in can also be called the main-level latch. Similarly, the sub-circuit structure in the latch, the basic latch can also be called the main-level basic latch, the transmission gate can also be called the main-level transmission gate, and the detection circuit can also be called the main-level detection circuit.

[0061] exist Figure 3 In the embodiment, the latch 110 at least includes a basic latch 111, a transmission gate 113 and a detection circuit 112; the input end of the basic latch 111 is connected to the input end of the latch 110, the output end of the basic latch 111 is connected to the input end of the transmission gate 113, the output end of the transmission gate 113 is connected to the output end of the latch 110, the input end of the detection circuit 112 is connected to the basic latch 110, and the output end of the detection circuit 112 is connected to the transmission gate 113.

[0062] The latch 110 uses the detection signal of the detection circuit 112 to determine the level flip state of the basic latch 111, and generates a control signal for controlling the latch 110 based on the level flip state of the basic latch 111; the output signal of the latch 110 is used as the input signal of the slave latch 120. Among them, the detection circuit 112 is a reinforced circuit structure of the latch 110; the working state of the latch 110 is opposite to that of the slave latch 120; that is, when the latch 110 is in a transparent state, the slave latch 120 is in a latched state; when the latch 110 is in a latched state, the slave latch 120 is in a transparent state; wherein the latch transparent state is pre-charged in the transmission stage, and the latched state is the calculation evaluation stage.

[0063] Based on this, the present invention provides a latch for resisting single-particle flip in a digital circuit, which is configured to include at least a basic latch, a transmission gate and a detection circuit; the input end of the basic latch is connected to the input end of the latch, the output end of the basic latch is connected to the input end of the transmission gate, the output end of the transmission gate is connected to the output end of the latch, the input end of the detection circuit is connected to the basic latch, and the output end of the detection circuit is connected to the transmission gate; the latch uses a detection signal of the detection circuit to judge the level flip state of the basic latch, and generates a control signal for controlling the output of the latch based on the level flip state of the basic latch; the output signal of the latch is used as the input signal of the slave latch; thereby, the latch structure can be restored to the correct level after being bombarded by single particles at multiple nodes, and the resistance to single-particle radiation effects is improved, so that it has the resistance to single-particle radiation effects and can work normally in a space radiation environment; the problem that the latch structure in the prior art cannot resist single-particle flips at multiple nodes in the digital circuit is solved. Furthermore, the detection circuit in the latch circuit proposed in the present invention is not on the critical path of the circuit, and therefore has a lower circuit delay, can improve the data transmission rate of the circuit, and is suitable for high-speed and high-performance circuit design.

[0064] Preferably, the basic latch 111 may include: a first PMOS tube, a second PMOS tube, a third PMOS tube, a sixth PMOS tube, a fourteenth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a sixth NMOS tube and a fourteenth NMOS tube; the transmission gate includes: a fourth PMOS tube, a fifth PMOS tube, a fourth NMOS tube and a fifth NMOS tube.

[0065] Specifically, the following methods can be used to connect the various MOS tubes: the source of the first PMOS tube is connected to the source of the third PMOS tube, the drain is connected to the second signal terminal b1, and the gate is connected to the first signal terminal b0; the source of the second PMOS tube is connected to the drain of the third PMOS tube, the drain is connected to the first signal terminal b0, and the gate is connected to the second signal terminal b1; the gate of the third PMOS tube is connected to the clock anti-signal terminal; the gate of the sixth PMOS tube is connected to the second signal terminal b1, the source is connected to the power supply terminal, and the drain is connected to the third signal terminal b1N; the gate of the fourteenth PMOS tube is connected to the clock signal terminal, the drain is connected to the input terminal of the latch, and the source is connected to the first signal terminal b0.

[0066] The drain of the first NMOS tube is connected to the second signal terminal b1, the source is connected to the source of the third NMOS tube, and the gate is connected to the first signal terminal b0; the source of the second NMOS tube is connected to the drain of the third NMOS tube, the drain is connected to the first signal terminal b0, and the gate is connected to the second signal terminal b1; the gate of the third NMOS tube is connected to the clock signal terminal; the gate of the sixth NMOS tube is connected to the second signal terminal b1, the source is grounded, and the drain is connected to the third signal terminal b1N; the gate of the fourteenth NMOS tube is connected to the clock anti-signal terminal, the drain is connected to the input terminal of the latch, and the source is connected to the first signal terminal b0.

[0067] The gate of the fourth PMOS tube is connected to the fifth signal terminal E1N, the drain is connected to the third signal terminal b1N, and the source is connected to the input terminal of the slave latch; the gate of the fifth PMOS tube is connected to the fourth signal terminal E1, the drain is connected to the second signal terminal b1, and the source is connected to the input terminal of the slave latch; the gate of the fourth NMOS tube is connected to the fourth signal terminal E1, the drain is connected to the third signal terminal b1N, and the source is connected to the input terminal of the slave latch; the gate of the fifth NMOS tube is connected to the fifth signal terminal E1N, the drain is connected to the second signal terminal b1, and the source is connected to the input terminal of the slave latch.

[0068] The following is an example of the circuit structure corresponding to the detection circuit in the reinforcement circuit of the latch. As an example, a latch of the present invention that resists single-particle flipping in a digital circuit adopts two types of detection circuit structures to form two high-speed radiation-resistant reinforcement latches, which are respectively implemented by different detection circuits and transmission modules. The following is an example of the latch. It should be noted that when the detection circuits (the first detection circuit and the second detection circuit) shown in the following two methods are applied to the slave latch, the input clock signal is inverted and the corresponding input is sufficient, and the connection method of other ports in the slave latch is the same as the connection method of the detection circuit in the latch.

[0069] Please refer to Figures 4 to 5 , Figure 4 A schematic diagram of the first detection circuit structure of a latch and a trigger for resisting single-particle upset in a digital circuit provided by the present invention; Figure 5A schematic diagram of the second detection circuit structure of a latch and a trigger that resists single-particle upset in a digital circuit provided by the present invention. After the above two detection circuit structures are respectively applied to a latch and a trigger that resists single-particle upset in a digital circuit provided by the present invention, both can realize that the latch structure (memory structure) in the trigger can be restored to the correct level after being bombarded by multi-node single particles, so that it has the ability to resist the single-particle radiation effect and can work normally in a space radiation environment; and it is not on the critical path of the circuit, has a lower circuit delay, and can thus improve the data transmission rate of the circuit, and is suitable for high-speed and high-performance circuit design.

[0070] Method 1: Figure 4 In the embodiment, the first detection circuit 1121 may include a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube and a thirteenth NMOS tube.

[0071] Specifically, the following methods can be used to connect the various MOS tubes: the drain of the seventh PMOS tube is connected to the third signal terminal b1N, the gate is connected to the clock inverse signal terminal, and the source is connected to the drain of the eighth PMOS tube; the gate of the eighth PMOS tube is connected to the first signal terminal b0, and the source is connected to the drain of the ninth PMOS tube; the gate of the ninth PMOS tube is connected to the clock inverse signal terminal, the source is connected to the power supply terminal, and the drain is connected to the seventh signal terminal C1; the gate of the tenth PMOS tube is connected to the clock signal terminal, the source is connected to the power supply terminal, and the drain is connected to the drain of the eleventh PMOS tube and the fourth signal terminal E1; the gate of the eleventh PMOS tube is connected to the first signal terminal b0; the drain of the twelfth PMOS tube is connected to the fourth signal terminal E1, and the gate is connected to the seventh signal terminal C1; the gate of the thirteenth PMOS tube is connected to the fourth signal terminal E1, the source is connected to the power supply terminal, and the drain is connected to the fifth signal terminal E1N.

[0072] The drain of the seventh NMOS tube is connected to the third signal terminal b1N, the gate is connected to the clock signal terminal, and the source is connected to the source of the seventh PMOS tube; the drain of the eighth NMOS tube is connected to the drain of the eighth PMOS tube, the gate is connected to the first signal terminal b0, and the source is connected to the drain of the ninth NMOS tube; the gate of the ninth NMOS tube is connected to the clock signal terminal, the source is grounded, and the drain is connected to the sixth signal terminal A1; the gate of the tenth NMOS tube is connected to the clock signal terminal, the source is grounded, and the drain is connected to the source of the eleventh NMOS tube; the gate of the eleventh NMOS tube is connected to the sixth signal terminal A1, and the drain is connected to the source of the eleventh PMOS tube; the source of the twelfth NMOS tube is connected to the drain of the tenth NMOS tube, the gate is connected to the first signal terminal b0, and the drain is connected to the source of the twelfth PMOS tube; the gate of the thirteenth NMOS tube is connected to the fourth signal terminal E1, the source is grounded, and the drain is connected to the fifth signal terminal E1N.

[0073] The latch of the detection circuit using method 1 works as follows:

[0074] When the latch is in a transparent state, it may include: the tenth PMOS tube in the first detection circuit 1121 is turned on, the tenth NMOS tube is turned off, the level output to the fourth signal terminal E1 node is high level, and the level output to the fifth signal terminal E1N node is low level; the third PMOS tube and the third NMOS tube in the basic latch are turned off, the seventh PMOS tube and the seventh NMOS tube are turned off, the ninth PMOS tube and the ninth NMOS tube are turned on, the sixth signal terminal A1 node is low level, and the seventh signal terminal C1 node is high level.

[0075] exist Figure 4 In the embodiment, the output signal terminal of the first detection circuit 1121 is connected to the fourth signal terminal E1 and the fifth signal terminal E1N; the input signal terminals are the second signal terminal b1, the third signal terminal b1N, the clock inverted signal terminal clkb and the clock signal terminal clkbb. It should be noted that E1 and E1N are inverted signal ports to each other, that is, when E1 is 0, E1N is 1; when E1 is 1, E1N is 0. Similarly, b1 and b1N are inverted signal ports to each other, clkb and clkbb are inverted signal ports to each other; and the signal ports involved in other paragraphs or drawings of the present invention, b3 and b3N are inverted signal ports to each other, E2 and E2N are inverted signal ports to each other, A2 and A2N are inverted signal ports to each other, and C2 and C2N are inverted signal ports to each other.

[0076] Preferably, when the latch is in a latched state, it may include: the ninth PMOS tube and the ninth NMOS tube in the first detection circuit 1121 are turned off, the seventh PMOS tube and the seventh NMOS tube are turned on, the tenth PMOS tube is turned off, and the tenth NMOS tube is turned on.

[0077] When the first signal terminal b0 in the basic latch is 1 and the second signal terminal b1 is 0; if no single-particle flip occurs, the latch output is the third signal terminal b1N; if a single-particle flip occurs at the first signal terminal b0 and / or the second signal terminal b1 node, the latch output is the electrical signal corresponding to the second signal terminal b1.

[0078] When the first signal terminal b0 in the basic latch is 1 and the second signal terminal b1 is 0; if no single-particle flip occurs, the latch output is the third signal terminal b1N; if a single-particle flip occurs at the first signal terminal b0 and / or the second signal terminal b1 node, the latch output is the electrical signal corresponding to the second signal terminal b1.

[0079] Specifically, the working principle of method 1 is as follows:

[0080] (1) Transparent state (clock clk is low level)

[0081] When the latch is in a transparent state, clkbb is low, MP10 is on, MN10 is off, E1 node is pulled up to a high level, EN1 output is low, so MP4 and MN4 are on, MP5 and MN5 are off, the detection circuit has no effect on the output of the latch, and the working state is equivalent to an ordinary latch; in the latch, since clkbb is low, the reverse clock signal clkb is high, MP3 and MN3 are off, the input signal IN is transmitted to b0 and then reaches the b1 node through an inverter and then passes through an inverter as the output OUT of the main stage, and MP7 and MN7 are turned off when clkbb is low, so the value of the b1N node will not be transmitted to the A1 and C1 nodes, MP9 and MN9 are on, MP14 and MN14 are on, so the A1 node is pulled down to a low level, and the C1 node is pulled up to a high level.

[0082] (2) Latched state (clock clk is high level)

[0083] When the latch is in the latched state, clkbb is high. MP9 and MN9 are off, MP7 and MN7 are on, MP10 is off, and MN10 is on. The circuit may be in two working states:

[0084] ①When b0=1,b1=0:

[0085] a) When no single particle upset occurs, at this time, since b0=1, MP8 is turned off, MN8 is turned on, b1N=1 is transmitted to the A1 node, so A1=1, and C1 maintains its original high level unchanged, and its high level can be maintained by the leakage current of MP8. Since b0=1, b1=0, A1=1, C1=1, MP11 and MP12 in the two pull-down paths of the E1 node are both turned off, E1 remains unchanged at 1, E1N=0, so MP4 and MN4 are turned on, MP5 and MN5 are turned off, and the detection circuit at this time has no effect on the output. The circuit output OUT is connected to the b1N node, so when no single particle upset occurs, the latch working state is equivalent to an ordinary latch.

[0086] b) When a single particle flip occurs at any node b0 and / or b1 in the basic latch, it will cause an erroneous latch. The irradiated particles will generate a low-level pulse in the NMOS and a high-level pulse in the PMOS. The b0 and b1 nodes are connected to both the NMOS and the PMOS, so the b0 and b1 nodes may flip from 0 to 1 or from 1 to 0. When b0=1, b1=0, the latch circuit state flips, that is, b0=0, b1=1. b1N=0, MP8 is turned on, b1N=0 is transmitted to C1, b0=0, C1=0, A1=1, MP11, MN11 is turned on, and there is a pull-down path at the E node. The level of the E1 node is pulled down to 0. At this time, MP4 and MN4 are turned off, MP5 and MN5 are turned on, and the output is b1 instead of b1N, so the output of the circuit is still 1.

[0087] c) For the nodes in the first detection circuit 1121, since the E1 node and the C1 node are surrounded by PMOS, they will only flip from 0 to 1 under the action of a single particle, and the A1 node is surrounded by NMOS, so it will only flip from 1 to 0. Therefore, when b0=1, b1=0, A1=1, C1=1, only the A1 node may flip to 0, and the flip of the A1 node to 0 will only turn off MN11, and the E1 node still does not have a pull-down path. E1 is still equal to 1, so the output is still the output of its latch b1N node. If only b1N jumps from 1 to 0, the situation is similar to the above-mentioned flip of the A1 node from 1 to 0.

[0088] ②When b0=0,b1=1:

[0089] a) When no single particle upset occurs in the latch structure, since b0=0, MP8 is turned on and C1 is pulled down to a low level. Since b0=0, b1=1, C1=0, and A1=0, MN11 and MN12 in the two pull-down paths of the E1 node are both turned off, E1 remains unchanged at 1, E1N=0, MP11 is turned on, and the E1 node is maintained at a high level, so MP4 and MN4 are turned on, and MP5 and MN5 are turned off. At this time, the detection circuit has no effect on the output, and the latch circuit output is connected to the b1N node. Therefore, when no single particle upset occurs, the working state is equivalent to an ordinary latch.

[0090] b) When a single particle flip occurs at any node b0 and / or b1 in the latch, it will cause an erroneous latch. The irradiated particles will generate a low-level pulse in the NMOS and a high-level pulse in the PMOS. The b0 and b1 nodes are connected to both the NMOS and the PMOS, so the b0 and b1 nodes may flip from 0 to 1 or from 1 to 0. When b0=1, b1=0, the latch circuit state flips, that is, b0=1, b1=0. b1N=1, so MN8 is turned on, A1 is pulled up to 1, at this time b0=1, b1=0, A1=1, C1=0, MP12 and MN12 in the pull-down path of the E1 node are turned on, so E1=0, E1N=1, MP4 and MN4 are turned off, MP5 and MN5 are turned on, and the output is b1 instead of b1N, so the output of the latch circuit is still 0.

[0091] c) For the nodes in the first detection circuit 1121, since the E1 node and the C1 node are surrounded by PMOS, they will only flip from 0 to 1 in a single particle operation, and the A1 node is surrounded by NMOS, so it will only flip from 1 to 0. Therefore, when b0=0, b1=1, A1=0, C1=0, and the C1 node flips to 1, it will only turn off MP12, and the E1 node still does not have a pull-down path. E1 is still equal to 1, so the output is still the output of its latch b1N node. If only b1N jumps from 1 to 0, the situation is similar to the above-mentioned A1 node flipping from 1 to 0.

[0092] For the reinforcement circuit corresponding to the slave latch, it is high-level transparent and low-level latched, so all clock control signals are opposite to those of the master.

[0093] Method 2: Figure 5In the embodiment, the second detection circuit 1122 may include a twenty-ninth PMOS tube, a thirtieth PMOS tube, a thirty-first PMOS tube, a thirty-second PMOS tube, a thirty-third PMOS tube, a thirty-fourth PMOS tube, a thirty-fifth PMOS tube, a thirty-sixth PMOS tube, a thirty-seventh PMOS tube, a thirty-eighth PMOS tube, a thirty-ninth PMOS tube, a twenty-ninth NMOS tube, a thirtieth NMOS tube, a thirty-first NMOS tube, a thirty-second NMOS tube, a thirty-third NMOS tube, a thirty-fourth NMOS tube, a thirty-fifth NMOS tube, a thirty-sixth NMOS tube and a thirty-seventh NMOS tube.

[0094] Specifically, the source of the twenty-ninth PMOS tube can be connected to the power supply terminal, the gate can be connected to the clock signal terminal, and the drain can be connected to the source of the thirtieth PMOS tube; the gate of the thirtieth PMOS tube can be connected to the first signal terminal b0, the drain can be connected to the drain of the thirty-first NMOS tube, and the source can be connected to the thirteenth signal terminal A2; the gate of the thirty-first NMOS tube can be connected to the clock signal terminal, and the source can be grounded; the gate of the thirty-second PMOS tube can be connected to the thirteenth signal terminal A2, the source can be connected to the power supply terminal, and the drain can be connected to the fourteenth signal terminal A2N; the drain of the thirty-second NMOS tube can be connected to the fourteenth signal terminal A2N, the source can be grounded, and the gate can be connected to the thirteenth signal terminal A2 The source of the thirty-first PMOS tube is connected to the power supply terminal, the gate is connected to the clock inverse signal terminal, and the drain is connected to the drain of the thirtieth NMOS tube; the source of the thirtieth NMOS tube is connected to the fifteenth signal terminal C2, the gate is connected to the first signal terminal b0, and the source is connected to the drain of the twenty-ninth NMOS tube; the gate of the twenty-ninth NMOS tube is connected to the clock inverse signal terminal, and the source is grounded; the source of the thirty-third PMOS tube is connected to the power supply terminal, the gate is connected to the fifteenth signal terminal C2, and the drain is connected to the sixteenth signal terminal C2N; the source of the thirty-third NMOS tube is grounded, the gate is connected to the fifteenth signal terminal C2, and the drain is connected to the sixteenth signal terminal C2N.

[0095] The gate of the thirty-fourth PMOS tube is connected to the clock signal terminal, the source is connected to the power supply terminal, and the drain is connected to the fourth signal terminal E1; the source of the thirty-fifth PMOS tube is connected to the power supply terminal, the gate is connected to the thirteenth signal terminal A2, and the drain is connected to the source of the thirty-seventh PMOS tube; the gate of the thirty-seventh PMOS tube is connected to the fifteenth signal terminal C2, and the drain is connected to the fourth signal terminal E1; the source of the thirty-sixth PMOS tube is connected to the power supply terminal, the gate is connected to the fourteenth signal terminal A2N, and the drain is connected to the source of the thirty-eighth PMOS tube; the gate of the thirty-eighth PMOS tube is connected to the sixteenth signal terminal C2N, and the drain is connected to the fourth signal terminal E1; the source of the thirty-ninth PMOS tube is connected to the power supply terminal, the gate is connected to the fourth signal terminal E1, and the drain is connected to the fifth signal terminal E1N; the drain of the thirty-fourth NMOS tube is connected to the source of the thirty-fifth NMOS tube, the gate is connected to the clock signal terminal, and the source is grounded; the drain of the thirty-fifth NMOS tube is connected to the source of the thirty-sixth NMOS tube, the gate is connected to the fourteenth signal terminal A2N; the gate of the thirty-sixth NMOS tube is connected to the fifteenth signal terminal C2, and the drain is connected to the fourth signal terminal E1; the drain of the thirty-seventh NMOS tube is connected to the fifth signal terminal E1N, the source is grounded, and the gate is connected to the fourth signal terminal E1.

[0096] Preferably, when the latch is in the latched state, it may include: the twenty-ninth PMOS tube and the twenty-ninth NMOS tube in the second detection circuit 1122 are turned off, and the thirty-first PMOS tube and the thirty-first NMOS tube are turned on.

[0097] When the first signal terminal b0 in the basic latch is 1 and the second signal terminal b1 is 0; if no single-particle flip occurs, the latch output is the third signal terminal b1N; if a single-particle flip occurs at the first signal terminal b0 and / or the second signal terminal b1 node, the latch output is the electrical signal corresponding to the second signal terminal b1.

[0098] When the first signal terminal b0 in the basic latch is 0 and the second signal terminal b1 is 1; if no single-particle flip occurs, the latch output is the third signal terminal b1N; if a single-particle flip occurs at the first signal terminal b0 and / or the second signal terminal b1 node, the latch output is the electrical signal corresponding to the second signal terminal b1.

[0099] Specifically, the latch of the detection circuit of the second mode is adopted, the output signals of the second detection circuit 1122 are E1 and E1N; the input signal terminals are the second signal terminal b1, the third signal terminal b1N, the clock inverted signal terminal clkb and the clock signal terminal clkbb; its working principle is:

[0100] (1) Transparent state (clock clk is low level)

[0101] When the basic latch is in a transparent state, clkbb is at a low level, MP34 is turned on, MN34 is turned off, the E1 node is pulled up to a high level, and the E1N output is at a low level, so MP4 and MN4 are turned on, MP5 and MN5 are turned off. At this time, the second detection circuit has no effect on the output of the latch, and the working state of the latch is equivalent to that of an ordinary latch; since clkbb is at a low level, the reverse clock signal clkb is at a high level, MP3 and MN3 are turned off, and the input signal is transmitted to b0 and then passes through an inverter to reach the b1 node, and then passes through an inverter and a transmission gate as the output of the main stage.

[0102] Since MP29 and MN29 are turned on and MP31 and MN31 are turned off, the A1 node is pulled up to a high level 1 and the C1 node is pulled down to a low level 0.

[0103] (2) Latched state (clock clk is high level)

[0104] When the latch is in the latched state, clkbb is at a high level, MP29 and MN29 are turned off, and MP31 and MN31 are turned on.

[0105] ①When b0=1,b1=0:

[0106] a) When the latch does not experience a single-particle upset, since b0=1, MN30 is turned on, C1 is pulled up to a high level, C1=1, C1N=0, A1=1, A1N=0, so MN35 in the pull-down path of node E is turned off, and MP36 and MP38 in the pull-up path are both turned on, so E1=1, E1N=0, at this time MP4 and MN4 are turned on, MP5 and MN5 are turned off, and the second detection circuit has no effect on the output of the latch, so when no single-particle upset occurs, the working state of the latch is equivalent to that of an ordinary latch, and the output level is b1N=1.

[0107] b) When a single particle flip occurs at any node b0 and / or b1 in the latch, it will cause an erroneous latch. The irradiated particles will generate a low-level pulse in the NMOS and a high-level pulse in the PMOS. The b0 and b1 nodes are connected to both the NMOS and the PMOS, so the b0 and b1 nodes may flip from 0 to 1 or from 1 to 0. When b0=1, b1=0, the state of the latch circuit flips, that is, b0=0, b1=1, so MP30 is turned on, A1 is pulled down to 0, A1=0, A1N=1, C1=1, C1N=0, MP36 and MP37 in the pull-up path of the E node are turned off, MN36 and MN35 in the pull-down path are turned on, E1=0, E1N=1, MP4 and MN4 are turned off, MP5 and MN5 are turned on, and the output is b1 instead of b1N, so the latch circuit still outputs b1=1.

[0108] c) For the nodes in the second detection circuit 1122, the A1 node is surrounded by PMOS and therefore only a 0 to 1 pulse will occur; the C1 node is surrounded by NMOS and therefore only a 1 to 0 pulse will occur; therefore, when b0=1, b1=0, A1=1, C1=1, and only the C1 node may flip to 0; however, since MN30 is turned on, C1 will soon be pulled back to a high level, and eventually the output of the latch circuit returns to normal.

[0109] ②When b0=0,b1=1:

[0110] a) When no single particle upset occurs, since b0=0, MP30 is turned on, MN30 is turned off, A1 is pulled down to a low level, C1=0, C1N=1, A1=0, A1N=1, MN36 in the pull-down path of node E is turned off, and MP35 and MP37 in the pull-up path are both turned on, so E1=1, EN=0, MP4 and MN4 are turned on, MP5 and MN5 are turned off, and the second detection circuit has no effect on the output at this time, so when no single particle upset occurs, the working state of the latch is equivalent to an ordinary latch.

[0111] b) When a single particle flip occurs at any node b0 and / or b1 in the latch, it will cause an erroneous latch. The irradiated particles will generate a low-level pulse in the NMOS and a high-level pulse in the PMOS. The b0 and b1 nodes are connected to both the NMOS and the PMOS, so the b0 and b1 nodes may flip from 0 to 1 or from 1 to 0. When b0=0, b1=1, the circuit state flips, that is, b0=1, b1=0, MN30 is turned on, C1 is pulled up to 1, A1=0, A1N=1, C1=1, C1N=0, MP36 and MP37 in the pull-up path of the E node are turned off, MN35 and MN36 in the pull-down path are turned on, E1=0, E1N=1, MP4 and MN4 are turned off, MP5 and MN5 are turned on, and the output is b1 instead of b1N, so the latch circuit still outputs b1=0.

[0112] c) For the nodes in the second detection circuit 1122, the A1 node is surrounded by PMOS and therefore only a 0 to 1 pulse will occur; the C1 node is surrounded by NMOS and therefore only a 1 to 0 pulse will occur; therefore, when b0=0, b1=1, A1=0, C1=0, only the A1 node may flip to 1, but since MP30 is turned on, A1 will soon be pulled back to a low level, and eventually the output of the latch circuit returns to normal.

[0113] For the reinforcement circuit corresponding to the slave latch, it is high-level transparent and low-level latched, so all clock control signals are opposite to those of the master.

[0114] Based on this, the present invention provides a latch that resists single-particle flips in digital circuits, and can use the signal of the detection circuit to determine whether the latch has a level state flip. If no single-particle flip occurs, the latch outputs data normally; if a single-particle flip occurs, the flip level is inverted before outputting. This structure can still output the correct logic level after a single-particle flip occurs, so it has good resistance to single-particle flip events. This structure has few sensitive node pairs, so it has good resistance to multi-node flips. At the same time, since the detection circuit as a latch reinforcement structure is located outside the critical path of data transmission, it has a high transmission rate characteristic and is suitable for the design of radiation-resistant reinforcement circuits for advanced processes; it is also suitable for single-particle reinforcement designs of latch circuits.

[0115] In a second aspect, the present invention provides a trigger for resisting single-particle upset in a digital circuit. Figure 3 . Figure 3 The entire circuit structure shown is a circuit structure corresponding to a trigger that resists single-particle flip-flops in digital circuits. In practical applications, Figure 3 The latch shown in the left half can also be called a master latch. The trigger is a rising edge master-slave latch structure, which consists of a latch circuit cascaded with transmission gates and a slave latch circuit. The two-stage structure is consistent. The detection circuit (particle flip detection circuit) outputs a signal to determine whether a particle flip occurs in the latch circuit, and the master-slave latch output signal is determined by the detection circuit output signal; and the slave detection circuit outputs a signal to determine whether a particle flip occurs in the corresponding circuit of the slave latch, and the slave detection circuit outputs a signal to determine the master-slave latch output signal.

[0116] The present invention provides a detection circuit in a latch and a trigger that resists single-particle flip-flops in a digital circuit. The detection circuit has the same structure as a slave detection circuit, and the difference lies in that the input clock signals of the detection circuit and the slave detection circuit are opposite, such as: when a clock signal is input to the first clock signal input terminal of the detection circuit, a clock inverse signal is input to the first clock signal input terminal of the slave detection circuit; when a clock inverse signal is input to the second clock signal input terminal of the detection circuit, a clock signal is input to the second clock signal input terminal of the slave detection circuit.

[0117] It should be noted that the detection circuit corresponding to the trigger is pre-charged during the transparent transmission stage of the latch and the latch state is evaluated; the single-particle upset detection circuit can identify whether a single-particle upset occurs in the latch and issue an alarm signal, providing conditions for architectural-level reinforcement; the latch output value is determined by the output level of the detection circuit. When no single-particle upset is detected, the latch outputs normally. When a single-particle upset is detected, the current level of the latch is inverted and the output is taken.

[0118] exist Figure 3 In the present invention, a trigger for resisting single-particle upset in a digital circuit is provided, and the trigger 100 at least includes a latch 110 and a slave latch 120.

[0119] The input terminal of the latch 110 is connected to the input terminal IN of the flip-flop 100 , the output terminal of the latch 110 is connected to the input terminal of the slave latch 120 , and the output terminal of the slave latch 120 is connected to the output terminal OUT of the flip-flop 100 .

[0120] The latch 110 includes at least a detection circuit 112 and a basic latch 111; the trigger 100 uses the detection signal of the detection circuit 112 to determine the level flip state of the basic latch 111, and generates a control signal for controlling the output of the latch 110 based on the level flip state of the basic latch 111.

[0121] The slave latch 120 includes at least a slave detection circuit 122 and a slave basic latch 121; the trigger 100 uses the detection signal of the slave detection circuit 122 to determine the level flip state of the slave basic latch 121, and generates a control signal for controlling the output of the slave latch 120 based on the level flip state of the slave basic latch 121.

[0122] Preferably, in the trigger for resisting single particle upset in a digital circuit provided by the present invention, the latch 110 may include a transmission gate 113 , and the slave latch 120 may further include a slave transmission gate 123 .

[0123] Specifically, the input end of the basic latch 111 is connected to the input end IN of the trigger 100, and the output end is connected to the input end of the transmission gate 113; the output end of the transmission gate 113 is connected to the input end of the slave latch 121, the output end of the slave latch 121 is connected to the input end of the slave transmission gate 123, and the output end of the slave transmission gate 123 is connected to the output end OUT of the trigger 100. The basic latch 111 is used to latch the storage level state of the master reinforcement circuit corresponding to the latch 110, and the slave basic latch 121 is used to latch the storage level state of the slave reinforcement circuit corresponding to the slave latch 120.

[0124] Preferably, the slave-level basic latch 121 may include: a fifteenth PMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube, a twentieth PMOS tube, a twenty-eighth PMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a seventeenth NMOS tube, a twentieth NMOS tube and a twenty-eighth NMOS tube; the slave-level transmission gate may include: an eighteenth PMOS tube, a nineteenth PMOS tube, an eighteenth NMOS tube and a nineteenth NMOS tube.

[0125] Specifically, the following methods can be used to connect the various MOS tubes: the source of the fifteenth PMOS tube is connected to the source of the seventeenth PMOS tube, the drain is connected to the ninth signal terminal b3, and the gate is connected to the eighth signal terminal b2; the source of the sixteenth PMOS tube is connected to the drain of the seventeenth PMOS tube, the drain is connected to the eighth signal terminal b2, and the gate is connected to the ninth signal terminal b3; the gate of the seventeenth PMOS tube is connected to the clock signal terminal; the gate of the twentieth PMOS tube is connected to the ninth signal terminal b3, the source is connected to the power supply terminal, and the drain is connected to the tenth signal terminal b3N; the gate of the twenty-eighth PMOS tube is connected to the clock anti-signal terminal, the drain is connected to the input terminal of the slave-level basic latch, and the source is connected to the eighth signal terminal b2; wherein the drain of the twenty-eighth PMOS tube is the input terminal of the slave-level reinforcement circuit corresponding to the slave-level latch.

[0126] The drain of the fifteenth NMOS tube is connected to the ninth signal terminal b3, the source is connected to the source of the seventeenth NMOS tube, and the gate is connected to the eighth signal terminal b2; the source of the sixteenth NMOS tube is connected to the drain of the seventeenth NMOS tube, the drain is connected to the eighth signal terminal b2, and the gate is connected to the ninth signal terminal b3; the gate of the seventeenth NMOS tube is connected to the clock inverse signal terminal; the gate of the twentieth NMOS tube is connected to the ninth signal terminal b3, the source is grounded, and the drain is connected to the tenth signal terminal b3N; the gate of the twenty-eighth NMOS tube is connected to the clock signal terminal, the drain is connected to the input terminal of the slave basic latch, and the source is connected to the input terminal of the slave latch.

[0127] The gate of the eighteenth PMOS tube is connected to the twelfth signal terminal E2N, the drain is connected to the tenth signal terminal b3N, and the source is connected to the OUT terminal; the gate of the nineteenth PMOS tube is connected to the eleventh signal terminal E2, the drain is connected to the ninth signal terminal b3, and the source is connected to the OUT terminal; the gate of the eighteenth NMOS tube is connected to the eleventh signal terminal E2, the drain is connected to the tenth signal terminal b3N, and the source is connected to the OUT terminal; the gate of the nineteenth NMOS tube is connected to the twelfth signal terminal E2N, the drain is connected to the ninth signal terminal b3, and the source is connected to the OUT terminal.

[0128] It should be noted that the circuit structure and working principle of the latch in the trigger are the same as the circuit structure and working principle of the latch for resisting single particle upset in a digital circuit described in the first aspect, and are not described in detail here. The working principle of the slave latch in the trigger is opposite to the working principle of the latch for resisting single particle upset in a digital circuit described in the first aspect, that is, by inputting a clock signal opposite to that in the latch into the slave latch, the slave latch circuit outputs a correct level signal when resisting particle collision in the slave latch.

[0129] Based on this, the trigger provided by the present invention for resisting single-particle flip-flops in digital circuits can also achieve the ability for the latch and / or slave latch to recover to the correct level after being bombarded by multi-node single particles, thereby improving the trigger circuit's resistance to single-particle radiation effects.

[0130] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0131] Although the present invention has been described in conjunction with specific features and embodiments thereof, it is apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present invention. Accordingly, this specification and the accompanying drawings are merely exemplary illustrations of the present invention as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present invention. Obviously, those skilled in the art may make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, the present invention is intended to include such modifications and variations if they fall within the scope of the claims of the present invention and their equivalents.

Claims

1. A latch for resisting single-particle upset in a digital circuit, characterized in that: The latch at least includes a basic latch, a transmission gate and a detection circuit; The input end of the basic latch is connected to the input end of the latch, the output end of the basic latch is connected to the input end of the transmission gate, the output end of the transmission gate is connected to the output end of the latch, the input end of the detection circuit is connected to the basic latch, and the output end of the detection circuit is connected to the transmission gate; The latch determines the level inversion state of the basic latch by using the detection signal of the detection circuit, and generates a control signal for controlling the output of the latch based on the level inversion state of the basic latch.

2. The latch according to claim 1, wherein: The detection circuit includes a first detection circuit, and the first detection circuit includes a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube and a thirteenth NMOS tube; The drain of the seventh PMOS tube is connected to the third signal terminal, the gate of the seventh PMOS tube is connected to the clock anti-signal terminal, and the source of the seventh PMOS tube is connected to the drain of the eighth PMOS tube; the gate of the eighth PMOS tube is connected to the first signal terminal, and the source of the eighth PMOS tube is connected to the drain of the ninth PMOS tube; the gate of the ninth PMOS tube is connected to the clock anti-signal terminal, the source of the ninth PMOS tube is connected to the power supply terminal, and the drain of the ninth PMOS tube is connected to the seventh signal terminal; the gate of the tenth PMOS tube is connected to the first signal terminal, and the source of the eighth PMOS tube is connected to the drain of the ninth PMOS tube; the gate of the ninth PMOS tube is connected to the clock anti-signal terminal, the source of the ninth PMOS tube is connected to the power supply terminal, and the drain of the ninth PMOS tube is connected to the seventh signal terminal; the gate of the tenth PMOS tube is connected to the The first PMOS tube is connected to the clock signal terminal, the source of the tenth PMOS tube is connected to the power supply terminal, the drain of the tenth PMOS tube is connected to the drain of the eleventh PMOS tube and the fourth signal terminal; the gate of the eleventh PMOS tube is connected to the first signal terminal; the drain of the twelfth PMOS tube is connected to the fourth signal terminal, and the gate of the twelfth PMOS tube is connected to the seventh signal terminal; the gate of the thirteenth PMOS tube is connected to the fourth signal terminal, the source of the thirteenth PMOS tube is connected to the power supply terminal, and the drain of the thirteenth PMOS tube is connected to the fifth signal terminal; The drain of the seventh NMOS tube is connected to the third signal terminal, the gate of the seventh NMOS tube is connected to the clock signal terminal, and the source of the seventh NMOS tube is connected to the source of the seventh PMOS tube; the drain of the eighth NMOS tube is connected to the drain of the eighth PMOS tube, the gate of the eighth NMOS tube is connected to the first signal terminal, and the source of the eighth NMOS tube is connected to the drain of the ninth NMOS tube; the gate of the ninth NMOS tube is connected to the clock signal terminal, the gate source of the ninth NMOS tube is grounded, and the drain of the ninth NMOS tube is connected to the sixth signal terminal; the gate of the tenth NMOS tube is connected to the clock signal terminal, and the gate of the tenth NMOS tube is connected to the clock signal terminal. The source of the NMOS tube is grounded, and the drain of the tenth NMOS tube is connected to the source of the eleventh NMOS tube; the gate of the eleventh NMOS tube is connected to the sixth signal terminal, and the drain of the eleventh NMOS tube is connected to the source of the eleventh PMOS tube; the source of the twelfth NMOS tube is connected to the drain of the tenth NMOS tube, the gate of the tenth NMOS tube is connected to the first signal terminal, and the drain of the tenth NMOS tube is connected to the source of the twelfth PMOS tube; the gate of the thirteenth NMOS tube is connected to the fourth signal terminal, the source of the thirteenth NMOS tube is grounded, and the drain of the thirteenth NMOS tube is connected to the fifth signal terminal.

3. The latch according to claim 2, wherein: When the latch is in a transparent state, the method comprises: In the first detection circuit, the tenth PMOS tube is turned on, the tenth NMOS tube is turned off, the level output to the fourth signal terminal node is a high level, and the level output to the fifth signal terminal node is a low level; In the basic latch, the third PMOS tube and the third NMOS tube are turned off, the seventh PMOS tube and the seventh NMOS tube are turned off, the ninth PMOS tube and the ninth NMOS tube are turned on, the fourteenth PMOS tube and the fourteenth NMOS tube are turned on, the sixth signal terminal node is at a low level, and the seventh signal terminal node is at a high level.

4. The latch according to claim 2, wherein: When the latch is in a latched state, the method comprises: In the first detection circuit, the ninth PMOS tube and the ninth NMOS tube are turned off, the seventh PMOS tube and the seventh NMOS tube are turned on, the tenth PMOS tube is turned off, and the tenth NMOS tube is turned on; When the first signal terminal in the basic latch is 1 and the second signal terminal is 0; if no single-particle upset occurs, the latch output is the third signal terminal; if a single-particle upset occurs at the first signal terminal and / or the second signal terminal node, the latch output is the electrical signal corresponding to the second signal terminal; When the first signal terminal in the basic latch is 1 and the second signal terminal is 0; if no single-particle flip occurs, the latch output is the third signal terminal; if a single-particle flip occurs at the first signal terminal and / or the second signal terminal node, the latch output is the electrical signal corresponding to the second signal terminal.

5. The latch according to claim 1, wherein: The detection circuit includes a second detection circuit, which includes a twenty-ninth PMOS tube, a thirtieth PMOS tube, a thirty-first PMOS tube, a thirty-second PMOS tube, a thirty-third PMOS tube, a thirty-fourth PMOS tube, a thirty-fifth PMOS tube, a thirty-sixth PMOS tube, a thirty-seventh PMOS tube, a thirty-eighth PMOS tube, a thirty-ninth PMOS tube, a twenty-ninth NMOS tube, a thirtieth NMOS tube, a thirty-first NMOS tube, a thirty-second NMOS tube, a thirty-third NMOS tube, a thirty-fourth NMOS tube, a thirty-fifth NMOS tube, a thirty-sixth NMOS tube and a thirty-seventh NMOS tube; The source of the 29th PMOS tube is connected to the power supply terminal, the gate of the 29th PMOS tube is connected to the clock signal terminal, and the drain of the 29th PMOS tube is connected to the source of the 30th PMOS tube; the gate of the 30th PMOS tube is connected to the first signal terminal, the drain of the 30th PMOS tube is connected to the drain of the 31st NMOS tube, and the source of the 30th PMOS tube is connected to the 13th signal terminal; the gate of the 31st NMOS tube is connected to the clock signal terminal, and the source of the 31st NMOS tube is grounded; the gate of the 32nd PMOS tube is connected to the 13th signal terminal, the source of the 32nd PMOS tube is connected to the power supply terminal, and the drain of the 32nd PMOS tube is connected to the 14th signal terminal; the drain of the 32nd NMOS tube is connected to the 14th signal terminal, the source of the 32nd NMOS tube is grounded, and the gate of the 32nd NMOS tube is connected to the 13th signal terminal; The source of the thirty-first PMOS tube is connected to the power supply terminal, the gate of the thirty-first PMOS tube is connected to the clock inverse signal terminal, and the drain of the thirty-first PMOS tube is connected to the drain of the thirtieth NMOS tube; the source of the thirtieth NMOS tube is connected to the fifteenth signal terminal, the gate of the thirtieth NMOS tube is connected to the first signal terminal, and the source of the thirtieth NMOS tube is connected to the drain of the twenty-ninth NMOS tube; the gate of the twenty-ninth NMOS tube is connected to the clock inverse signal terminal, and the source of the twenty-ninth NMOS tube is grounded; the source of the thirty-third PMOS tube is connected to the power supply terminal, the gate of the thirty-third PMOS tube is connected to the fifteenth signal terminal, and the drain of the thirty-third PMOS tube is connected to the sixteenth signal terminal; the source of the thirty-third NMOS tube is grounded, the gate of the thirty-third NMOS tube is connected to the fifteenth signal terminal, and the gate and drain of the thirty-third NMOS tube are connected to the sixteenth signal terminal; The gate of the thirty-fourth PMOS tube is connected to the clock signal terminal, the source of the thirty-fourth PMOS tube is connected to the power supply terminal, and the drain of the thirty-fourth PMOS tube is connected to the fourth signal terminal; the source of the thirty-fifth PMOS tube is connected to the power supply terminal, the gate of the thirty-fifth PMOS tube is connected to the thirteenth signal terminal, and the drain of the thirty-fifth PMOS tube is connected to the source of the thirty-seventh PMOS tube; the gate of the thirty-seventh PMOS tube is connected to the fifteenth signal terminal, and the drain is connected to the fourth signal terminal; the source of the thirty-sixth PMOS tube is connected to the power supply terminal, the gate of the thirty-sixth PMOS tube is connected to the fourteenth signal terminal, and the drain of the thirty-sixth PMOS tube is connected to the source of the thirty-eighth PMOS tube; the gate of the thirty-eighth PMOS tube is connected to the sixteenth signal terminal, and the drain is connected to the fourth signal terminal; The source of the MOS tube is connected to the power supply terminal, the gate of the thirty-ninth PMOS tube is connected to the fourth signal terminal, and the drain of the thirty-ninth PMOS tube is connected to the fifth signal terminal; the drain of the thirty-fourth NMOS tube is connected to the source of the thirty-fifth NMOS tube, the gate of the thirty-fourth NMOS tube is connected to the clock signal terminal, and the source of the thirty-fourth NMOS tube is grounded; the drain of the thirty-fifth NMOS tube is connected to the source of the thirty-sixth NMOS tube, and the gate of the thirty-fifth NMOS tube is connected to the fourteenth signal terminal; the gate of the thirty-sixth NMOS tube is connected to the fifteenth signal terminal, and the drain of the thirty-sixth NMOS tube is connected to the fourth signal terminal; the drain of the thirty-seventh NMOS tube is connected to the fifth signal terminal, the source of the thirty-seventh NMOS tube is grounded, and the gate of the thirty-seventh NMOS tube is connected to the fourth signal terminal.

6. The latch according to claim 5, wherein: When the latch is in a latched state, the method comprises: The twenty-ninth PMOS tube and the twenty-ninth NMOS tube in the second detection circuit are turned off, and the thirty-first PMOS tube and the thirty-first NMOS tube are turned on; When the first signal terminal in the basic latch is 1 and the second signal terminal is 0; if no single-particle upset occurs, the latch output is the third signal terminal; if a single-particle upset occurs at the first signal terminal and / or the second signal terminal node, the latch output is the electrical signal corresponding to the second signal terminal; When the first signal terminal in the basic latch is 0 and the second signal terminal is 1; if no single particle upset occurs, the latch output is the third signal terminal; if a single particle upset occurs at the first signal terminal and / or the second signal terminal node, the latch output is the electrical signal corresponding to the second signal terminal.

7. The latch according to claim 1, wherein: The basic latch includes: a first PMOS tube, a second PMOS tube, a third PMOS tube, a sixth PMOS tube, a fourteenth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a sixth NMOS tube and a fourteenth NMOS tube; the transmission gate includes: a fourth PMOS tube, a fifth PMOS tube, a fourth NMOS tube and a fifth NMOS tube; The source of the first PMOS tube is connected to the source of the third PMOS tube, the drain of the first PMOS tube is connected to the second signal terminal, and the gate of the first PMOS tube is connected to the first signal terminal; the source of the second PMOS tube is connected to the drain of the third PMOS tube, the drain of the second PMOS tube is connected to the first signal terminal, and the gate of the second PMOS tube is connected to the second signal terminal; the gate of the third PMOS tube is connected to the clock anti-signal terminal; the gate of the sixth PMOS tube is connected to the second signal terminal, the source of the sixth PMOS tube is connected to the power supply terminal, and the drain of the sixth PMOS tube is connected to the third signal terminal; the gate of the fourteenth PMOS tube is connected to the clock signal terminal, the drain of the fourteenth PMOS tube is connected to the input terminal of the latch, and the source of the fourteenth PMOS tube is connected to the first signal terminal; The drain of the first NMOS tube is connected to the second signal terminal, the source of the first NMOS tube is connected to the source of the third NMOS tube, and the gate of the first NMOS tube is connected to the first signal terminal; the source of the second NMOS tube is connected to the drain of the third NMOS tube, the drain of the second NMOS tube is connected to the first signal terminal, and the gate of the second NMOS tube is connected to the second signal terminal; the gate of the third NMOS tube is connected to the clock signal terminal; the gate of the sixth NMOS tube is connected to the second signal terminal, the source of the sixth NMOS tube is grounded, and the drain of the sixth NMOS tube is connected to the third signal terminal; the gate of the fourteenth NMOS tube is connected to the clock anti-signal terminal, the drain of the fourteenth NMOS tube is connected to the input terminal of the latch, and the source of the fourteenth NMOS tube is connected to the first signal terminal; The gate of the fourth PMOS tube is connected to the fifth signal terminal, the drain of the fourth PMOS tube is connected to the third signal terminal, and the source of the fourth PMOS tube is connected to the input terminal of the slave-level latch; the gate of the fifth PMOS tube is connected to the fourth signal terminal, the drain of the fifth PMOS tube is connected to the second signal terminal, and the source of the fifth PMOS tube is connected to the input terminal of the slave-level latch; the gate of the fourth NMOS tube is connected to the fourth signal terminal, the drain of the fourth NMOS tube is connected to the third signal terminal, and the source of the fourth NMOS tube is connected to the input terminal of the slave-level latch; the gate of the fifth NMOS tube is connected to the fifth signal terminal, the drain of the fifth NMOS tube is connected to the second signal terminal, and the source of the fifth NMOS tube is connected to the input terminal of the slave-level latch.

8. A trigger for resisting single-event upset in a digital circuit, characterized in that: The trigger includes at least a latch and a slave latch; The input end of the latch is connected to the input end of the trigger, the output end of the latch is connected to the input end of the slave latch, and the output end of the slave latch is connected to the output end of the trigger; The latch at least includes a detection circuit and a basic latch; the trigger uses the detection signal of the detection circuit to determine the level flip state of the basic latch, and generates a control signal for controlling the output of the latch based on the level flip state of the basic latch; The slave latch at least comprises a slave detection circuit and a slave basic latch; The trigger determines the level inversion state of the slave basic latch by using the detection signal of the slave detection circuit, and generates a control signal for controlling the output of the slave latch based on the level inversion state of the slave basic latch.

9. The trigger according to claim 8, characterized in that The latch further comprises a transmission gate, and the slave latch further comprises a slave transmission gate; The input end of the basic latch is connected to the input end of the trigger, and the output end of the basic latch is connected to the input end of the transmission gate; the output end of the transmission gate is connected to the input end of the slave basic latch, the output end of the slave basic latch is connected to the input end of the slave transmission gate, and the output end of the slave transmission gate is connected to the output end of the trigger; The basic latch is used to latch the storage level state of the latch; The slave basic latch is used to latch the storage level state of the slave latch.

10. The trigger according to claim 9, characterized in that The slave-level basic latch includes: a fifteenth PMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube, a twentieth PMOS tube, a twenty-eighth PMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a seventeenth NMOS tube, a twentieth NMOS tube and a twenty-eighth NMOS tube; the slave-level transmission gate includes: an eighteenth PMOS tube, a nineteenth PMOS tube, an eighteenth NMOS tube and a nineteenth NMOS tube; The source of the fifteenth PMOS tube is connected to the source of the seventeenth PMOS tube, the drain of the fifteenth PMOS tube is connected to the ninth signal terminal, and the gate of the fifteenth PMOS tube is connected to the eighth signal terminal; the source of the sixteenth PMOS tube is connected to the drain of the seventeenth PMOS tube, the drain of the sixteenth PMOS tube is connected to the eighth signal terminal, and the gate of the sixteenth PMOS tube is connected to the ninth signal terminal; the gate of the seventeenth PMOS tube is connected to the clock signal terminal; the gate of the 20th PMOS tube is connected to the ninth signal terminal, the source of the 20th PMOS tube is connected to the power supply terminal, and the drain of the 20th PMOS tube is connected to the tenth signal terminal; the gate of the twenty-eighth PMOS tube is connected to the clock anti-signal terminal, the drain of the twenty-eighth PMOS tube is connected to the input terminal of the slave basic latch, and the source of the twenty-eighth PMOS tube is connected to the eighth signal terminal; The drain of the fifteenth NMOS tube is connected to the ninth signal terminal, the source of the fifteenth NMOS tube is connected to the source of the seventeenth NMOS tube, and the gate of the fifteenth NMOS tube is connected to the eighth signal terminal; the source of the sixteenth NMOS tube is connected to the drain of the seventeenth NMOS tube, the drain of the sixteenth NMOS tube is connected to the eighth signal terminal, and the gate of the sixteenth NMOS tube is connected to the ninth signal terminal; the gate of the seventeenth NMOS tube is connected to the clock inverse signal terminal; the gate of the 20th NMOS tube is connected to the ninth signal terminal, the source of the 20th NMOS tube is grounded, and the drain of the 20th NMOS tube is connected to the tenth signal terminal; the gate of the 28th NMOS tube is connected to the clock signal terminal, the drain of the 28th NMOS tube is connected to the input terminal of the slave basic latch, and the source of the 28th NMOS tube is connected to the eighth signal terminal; The gate of the eighteenth PMOS tube is connected to the twelfth signal terminal, the drain of the eighteenth PMOS tube is connected to the tenth signal terminal, and the source of the eighteenth PMOS tube is connected to the output terminal of the trigger; the gate of the nineteenth PMOS tube is connected to the eleventh signal terminal, the drain of the nineteenth PMOS tube is connected to the ninth signal terminal, and the source of the nineteenth PMOS tube is connected to the output terminal of the trigger; the gate of the eighteenth NMOS tube is connected to the eleventh signal terminal, the drain of the eighteenth NMOS tube is connected to the tenth signal terminal, and the source of the eighteenth NMOS tube is connected to the output terminal of the trigger; the gate of the nineteenth NMOS tube is connected to the twelfth signal terminal, the drain of the nineteenth NMOS tube is connected to the ninth signal terminal, and the source of the nineteenth NMOS tube is connected to the output terminal of the trigger.

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