Chip reset circuit, battery management system, battery pack and power-consuming equipment

Abstract

A chip reset circuit comprises: a first chip and a second chip, the chip reset circuit further comprising a pull-down subcircuit; the first chip comprises a reference power pin, a first end of the pull-down subcircuit is electrically connected to the reference power pin, a second end of the pull-down subcircuit is grounded, and a third end of the pull-down subcircuit is electrically connected to the second chip; the chip reset circuit is configured as follows: in response to the second chip outputting a first control signal to the pull-down subcircuit, the pull-down subcircuit electrically connects the reference power pin to the ground to reset the hardware of the first chip; in response to the second chip outputting a second control signal to the pull-down subcircuit, the pull-down subcircuit disconnects the electrical connection between the reference power pin and the ground.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to a chip reset circuit, a battery management system, a battery pack and an electrical device. Background Art

[0002] The analog front end unit (AFE) is an integrated circuit that is at the front end (input end) of the processing chain in electronic equipment and is used to process analog signals. AFE usually integrates analog-to-digital converters (ADC), amplifiers, reference power supplies, excitation circuits, modulation and demodulation circuits, etc., and can digitize the input analog signals. Because AFE is at the front end of the processing chain, its normal operation plays a vital role in the normal operation of electronic equipment. Therefore, when an abnormality occurs in AFE, it is necessary to reset (restart) AFE to ensure the normal operation of AFE.

[0003] In the prior art, the AFE is reset by sending a reset message to the AFE through a microcontroller unit, or by pulling up the level of the AFE reset pin through the microcontroller unit. After receiving and identifying the reset message, the AFE resets itself according to a preset program, or when the level of its own reset pin is pulled high, it resets itself according to a preset program. However, when the above reset method is used, when the internal restart-related program of the AFE is abnormal, the above two reset methods will fail, thereby affecting the normal operation of the electronic device. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a chip reset circuit, a battery management system, a battery pack and an electric device to improve the technical problem that the chip cannot be reset when the program related to the internal restart of the chip is abnormal. The specific technical solution is as follows:

[0005] In a first aspect, an embodiment of the present application provides a chip reset circuit, comprising a first chip and a second chip, the chip reset circuit further comprising a pull-down sub-circuit; the first chip comprises a reference power pin, a first end of the pull-down sub-circuit is electrically connected to the reference power pin, a second end of the pull-down sub-circuit is grounded, and a third end of the pull-down sub-circuit is electrically connected to the second chip; the chip reset circuit is configured as follows: in response to the second chip outputting a first control signal of a high level to the pull-down sub-circuit, the pull-down sub-circuit electrically connects the reference power pin to the ground to perform a hardware reset of the first chip; in response to the second chip outputting a second control signal of a low level to the pull-down sub-circuit, the pull-down sub-circuit disconnects the electrical connection between the reference power pin and the ground.

[0006] In one possible implementation, the pull-down sub-circuit includes a switch unit, the ground includes a first ground, and the switch unit is electrically connected to the reference power pin, the first ground, and the second chip, respectively; the switch unit is configured as: in response to the second chip outputting a first control signal to the switch unit, the switch unit is turned on, and in response to the second chip outputting a second control signal to the switch unit, the switch unit is turned off; or, the chip reset circuit also includes a first power supply, the pull-down sub-circuit includes a switch unit and an isolation unit, and the ground includes a third ground and a second ground; the first end of the switch unit is electrically connected to the second chip, the second end of the switch unit is electrically connected to the third ground, the third end of the switch unit is electrically connected to the first power supply through the input end of the isolation unit, and the reference power pin is electrically connected to the second ground through the output end of the isolation unit; the switch unit and the isolation unit are configured as: in response to the second chip outputting a first control signal to the switch unit, the switch unit is turned on, and the isolation unit is turned on; in response to the second chip outputting a second control signal to the switch unit, the switch unit is turned off, and the isolation unit is turned off.

[0007] In a possible implementation, the switch unit includes a first switch unit, the first switch unit includes a first switch, a first resistor and a second resistor; the first end of the first switch is electrically connected to the first end of the first resistor and the first end of the second resistor, respectively, the second end of the first switch is electrically connected to the first ground or to the third ground, the third end of the first switch is electrically connected to the reference power supply pin or to the input end of the isolation unit; the second end of the first resistor is electrically connected to the first ground or to the third ground, and the second end of the second resistor is electrically connected to the second chip.

[0008] In a possible implementation manner, the first switch is an N-type FET or an NPN-type transistor.

[0009] In a possible implementation, the chip reset circuit also includes a second power supply; the switch unit includes a second switch unit, and the second switch unit includes a second switch, a third switch and a fourth switch; the second switch is electrically connected to the second chip, and the second switch is also electrically connected to the third switch, the second power supply and the first ground, the second power supply is electrically connected to the third switch, and the third switch is electrically connected to the fourth switch; the fourth switch is electrically connected to the reference voltage pin and the first ground, or the fourth switch is electrically connected to the isolation unit and the third ground; the second switch, the third switch and the fourth switch are configured to perform the following operations: in response to the second chip outputting a first control signal to the second switch, the second switch is turned on, in response to the second switch being turned on, the third switch is turned on and the fourth switch is turned on; in response to the second chip outputting a second control signal to the second switch, the second switch is turned off, and in response to the second switch being turned off, the third switch is turned off and the fourth switch is turned off.

[0010] In a possible implementation, the second switch unit further includes a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, and a ninth resistor; the first end of the second switch is electrically connected to the first end of the eighth resistor and the first end of the ninth resistor, respectively, the second end of the second switch is electrically connected to the first ground or the third ground, and the third end of the second switch is electrically connected to the first end of the sixth resistor; the second end of the ninth resistor is electrically connected to the second chip, and the second end of the eighth resistor is electrically connected to the first ground or the third ground; the second end of the sixth resistor is electrically connected to the first end of the third switch and the first end of the seventh resistor, respectively, and the second end of the third switch and the second end of the seventh resistor are both electrically connected to the first end of the ninth resistor. The second power supply is electrically connected, the third end of the third switch is electrically connected to the first end of the fifth resistor; the second end of the fifth resistor is electrically connected to the first end of the fourth switch and the first end of the fourth resistor respectively; the second end of the fourth switch and the second end of the fourth resistor are both electrically connected to the first ground, and the third end of the fourth switch is electrically connected to the reference power supply pin, or the second end of the fourth switch and the second end of the fourth resistor are both electrically connected to the third ground, and the third end of the fourth switch is electrically connected to the input end of the isolation unit; wherein the second switch is an NPN transistor or an N-type FET, the third switch is a PNP transistor or a P-type FET, and the fourth switch is an NPN transistor or an N-type FET.

[0011] In a possible implementation, the isolation unit includes a photocoupler, a photorelay, or a photothyristor.

[0012] In a possible implementation, the chip reset circuit further includes a voltage stabilizing unit; a first end of the voltage stabilizing unit is connected to the reference power pin, and a second end of the voltage stabilizing unit is grounded.

[0013] In a possible implementation manner, the voltage stabilizing unit satisfies one of the following conditions:

[0014] i) the voltage stabilizing unit comprises a first capacitor, one end of the first capacitor is connected to the reference power supply pin, and the other end of the first capacitor is grounded;

[0015] ii) The voltage stabilizing unit includes a first capacitor and a second capacitor connected in parallel with the first capacitor, one end of the first capacitor is connected to the reference power pin, the other end of the first capacitor is grounded, one end of the second capacitor is connected to the reference power pin, and the other end of the second capacitor is grounded.

[0016] In a possible implementation, the chip reset circuit also includes: a communication circuit and a reset sub-circuit; one end of the communication circuit is connected to the communication pin of the first chip, and the other end of the communication circuit is connected to the communication pin of the second chip; one end of the reset sub-circuit is connected to the reset pin of the first chip, and the other end of the reset sub-circuit is connected to the second chip.

[0017] In a possible implementation, the first chip includes an analog front-end chip, and the second chip includes a microcontroller.

[0018] In a second aspect, an embodiment of the present application provides a battery management system, comprising a chip reset circuit of any one of the items in the present application.

[0019] In a third aspect, an embodiment of the present application provides a battery pack, including a battery module and the battery management system of the present application.

[0020] In a fourth aspect, an embodiment of the present application provides an electrical device, including a load and a battery pack in the present application.

[0021] Beneficial effects of the embodiments of the present invention:

[0022] The chip reset circuit, battery management system, battery pack and electrical equipment provided by the embodiments of the present invention utilize a pull-down sub-circuit to lower the voltage of the reference power pin of the first chip. When the voltage of the reference power pin of the first chip is pulled down, the first chip will perform a hardware reset. Therefore, even if the internal program of the first chip is abnormal, the first chip can be reset by hardware reset.

[0023] In the field of circuits, the reference power pin in a chip is connected to the reference power level of the chip. The reference power level is used as a reference to calibrate and compare other voltage signals. The reference power level is the basis for the normal operation of the electronic system. It is necessary to maintain the stability of the reference power level to ensure the normal operation of the electronic system. However, when the inventor of the present application faced the technical problem that the chip could not be reset, he innovatively changed the conventional design of maintaining the stability of the reference power level and proposed to improve the technical problem that the reset software or reset program inside the chip is abnormal, which causes the chip to be unable to reset, by lowering the reference power level and restarting it by hardware.

[0024] Of course, it is not necessary to achieve all of the advantages described above at the same time to implement any product or method of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0026] Figure 1 This is a first schematic diagram of a chip reset circuit according to an embodiment of the present application;

[0027] Figure 2 A second schematic diagram of a chip reset circuit according to an embodiment of the present application;

[0028] Figure 3 A third schematic diagram of the chip reset circuit according to an embodiment of the present application;

[0029] Figure 4 This is a fourth schematic diagram of the chip reset circuit according to an embodiment of the present application;

[0030] Figure 5 This is a fifth schematic diagram of the chip reset circuit according to an embodiment of the present application;

[0031] Figure 6 This is a sixth schematic diagram of the chip reset circuit according to an embodiment of the present application;

[0032] Figure 7 This is a seventh schematic diagram of the chip reset circuit according to an embodiment of the present application;

[0033] Figure 8 This is an eighth schematic diagram of the chip reset circuit according to an embodiment of the present application;

[0034] Fig. 9 This is a ninth schematic diagram of the chip reset circuit according to an embodiment of the present application;

[0035] Fig.10 This is the tenth schematic diagram of the chip reset circuit according to an embodiment of the present application. DETAILED DESCRIPTION

[0036] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field based on this application belong to the scope of protection of the present invention.

[0037] In the prior art, when an abnormality occurs in the AFE, the microcontroller unit will send a reset message to the AFE, or the microcontroller unit will pull up the level of the AFE reset pin to reset the AFE. After receiving and identifying the reset message, the AFE resets itself according to a preset program, or when the level of its own reset pin is pulled high, it resets itself according to a preset program. However, when the above reset method is used, when the program related to the internal restart of the AFE is abnormal, the above two reset methods will fail, making the AFE unable to reset normally, thereby affecting the normal operation of the electronic device.

[0038] In order to improve the above problems, the embodiments of the present application provide a chip reset circuit, a battery management system and a battery pack, which are described in detail below.

[0039] See also Figure 1 , Figure 1This is a schematic diagram of a chip reset circuit in an embodiment of the present application, including a first chip 01 , a second chip 02 , and a pull-down sub-circuit 03 .

[0040] The first chip 01 includes a reference power pin 011, a first end of the pull-down sub-circuit 03 is electrically connected to the reference power pin 011, a second end of the pull-down sub-circuit 03 is grounded, and a third end of the pull-down sub-circuit 03 is electrically connected to the second chip 02; the chip reset circuit is configured as follows: the second chip 02 outputs a first control signal to the pull-down sub-circuit 03, the pull-down sub-circuit 03 electrically connects the reference power pin 011 to the ground, so as to hardware reset the first chip 01; the second chip 02 outputs a second control signal of low level to the pull-down sub-circuit 03, and the pull-down sub-circuit 03 disconnects the electrical connection between the reference power pin 011 and the ground.

[0041] The first chip 01 is a chip at the front end of the processing chain in an electronic device, such as AFE. The second chip 02 is used to control the first chip 01 to reset. The second chip 02 can be a microcontroller unit, a field programmable gate array (FPGA), or a system on chip. The second control signal is an invalid signal. When the third end of the pull-down subcircuit 03 receives the second control signal, the first end and the second end of the pull-down subcircuit 03 are kept disconnected. The first control signal is a valid signal. When the third end of the pull-down subcircuit 03 receives the first control signal, the pull-down subcircuit 03 connects the first end and the second end of the pull-down subcircuit, that is, the reference power pin 011 is grounded, thereby lowering the voltage of the reference power pin 011 to reset the first chip 01 by hardware. Therefore, even if the internal program of the first chip is abnormal, the reset of the first chip can be achieved by hardware reset.

[0042] It can be understood by those skilled in the art that, in the field of circuits, the reference power pin in the chip is connected to the reference power level of the chip, and the reference power level is used as a reference to calibrate and compare other voltage signals. The reference power level is the basis for the normal operation of the electronic system. In order to ensure the normal operation of the electronic system, it is necessary to ensure the stability of the reference power level. However, in this application, in the face of the conventional thinking that only by ensuring the stability of the reference power level can the normal operation of the electronic system be guaranteed, it is creatively proposed to solve the software anomaly of the chip by lowering the reference power level and restarting the chip by hardware, overcoming the technical prejudice in the prior art that the electronic system can only operate normally if the reference power level is stable, and the chip can be reset when the program related to the internal restart of the chip is abnormal.

[0043] In a possible implementation, the chip reset circuit also includes: a communication circuit and a reset sub-circuit; one end of the communication circuit is connected to the communication pin of the first chip 01, and the other end of the communication circuit is connected to the communication pin of the second chip 02; one end of the reset sub-circuit is connected to the reset pin of the first chip 01, and the other end of the reset sub-circuit is connected to the second chip 02.

[0044] The specific structure of the communication circuit and the reset subcircuit can be found in the relevant technology, and is not specifically limited in this application. In some embodiments, when the first chip 01 is abnormal, the second chip 02 will first try a software reset. When the software reset fails, the second chip 02 will perform a hardware reset on the first chip 01. In one possible implementation, the second chip 02 is configured to perform the following operations: when the preset reset conditions are met, the second chip 02 sends a reset message to the first chip 01 through the communication circuit and / or the reset subcircuit. When the first chip 01 does not respond to the reset message or the first chip 01 cannot be reset normally, the second chip 02 sends a first control signal to the pull-down subcircuit 03 to reset the first chip 01 by hardware reset. In addition, when there is no need to reset the first chip 01 by hardware, the second chip 02 sends a second control signal (invalid signal) to the pull-down subcircuit 03.

[0045] In some other embodiments, the second chip 02 directly sends the first control signal to the pull-down sub-circuit 03 to reset the first chip 01 .

[0046] The specific structure of the pull-down sub-circuit 03 in the embodiment of the present application is described below.

[0047] For the scenario where the first chip 01 and the second chip 02 do not need to be electrically isolated, in one embodiment, see Figure 2 The pull-down sub-circuit 03 includes a switch unit 031, the ground includes a first ground GND1, and the switch unit 031 is electrically connected to the reference power pin 011, the first ground GND1, and the second chip 02. The switch unit 031 is configured to: in response to the second chip 02 outputting a first control signal to the switch unit 031, the switch unit 031 is turned on; in response to the second chip 02 outputting a second control signal to the switch unit 031, the switch unit 031 is turned off.

[0048] When the first chip 01 and the second chip 02 do not need to be electrically isolated, the grounds of the first chip 01 and the second chip 02 are the same, both being the first ground GND1. In this case, no isolation design is required, and the switch unit 031 can be directly used to realize the grounding control of the reference power pin 011.

[0049] In order to simplify the circuit design and reduce the circuit cost, the switch unit 031 adopts the design of semiconductor devices and resistors. Figure 4The switch unit 031 includes a first switch unit, and the first switch unit includes a first switch T1, a first resistor R1, and a second resistor R2. The first end of the first switch T1 is electrically connected to the first end of the first resistor R1 and the first end of the second resistor R2, respectively, the second end of the first switch T1 is electrically connected to the first ground GND1, and the third end of the first switch T1 is electrically connected to the reference power pin 011; the second end of the first resistor R1 is electrically connected to the first ground GND1, and the second end of the second resistor R2 is electrically connected to the second chip 02.

[0050] The first switch T1 is a semiconductor switch device, for example, the first switch T1 is specifically a field effect transistor (FieldEffect Transistor, FET) or a triode (Bipolar Junction Transistor). In one example, the first switch T1 is an N-type FET, the first control signal is a high-level signal, and the second control signal is a low-level signal, then the first end of the first switch T1 is a gate, the second end of the first switch T1 is a source, and the third end of the first switch T1 is a drain. In one example, the first switch T1 is an NPN-type triode, the first control signal is a high-level signal, and the second control signal is a low-level signal, then the first end of the first switch T1 is a base, the second end of the first switch T1 is an emitter, and the third end of the first switch T1 is a collector.

[0051] In another embodiment, see Figure 6 The chip reset circuit includes a second power supply 05, and the switch unit 031 includes a second switch unit, and the second switch unit includes a second switch T2, a third switch T3, and a fourth switch T4. The second switch T2 is electrically connected to the second chip 02, and the second switch T2 is also electrically connected to the third switch T3, the second power supply 05, and the first ground GND1, the second power supply 05 is electrically connected to the third switch T3, the third switch T3 is electrically connected to the fourth switch T4, and the fourth switch T4 is electrically connected to the reference voltage pin 011 and the first ground GND1;

[0052] The second switch T2, the third switch T3 and the fourth switch T4 are configured to perform the following operations: in response to the second chip 02 outputting a first control signal to the second switch T2, the second switch T2 is turned on, in response to the second switch T2 being turned on, the third switch T3 is turned on and the fourth switch T4 is turned on; in response to the second chip 02 outputting a second control signal to the second switch T2, the second switch T2 is turned off, in response to the second switch T2 being turned off, the third switch T3 is turned off and the fourth switch T4 is turned off.

[0053] See also Figure 6The chip reset circuit also includes a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9. The first end of the second switch T2 is electrically connected to the first end of the eighth resistor R8 and the first end of the ninth resistor R9, respectively, the second end of the second switch T2 is electrically connected to the first ground GND1, the third end of the second switch T2 is electrically connected to the first end of the sixth resistor R6, the second end of the ninth resistor R9 is electrically connected to the second chip 02, the second end of the eighth resistor R8 is electrically connected to the first ground GND1, the second end of the sixth resistor R6 is electrically connected to the first end of the third switch T3 and the first end of the seventh resistor R7, respectively, the second end of the third switch T3 and the second end of the seventh resistor R7 are both electrically connected to the second power supply 05, the third end of the third switch T3 is electrically connected to the first end of the fifth resistor R5, the second end of the fifth resistor R5 is electrically connected to the first end of the fourth switch T4 and the first end of the fourth resistor R4, respectively, the second end of the fourth switch T4 and the second end of the fourth resistor R4 are both electrically connected to the first ground GND1, and the third end of the fourth switch T4 is electrically connected to the reference power pin 011.

[0054] In some embodiments, the second switch is an NPN transistor or an N-type FET, the third switch is a PNP transistor or a P-type FET, and the fourth switch is an NPN transistor or an N-type FET. The polarity of each end of the transistor or FET can refer to the polarity description of the first end, the second end, and the third end of the transistor or FET in the above embodiment, which will not be repeated here.

[0055] In the above embodiment, for the scenario where the first chip 01 and the second chip 02 do not need to be electrically isolated, a specific circuit implementation of the pull-down sub-circuit 03 is provided, and the reference power pin 011 is grounded by the pull-down sub-circuit 03, thereby lowering the voltage of the reference power pin 011 to perform a hardware reset of the first chip 01.

[0056] For the scenario where the first chip 01 and the second chip 02 need to be electrically isolated, in some other embodiments, see Figure 3 The chip reset circuit includes a first power supply 04, the pull-down sub-circuit 03 includes a switch unit 031 and an isolation unit 032, and the ground includes a second ground GND2 and a third ground GND3.

[0057] The first end of the switch unit 031 is electrically connected to the second chip 02, the second end of the switch unit 031 is electrically connected to the third ground GND3, the third end of the switch unit 031 is electrically connected to the first power supply 04 through the input end of the isolation unit 032, and the reference power pin 011 is electrically connected to the second ground GND2 through the output end of the isolation unit 032.

[0058] The switch unit 031 and the isolation unit 032 are configured as follows: in response to the second chip 02 outputting a first control signal to the switch unit 031, the switch unit 031 is turned on and the isolation unit 032 is turned on; in response to the second chip 02 outputting a second control signal to the switch unit 031, the switch unit 031 is turned off and the isolation unit 032 is turned off.

[0059] When the first chip 01 and the second chip 02 need to be electrically isolated, the grounds of the first chip 01 and the second chip 02 are different. The ground of the second chip 02 is the third ground GND3, and the ground of the first chip 01 is the second ground GND2. In this case, an isolation design is required, and the isolation unit 032 is used to achieve electrical isolation between the first chip 01 and the second chip 02.

[0060] The isolation unit 032 may be a photocoupler, a photorelay, a photoelectric thyristor or other switching devices with electrical isolation function, all of which are within the protection scope of the present application.

[0061] In order to simplify the circuit design and reduce the circuit cost, the switch unit 031 adopts the design of semiconductor devices and resistors. Figure 5 The switch unit 031 includes a first switch unit, and the first switch unit includes a first switch T1, a first resistor R1, and a second resistor R2. The first end of the first switch T1 is electrically connected to the first end of the first resistor R1 and the first end of the second resistor R2, respectively, the second end of the first switch T1 is electrically connected to the third ground GND3, the third end of the first switch T1 is electrically connected to the input end of the isolation unit 032, the second end of the first resistor R1 is electrically connected to the third ground GND3, and the second end of the second resistor R2 is electrically connected to the second chip 02.

[0062] The first switch T1 is a semiconductor switch device, for example, the first switch T1 is a field effect transistor (FET) or a bipolar junction transistor. In one example, the first switch T1 is an N-type FET, the first control signal is a high-level signal, the second control signal is a low-level signal, the first end of the first switch T1 is a gate, the second end of the first switch T1 is a source, and the third end of the first switch T1 is a drain. In one example, the first switch T1 is an NPN-type transistor, the first control signal is a high-level signal, and the second control signal is a low-level signal, then the first end of the first switch T1 is a base, the second end of the first switch T1 is an emitter, and the third end of the first switch T1 is a collector.

[0063] In some other embodiments, see Figure 7The chip reset circuit also includes a second power supply 05, the switch unit 031 includes a second switch unit, and the second switch unit includes a second switch T2, a third switch T3, and a fourth switch T4. The second switch T2 is electrically connected to the second chip 02, and the second switch T2 is also electrically connected to the third switch T3, the second power supply 05, and the third ground GND3. The second power supply 05 is electrically connected to the third switch T3, the third switch T3 is electrically connected to the fourth switch T4, and the fourth switch T4 is electrically connected to the input end of the isolation unit 032 and the third ground GND3.

[0064] The second switch T2, the third switch T3 and the fourth switch T4 are configured to perform the following operations: in response to the second chip 02 outputting a first control signal to the second switch T2, the second switch T2 is turned on, in response to the second switch T2 being turned on, the third switch T3 is turned on and the fourth switch T4 is turned on; in response to the second chip 02 outputting a second control signal to the second switch T2, the second switch T2 is turned off, in response to the second switch T2 being turned off, the third switch T3 is turned off and the fourth switch T4 is turned off.

[0065] See also Figure 7 The chip reset circuit also includes a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9. The first end of the second switch T2 is electrically connected to the first end of the eighth resistor R8 and the first end of the ninth resistor R9, respectively; the second end of the second switch T2 is electrically connected to the third ground GND3; the third end of the second switch T2 is electrically connected to the first end of the sixth resistor R6; the second end of the ninth resistor R9 is electrically connected to the second chip 02; the second end of the eighth resistor R8 is electrically connected to the third ground GND3; the second end of the sixth resistor R6 is electrically connected to the first end of the third switch T3 and the first end of the seventh resistor R7, respectively; the second end of the third switch T3 and the second end of the seventh resistor R7 are both electrically connected to the second power supply 05; the third end of the third switch T3 is electrically connected to the first end of the fifth resistor R5; the second end of the fifth resistor R5 is electrically connected to the first end of the fourth switch T4 and the first end of the fourth resistor R4, respectively; the second end of the fourth switch T4 and the second end of the fourth resistor R4 are both electrically connected to the third ground GND3; and the third end of the fourth switch T4 is electrically connected to the input end of the isolation unit 032.

[0066] In some embodiments, the second switch is an NPN transistor or an N-type FET, the third switch is a PNP transistor or a P-type FET, and the fourth switch is an NPN transistor or an N-type FET. The polarity of each end of the transistor or FET refers to the polarity description of the first end, the second end, and the third end of the transistor or FET in the above embodiment, which will not be repeated here.

[0067] In an embodiment of the present application, a specific circuit implementation of the pull-down sub-circuit 03 is provided for a scenario where electrical isolation is required between the first chip 01 and the second chip 02. The pull-down sub-circuit 03 is utilized to ground the reference power pin 011, thereby pulling down the voltage of the reference power pin 011 to reset the hardware of the first chip 01.

[0068] As mentioned above, the reference power level is the basis for the normal operation of the electronic system. In order to increase the stability of the reference power level in a non-hardware reset scenario, in one implementation, see Figure 8 The chip reset circuit further includes a voltage stabilizing unit 06. A first end of the voltage stabilizing unit 06 is connected to the reference power pin 011, and a second end of the voltage stabilizing unit 06 is grounded.

[0069] In some embodiments, see Fig. 9 The voltage stabilizing unit 06 includes a first capacitor C1, one end of the first capacitor C1 is connected to the reference power pin 011, and the other end of the first capacitor C1 is grounded.

[0070] In some further embodiments, see Fig.10 The voltage stabilizing unit includes a first capacitor C1 and a second capacitor C2 connected in parallel with the first capacitor C1, one end of the first capacitor C1 is connected to the reference power pin 011, the other end of the first capacitor C1 is grounded, one end of the second capacitor C2 is connected to the reference power pin 011, and the other end of the second capacitor C2 is grounded.

[0071] The capacitance values ​​of the first capacitor C1 and the second capacitor C2 are set according to the actual needs of the first chip 01. In an example, the capacitance values ​​of the first capacitor C1 and the second capacitor C2 can be set in a step distribution, so that noise in a larger frequency range can be filtered. In an example, taking the first chip 01 as an AFE, the capacitance value of the first capacitor C1 is 10nf, and the capacitance value of the second capacitor C2 is 100pf. Setting two capacitors with a step distribution and connected in parallel can filter ripples in a larger frequency range.

[0072] In the embodiment of the present application, the voltage stabilizing unit 06 helps to reduce the influence of the pull-down sub-circuit 03 on the level of the reference power pin 011 in the non-hardware reset scenario, thereby increasing the stability of the reference power supply in the non-hardware reset scenario.

[0073] The embodiment of the present application also provides an analog front end unit reset method, which is applied to the second chip, and the method includes:

[0074] Step 1: When a preset reset condition is met, a reset message is sent to the first chip.

[0075] The preset reset condition can be customized according to the actual reset requirement, and is not specifically limited in this application. The second chip is connected to the first chip for communication.

[0076] Step 2: When the first chip does not respond to the reset message, a reset level signal is sent to the reset pin of the first chip.

[0077] In addition to the communication connection, the second chip is also connected to the reset pin of the first chip. If the first chip does not respond to the reset message, the second chip sends a reset level signal to pull up the level of the reset pin of the first chip, thereby attempting to reset the first chip.

[0078] Step three, when the first chip does not respond to the reset level signal, send a first control signal to the pull-down sub-circuit, so that the pull-down sub-circuit responds to the first control signal and pulls down the voltage of the reference power level pin of the first chip, so that the first chip is hardware reset.

[0079] After the software reset of the first chip fails, the second chip controls the pull-down subcircuit to pull down the voltage of the reference power level pin of the first chip, thereby hardware resetting the first chip. When the internal program of the first chip is abnormal, the first chip is reset by hardware reset.

[0080] An embodiment of the present application also provides a battery management system, comprising any chip reset circuit in the present application.

[0081] An embodiment of the present application also provides a battery pack, including a battery module and the battery management system of the present application.

[0082] The embodiment of the present application also provides an electrical device, including a load and a battery pack in the present application. It is understandable that the electrical devices of the present application include: electric vehicles, such as electric bicycles, electric motorcycles, electric tricycles and electric cars, etc.; drones, such as agricultural drones, consumer drones, etc.; energy storage systems, such as household energy storage systems, industrial energy storage systems, commercial energy storage systems, uninterruptible power supplies, etc.; electric tools, such as electric drills, electric lawn mowers, etc.

[0083] In this article, relational terms such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0084] Each embodiment in this specification is described in a related manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referenced to each other.

[0085] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A chip reset circuit, comprising a first chip (01) and a second chip (02), characterized in that: The chip reset circuit also includes a pull-down subcircuit (03); The first chip (01) comprises a reference power pin (011), a first end of the pull-down sub-circuit (03) is electrically connected to the reference power pin (011), a second end of the pull-down sub-circuit (03) is grounded, and a third end of the pull-down sub-circuit (03) is electrically connected to the second chip (02); The chip reset circuit is configured as follows: In response to the second chip (02) outputting a first control signal to the pull-down sub-circuit (03), the pull-down sub-circuit (03) electrically connects the reference power pin (011) to the ground, so as to perform a hardware reset on the first chip (01); In response to the second chip (02) outputting a second control signal to the pull-down sub-circuit (03), the pull-down sub-circuit (03) disconnects the electrical connection between the reference power pin (011) and the ground.

2. The chip reset circuit according to claim 1, characterized in that: The pull-down subcircuit (03) comprises a switch unit (031), the ground comprises a first ground (GND1), and the switch unit (031) is electrically connected to the reference power pin (011), the first ground and the second chip (02) respectively; The switch unit (031) is configured to: in response to the second chip (02) outputting a first control signal to the switch unit (031), the switch unit (031) is turned on; in response to the second chip (02) outputting a second control signal to the switch unit (031), the switch unit (031) is turned off; or, The chip reset circuit further comprises a first power supply (04); the pull-down sub-circuit (03) comprises a switch unit (031) and an isolation unit (032); and the ground comprises a third ground (GND3) and a second ground (GND2); The first end of the switch unit (031) is electrically connected to the second chip (02), the second end of the switch unit (031) is electrically connected to the third ground (GND3), the third end (the third end of Q124) of the switch unit (031) is electrically connected to the first power supply (04) via the input end of the isolation unit (032), and the reference power supply pin (011) is electrically connected to the second ground (GND2) via the output end of the isolation unit (032); The switch unit (031) and the isolation unit (032) are configured such that: in response to the second chip (02) outputting a first control signal to the switch unit (031), the switch unit (031) is turned on and the isolation unit (032) is turned on; in response to the second chip (02) outputting a second control signal to the switch unit (031), the switch unit (031) is turned off and the isolation unit (032) is turned off.

3. The chip reset circuit according to claim 2, characterized in that: The switch unit (031) comprises a first switch unit, wherein the first switch unit comprises a first switch (T1), a first resistor (R1) and a second resistor (R2); The first end of the first switch (T1) is electrically connected to the first end of the first resistor (R1) and the first end of the second resistor (R2), respectively; the second end of the first switch (T1) is electrically connected to the first ground (GND1) or to the third ground (GND3); and the third end of the first switch (T1) is electrically connected to the reference power pin (011) or to the input end of the isolation unit (032); The second end of the first resistor (R1) is electrically connected to the first ground (GND1) or the third ground (GND3), and the second end of the second resistor (R2) is electrically connected to the second chip (02).

4. The chip reset circuit according to claim 3, characterized in that: The first switch (T1) is an N-type FET or an NPN-type transistor.

5. The chip reset circuit according to claim 2, characterized in that: The chip reset circuit also includes a second power supply (05); The switch unit (031) comprises a second switch unit, wherein the second switch unit comprises a second switch (T2), a third switch (T3) and a fourth switch (T4); The second switch (T2) is electrically connected to the second chip (02), the second switch (T2) is also electrically connected to the third switch (T3), the second power supply (05) and the first ground (GND1), the second power supply (05) is electrically connected to the third switch (T3), and the third switch (T3) is electrically connected to the fourth switch (T4); The fourth switch (T4) is electrically connected to the reference voltage pin (011) and the first ground (GND1), or the fourth switch (T4) is electrically connected to the isolation unit (032) and the third ground (GND3); The second switch (T2), the third switch (T3) and the fourth switch (T4) are configured to perform the following operations: in response to the second chip (02) outputting a first control signal to the second switch (T2), the second switch (T2) is turned on, and in response to the second switch (T2) being turned on, the third switch (T3) is turned on and the fourth switch (T4) is turned on; in response to the second chip (02) outputting a second control signal to the second switch (T2), the second switch (T2) is turned off, and in response to the second switch (T2) being turned off, the third switch (T3) is turned off and the fourth switch (T4) is turned off.

6. The chip reset circuit according to claim 5, characterized in that: The second switch unit further includes a fourth resistor (R4), a fifth resistor (R5), a sixth resistor (R6), a seventh resistor (R7), an eighth resistor (R8), and a ninth resistor (R9); The first end of the second switch (T2) is electrically connected to the first end of the eighth resistor (R8) and the first end of the ninth resistor (R9), respectively; the second end of the second switch (T2) is electrically connected to the first ground (GND1) or the third ground (GND3); and the third end of the second switch (T2) is electrically connected to the first end of the sixth resistor (R6); The second end of the ninth resistor (R9) is electrically connected to the second chip (02), and the second end of the eighth resistor (R8) is electrically connected to the first ground (GND1) or the third ground (GND3); The second end of the sixth resistor (R6) is electrically connected to the first end of the third switch (T3) and the first end of the seventh resistor (R7), respectively; the second end of the third switch (T3) and the second end of the seventh resistor (R7) are both electrically connected to the second power supply (05); and the third end of the third switch (T3) is electrically connected to the first end of the fifth resistor (R5); The second end of the fifth resistor (R5) is electrically connected to the first end of the fourth switch (T4) and the first end of the fourth resistor (R4) respectively; The second end of the fourth switch (T4) and the second end of the fourth resistor (R4) are both electrically connected to the first ground (GND1), and the third end of the fourth switch (T4) is electrically connected to the reference power pin (011), or the second end of the fourth switch (T4) and the second end of the fourth resistor (R4) are both electrically connected to the third ground (GND3), and the third end of the fourth switch (T4) is electrically connected to the input end of the isolation unit (032); The second switch (T2) is an NPN transistor or an N-type FET, the third switch (T3) is a PNP transistor or a P-type FET, and the fourth switch (T4) is an NPN transistor or an N-type FET.

7. The chip reset circuit according to any one of claims 2 to 6, characterized in that: The isolation unit (032) comprises one of a photoelectric coupler, a photorelay and a photoelectric thyristor.

8. The chip reset circuit according to any one of claims 1 to 7, characterized in that: The chip reset circuit also includes a voltage stabilizing unit (06); A first end of the voltage stabilizing unit (06) is connected to the reference power supply pin (011), and a second end of the voltage stabilizing unit (06) is connected to the ground.

9. The chip reset circuit according to claim 1, characterized in that: The voltage stabilizing unit (06) satisfies one of the following conditions: i) the voltage stabilizing unit (06) comprises a first capacitor (C1), one end of the first capacitor (C1) is connected to the reference power pin, and the other end of the first capacitor (C1) is connected to the ground; ii) The voltage stabilizing unit (06) comprises a first capacitor (C1) and a second capacitor (C2) connected in parallel with the first capacitor (C1), one end of the first capacitor (C1) is connected to the reference power pin (011), and the other end of the first capacitor (C1) is connected to the ground, one end of the second capacitor (C2) is connected to the reference power pin (011), and the other end of the second capacitor (C2) is connected to the ground.

10. The chip reset circuit according to any one of claims 1 to 9, characterized in that: The chip reset circuit also includes: a communication circuit and a reset subcircuit; One end of the communication circuit is connected to the communication pin of the first chip, and the other end of the communication circuit is connected to the communication pin of the second chip; One end of the reset subcircuit is connected to the reset pin of the first chip, and the other end of the reset subcircuit is connected to the second chip.

11. The chip reset circuit according to any one of claims 1 to 10, characterized in that: The first chip includes an analog front-end chip, and the second chip includes a microcontroller.

12. A battery management system, characterized in that: Comprising a chip reset circuit as described in any one of claims 1-11.

13. A battery pack, characterized in that: It comprises a battery module and a battery management system as claimed in claim 12.

14. An electrical device, characterized in that: The invention comprises a load and the battery pack as claimed in claim 13.

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