Glitch-free clock switching circuit, chip and electronic device

Abstract

The present application provides a glitch-free clock switching circuit, chip and electronic device, which belongs to the field of electronic technology. In the glitch-free clock switching circuit, the input circuit can output the input signal to the sampling circuit based on the selection signal and the sampling result, the sampling circuit can perform multiple continuous sampling of the input signal based on the clock signal and output the sampling result to the output circuit, and the output circuit can switch between different clock signals based on the sampling result. Therefore, the sampling method can be flexibly set to cooperate with the output circuit to achieve synchronous switching of the clock signal, avoiding glitches in the clock signal of the switching output. Furthermore, it can ensure reliable drive of the load to avoid circuit failure in the load.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a glitch-free clock switching circuit, chip and electronic equipment. Background Art

[0002] A clock switching circuit is a circuit used to select and switch between different clock signals to dynamically select a clock signal of the required frequency to drive the load to work, thereby meeting functional requirements in different scenarios.

[0003] In the related art, a clock switching circuit generally includes a plurality of interconnected logic units, such as an AND gate, an OR gate, and a NOT gate. The plurality of logic units are used to receive a selection signal and a plurality of clock signals, and are used to select a clock signal from the plurality of clock signals within a time period under the control of the selection signal and output it to a load, thereby realizing the switching of different clock signals.

[0004] However, due to various factors (such as improper switching timing), the current clock switching circuit is prone to generate glitches when switching the selected clock signal, that is, the output clock signal is prone to unexpected jumps, which is not conducive to driving the load. For example, it may cause a circuit failure in the load. Summary of the invention

[0005] The present application provides a glitch-free clock switching circuit, chip and electronic device, which can solve the technical problem of glitch generation during clock switching in the related art. The technical solution is as follows:

[0006] On the one hand, a glitch-free clock switching circuit is provided, the glitch-free clock switching circuit comprising: an input circuit, a sampling circuit and an output circuit, the input circuit is connected to the sampling circuit, and the sampling circuit is also connected to the output circuit;

[0007] The input circuit is used to: output a first input signal based on a received first selection signal and a first sampling result, and output a second input signal based on a received second selection signal and a second sampling result, wherein the second selection signal and the first selection signal are mutually inverted signals;

[0008] The sampling circuit is used to: perform multiple continuous sampling on the first input signal based on the received first clock signal to output the second sampling result, and perform multiple continuous sampling on the second input signal based on the received second clock signal to output the first sampling result;

[0009] The output circuit is used to switch between the first clock signal and the second clock signal based on the first sampling result and the second sampling result to output a target clock signal.

[0010] Optionally, the output circuit includes: a first output subcircuit and a second output subcircuit; the first output subcircuit is connected to the sampling circuit and the second output subcircuit respectively;

[0011] The first output subcircuit is used to: select to output the first clock signal based on the second sampling result, and select to output the second clock signal based on the first sampling result;

[0012] The second output subcircuit is used to switch between the first clock signal and the second clock signal output by the first output subcircuit to output the target clock signal.

[0013] Optionally, the first output subcircuit includes: a first output unit and a second output unit;

[0014] The first output unit is used to: when the second sampling result is valid, select to output the first clock signal;

[0015] The second output unit is used to select and output the second clock signal when the first sampling result is valid.

[0016] Optionally, the first output unit includes: a first integrated clock gating; and / or the second output unit includes: a second integrated clock gating;

[0017] The enable end of the first integrated clock gating is connected to the sampling circuit to receive the second sampling result output by the sampling circuit, the clock end of the first integrated clock gating is used to receive the first clock signal, and the output end of the first integrated clock gating is connected to the second output sub-circuit to output the first clock signal to the second output sub-circuit;

[0018] The enable end of the second integrated clock gating is connected to the sampling circuit to receive the first sampling result output by the sampling circuit, the clock end of the second integrated clock gating is used to receive the second clock signal, and the output end of the second integrated clock gating is connected to the second output sub-circuit to output the second clock signal to the second output sub-circuit.

[0019] Optionally, the second output sub-circuit is used to: perform first logic processing on the first clock signal and the second clock signal output by the first output sub-circuit to switch between the first clock signal and the second clock signal output by the first output sub-circuit to output the target clock signal.

[0020] Optionally, the first logic processing is a phase OR logic processing; and the second output subcircuit includes: an OR gate.

[0021] Optionally, the sampling circuit includes: a first sampling subcircuit and a second sampling subcircuit;

[0022] The first sampling subcircuit is used to: perform two consecutive samplings on the first input signal under the control of the falling edge of the first clock signal to output the second sampling result;

[0023] The second sampling subcircuit is used for: under the control of the falling edge of the second clock signal, performing two consecutive samplings on the second input signal to output the first sampling result.

[0024] Optionally, the first sampling subcircuit includes: a first trigger and a second trigger; the main output terminal of the second trigger is connected to the output circuit; the inverting output terminal of the second trigger is connected to the input circuit; the second sampling result output by the second trigger through the main output terminal and the third sampling result output by the second trigger through the inverting output terminal are inverted signals of each other; the glitch-free clock switching circuit also includes: a first inverting circuit; the first inverting circuit is connected between the inverting output terminal of the second trigger and the input circuit;

[0025] The first inverting circuit is used to invert the third sampling result outputted by the second trigger via the inverting output terminal to obtain the second sampling result, and output the second sampling result to the input circuit.

[0026] Optionally, the second sampling subcircuit includes: a third trigger and a fourth trigger; the main output terminal of the fourth trigger is connected to the output circuit; the inverting output terminal of the fourth trigger is connected to the input circuit; the first sampling result output by the fourth trigger through the main output terminal and the fourth sampling result output by the fourth trigger through the inverting output terminal are inverted signals to each other; the glitch-free clock switching circuit also includes: a second inverting circuit; the second inverting circuit is connected between the inverting output terminal of the fourth trigger and the input circuit;

[0027] The second inverting circuit is used to invert the fourth sampling result outputted from the inverting output terminal of the fourth trigger to obtain the first sampling result, and output the first sampling result to the input circuit.

[0028] Optionally, the input circuit comprises: a first input subcircuit and a second input subcircuit;

[0029] The first input subcircuit is used to: perform second logic processing on the first selection signal and the first sampling result to output the first input signal;

[0030] The second input sub-circuit is used to perform a third logic process on the second selection signal and the second sampling result to output the second input signal.

[0031] Optionally, the second logic operation processing is an AND logic processing; the first input sub-circuit includes: a first AND gate; and / or, the third logic operation processing is an AND logic processing; the second input sub-circuit includes: a second AND gate.

[0032] Optionally, the glitch-free clock switching circuit further includes: a third inverting circuit; the third inverting circuit is connected to the input circuit;

[0033] The third inverting circuit is used for inverting the received first selection signal to output the second selection signal.

[0034] Optionally, the first clock signal and the second clock signal are asynchronous clock signals;

[0035] The first clock signal and the second clock signal as the target clock signal are non-overlapping clock signals.

[0036] On the other hand, a chip is provided, the chip comprising: a clock source, and the glitch-free clock switching circuit as described in the above aspect; the clock source is connected to the glitch-free clock switching circuit;

[0037] The clock source is used to: output a first clock signal and a second clock signal to the glitch-free clock switching circuit;

[0038] The glitch-free clock switching circuit is used to switch a selected clock signal between the first clock signal and the second clock signal based on a received selection signal.

[0039] In another aspect, an electronic device is provided, the electronic device comprising: a load, and the chip as described in the above another aspect;

[0040] The glitch-free clock switching circuit in the chip is connected to the load and is used to output a switched selected clock signal to the load to drive the load to operate.

[0041] In summary, the technical solution provided by this application can at least bring the following beneficial effects:

[0042] The present application provides a glitch-free clock switching circuit, chip and electronic device, which belongs to the field of electronic technology. In the glitch-free clock switching circuit, the input circuit can output the input signal to the sampling circuit based on the selection signal and the sampling result, the sampling circuit can perform multiple continuous sampling of the input signal based on the clock signal and output the sampling result to the output circuit, and the output circuit can switch between different clock signals based on the sampling result. Therefore, the sampling method can be flexibly set to cooperate with the output circuit to achieve synchronous switching of the clock signal, avoiding glitches in the clock signal of the switching output. Furthermore, it can ensure reliable drive of the load to avoid circuit failure in the load. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0044] Figure 1 It is a structural schematic diagram of a glitch-free clock switching circuit provided in an embodiment of the present application;

[0045] Figure 2 is a structural schematic diagram of another glitch-free clock switching circuit provided in an embodiment of the present application;

[0046] Figure 3 It is a structural schematic diagram of another glitch-free clock switching circuit provided in an embodiment of the present application;

[0047] Figure 4 It is a circuit structure diagram of a glitch-free clock switching circuit provided in an embodiment of the present application;

[0048] Figure 5 It is a schematic diagram of a circuit structure of integrated clock gating provided in an embodiment of the present application;

[0049] Figure 6 It is a circuit structure diagram of another glitch-free clock switching circuit provided in an embodiment of the present application;

[0050] Figure 7 It is a timing simulation schematic diagram of a glitch-free clock switching circuit provided in an embodiment of the present application;

[0051] Figure 8 It is a schematic diagram of the structure of a chip provided in an embodiment of the present application;

[0052] Fig. 9 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0053] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0054] In view of the technical problems mentioned in the background technology, in some embodiments, a glitch-free clock switching circuit capable of filtering glitches is proposed, also called a glitch filtering switching circuit or a glitch-free clock switching circuit. The glitch-free clock switching circuit can make two randomly inverted clock signals (such as asynchronous clock signals) have no glitches when switching, thereby avoiding circuit failure. The glitch-free clock switching circuit is widely used in digital integrated circuits (integrated circuit, IC). Among them, the asynchronous clock signal can refer to a clock signal from different clock sources, and the phase and frequency of the asynchronous clock signal are generally different. At present, the common glitch-free clock switching circuit usually includes multiple circuits such as latches, multiple logic gates, registers, etc. The circuit structure is relatively complex and is not conducive to timing analysis.

[0055] Based on this, the embodiment of the present application provides a new glitch-free clock switching circuit, which has a simple circuit structure and is conducive to timing analysis, and can be widely used in digital ICs. Figure 1 As shown, the glitch-free clock switching circuit includes: an input circuit 01, a sampling circuit 02 and an output circuit 03. The input circuit 01 is connected to the sampling circuit 02, and the sampling circuit 02 is also connected to the output circuit 03.

[0056] The input circuit 01 is used to output a first input signal D1 based on a received first selection signal SEL and a first sampling result Q1, and to output a second input signal D2 based on a received second selection signal SEL′ and a second sampling result Q2.

[0057] Among them, the second selection signal SEL' and the first selection signal SEL are mutually inverted signals. That is, in the same period, the phases of the second selection signal SEL' and the first selection signal SEL can be exactly opposite. For example, when the level of the first selection signal SEL is a high level 1, the level of the second selection signal SEL' can be a low potential 0. When the level of the first selection signal SEL is a low level 0, the level of the second selection signal SEL' can be a high level 1. Here, the high level and the low level are relative.

[0058] Optionally, in some embodiments, the first selection signal SEL may come from a register (or a trigger) in the clock domain, and the second selection signal SEL' may be a signal obtained by inverting the first selection signal SEL. Accordingly, the input circuit 01 may also be connected to a register to receive the first selection signal SEL provided by the register. In addition, an inverter may be included to invert the first selection signal SEL and output the second selection signal SEL'. Of course, in some other embodiments, the first selection signal SEL and the second selection signal SEL' may also come from different registers.

[0059] For example, the input circuit 01 can perform logic processing on the first selection signal SEL and the first sampling result Q1 to generate the first input signal D1. Similarly, the input circuit 01 can perform logic processing on the second selection signal SEL' and the second sampling result Q2 to generate the second input signal D2. Since the input circuit 01 is connected to the sampling circuit 02, the input circuit 01 can output the generated first input signal D1 and the second input signal to the sampling circuit 02 as input signals received by the sampling circuit 02.

[0060] The sampling circuit 02 is used to: perform multiple continuous sampling on the first input signal D1 based on the received first clock signal CLKA to output the second sampling result Q2, and perform multiple continuous sampling on the second input signal D2 based on the received second clock signal CLKB to output the first sampling result Q1.

[0061] Optionally, in some embodiments, the first clock signal CLKA and the second clock signal CLKB may come from different clock sources, respectively, and are asynchronous clock signals provided by the different clock sources. Accordingly, the sampling circuit 02 may also be connected to two different clock sources to receive the first clock signal CLKA and the second clock signal CLKB provided by the two clock sources. Of the two clock sources, one clock source may provide the first clock signal CLKA, and the other clock source may provide the second clock signal CLKB. Of course, in some other embodiments, the first clock signal CLKA and the second clock signal CLKB may also come from the same clock source. In addition, based on the foregoing description, it can be seen that the first input signal D1 and the second input signal D2 may both come from the input circuit 01.

[0062] For example, the sampling circuit 02 can perform two consecutive samples on the first input signal D1 under the control of the falling edge of the first clock signal CLKA to output the second sampling result Q2. Similarly, the sampling circuit 02 can perform two consecutive samples on the second input signal D2 under the control of the falling edge of the second clock signal CLKB to output the first sampling result Q1. That is, the first sampling result Q1 and the second sampling result Q2 received by the input circuit 01 can both come from the sampling circuit 02.

[0063] The falling edge of the clock signal may refer to: the transition edge of the clock signal from a high level 1 to a low level 0. Sampling under the control of the falling edge may refer to: sampling again when the falling edge comes.

[0064] It can be understood that performing multiple continuous sampling of the input signal based on the clock signal may mean: first sampling the input signal once based on the clock signal, and then performing a second sampling on the sampling result after the aforementioned first sampling based on the clock signal, and so on, until the sampling is completed. For example, performing two continuous samplings of the first input signal D1 based on the first clock signal CLKA may mean: first sampling the first input signal D1 once based on the first clock signal CLKA, and then performing a second sampling on the sampling result of the first sampling based on the first clock signal CLKA, and the result of the second sampling is the second sampling result Q2. Similarly, performing two continuous samplings of the second input signal D2 based on the second clock signal CLKB may mean: first sampling the second input signal D2 once based on the second clock signal CLKB, and then performing a second sampling on the sampling result of the first sampling based on the second clock signal CLKB, and the result of the second sampling is the first sampling result Q1.

[0065] The output circuit 03 is used to switch between the first clock signal CLKA and the second clock signal CLKB based on the first sampling result Q1 and the second sampling result Q2 to output the target clock signal CLK0.

[0066] It is understandable that the output circuit 03 can also be connected to the two clock sources connected to the sampling circuit 02 to receive the first clock signal CLKA and the second clock signal CLKB provided by the two clock sources. In addition, based on the above description, it can be known that the first sampling result Q1 and the second sampling result Q2 can both come from the sampling circuit 02.

[0067] For example, the output circuit 03 can select and output the first clock signal CLKA when the first sampling result Q1 is valid and the second sampling result Q2 is invalid. At this time, the frequency and phase of the output target clock signal CLK0 are the same as the first clock signal CLKA. Similarly, the output circuit 03 can select and output the second clock signal CLKB when the second sampling result Q2 is valid and the first sampling result Q1 is invalid. At this time, the frequency and phase of the output target clock signal CLK0 are the same as the second clock signal CLKB. In this way, the selection and switching of different clock signals is realized.

[0068] It can be understood that the sampling result is valid, which means that the level indicated by the sampling result is a valid level (e.g., high level 1), and at this time, the output circuit 03 can be enabled to output the clock signal used to obtain the sampling result; the sampling result is invalid, which means that the level indicated by the sampling result is an invalid level (e.g., low level 0), and at this time, the output circuit 03 can be disabled to stop outputting the clock signal used to obtain the sampling result. For example, the first sampling result Q1 is valid, which means that the level indicated by the first sampling result Q1 is a valid level, and at this time, the output circuit 03 can be enabled to output the first clock signal CLKA used to obtain the first sampling result Q1. Similarly, the second sampling result Q2 is valid, which means that the level indicated by the second sampling result Q2 is a valid level, and at this time, the output circuit 03 can be enabled to output the second clock signal CLKB used to obtain the second sampling result Q2. In this way, glitch-free switching of the first clock signal CLKA and the second clock signal CLKB is achieved.

[0069] In summary, an embodiment of the present application provides a glitch-free clock switching circuit. The glitch-free clock switching circuit includes an input circuit, a sampling circuit, and an output circuit. Since the input circuit can output an input signal to the sampling circuit based on a selection signal and a sampling result, the sampling circuit can perform multiple continuous samplings of the input signal based on the clock signal and output the sampling result to the output circuit, and the output circuit can switch between different clock signals based on the sampling result. Therefore, the sampling method can be flexibly set to cooperate with the output circuit to achieve synchronous switching of the clock signal, thereby avoiding glitches in the clock signal of the switching output. Furthermore, it can ensure that the load is reliably driven to work and avoid failures in the circuits in the load.

[0070] Optionally, Figure 2 is a schematic diagram of the structure of another glitch-free clock switching circuit provided by an embodiment of the present application. Figure 2 As shown, the output circuit 03 may include: a first output sub-circuit 031 and a second output sub-circuit 032. The first output sub-circuit 031 may be connected to the sampling circuit 02 and the second output sub-circuit 032, respectively.

[0071] The first output sub-circuit 031 may be used to: select and output the first clock signal CLKA based on the second sampling result Q2, and select and output the second clock signal CLKB based on the first sampling result Q1.

[0072] For example, the first output subcircuit 031 can output the first clock signal CLKA to the second output subcircuit 032 when the second sampling result Q2 is valid. Similarly, the first output subcircuit 031 can output the second clock signal CLKB to the second output subcircuit 032 when the first sampling result Q1 is valid.

[0073] In this way, it can also be understood that the first output sub-circuit 031 may be connected to the two clock sources mentioned above to receive the first clock signal CLKA and the second clock signal CLKB provided by the two clock sources.

[0074] The second output sub-circuit 032 can be used to switch between the first clock signal CLKA and the second clock signal CLKB output by the first output sub-circuit 031 to output the target clock signal CLK0.

[0075] For example, the second output sub-circuit 032 can perform a first logic process on the first clock signal CLKA and the second clock signal CLKB output by the first output sub-circuit 031 to switch between the first clock signal CLKA and the second clock signal CLKB output by the first output sub-circuit 031 to output the target clock signal CLK0.

[0076] For example, the first logic processing may be an OR logic processing. The OR logic processing is a binary logic operation processing, which is used to output a high level 1 when the level of at least one input signal among the two received input signals is a high level 1.

[0077] Optionally, Figure 3 is a schematic diagram of the structure of another glitch-free clock switching circuit provided by an embodiment of the present application. Figure 3 As shown, the first output sub-circuit 031 may include: a first output unit 0311 and a second output unit 0312 .

[0078] The first output unit 0311 can be used to select and output the first clock signal CLKA when the second sampling result Q2 is valid.

[0079] The second output unit 0312 can be used to select and output the second clock signal CLKB when the first sampling result Q1 is valid.

[0080] That is, different output units may respectively select to output the first clock signal CLKA or the second clock signal CLKB to the second output sub-circuit 032 based on the first sampling result Q1 and the second sampling result Q2.

[0081] And, understandably, combined Figure 2 and Figure 3 It can be seen that the first output unit 0311 and the second output unit 0312 can be connected to the sampling circuit 02 and the second output sub-circuit 032 respectively.

[0082] Optionally, Figure 4 Schematic diagram of the circuit structure of a glitch-free clock switching circuit provided by an embodiment of the present application. Figure 4 As shown, the first output unit 0311 may include: a first integrated clock gating (ICG) ICG1. And / or, the second output unit 0312 may include: a second integrated clock gating ICG2.

[0083] The enable terminal E of the first integrated clock gating ICG1 can be connected to the sampling circuit 02 to receive the second sampling result Q2 output by the sampling circuit 02. The clock terminal CK of the first integrated clock gating ICG1 can be used to receive the first clock signal CLKA, such as being connected to one of the two different clock sources described above to receive the first clock signal CLKA provided by the one clock source. The output terminal (not marked) of the first integrated clock gating ICG1 can be connected to the second output sub-circuit 032 to output the first clock signal CLKA to the second output sub-circuit 032.

[0084] The enable terminal E of the second integrated clock gating ICG2 can be connected to the sampling circuit 02 to receive the first sampling result Q1 output by the sampling circuit 02. The clock terminal CK of the second integrated clock gating ICG2 can be used to receive the second clock signal CLKB, such as being connected to the other clock source of the two different clock sources described above to receive the second clock signal CLKB provided by the other clock source. The output terminal (not marked) of the second integrated clock gating ICG2 can be connected to the second output sub-circuit 032 to output the second clock signal CLKB to the second output sub-circuit 032.

[0085] Optionally, the structures of the first integrated clock gating ICG1 and the second integrated clock gating ICG2 may be the same. Taking the first integrated clock gating ICG1 as an example, Figure 5 The following schematically shows a circuit structure diagram of integrated clock gating. Figure 5As shown, the integrated clock gating ICG may have two enable terminals TE and E, a clock terminal CK, and an output terminal Q0. The integrated clock gating ICG may select the clock signal received by the output clock terminal CK to the output terminal Q0 based on the enable signal provided by each enable terminal. In the embodiment of the present application, only one enable terminal E is required.

[0086] Optionally, continue to refer to Figure 5 It can be seen that the integrated clock gating ICG may include: an OR gate OR0, a latch Latch and an AND gate AND0. The two input ends of the OR gate OR0 may be connected to the two enable terminals TE and E respectively, and the output end of the OR gate OR0 may be connected to the input end of the latch Latch. The latch Latch may also be connected to the clock terminal CK. The two input ends of the AND gate AND0 may be connected to the output end of the latch Latch and the clock terminal CK respectively, and the output end of the AND gate AND0 may be used as the output end Q0 of the integrated clock gating ICG.

[0087] Based on this structure, the signal IQ outputted from the output end of the latch Latch can satisfy: IQ=!CK? (TE|E), and the signal Qout outputted from the output end of the AND gate AND=IQ&CK. Among them, !CK refers to the logical negation operation of the clock signal provided by the clock end CK. For example, when the level of the clock signal provided by the clock end CK is high level 1, !CK is 0; when the level of the clock signal provided by the clock end CK is low potential 0, !CK is 1. !CK? refers to the selection of whether to perform the logical operation of TE|E according to the result of the logical negation operation of the clock signal provided by the clock end CK. For example, if !CK? is 0, the logical operation of TE|E is performed; otherwise, it is not performed. TE|E refers to the logical OR operation of the enable signals provided by the two enable ends TE and E. The logical OR operation is also the phase OR logic processing described above. IQ&CK refers to the logical AND operation of the signal IQ and the clock signal provided by the clock end CK. Logical AND operation is also a binary logic operation, which is used to output 1 when both input signals received are 1; otherwise, it outputs 0.

[0088] certainly, Figure 5 The circuit structure of the integrated clock gating ICG shown is only a schematic illustration, and any integrated clock gating ICG circuit that can be applied to the embodiments of the present application can be applied to the present application.

[0089] Optionally, based on the first logical processing being a phase OR logical processing, continue to refer to Figure 4 and Figure 6 It can be seen that the second output sub-circuit 032 may include: an OR gate OR1.

[0090] The first input terminal and the second input terminal of the OR gate OR1 can be connected to the first output sub-circuit 031 to receive the first clock signal CLKA or the second clock signal CLKB output by the first output sub-circuit 031. The output terminal of the OR gate OR1 can be used as the output signal terminal Z of the glitch-free clock switching circuit to connect to a load to output the target clock signal CLK0 to the load.

[0091] Optionally, the load may be any circuit that needs to work under the drive of the target clock signal CLK0 , such as a data processing unit (DPU).

[0092] And, understandably, combined Figure 4 and Figure 6 It can be seen that, on the basis that the first output subcircuit 031 includes the first output unit 0311 and the second output unit 0312, and the first output unit 0311 includes the first integrated clock gating ICG1, and the second output unit 0312 includes the second integrated clock gating ICG2, the first input terminal and the second input terminal of the OR gate OR1 can be respectively connected to the output terminal of the first integrated clock gating ICG1 and the output terminal of the second integrated clock gating ICG2. For example, the first input terminal of the OR gate OR1 is connected to the output terminal of the first integrated clock gating ICG1 to receive the first clock signal CLKA outputted via the output terminal of the first integrated clock gating ICG1. The second input terminal of the OR gate OR1 is connected to the output terminal of the second integrated clock gating ICG2 to receive the second clock signal CLKB outputted via the output terminal of the second integrated clock gating ICG2.

[0093] Optionally, continue to refer to Figure 2 and Figure 3 It can be seen that the sampling circuit 02 may include: a first sampling sub-circuit 021 and a second sampling sub-circuit 022 .

[0094] The first sampling sub-circuit 021 may be used to: under the control of the falling edge of the first clock signal CLKA, perform two consecutive samples on the first input signal D1 to output a second sampling result Q2.

[0095] The second sampling sub-circuit 022 may be used to: under the control of the falling edge of the second clock signal CLKB, perform two consecutive samples on the second input signal D2 to output a first sampling result Q1.

[0096] That is, different sampling sub-circuits may respectively perform multiple consecutive samplings on the first input signal D1 and the second input signal D2 to correspondingly output the second sampling result Q2 and the first sampling result Q1.

[0097] And, understandably, combined Figure 2 and Figure 3 It can be seen that the first sampling subcircuit 021 and the second sampling subcircuit 022 can be connected to the input circuit 01 and the output circuit 03 respectively. Figure 4 and Figure 6 It can be seen that, based on dividing the output circuit 03 into the first output sub-circuit 031 and the second output sub-circuit 032, dividing the first output sub-circuit 031 into the first output unit 0311 and the second output unit 0312, and the first output unit 0311 includes the first integrated clock gating ICG1, and the second output unit 0312 includes the second integrated clock gating ICG2, the first sampling sub-circuit 021 can be connected to the enable terminal E of the first integrated clock gating ICG1, and the second sampling sub-circuit 022 can be connected to the enable terminal E of the second integrated clock gating ICG2.

[0098] Optionally, continue to refer to Figure 4 and Figure 6 It can be seen that the first sampling sub-circuit 021 may include: a first flip flop (FF) FF1 and a second flip flop FF2.

[0099] The input terminal D of the first flip-flop FF1 can be connected to the input circuit 01 to receive the first input signal D1 output by the input circuit 01. The output terminal Q of the first flip-flop FF1 can be connected to the input terminal D of the second flip-flop FF2. The output terminal Q of the second flip-flop FF2 can be connected to the output circuit 03 and the input circuit 01, respectively, to output the second sampling result Q2 to the output circuit 03 and the input circuit 01. The clock terminal CK of the first flip-flop FF1 and the clock terminal CK of the second flip-flop FF2 can both be used to receive the first clock signal CLKA.

[0100] On this basis, it can be known that, first, the first trigger FF1 can sample the first input signal D1 once when the falling edge of the first clock signal CLKA arrives, and output the sampling result to the second trigger FF2; then, the second trigger FF2 can re-sample the sampling result output by the first trigger FF1 when the falling edge of the first clock signal CLKA arrives, so as to output the second sampling result Q2.

[0101] Optionally, continue to refer to Figure 4 and Figure 6 It can be seen that the second sampling sub-circuit 022 may include: a third flip-flop FF3 and a fourth flip-flop FF4.

[0102] The input terminal D of the third flip-flop FF3 can be connected to the input circuit 01 to receive the second input signal D2 output by the input circuit 01. The output terminal Q of the third flip-flop FF3 can be connected to the input terminal D of the fourth flip-flop FF4. The output terminal Q of the fourth flip-flop FF4 can be connected to the output circuit 03 and the input circuit 01, respectively, to output the first sampling result Q1 to the output circuit 03 and the input circuit 01. The clock terminal CK of the third flip-flop FF3 and the clock terminal CK of the fourth flip-flop FF4 can both be used to receive the second clock signal CLKB.

[0103] On this basis, it can be known that, first, the third trigger FF3 can sample the second input signal D2 once when the falling edge of the second clock signal CLKB arrives, and output the sampling result to the fourth trigger FF4; then, the fourth trigger FF4 can re-sample the sampling result output by the third trigger FF3 when the falling edge of the second clock signal CLKB arrives, so as to output the first sampling result Q1.

[0104] Optionally, each of the first to fourth triggers FF1 to FF4 may be Figure 4 Of course, in some other embodiments, other types of triggers may also be used.

[0105] Furthermore, it can be understood that the output terminal Q of the second flip-flop FF2 in the first sampling sub-circuit 021 can be connected to the enable terminal E of the first integrated clock gating ICG1 included in the first output unit 0311 in the output circuit 03, and the output terminal Q of the fourth flip-flop FF4 in the second sampling sub-circuit 022 can be connected to the enable terminal E of the second integrated clock gating ICG2 included in the second output unit 0312 in the output circuit 03.

[0106] Optionally, continue to refer to Figure 4 and Figure 6 It can be seen that the main output terminal Q of the second flip-flop FF2 can be connected to the output circuit 03. That is, the main output terminal Q of the second flip-flop FF2 can be connected to the enable terminal E of the first integrated clock gate ICG1 in the output circuit 03. It can be connected to the input circuit 01. That is, the output terminal Q indicated above can refer to the main output terminal.

[0107] The second sampling result Q2 outputted by the second flip-flop FF2 through the main output terminal Q and the second sampling result Q2 outputted by the second flip-flop FF2 through the inverting output terminal The output third sampling result Q2' can be an inverted signal. That is, in the same period, the phases of the second sampling result Q2 and the third sampling result Q2' can be exactly opposite. For example, when the level of the second sampling result Q2 is a high level 1, the level of the third sampling result Q2' can be a low level 0; when the level of the second sampling result Q2 is a low level 0, the level of the third sampling result Q2' can be a high level 1.

[0108] Accordingly, continue to refer to Figure 4 and Figure 6 It can be seen that the glitch-free clock switching circuit may further include: a first inverting circuit 04. The first inverting circuit 04 may be connected to the inverting output terminal of the second trigger FF2. and between input circuit 01.

[0109] The first inverting circuit 04 can be used to: The output third sampling result Q2 ′ is inverted to obtain a second sampling result Q2 , and the second sampling result Q2 is output to the input circuit 01 .

[0110] That is, the second sampling result Q2 received by the input circuit 01 is not the second sampling result Q2 directly outputted via the main output terminal Q of the second flip-flop FF2, but the second sampling result Q2 directly outputted via the inverting output terminal Q of the second flip-flop FF2 by the first inverting circuit 04. The output third sampling result Q2' is the second sampling result Q2 after inversion processing. The second sampling result Q2 received by the output circuit 03 is the second sampling result Q2 directly output by the second flip-flop FF2 via the main output terminal Q. In this way, the sampling results received by the output circuit 03 and the input circuit 01 can be separated to avoid interference. Of course, in some other embodiments, the first inversion circuit 04 may not be provided, but the main output terminal Q of the second flip-flop FF2 may be directly connected to the input circuit 01.

[0111] Optionally, similarly, continue to refer to Figure 4 and Figure 6 It can be seen that the main output terminal Q of the fourth flip-flop FF4 can be connected to the output circuit 03. That is, the main output terminal Q of the fourth flip-flop FF4 can be connected to the enable terminal E of the second integrated clock gate ICG2 in the output circuit 03. Can be connected to input circuit 01.

[0112] The first sampling result Q1 outputted by the fourth flip-flop FF4 through the main output terminal Q and the first sampling result Q2 outputted by the fourth flip-flop FF4 through the inverting output terminal Q The output fourth sampling result Q1' can be an inverted signal. That is, in the same period, the phases of the first sampling result Q1 and the fourth sampling result Q1' can be exactly opposite. For example, when the level of the first sampling result Q1 is a high level 1, the level of the fourth sampling result Q1' can be a low level 0; when the level of the first sampling result Q1 is a low level 0, the level of the fourth sampling result Q1' can be a high level 1.

[0113] Accordingly, continue to refer to Figure 4 and Figure 6 It can be seen that the glitch-free clock switching circuit may further include: a second inverting circuit 05. The second inverting circuit 05 may be connected to the inverting output terminal of the fourth flip-flop FF4. and between input circuit 01.

[0114] The second inverting circuit 05 can be used to: The output fourth sampling result Q1 ′ is inverted to obtain the first sampling result Q1 , and the first sampling result Q1 is output to the input circuit 01 .

[0115] That is, the first sampling result Q1 received by the input circuit 01 is not the first sampling result Q1 directly outputted via the main output terminal Q of the fourth flip-flop FF4, but the first sampling result Q1 directly outputted via the inverting output terminal Q of the fourth flip-flop FF4 by the second inverting circuit 05. The output fourth sampling result Q1' is the first sampling result Q1 after inversion processing. The first sampling result Q1 received by the output circuit 03 is the first sampling result Q1 directly output by the fourth flip-flop FF4 via the main output terminal Q. In this way, the sampling results received by the output circuit 03 and the input circuit 01 can be separated to avoid interference. Of course, in some other embodiments, the second inversion circuit 05 may not be provided, but the main output terminal Q of the fourth flip-flop FF4 may be directly connected to the input circuit 01.

[0116] Optionally, continue to refer to Figure 6 It can also be seen that the first inverting circuit 04 may include: a first inverter (inverted, INV) INV1.

[0117] The input terminal of the first inverter INV1 can be connected to the inverting output terminal of the second flip-flop FF2. connected to receive the second flip-flop FF2 via the inverting output terminal The input terminal of the first inverter INV1 can be connected to the input circuit 01 to output the second sampling result Q2 to the input circuit 01 .

[0118] Optionally, continue to refer to Figure 6It can also be seen that the second inverting circuit 05 may include: a second inverter INV2.

[0119] The input terminal of the second inverter INV2 can be connected to the inverting output terminal of the fourth flip-flop FF4. connected to receive the inverting output terminal of the fourth flip-flop FF4 The input terminal INV2 of the second inverter can be connected to the input circuit 01 to output the first sampling result Q1 to the input circuit 01 .

[0120] Optionally, continue to refer to Figure 2 and Figure 3 It can be seen that the input circuit 01 may include: a first input sub-circuit 011 and a second input sub-circuit 012 .

[0121] The first input sub-circuit 011 may be used to perform a second logic process on the first selection signal SEL and the first sampling result Q1 to output a first input signal D1 .

[0122] The second input sub-circuit 012 can be used to perform a third logic process on the second selection signal SEL′ and the second sampling result Q2 to output a second input signal D2.

[0123] That is, different input sub-circuits may respectively perform logic processing on different selection signals and sampling results to correspondingly output the first input signal D1 and the second input signal D2.

[0124] And, understandably, combined Figure 2 and Figure 3 It can be seen that the first input subcircuit 011 and the second input subcircuit 012 can both be connected to the sampling circuit 02. And, in combination Figure 4 and Figure 6 It can be seen that, on the basis of dividing the sampling circuit 02 into the first sampling sub-circuit 021 and the second sampling sub-circuit 022, and the first sampling sub-circuit 021 includes the first flip-flop FF1 and the second flip-flop FF2 connected in sequence, and the second sampling sub-circuit 022 includes the third flip-flop FF3 and the fourth flip-flop FF4 connected in sequence, the first input sub-circuit 011 can be respectively connected to the input terminal D of the first flip-flop FF1 and the output terminal Q of the fourth flip-flop FF4, and the second input sub-circuit 012 can be respectively connected to the input terminal D of the third flip-flop FF3 and the output terminal Q of the second flip-flop FF2. In addition, on the basis of also including the first inverter INV1 and the second inverter INV2, the first input sub-circuit 011 can be connected to the inverting output terminal of the fourth flip-flop FF4 through the second inverter INV2. That is, the first input sub-circuit 011 may be connected to the output terminal of the second inverter INV2. The second input sub-circuit 012 may be connected to the inverting output terminal of the second flip-flop FF2 via the first inverter INV1. That is, the second input sub-circuit 012 may be connected to the output terminal of the first inverter INV1.

[0125] Optionally, in some embodiments, the second logic operation process may be an AND logic process. Figure 4 and Figure 6 As shown, the first input subcircuit 021 may include: a first AND gate AND1. And / or, the third logic operation processing may also be an AND logic processing. The second input subcircuit 022 may include: a second AND gate AND2. It can be understood that the AND logic processing is also the logic AND operation described above, which is used to output 1 when both received input signals are 1; otherwise, output 0.

[0126] The first input terminal of the first AND gate AND1 can be used to receive the first selection signal SEL. The second input terminal of the first AND gate AND1 can be connected to the output terminal of the sampling circuit 02 to receive the first sampling result Q1 output by the sampling circuit 02. The output terminal of the first AND gate AND1 can be connected to the input terminal of the sampling circuit 02 to output the first input signal D1 to the sampling circuit 02.

[0127] The first input terminal of the second AND gate AND2 can be used to receive the second selection signal SEL'. The second input terminal of the second AND gate AND2 can be connected to the output terminal of the sampling circuit 02 to receive the second sampling result Q2 output by the sampling circuit 02. The output terminal of the second AND gate AND2 can be connected to the input terminal of the sampling circuit 02 to output the second input signal D2 to the sampling circuit 02.

[0128] Furthermore, it can be understood that, on the basis of further providing the first inverter INV1 and the second inverter INV2, the second input terminal of the first AND gate AND1 can be connected to the output terminal of the second inverter INV2, so as to be connected to the inverting output terminal of the fourth flip-flop FF4 included in the sampling circuit 02 via the second inverter INV2. The second input terminal of the second AND gate AND2 can be connected to the output terminal of the first inverter INV1 to be connected to the inverting output terminal of the second flip-flop FF2 included in the sampling circuit 02 via the first inverter INV1. In addition, the output terminal of the first AND gate AND1 may be connected to the input terminal D of the first flip-flop FF1 included in the sampling circuit 02. The output terminal of the second AND gate AND2 may be connected to the input terminal D of the third flip-flop FF3 included in the sampling circuit 02.

[0129] Optionally, continue to refer to Figure 2 and Figure 3 It can be seen that the glitch-free clock switching circuit may further include a third inverting circuit 06 . The third inverting circuit 06 may be connected to the input circuit 01 .

[0130] The third inverting circuit 06 can be used to invert the received first selection signal SEL to output the second selection signal SEL'. That is, an inverting circuit can be set to invert the first selection signal SEL to obtain the second selection signal SEL'. In this way, only one register can be set to connect the glitch-free clock switching circuit to provide the first selection signal SEL.

[0131] And, it is understandable that if Figures 2 to 4 ,as well as Figure 6 As shown, on the basis that the input circuit 01 is divided into a first input sub-circuit 011 and a second input sub-circuit 012, and the first input sub-circuit 011 includes a first AND gate AND1, and the second input sub-circuit 012 includes a second AND gate AND2, the third inverting circuit 06 can be connected to the first input terminal of the second AND gate AND2 included in the second input sub-circuit 012 to output the second selection signal SEL' to the first input terminal of the second AND gate AND2.

[0132] Optionally, continue to refer to Figure 4 and Figure 6 It can be seen that the third inverting circuit 06 may include a third inverter INV3 .

[0133] The input end of the third inverter INV3 can be used to receive the first selection signal SEL, and the output end of the third inverter INV3 can be connected to the input circuit 01 to output the second selection signal SEL′ to the input circuit 01 .

[0134] And, it is understandable that if Figure 4 and Figure 6 As shown, the output terminal of the third inverter INV3 may be connected to the first input terminal of the second AND gate AND2 included in the input circuit 01 .

[0135] Optionally, as described above, the first clock signal CLKA and the second clock signal CLKB described in the embodiment of the present application may be asynchronous clock signals. For example, they may be asynchronous clock signals from different clock sources. The first clock signal CLKA and the second clock signal CLKB as the target clock signal CLK0 may be non-overlapping clock signals. Non-overlapping clock signals are also physically exclusive clock signals.

[0136] by Figure 6The circuit structure shown in the figure, and taking the first clock signal CLKA and the second clock signal CLKB as asynchronous clock signals, and the first clock signal CLKA and the second clock signal CLKB as non-overlapping clock signals of the target clock signal CLK0 as an example, the following embodiment shows the SDC constraint file or SDC constraint command designed for the glitch-free clock switching circuit, and the SDC constraint file is used in the static timing analysis (STA) tool to verify whether the circuit meets the requirements. SDC satisfies:

[0137] (1)create_clock[get_ports CLKA]-name CLKA-period 10-waveform{0 5}–add;

[0138] (2)create_clock[get_ports CLKB]-name CLKB-period 5-waveform{2.5 5}-add;

[0139] (3)create_generated_clock[get_pins OR1 / Z]-name CLK_MUX_CLKA-source[get_ports CLKA]-master_clock CLKA-edges{1 2 3}-add-combinational;

[0140] (4)create_generated_clock[get_pins OR1 / Z]-name CLK_MUX_CLKB-source[get_ports CLKB]-master_clock CLKB-edges{1 2 3}-add-combinational;

[0141] (5)set_clock_group-asynchronous-name async_grps;

[0142] -group[get_clocks{CLKACLK_MUX_CLKA}];

[0143] -group[get_clocks{CLKB CLK_MUX_CLKB}];

[0144] (6)set_clock_group-physically_exclusive mux_phy_grps;

[0145] -group[get_clocks{CLK_MUX_CLKA}];

[0146] -group[get_clocks{CLK_MUX_CLKB}].

[0147] Among them, (1) in SDC may mean: create clock [specify the source port of the clock as CLKA] - name it CLKA - clock period is 10 - clock pulse width is 5 - add it to the design. That is, the first clock signal CLKA with a period of 10 and a pulse width of 5 can be designed as a clock signal. Of course, the clock period and pulse width here are only for schematic illustration, and the embodiments of the present application do not limit them.

[0148] (2) in SDC may mean: create another clock [specify the source port of the clock as CLKB] - name it CLKB - clock period is 5 - clock pulse width is 2.5 - add it to the design. That is, a second clock signal CLKB with a period of 5 and a pulse width of 2.5 may be designed as another clock signal. Of course, the clock period and pulse width here are only for schematic illustration, and are not limited in the embodiments of the present application.

[0149] (3) in SDC can mean: create a generated clock [specify the source pin of the generated clock as OR / Z] - name the generated clock as CLK MUX CLKA - set the clock source to CLKA - specify the master clock as CLKA - define the rising edge, high level and falling edge of the clock - add to the design - the generated clock is generated by combinational logic and does not require a clock enable signal. That is, the clock signal output through the output terminal of the OR gate OR1 (that is, the output signal terminal Z of the glitch-free clock switching circuit) can be defined as the generated clock, and the generated clock that selects the first clock signal CLKA to be output is called CLK_MUX_CLKA.

[0150] (4) in SDC can mean: create another generated clock [specify the source pin of the generated clock as OR / Z] - name the generated clock as CLK_MUX_CLKB - set the clock source to CLKB - specify the master clock as CLKB - define the rising edge, high level and falling edge of the clock - add to the design - the generated clock is generated by combinational logic and does not require a clock enable signal. That is, the clock signal output through the output end of the OR gate OR1 (that is, the output signal end Z of the glitch-free clock switching circuit) can also be defined as a generated clock, and the generated clock that selects the second clock signal CLKB to be output is called CLK_MUX_CLKB.

[0151] (5) in SDC may refer to: setting the clock group - setting the clock group to an asynchronous clock group - naming it async_grps - adding the clock CLKA and the generated clock CLK_MUX_CLKA to the asynchronous clock group - adding the clock CLKB and the generated clock CLK_MUX_CLKB to the asynchronous clock group. That is, the first clock signal CLKA and the generated clock CLK_MUX_CLKA may be defined as an asynchronous clock group, and the second clock signal CLKB and the generated clock CLK_MUX_CLKB may be defined as an asynchronous clock group.

[0152] (6) in SDC may refer to: setting a physically exclusive clock group - setting the clock group to a physically exclusive clock group - naming it mux_phy_grps - adding the generated clock CLK_MUX_CLKA to the physically exclusive clock group - adding the generated clock CLK_MUX_CLKB to the physically exclusive clock group. That is, the generated clocks CLK_MUX_CLKA and CLK_MUX_CLKB may be defined as a physically exclusive clock group.

[0153] It can be understood that an asynchronous clock group refers to: two or more clock signals that have no synchronization relationship, usually from different clock sources. A physically exclusive clock group may refer to: in physical implementation, two or more clock signals are mutually exclusive and cannot drive the same load to work at the same time. Based on this, through the above-mentioned SDC design, it is possible to reliably select a clock signal from two asynchronous clock signals (such as CLKA and CLKB) as the target clock signal CLK0 output without glitches, and it is possible to prevent interference between different clock signals in the output target clock signal CLK0, thereby reliably driving the load to work.

[0154] It is also understandable that, if a glitch-free clock switch is to be achieved, Figure 6The structure shown also needs to pre-set the signal transmission method to meet the following requirements: 1. The signal output by the first trigger FF1 can be reliably transmitted to the second trigger FF2, that is, From FF1 to FF2. 2. The signal output by the third trigger FF3 can be reliably transmitted to the fourth trigger FF4, that is, From FF3 to FF4. 3. The signal output by the second trigger FF2 can be reliably transmitted to the third trigger FF3, that is, From FF2 to FF3. 4. The signal output by the fourth trigger FF4 can be reliably transmitted to the first trigger FF1, that is, From FF4 to FF1. 5. The signal output by the second trigger FF2 can be reliably transmitted to the first integrated clock gating ICG1, that is, From FF2 to ICG1. 6. The signal output by the fourth trigger FF4 can be reliably transmitted to the second integrated clock gating ICG2, that is, From FF4 to ICG2. That is, the above signal path needs to be repaired to ensure the reliable transmission of the signal, so as to ensure that the target clock signal that can be output in the end is free of glitches. Of course, in some embodiments, the transmission of the first selection signal SEL to the first flip-flop FF1 and the transmission of the second selection signal SEL' to the third flip-flop FF3 can also be repaired in the same way. This can be set and completed in the circuit design stage.

[0155] Based on the above embodiments, Figure 7 A timing simulation diagram of clock switching is shown. Figure 6 and Figure 7 It can be seen that when the level of the first selection signal SEL is 1, the level of the second selection signal SEL' is 0. At this time, the glitch-free clock switching circuit can select and output the first clock signal CLKA as the target clock signal CLK0 via the output signal terminal Z. When the level of the first selection signal SEL is 0, the level of the second selection signal SEL' is 1. At this time, the glitch-free clock switching circuit can select and output the second clock signal CLKB as the target clock signal CLK0 via the output signal terminal Z. And refer to Figure 7 It can also be seen that the first clock signal CLKA and the second clock signal CLKB in the output target clock signal CLK0 can be switched seamlessly without glitches, that is, glitches can be filtered.

[0156] Combined with the previous records, it can be seen that, on the one hand, since the embodiment of the present application does not use latches alone, it will not introduce complex timing paths and timing problems, which can make timing analysis easier. On the other hand, since the timing paths between each trigger are full-cycle clock paths, there is enough time for signal transmission in each cycle of the clock signal, which provides a stable timing relationship and is also more beneficial for timing analysis. On the other hand, by directly setting the integrated clock gating ICG to switch the selected clock signal, the timing analysis (such as STA analysis) can be checked on the integrated clock gating ICG. Compared with the traditional method where the integrated clock gating ICG is not set, the timing library can be directly defined by the manufacturer providing the integrated clock gating ICG, so that the timing sign-off verification can be performed more accurately. On the other hand, since only an integrated clock gating ICG and an OR gate OR1 are required to switch the clock signal, this is also beneficial to the quality of the clock signal. On the other hand, the SDC timing constraints provided in the embodiments of the present application can ensure that different clock signals outputted through the output signal terminal Z have no cross interference, and can ensure that there are no redundant timing paths, so that all constrained timing paths are valid. Figure 7 It can also be seen from the simulation results shown that the target clock signal finally output by the glitch-free clock switching circuit provided in the embodiment of the present application is glitch-free, that is, it can be ensured that no glitch is generated during clock switching.

[0157] That is, the embodiment of the present application provides a glitch-free clock switching circuit, which is not only simple in structure and can filter glitches, but also very convenient for timing analysis and has good circuit stability. The glitch-free clock switching circuit and the matching SDC can be widely used in digital ICs to filter glitches when switching clocks.

[0158] In summary, an embodiment of the present application provides a glitch-free clock switching circuit. The glitch-free clock switching circuit includes an input circuit, a sampling circuit, and an output circuit. Since the input circuit can output an input signal to the sampling circuit based on a selection signal and a sampling result, the sampling circuit can perform multiple continuous samplings of the input signal based on the clock signal and output the sampling result to the output circuit, and the output circuit can switch between different clock signals based on the sampling result. Therefore, the sampling method can be flexibly set to cooperate with the output circuit to achieve synchronous switching of the clock signal, thereby avoiding glitches in the clock signal of the switching output. Furthermore, it can ensure that the load is reliably driven to work and avoid failures in the circuits in the load.

[0159] The present application also provides a chip. Figure 8 As shown, the chip includes: a clock source, and Figures 1 to 6 Any of the glitch-free clock switching circuits 00 shown. A clock source is connected to the glitch-free clock switching circuit 00.

[0160] The clock source is used to output a first clock signal CLKA and a second clock signal CLKB to the glitch-free clock switching circuit 00. Optionally, the chip may include two different clock sources 1 and 2 to provide the first clock signal CLKA and the second clock signal CLKB respectively.

[0161] The glitch-free clock switching circuit 00 is used to: based on the received selection signal ( Figure 8 (not shown) a clock signal is switched between the first clock signal CLKA and the second clock signal CLKB.

[0162] Optionally, in some embodiments, the chip may be a display chip. Of course, it may also be any chip that requires a glitch-free clock signal, which is not limited in the embodiments of the present application.

[0163] It is understandable that, since the chip has substantially the same technical effects as the aforementioned glitch-free clock switching circuit, the technical effects of the chip will not be described repeatedly here for the purpose of brevity.

[0164] The present application also provides an electronic device. Fig. 9 As shown, the electronic device includes: a load 100, and Figure 8 Chip 000 is shown.

[0165] Combination Figure 8 and Fig. 9 It can be known that the glitch-free clock switching circuit 00 in the chip 000 is connected to the load 100 and is used to output a switched selected clock signal to the load 100 to drive the load 100 to work.

[0166] Optionally, based on the chip 000 being a display chip, the electronic device can be a display device, and the load 100 can be a video memory in the display device, that is, the electronic device can have a display component, and the display component can display images under the drive of the display chip.

[0167] Optionally, the display device includes but is not limited to any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, and an e-book.

[0168] It is understandable that, since the electronic device has substantially the same technical effects as the aforementioned glitch-free clock switching circuit, the technical effects of the electronic device will not be repeated here for the purpose of brevity.

[0169] It is understood that the terms used in the embodiments of the present application are only used to explain the embodiments of the present application, and are not intended to limit the present application. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be the common meanings understood by people with ordinary skills in the field to which the present application belongs.

[0170] For example, the words "first", "second" or "third" and similar words used in the patent application specification and claims of this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "a" do not indicate a quantitative limitation, but indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. "Up", "down", "left" or "right" are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. "Connect" or "couple" refers to electrical connection. "And / or" means that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0171] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A glitch-free clock switching circuit, characterized in that: The glitch-free clock switching circuit comprises: an input circuit, a sampling circuit and an output circuit, wherein the input circuit is connected to the sampling circuit, and the sampling circuit is also connected to the output circuit; The input circuit is used to: output a first input signal based on a received first selection signal and a first sampling result, and output a second input signal based on a received second selection signal and a second sampling result, wherein the second selection signal and the first selection signal are mutually inverted signals; The sampling circuit is used to: perform multiple continuous sampling on the first input signal based on the received first clock signal to output the second sampling result, and perform multiple continuous sampling on the second input signal based on the received second clock signal to output the first sampling result; The output circuit is used to switch between the first clock signal and the second clock signal based on the first sampling result and the second sampling result to output a target clock signal.

2. The glitch-free clock switching circuit according to claim 1, characterized in that: The output circuit comprises: a first output subcircuit and a second output subcircuit; the first output subcircuit is connected to the sampling circuit and the second output subcircuit respectively; The first output subcircuit is used to: select to output the first clock signal based on the second sampling result, and select to output the second clock signal based on the first sampling result; The second output subcircuit is used to switch between the first clock signal and the second clock signal output by the first output subcircuit to output the target clock signal.

3. The glitch-free clock switching circuit according to claim 2, characterized in that: The first output subcircuit comprises: a first output unit and a second output unit; The first output unit is used to: when the second sampling result is valid, select to output the first clock signal; The second output unit is used to select and output the second clock signal when the first sampling result is valid.

4. The glitch-free clock switching circuit according to claim 3, characterized in that: The first output unit includes: a first integrated clock gating; and / or, the second output unit includes: a second integrated clock gating; The enable end of the first integrated clock gating is connected to the sampling circuit to receive the second sampling result output by the sampling circuit, the clock end of the first integrated clock gating is used to receive the first clock signal, and the output end of the first integrated clock gating is connected to the second output sub-circuit to output the first clock signal to the second output sub-circuit; The enable end of the second integrated clock gating is connected to the sampling circuit to receive the first sampling result output by the sampling circuit, the clock end of the second integrated clock gating is used to receive the second clock signal, and the output end of the second integrated clock gating is connected to the second output sub-circuit to output the second clock signal to the second output sub-circuit.

5. The glitch-free clock switching circuit according to claim 2, characterized in that: The second output subcircuit is used to perform first logic processing on the first clock signal and the second clock signal output by the first output subcircuit to switch between the first clock signal and the second clock signal output by the first output subcircuit to output the target clock signal.

6. The glitch-free clock switching circuit according to claim 5, characterized in that: The first logic processing is a phase OR logic processing; the second output sub-circuit includes: an OR gate.

7. The glitch-free clock switching circuit according to any one of claims 1 to 6, characterized in that: The sampling circuit comprises: a first sampling subcircuit and a second sampling subcircuit; The first sampling subcircuit is used to: perform two consecutive samplings on the first input signal under the control of the falling edge of the first clock signal to output the second sampling result; The second sampling subcircuit is used for: under the control of the falling edge of the second clock signal, performing two consecutive samplings on the second input signal to output the first sampling result.

8. The glitch-free clock switching circuit according to claim 7, characterized in that: The first sampling subcircuit comprises: a first trigger and a second trigger; the main output terminal of the second trigger is connected to the output circuit; the inverting output terminal of the second trigger is connected to the input circuit; the second sampling result outputted by the second trigger via the main output terminal and the third sampling result outputted by the second trigger via the inverting output terminal are inverted signals to each other; the glitch-free clock switching circuit further comprises: a first inverting circuit; the first inverting circuit is connected between the inverting output terminal of the second trigger and the input circuit; The first inverting circuit is used to invert the third sampling result outputted by the second trigger via the inverting output terminal to obtain the second sampling result, and output the second sampling result to the input circuit.

9. The glitch-free clock switching circuit according to claim 7, characterized in that: The second sampling subcircuit includes: a third trigger and a fourth trigger; the main output terminal of the fourth trigger is connected to the output circuit; the inverting output terminal of the fourth trigger is connected to the input circuit; the first sampling result outputted by the fourth trigger through the main output terminal and the fourth sampling result outputted by the fourth trigger through the inverting output terminal are mutually inverted signals; the glitch-free clock switching circuit also includes: a second inverting circuit; the second inverting circuit is connected between the inverting output terminal of the fourth trigger and the input circuit; The second inverting circuit is used to invert the fourth sampling result outputted from the inverting output terminal of the fourth trigger to obtain the first sampling result, and output the first sampling result to the input circuit.

10. The glitch-free clock switching circuit according to any one of claims 1 to 6, characterized in that: The input circuit comprises: a first input subcircuit and a second input subcircuit; The first input subcircuit is used to: perform second logic processing on the first selection signal and the first sampling result to output the first input signal; The second input sub-circuit is used to perform a third logic process on the second selection signal and the second sampling result to output the second input signal.

11. The glitch-free clock switching circuit according to claim 10, characterized in that: The second logic operation processing is an AND logic processing; The first input sub-circuit includes: a first AND gate; and / or the third logic operation processing is an AND logic processing; the second input sub-circuit includes: a second AND gate.

12. The glitch-free clock switching circuit according to any one of claims 1 to 6, characterized in that: The glitch-free clock switching circuit further includes: a third inverting circuit; the third inverting circuit is connected to the input circuit; The third inverting circuit is used for inverting the received first selection signal to output the second selection signal.

13. The glitch-free clock switching circuit according to any one of claims 1 to 6, characterized in that: The first clock signal and the second clock signal are asynchronous clock signals; The first clock signal and the second clock signal as the target clock signal are non-overlapping clock signals.

14. A chip, characterized in that: The chip comprises: a clock source, and a glitch-free clock switching circuit according to any one of claims 1 to 13; the clock source is connected to the glitch-free clock switching circuit; The clock source is used to: output a first clock signal and a second clock signal to the glitch-free clock switching circuit; The glitch-free clock switching circuit is used to switch a selected clock signal between the first clock signal and the second clock signal based on a received selection signal.

15. An electronic device, characterized in that: The electronic device comprises: a load, and the chip according to claim 14; The glitch-free clock switching circuit in the chip is connected to the load and is used to output a switched selected clock signal to the load to drive the load to operate.

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