Incremental Delta-Sigma analog-to-digital conversion circuit

Abstract

The invention provides an incremental Delta-Sigma analog-to-digital conversion circuit. The incremental Delta-Sigma analog-to-digital conversion circuit comprises a modulator and an integrator cascade filter, the order of the incremental Delta-Sigma analog-to-digital conversion circuit is L, and L is a constant greater than 1; the modulator comprises a chopping control signal generation module; the chopping control signal generation module comprises L frequency division signal input ends of the sampling clock, and the chopping control signal generation module obtains a chopping control signal through combinational logic based on L frequency division signals of the sampling clock; the modulator outputs a modulation signal based on the chopping control signal; and the integrator cascade filter receives the modulation signal, and outputs a corresponding conversion signal based on the error of the average analog-to-digital conversion circuit in the conversion period. Under chopping time sequence control, a modulator code stream is processed by an integrator cascade filter, complete offset of direct current offset can be realized in a chopping period, residual offset of an analog-to-digital conversion circuit is eliminated, and influence of flicker noise can be reduced at the same time.

Description

Technical Field

[0001] The present disclosure relates to the technical field of data conversion circuits, and in particular to an incremental Delta-Sigma analog-to-digital conversion circuit. Background Art

[0002] In the existing single-loop discrete-time incremental Delta-Sigma analog-to-digital conversion circuit, the difference between the input signal and the feedback signal is continuously accumulated in a conversion cycle, and the quantization error is averaged. After a conversion cycle, the integrator and the filter are reset, and then the next conversion cycle is entered. The quantization accuracy of the ADC depends on the degree to which the quantization error is averaged, and the degree to which the quantization error is averaged is related to the order L of the loop filter and the number of clock cycles contained in a conversion cycle.

[0003] Due to the existence of periodic reset in the incremental Delta-Sigma analog-to-digital conversion circuit, when the loop filter order is greater than 1, the weight of the signal processed by the downsampling filter is uneven. Taking the cascade of integrators (CoI) filter as an example, the distribution of the CoI filter signal weight is related to the order. The higher the order, the greater the unevenness of the signal weight. For the high-order incremental Delta-Sigma analog-to-digital conversion circuit, there is still an offset (DC offset) residual, and the residual value of the offset increases with the increase of the order and decreases with the increase of the downsampling rate M. Summary of the invention

[0004] The technical problem to be solved by the present disclosure is to overcome the defect that the DC offset of the incremental Delta-Sigma analog-to-digital conversion circuit in the prior art cannot be eliminated, and to provide an incremental Delta-Sigma analog-to-digital conversion circuit.

[0005] The present invention solves the above technical problems through the following technical solutions:

[0006] The present disclosure provides an incremental Delta-Sigma analog-to-digital conversion circuit, comprising a modulator and an integrator cascade filter;

[0007] The order of the incremental Delta-Sigma analog-to-digital conversion circuit is L, where L is a constant greater than 1;

[0008] The modulator includes a chopping control signal generating module;

[0009] The chopping control signal generating module comprises L frequency-divided signal input terminals of the sampling clock, and the chopping control signal generating module modulates the L frequency-divided signals of the sampling clock to obtain the chopping control signal;

[0010] The modulator outputs a modulation signal based on the chopping control signal;

[0011] Wherein, the modulation signal includes a DC offset, the DC offset matches the chopping timing of the chopping control signal, and the DC offsets of all the modulation signals within the same chopping period of the chopping timing are weighted averaged to cancel each other out;

[0012] The integrator cascade filter receives the modulation signal and outputs a corresponding conversion signal based on averaging the error of the incremental Delta-Sigma analog-to-digital conversion circuit within a conversion period.

[0013] Preferably, the modulator includes a loop filter, and the chopping control signal generating module includes a clock signal modulation unit and a chopping signal output unit;

[0014] The clock signal modulation unit includes L frequency-divided clock signal input terminals and L-1 XEN-OR logic gates corresponding to the sampling clock signal;

[0015] The clock signal modulation unit is used to modulate the received L divided clock signals based on L-1 XEN-OR logic gates to obtain the chopping control signal;

[0016] The chopping signal output unit is connected to the input end and the output end of the loop filter respectively;

[0017] The chopping signal output unit is used to modulate the input signal of the loop filter based on the chopping control signal, demodulate the output signal of the loop filter based on the chopping control signal, and modulate the DC offset output by the loop filter;

[0018] The loop filter is used to perform an integration operation on the input signal of the loop filter and output a corresponding modulated analog signal.

[0019] Preferably, the frequency of the divided clock signal inputted at the divided clock signal input terminal is , n=1,2,3...L, is the sampling clock signal frequency.

[0020] Preferably, when L=3, the clock signal modulation unit includes a frequency of The first frequency-divided clock signal input terminal, the frequency is The second divided clock signal input terminal and the frequency are A third frequency-divided clock signal input terminal, and a first XNOR logic gate and a second XNOR logic gate;

[0021] The first frequency-divided clock signal input terminal and the second frequency-divided clock signal input terminal are input into a first XOR logic gate to output a first modulated clock signal;

[0022] The output end of the first XOR gate and the input end of the third frequency-divided clock signal are input into a second XOR logic gate to output a second modulated clock signal;

[0023] The second modulated clock signal is used as the chopping control signal and is output by the chopping signal output unit.

[0024] Preferably, when L=4, the clock signal modulation unit also includes a frequency of a fourth frequency-divided clock signal input terminal and a third XNOR logic gate;

[0025] The output end of the second XNOR logic gate and the input end of the fourth frequency-divided clock signal are input into the third XNOR logic gate to output a third modulated clock signal;

[0026] The third modulated clock signal is used as the chopping control signal and is output by the chopping signal output unit.

[0027] Preferably, the chopping signal output unit and the input end and the output end of the loop filter respectively include:

[0028] The chopping signal output unit is connected to the input end of the loop filter through a first logic switch to control the polarity of the input signal of the loop filter;

[0029] The chopping signal output unit is connected to the output end of the loop filter via a second logic switch to control the polarity of the output signal of the loop filter.

[0030] Preferably, the modulator further comprises a quantizer, and the quantizer is connected to the output end of the loop filter;

[0031] The quantizer is used to receive the modulated analog signal demodulated by the chopping control signal, and convert the demodulated modulated analog signal into a corresponding digital signal.

[0032] Preferably, the modulator further comprises a feedback loop, an input end of the feedback loop is connected to an output end of the quantizer;

[0033] The feedback loop is used to feed back the quantized digital signal, perform differential processing on the input signal of the modulator and the quantized digital signal to obtain a differential input signal, and send the differential input signal to the input end of the loop filter.

[0034] Preferably, the feedback loop comprises a digital-to-analog converter and an adder;

[0035] The input end of the digital-to-analog converter is connected to the output end of the quantizer, and the output end of the digital-to-analog converter is connected to the adder;

[0036] The input end of the adder receives an input analog signal, and the output end of the adder is connected to the input end of the loop filter;

[0037] The digital-to-analog converter is used to convert the quantized digital signal into an analog signal as a feedback signal, and feed it back to the adder;

[0038] The adder is used to add the input analog signal and the feedback signal to obtain a differential signal, and use the differential signal as the input signal of the loop filter. Preferably, it also includes a downsampling module, and the downsampling module is connected to the integrator cascade filter;

[0039] The downsampling module is used to extract the conversion signal output by the integrator cascade filter at a downsampling rate M to obtain an output digital signal;

[0040] The output digital signal is used as the output of the incremental Delta-Sigma analog-to-digital conversion circuit.

[0041] The positive and progressive effect of the present disclosure is that: in view of the non-uniform processing weight of the modulation signal output by the modulator by the integrator cascade filter in the high-order incremental Delta-Sigma analog-to-digital conversion circuit, under the timing control of the chopping control signal generation module, the modulator code stream is processed by the integrator cascade filter, and the DC offset can be completely offset within one chopping cycle. The DC offset of the final single conversion result is zero, thereby eliminating the residual offset caused by the non-uniform signal weight of the high-order incremental Delta-Sigma analog-to-digital conversion circuit, and at the same time reducing the influence of flicker noise. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A schematic diagram of a module of an incremental Delta-Sigma analog-to-digital conversion circuit provided by an exemplary embodiment of the present disclosure;

[0043] Figure 2 A schematic diagram of signal weight distribution of the first to fourth order integrator cascade filters in an incremental Delta-Sigma analog-to-digital conversion circuit provided by an exemplary embodiment of the present disclosure;

[0044] Figure 3A schematic diagram of the circuit structure of an incremental Delta-Sigma analog-to-digital conversion circuit provided by an exemplary embodiment of the present disclosure;

[0045] Figure 4 A schematic diagram of the timing sequence of chopping signals of an incremental Delta-Sigma analog-to-digital conversion circuit at the third order provided by an exemplary embodiment of the present disclosure;

[0046] Figure 5 A schematic diagram of the timing sequence of chopping signals of an incremental Delta-Sigma analog-to-digital conversion circuit at the fourth order provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0047] The present disclosure is further described below by way of examples, but the present disclosure is not limited to the scope of the examples.

[0048] Prefixes such as "first" and "second" are used in the embodiments of the present disclosure only to distinguish different description objects, and have no limiting effect on the position, order, priority, quantity or content of the described objects. The use of prefixes such as ordinal numbers to distinguish description objects in the embodiments of the present disclosure does not constitute a limitation on the described objects. For the statement of the described objects, please refer to the description in the context of the claims or embodiments, and no unnecessary limitation should be constituted due to the use of such prefixes. In addition, in the description of the present embodiment, unless otherwise specified, the meaning of "plurality" is two or more.

[0049] In the incremental Delta-Sigma analog-to-digital conversion circuit, for the first to fourth order CoI filters, the transfer functions are:

[0050] ;

[0051] ;

[0052] ;

[0053] ;

[0054] Where M is the downsampling rate, is the unit delay, The input signal is delayed by k sampling periods, where k is a constant.

[0055] When the loop filter order is greater than 1, the sampling clock frequency is , the chopper frequency of the integrator is The system rejection ratio r of the offset voltage equivalent to the input of the loop filter after one conversion cycle is calculated as follows:

[0056] ;

[0057] ;

[0058] ;

[0059] Example 1

[0060] This embodiment provides an incremental Delta-Sigma analog-to-digital conversion circuit, such as Figure 1 As shown, it includes a modulator 100 and an integrator cascade filter 200;

[0061] The order of the incremental Delta-Sigma analog-to-digital conversion circuit is L, where L is a constant greater than 1;

[0062] The modulator 100 includes a chopping control signal generating module 110;

[0063] The chopping control signal generating module 110 includes L frequency-divided signal input terminals of the sampling clock, and the chopping control signal generating module 110 modulates the L frequency-divided signals of the sampling clock to obtain the chopping control signal;

[0064] The modulator 100 outputs a modulation signal based on the chopping control signal;

[0065] Wherein, the modulation signal includes a DC offset, the DC offset matches the chopping timing of the chopping control signal, and the DC offsets of all the modulation signals within the same chopping period of the chopping timing are weighted averaged to cancel each other out;

[0066] The integrator cascade filter 200 receives the modulation signal, and outputs a corresponding conversion signal based on averaging the error of the incremental Delta-Sigma analog-to-digital conversion circuit within a conversion period.

[0067] In this scheme, the distribution of the signal weights of the first to fourth order CoI filters varies with the data sequence number as follows: Figure 2 As shown in the figure, the vertical axis represents the signal weight, and the horizontal axis represents the corresponding data position. In the second to fourth orders, the modulation signal weight is an uneven weight. Since the unevenness of the modulation signal weight increases with the increase of the order, for the kth data, its modulation signal weight is closest to the modulation signal weight corresponding to the (k-1)th and (k+1)th data, and the change of the modulation signal weight is a monotonic function. Therefore, for systems of different orders, the chopping control signal generation module 110 outputs a modulation signal that matches the modulation signal weight, so that the offset can be offset to the greatest extent.

[0068] In one embodiment, taking the incremental Delta-Sigma analog-to-digital conversion circuit as the second order as an example, the change of the modulation signal weight is uniformly decreasing. For the kth data, based on the second-order transfer function of the CoI filter, the input modulation signal weight is (2(M-k+1)) / (M(M+1)). Usually, the modulation signal weight corresponding to the first data is the largest. The chopping control signal generation module 110 outputs a chopping control signal that matches the second order. The chopping timing corresponding to the chopping control signal is In the same chopping cycle of the chopping sequence, the first offset corresponding to the first data and the second offset corresponding to the second data offset each other, generating a positive Similarly, the third offset corresponding to the third data offsets the fourth offset corresponding to the fourth data, resulting in a negative ;Will and By offsetting them again, the offset can be completely eliminated.

[0069] As a feasible approach, Figure 3 As shown, the modulator 100 includes a loop filter 120, and the chopping control signal generating module 110 includes a clock signal modulating unit 111 and a chopping signal output unit 112;

[0070] The clock signal modulation unit 111 includes L frequency-divided clock signal input terminals corresponding to the sampling clock signal and L-1 XEN-OR logic gates;

[0071] The clock signal modulation unit 111 is used for modulating the received L divided clock signals based on L-1 XNOR logic gates 1112 to obtain the chopping control signal;

[0072] The chopping signal output unit 112 is connected to the input end and the output end of the loop filter 120 respectively;

[0073] The chopping signal output unit 112 is used to modulate the input signal of the loop filter 120 based on the chopping control signal, demodulate the output signal of the loop filter 120 based on the chopping control signal, and modulate the DC offset output by the loop filter;

[0074] The loop filter 120 is used to perform an integration operation on the input signal of the loop filter and output a corresponding modulated analog signal.

[0075] In this solution, the clock signal modulation unit 111 sets corresponding cascaded XOR logic gates and L frequency-divided clock signal input terminals 1111 based on the order L. The frequency-divided clock signal input terminal 1111 inputs a sampling clock divided-by-two signal such as ck_div2, a sampling clock divided-by-four signal such as ck_div4, and ck_div2. L Sampling clock 2 L The frequency division signal is used to provide a stable timing control, and a chopping control signal matching the order L is generated. The chopping signal output unit 112 modulates the input signal of the loop filter 120 with the chopping control signal ck_chop. The chopping control signal ck_chop also demodulates the output valid signal of the loop filter 120, and modulates the DC offset at the output end of the loop filter, so that the DC offset of all the modulated signals output by the modulator 100 within the same chopping cycle of the chopping timing can be offset after being averaged with non-uniform weights. The input signal of the loop filter 120 includes a DC offset.

[0076] As a feasible method, the frequency of the divided clock signal inputted into the divided clock signal input terminal is , n=1,2,3...L, is the sampling clock signal frequency.

[0077] In this solution, different from the prior art which uses a single frequency The chopping control signal is adjusted with L divided clock signals matching the order L to obtain a chopping control signal that can match the weight of the modulation signal in the corresponding order, thereby achieving complete cancellation of the DC offset of all the modulation signals in the same chopping cycle of the chopping timing.

[0078] As an implementable method, when L=3, the clock signal modulation unit 111 includes a frequency of The first frequency-divided clock signal input terminal, the frequency is The second divided clock signal input terminal and the frequency are A third frequency-divided clock signal input terminal, and a first XNOR logic gate and a second XNOR logic gate;

[0079] The first frequency-divided clock signal input terminal and the second frequency-divided clock signal input terminal are input into a first XOR logic gate to output a first modulated clock signal;

[0080] The output end of the first XOR gate and the input end of the third frequency-divided clock signal are input into a second XOR logic gate to output a second modulated clock signal;

[0081] The second modulated clock signal is used as the chopping control signal and is output by the chopping signal output unit 112 .

[0082] In this scheme, for the third-order system, the change of signal weight decreases non-uniformly. For the kth data, based on the third-order transfer function of the CoI filter, the modulation signal weight is , the difference between the modulation weights of the kth and (k+1)th data is The chopping control signal generation module 110 outputs a chopping control signal that matches the third order, such as Figure 4 As shown, ck is the timing of the sampling clock signal, ck_chop_2nd is the frequency The first modulation clock signal has a frequency of The divided clock signal and frequency are The frequency division signal of is obtained by OR calculation, and ck_chop_3rd is the frequency of The second modulated clock signal is composed of the first modulated clock signal and a frequency of The frequency division signal is obtained by OR calculation, the timing of the second modulation clock signal is the chopping timing corresponding to the chopping control signal, and the sequence of a chopping cycle in the chopping timing corresponding to the chopping control signal is , the remaining positive value after the first four data are offset , whose weight value is , after the last four data are offset, the remaining negative , whose weight value is , it can be seen that the modulated signal weight of the residual offset after the accumulation of 8 data has nothing to do with k. and The chopping control signal generating module 110 obtains a chopping control signal that can match the weight of the modulation signal in the corresponding order based on the input frequency-divided clock signal, so as to achieve complete cancellation of the DC offsets of all the modulation signals in the same chopping cycle of the chopping sequence.

[0083] As an implementable method, when L=4, the clock signal modulation unit 111 also includes a frequency of a fourth frequency-divided clock signal input terminal and a third XNOR logic gate;

[0084] The output end of the second XNOR logic gate and the input end of the fourth frequency-divided clock signal are input into the third XNOR logic gate to output a third modulated clock signal;

[0085] The third modulated clock signal is used as the chopping control signal and is output by the chopping signal output unit 112 .

[0086] In this scheme, on the basis of the third-order system, for the fourth-order system, for the kth data, the fourth-order transfer function based on the CoI filter, its modulated signal weight is , the difference between the modulation signal weights of the kth and (k+1)th data is .like Figure 5 As shown, ck is the timing of the sampling clock signal, ck_chop_2nd is the frequency The first modulation clock signal has a frequency of The divided clock signal and frequency are The frequency division signal of ck_chop_3rd is obtained by OR calculation. The second modulated clock signal is composed of the first modulated clock signal and a frequency of The frequency division signal of ck_chop_4th is obtained by OR calculation. The timing of the third modulation clock signal is composed of the second modulation clock signal and a frequency of The frequency division signal is obtained by the same or calculation, the timing of the third modulation clock signal is the chopping timing corresponding to the chopping control signal, and the chopping timing corresponding to the chopping control signal adopts a sequence of one chopping cycle as follows: , the remaining positive value after the first four data are offset , whose weight value is , after the last four data are offset, the remaining negative , whose weight value is , and Offset again, the remaining positive , whose weight value is As with the third-order system, the weight of the residual offset after the first 8 data are accumulated has nothing to do with k; similarly, by calculation, the weight of the residual offset after the last 8 data are accumulated can be obtained as Therefore, for a fourth-order system, the chopping control signal obtained by modulation based on the XOR logic gate with the first frequency-divided clock signal, the second frequency-divided clock signal, the third frequency-divided clock signal and the fourth frequency-divided clock signal can match the weight of the modulation signal in the corresponding order, so as to achieve complete cancellation of the DC offset of all the modulation signals in the same chopping cycle of the chopping timing.

[0087] In an implementable manner, the chopping signal output unit 112 and the input and output ends of the loop filter 120 respectively include:

[0088] The chopping signal output unit 112 is connected to the input end of the loop filter 130 through the first logic switch 130 to control the polarity of the input signal of the loop filter 130;

[0089] The chopping signal output unit 112 is connected to the output end of the loop filter 130 via the second logic switch 120 to control the polarity of the output signal of the loop filter 130 .

[0090] In this solution, the first logic switch 130 is used to multiply the input signal of the loop filter 120 with the chopping control signal to achieve signal modulation. The first logic switch 130 realizes the function of a multiplier. The second logic switch 140 is used to multiply the output signal of the loop filter 120 with the chopping control signal to achieve signal demodulation. The second logic switch 140 also realizes the function of a multiplier. The modulation and demodulation process reduces the offset voltage and low-frequency noise, which helps to convert DC offset and low-frequency noise to high frequency, so that they can be filtered out by a subsequent digital filter.

[0091] As an implementable manner, the modulator 100 further includes a quantizer 160, and the quantizer 160 is connected to the output end of the loop filter 120;

[0092] The quantizer 160 is used to receive the modulated analog signal demodulated by the chopping control signal, and convert the demodulated modulated analog signal into a corresponding digital signal.

[0093] As a feasible method for feedback, the low-precision code stream, the modulator 100 further includes a feedback loop, the input end of the feedback loop is connected to the output end of the quantizer 160;

[0094] The feedback loop is used to feed back the quantized digital signal, perform differential processing on the input signal of the modulator 100 and the quantized digital signal to obtain a differential input signal, and send the differential input signal to the input end of the loop filter 120.

[0095] In this scheme, the quantization error feedback is performed through the feedback circuit. In the incremental Delta-Sigma analog-to-digital conversion circuit, the quantization process of the modulator 100 will produce a quantization error. The feedback loop feeds the quantization error back from the output end to the input end, so that the quantization error can be fed back and processed together with the new input signal in the subsequent sampling cycle.

[0096] As an implementable manner, the feedback loop includes a digital-to-analog converter 170 and an adder 150;

[0097] The input end of the digital-to-analog converter 170 is connected to the output end of the quantizer 160, and the output end of the digital-to-analog converter 170 is connected to the adder 150;

[0098] The input end of the adder 150 receives the input analog signal, and the output end of the adder 150 is connected to the input end of the loop filter 120;

[0099] The digital-to-analog converter 170 is used to convert the quantized digital signal into an analog signal as a feedback signal, and feed it back to the adder 150;

[0100] The adder 150 is used to add the input analog signal and the feedback signal to obtain a differential signal, and use the differential signal as the input signal of the loop filter 130 .

[0101] In this solution, in the incremental Delta-Sigma analog-to-digital conversion circuit, the adder 150 adds the input signal and the feedback signal to obtain a differential signal, wherein the subtraction is achieved by adding a negative feedback signal in the adder 150, and the obtained differential signal reflects the difference between the input signal and the feedback signal, that is, the quantization error. The quantization error is sent to the subsequent modulator 100 for processing, so that the spectrum distribution of the quantization noise is changed, that is, noise shaping is achieved.

[0102] As an implementable manner, it further includes a downsampling module, and the downsampling module is connected to the integrator cascade filter 200;

[0103] The downsampling module is used to extract the conversion signal output by the integrator cascade filter 200 at a downsampling rate M to obtain an output digital signal;

[0104] The output digital signal is used as the output of the incremental Delta-Sigma analog-to-digital conversion circuit.

[0105] In this solution, the output rate of the signal is reduced by the downsampling module, which significantly reduces the amount of data. After downsampling, the high-frequency noise and the modulated high-frequency offset in the signal are filtered out, so that subsequent digital processing can be performed on the basis of a purer signal, thereby improving the accuracy and reliability of the final output signal.

[0106] The incremental Delta-Sigma analog-to-digital conversion circuit provided in this embodiment targets the non-uniform processing weights of the modulation signal output by the modulator by the integrator cascade filter in the high-order incremental Delta-Sigma analog-to-digital conversion circuit. Under the timing control of the chopping control signal generating module, the modulator code stream is processed by the integrator cascade filter, and the DC offset can be completely offset within one chopping cycle. The DC offset of the single conversion result finally obtained is zero, thereby eliminating the residual offset caused by the non-uniform signal weights of the high-order incremental Delta-Sigma analog-to-digital conversion circuit, and also reducing the influence of flicker noise.

[0107] Although the specific embodiments of the present disclosure are described above, those skilled in the art should understand that this is only an example, and the protection scope of the present disclosure is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present disclosure, but these changes and modifications all fall within the protection scope of the present disclosure.

Claims

1. An incremental Delta-Sigma analog-to-digital conversion circuit, characterized in that: Includes modulator and integrator cascade filter; The order of the incremental Delta-Sigma analog-to-digital conversion circuit is L, where L is a constant greater than 1; The modulator includes a chopping control signal generating module; The chopping control signal generating module includes L frequency-divided signal input terminals of the sampling clock, and the chopping control signal generating module obtains the chopping control signal through combinational logic based on the L frequency-divided signals of the sampling clock; The modulator outputs a modulation signal based on the chopping control signal; Wherein, the modulation signal includes a DC offset, the DC offset matches the chopping timing of the chopping control signal, and the DC offsets of all the modulation signals within the same chopping period of the chopping timing are weighted averaged to cancel each other out; The integrator cascade filter receives the modulation signal and outputs a corresponding conversion signal based on averaging the error of the incremental Delta-Sigma analog-to-digital conversion circuit within a conversion period.

2. The incremental Delta-Sigma analog-to-digital conversion circuit according to claim 1, characterized in that: The modulator includes a loop filter, and the chopping control signal generating module includes a clock signal modulation unit and a chopping signal output unit; The clock signal modulation unit includes L frequency-divided clock signal input terminals and L-1 XEN-OR logic gates corresponding to the sampling clock signal; The clock signal modulation unit is used to modulate the received L divided clock signals based on L-1 XEN-OR logic gates to obtain the chopping control signal; The chopping signal output unit is connected to the input end and the output end of the loop filter respectively; The chopping signal output unit is used to modulate the input signal of the loop filter based on the chopping control signal, demodulate the output signal of the loop filter based on the chopping control signal, and modulate the DC offset output by the loop filter; The loop filter is used to perform an integration operation on the input signal of the loop filter and output a corresponding modulated analog signal.

3. The incremental Delta-Sigma analog-to-digital conversion circuit according to claim 2, characterized in that: The frequency of the divided clock signal input at the divided clock signal input terminal is , n=1,2,3...L, is the sampling clock signal frequency.

4. The incremental Delta-Sigma analog-to-digital conversion circuit according to claim 3, characterized in that: When L=3, the clock signal modulation unit includes a frequency of The first frequency-divided clock signal input terminal, the frequency is The second divided clock signal input terminal and the frequency are A third frequency-divided clock signal input terminal, and a first XNOR logic gate and a second XNOR logic gate; The first frequency-divided clock signal input terminal and the second frequency-divided clock signal input terminal are input into a first XOR logic gate to output a first modulated clock signal; The output end of the first XOR gate and the input end of the third frequency-divided clock signal are input into a second XOR logic gate to output a second modulated clock signal; The second modulated clock signal is used as the chopping control signal and is output by the chopping signal output unit.

5. The incremental Delta-Sigma analog-to-digital conversion circuit according to claim 4, characterized in that: When L=4, the clock signal modulation unit also includes a frequency of a fourth frequency-divided clock signal input terminal and a third XNOR logic gate; The output end of the second XNOR logic gate and the input end of the fourth frequency-divided clock signal are input into the third XNOR logic gate to output a third modulated clock signal; The third modulated clock signal is used as the chopping control signal and is output by the chopping signal output unit.

6. The incremental Delta-Sigma analog-to-digital conversion circuit according to claim 2, characterized in that: The chopping signal output unit and the input end and output end of the loop filter respectively include: The chopping signal output unit is connected to the input end of the loop filter through a first logic switch to control the polarity of the input signal of the loop filter; The chopping signal output unit is connected to the output end of the loop filter via a second logic switch to control the polarity of the output signal of the loop filter.

7. The incremental Delta-Sigma analog-to-digital conversion circuit according to claim 6, characterized in that: The modulator further comprises a quantizer, and the quantizer is connected to the output end of the loop filter; The quantizer is used to receive the modulated analog signal demodulated by the chopping control signal, and convert the demodulated modulated analog signal into a corresponding digital signal.

8. The incremental Delta-Sigma analog-to-digital conversion circuit according to claim 7, characterized in that: The modulator further comprises a feedback loop, an input end of the feedback loop being connected to an output end of the quantizer; The feedback loop is used to feed back the quantized digital signal, perform differential processing on the input signal of the modulator and the quantized digital signal to obtain a differential input signal, and send the differential input signal to the input end of the loop filter.

9. The incremental Delta-Sigma analog-to-digital conversion circuit according to claim 8, characterized in that: The feedback loop includes a digital-to-analog converter and an adder; The input end of the digital-to-analog converter is connected to the output end of the quantizer, and the output end of the digital-to-analog converter is connected to the adder; The input end of the adder receives an input analog signal, and the output end of the adder is connected to the input end of the loop filter; The digital-to-analog converter is used to convert the quantized digital signal into an analog signal as a feedback signal, and feed it back to the adder; The adder is used to add the input analog signal and the feedback signal to obtain a differential signal, and use the differential signal as the input signal of the loop filter.

10. The incremental Delta-Sigma analog-to-digital conversion circuit according to claim 2, characterized in that: It also includes a downsampling module, and the downsampling module is connected to the integrator cascade filter; The downsampling module is used to extract the conversion signal output by the integrator cascade filter at a downsampling rate M to obtain an output digital signal; The output digital signal is used as the output of the incremental Delta-Sigma analog-to-digital conversion circuit.

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